JP2004259866A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bonding technique by which an inner lead can be bonded properly to an electrode pad. <P>SOLUTION: When a plurality of the inner leads 25 are thermocompression-bonded collectively on a plurality of bumps 15, a touch speed 61 of a bonding tool 51, an initial load applying speed 64, an initial load search speed 65, load change speed 68, a second load search speed 69, a load reducing speed 73, and a second bonding-tool elevating speed 75 are controlled as factors excepting a bonding temperature, a bonding load and a load holding time. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a bonding technology for bonding an inner lead laid on a carrier to an electrode pad of a semiconductor chip (hereinafter, referred to as a chip) in which an integrated circuit including a semiconductor element is built. For example, the present invention relates to a device that is effective when used in a method of manufacturing a semiconductor integrated circuit device (hereinafter, referred to as COF · IC) provided with a chip-on-film package (Chip On Film Package).
[0002]
[Prior art]
A COF IC in which a plurality of inner leads laid on a film-like carrier are bonded to a plurality of electrode pads of a chip is used for a driver of a liquid crystal display device.
[0003]
As a bonding apparatus for performing an inner lead bonding step of bonding inner leads to electrode pads of a chip in a COF / IC manufacturing method, a large number of inner leads are collectively bonded to a large number of electrode pads of a chip by a bonding tool. There is an inner lead bonding apparatus (hereinafter, referred to as a die bonder) (for example, see Non-Patent Document 1).
[0004]
[Non-patent document 1]
"Electronic Materials November 1999 Separate Volume," Industrial Research Council, November 25, 1999, p. 115-120
[0005]
[Problems to be solved by the invention]
However, it has been clarified by the present inventor that the above-described die bonder has a problem in that when the COF · IC is manufactured, the pressure expansion strength between the electrode pad and the inner lead is reduced due to the thermal expansion and thermal contraction of the tape. Was.
[0006]
An object of the present invention is to provide a bonding technique that can properly bond an inner lead to an electrode pad.
[0007]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a typical invention disclosed in the present application will be described as follows.
[0009]
That is, a method for manufacturing a semiconductor device including a bonding step in which a plurality of electrode pads of a semiconductor chip are thermocompression-bonded together by a bonding tool to a plurality of inner leads laid on a carrier,
Factors other than the bonding temperature, bonding load, and load hold time are controlled by the touch speed, initial load application speed, initial load search speed, load change speed, second load search speed, load reduction speed, and release speed of the bonding tool. It is characterized by the following.
[0010]
According to the above-described means, the pressure contact strength between the inner lead and the bump can be increased, so that gang bonding can be appropriately performed even in the case of a multi-pin narrow pitch such as 50 μm with 444 pins.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0012]
In the present embodiment, the method of manufacturing a semiconductor device according to the present invention is configured as a method of manufacturing a COF.IC. The inner lead bonding step, which is a characteristic step of the method, is performed by using the chip 10 shown in FIG. This is performed by the die bonder 30 shown in FIG. 3 for inner lead bonding to the carrier tape 20 shown in FIG.
[0013]
A chip 10, which is one of the works of the die bonder, has a rectangular flat plate shape as shown in FIG. 1 after an integrated circuit is formed in a state of a semiconductor wafer in a so-called pre-process in a COF / IC manufacturing method. And supplied to the die bonder 30. That is, a plurality of electrode pads 13 for taking out an integrated circuit to the outside are provided on the active area side main surface (hereinafter, referred to as a first main surface) 12 of the substrate 11 of the chip 10 at both ends on the long side. They are arranged and opened at appropriate intervals so as not to interfere with each other. On the first main surface 12 of the chip 10, a passivation film 14 is uniformly applied as a whole with the electrode pads (hereinafter, referred to as pads) 13 exposed. On each pad 13, a bump 15 made of a gold-based material (Au or Au alloy) is projected. The bump 15 is formed in a substantially hemispherical shape using a wire bonding technique, and is in a state of protruding from the passivation film 14.
[0014]
The carrier tape 20 shown in FIG. 2 is supplied to the die bonder 30 used in the COF / IC manufacturing method according to the present embodiment as the other work. The carrier tape 20 corresponds to a TAB (tape automated bonding) tape used in a method for manufacturing a TCP IC (IC having a tape carrier package). Since the carrier tape 20 is configured so that the same pattern is repeated in the longitudinal direction, the description and illustration of the configuration will be made for only one unit.
[0015]
As shown in FIG. 2, the carrier tape 20 includes a tape body 21 formed in a tape shape by using an insulating material such as a polyimide resin. The holes 22 are arranged at predetermined intervals along the both sides. A large number of virtually formed substantially rectangular bonding areas 23 are arranged at predetermined intervals on the center line of the tape body 21, and the long axis direction of each bonding area 23 is orthogonal to the center line of the tape body 21. Have been. A pair of left and right outer lead holes 24 are formed on both left and right sides of the bonding area 23 symmetrically. A plurality of inner leads 25 for taking out the integrated circuit to the outside are laid on one main surface (hereinafter, referred to as a first main surface) of the tape main body 21 so as to be electrically disconnected from each other. . A plurality of inner leads 25 are distributed to the left and right of the bonding area 23, and the tips of the left and right inner leads 25, 25 are arranged so as to protrude into the bonding area 23 and correspond to the pads 13 of the chip 10. I have. Outer leads 26 are integrally formed outside the inner leads 25, and the outer leads 26 are formed so as to straddle the left and right outer lead holes 24 of the tape body 21, respectively. The surface of the inner lead 25 and the outer lead 26 is partially or entirely covered with a tin plating film.
[0016]
As shown in FIG. 3, the die bonder 30 includes a plurality of tape guides 31 for guiding the carrier tape 20 in one direction, and the carrier tape 20 bridged between the plurality of tape guides 31 includes: The pitch is fed in one direction by a pitch feeder (not shown). A bonding station 32 is set in the middle of the adjacent tape guides 31 at a predetermined position, and an upper clamper 33A and a lower clamper 33B for clamping the carrier tape 20 are installed in the bonding station 32. A heat block 34 is provided in the bonding station 32, and a first bonding tool 35 is provided on the heat block 34. The first bonding tool 35 is configured to hold the chip 10 with the bump 15 side facing upward. The heat block 34 is supported by a Z table 37 via a heat insulating block 36, and the Z table 37 is configured to raise and lower the first bonding tool 35 in the vertical (Z) direction. The Z table 37 is supported by a Θ table 38, and the Θ table 38 is configured to rotate the Z table 37 in a horizontal plane. The Θ table 38 is supported by an X table 39, and the X table 39 is configured to reciprocate the Θ table 38 in the X direction, which is a direction orthogonal to the feed direction (Y direction) of the carrier tape 20 in a horizontal plane. ing. The X table 39 is supported by a Y table 40, and the Y table 40 is configured to reciprocate the X table 39 in the Y direction which is the feed direction of the carrier tape 20 in a horizontal plane.
[0017]
An upper Y table 41 is installed horizontally above the bonding station 32, and an upper X table 42 is supported on the upper Y table 41. The upper Y table 41 is configured to reciprocate the upper X table 42 in the Y direction in a horizontal plane. A bracket 43 is vertically supported on a side surface of the upper X table 42 facing the bonding station 32, and the upper X table 42 is configured to reciprocate the bracket 43 in the X direction in a horizontal plane. At the upper end of the side of the bracket 43 facing the bonding station 32, a load application device 44 is installed. The load application device 44 includes a load cell 45, a tool flatness Δy adjustment unit 46, and a tool flatness Δx adjustment unit 47. The second bonding tool 51 is connected via a tool flatness adjusting section 48, a heat insulating section 49 and a holding section 50. The load application device 44 is configured to apply a load to the second bonding tool 51 by a feed screw shaft device, and the load cell 45 is configured to perform feedback control of the load application device 44. The second bonding tool 51 is formed in a rectangular bar shape corresponding to the bonding area 23, and the second bonding tool 51 has a built-in heater (not shown). Although not shown, an image recognition device is installed on the bracket 43 in a vertically downward direction. Each table and the load applying device 44 are configured to be controlled by a controller.
[0018]
The inner lead bonding step in the method of manufacturing a COF / IC by the die bonder 30 according to the above configuration will be described.
[0019]
When the chip 10 is subjected to the inner lead bonding to the carrier tape 20, as shown in FIG. 3, the carrier tape 20, which is one of the works, is disposed with the first main surface on the inner lead 25 side facing downward. The tape is stretched between a plurality of tape guides 31 and fed in one direction. The chip 10, which is the other work, is held by the first bonding tool 35 with the first main surface on the bump 15 side facing upward.
[0020]
When the carrier tape 20 is intermittently stopped and clamped by the upper clamper 33A and the lower clamper 33B, as shown in FIG. The first bonding tool 35 is raised while being aligned with the tip of the inner lead 25 so as to face the bonding area 23 of the tape 20.
[0021]
In this state, as shown in FIG. 4B, when the second bonding tool 51 is lowered by the load applying device 44, each bump 15 is attached to the tip of each inner lead 25 by the first bonding tool 35. And the second bonding tool 51 to perform thermocompression bonding. That is, a gold-tin eutectic layer is formed between the tin plating film deposited on the surface of the inner lead 25 and the bump 15 made of a gold-based material. 25 is mechanically and electrically connected by the bumps 15.
[0022]
When the gang bonding by the cooperation of the first bonding tool 35 and the second bonding tool 51 is completed, the second bonding tool 51 is raised as shown in FIG. 4C. Subsequently, as shown in FIG. 4D, the first bonding tool 35 is lowered.
[0023]
Thereafter, the inner lead bonding is sequentially performed for each unit of the carrier tape 20 by repeating the above operation.
[0024]
When the inner lead bonding step is completed, as shown in FIG. 5, an assembly 27 in which the chip 10 is mechanically and electrically connected to the carrier tape 20 by the bumps 15 is manufactured. That is, as shown in FIG. 5, the bumps 15 protruding from the pads 13 of the chip 10 are mechanically and electrically connected to the tips of the inner leads 25 facing the bonding area 23 of the carrier tape 20. Have been.
[0025]
An assembly 27 formed by inner lead bonding of the chip 10 to the carrier tape 20 in the inner lead bonding step is supplied to a resin sealing body forming step. Although not shown, in the resin sealing body forming step, a resin sealing body is formed in the assembly 27 by a potting method, and a molded product is manufactured. In the molded product, the resin-sealed body is in a state where the chip 10, the inner leads 25 and the bumps 15 are sealed with the resin, and the resin-sealed body is integrally connected to the tape body 21 and the chip 10. Has become.
[0026]
Thereafter, when the molded product is cut at the front and rear sides of the resin seal of the tape body 21 with the left and right outer leads 26, 26, the COF / IC is manufactured. In the COF · IC, a plurality of pads 13 are arranged in two rows on the upper surface of the chip 10, and the tips of the inner leads 25 are gang-bonded to the pads 13 via the bumps 15 in the bonding area 23, respectively. Are electrically and electrically connected, and are sealed with a resin sealing body.
[0027]
By the way, as the number of pins and the pitch of the pads and inner leads in the COF · IC increase, the applied load and the heating temperature for gang bonding a plurality of inner leads to a plurality of pads increase. For example, when the pitch becomes 50 μm with 444 pins, the load becomes 490 N, and the heating temperature becomes 500 ° C. on the first bonding tool 35 side and 200 ° C. on the second bonding tool 51 side. As described above, when the heating temperature of the chip 10 is increased, the inner lead is pulled from the heat-bonded pad by the thermal expansion of the tape during the bonding and holding and the thermal contraction force of the tape when the heating and holding is released. It has been clarified by the present inventors that there is a problem that the pressure contact strength between the lead and the inner lead is reduced. That is, the bonding temperature, the bonding load, and the load holding time are controlled, and the 50 μm inner leads and the bumps are collectively thermocompression-bonded with 444 pins, and after gold-tin eutectic bonding, respectively, the carrier tape 20 is fixed. When an experiment of pulling the chip 10 was performed, peeling occurred at the gold-tin eutectic junction between the inner lead 25 and the bump 15. If the eutectic bonding strength of the gold-tin eutectic bonding portion between the inner lead 25 and the bump 15 is proper, the bonding (adhesion) strength between the outer lead 26 and the tape body 21 is lower. Peeling occurs.
[0028]
Therefore, in the present embodiment, the eutectic bonding strength between the pad and the inner lead is increased by setting the control sequence of the bonding load as shown in FIG. 6 in the above-described inner lead bonding step. And
[0029]
Hereinafter, the control sequence of the bonding load in the inner lead bonding step according to the embodiment of the present invention shown in FIG. 6 will be described. In FIG. 6, the horizontal axis represents time (seconds), and the vertical axis represents applied load (N). The heating temperature at the time of bonding is 500 ° C. on the first bonding tool 35 side and 200 ° C. on the second bonding tool 51 side.
[0030]
In FIG. 6, reference numeral 61 denotes a detected load straight line at a touch speed when the second bonding tool 51 descends and a load is applied to the chip 10. The touch speed in the present embodiment is 8 mm / sec, and the touch speed is set to a low speed in order to prevent the chip 10 from being damaged by an impact or the like.
[0031]
In FIG. 6, reference numeral 62 denotes a landing detection load, which is a load value applied to the chip 10 when the load cell 45 detects a preset load, and is 20 N in the present embodiment. The load cell 45 is correlated with a load value applied to the chip 10 in advance. 63 is a shock wave at the time of landing.
[0032]
Thereafter, a load is applied from the detected landing detection load 62 to the vicinity of the initial bonding load 66 with an initial load application speed (applied load per unit time; hereinafter, the same applies to the load application speed) 64, and subsequently, a load is applied. A load is applied with an initial load search speed 65. In the present embodiment, the initial load application speed 64 is 200 N / sec, and the value of the initial bonding load 66 is 70 N. By controlling the initial load application speed 64 in this manner, the spread of the bump 15 in the width direction can be suppressed, so that the bonding area can be increased, and the joint between the bump 15 and the inner lead 25 can be reduced. Crystal bonding strength can be increased. In addition, by controlling the initial bonding load 66, the amount of the inner lead pushed into the bump can be controlled.
[0033]
Next, after the initial bonding load hold time 67 has elapsed, a load is applied at a load changing speed 68 from the initial bonding load 66 to near the second bonding load 70, and subsequently, a load is applied at a second load search speed 69. You. In the present embodiment, the initial bonding load hold time 67 is 0.25 seconds, the load change speed 68 is 10 N / second, and the value of the second bonding load 70 is 58 N.
[0034]
After the second bonding load hold time 71 has elapsed since the time when the value of the second bonding load 70 was detected, the applied load is reduced to the speed switching load 74 at the load reduction speed 73. In the present embodiment, the second bonding load hold time 71 is 1.25 seconds, the load reduction speed 73 is 150 N / second, and the value of the speed switching load 74 is 25 N. The total bonding load hold time 72 from the beginning of the initial bonding load hold time 67 to the end of the second bonding load hold time 71 is 2 seconds. By controlling the load reduction speed 73 in this manner, the eutectic bonding strength can be increased when the load is reduced.
[0035]
The load cell 45 confirms that the applied load has been reduced to the speed switching load 74, and the second bonding tool 51 is raised with the second bonding tool raising speed 75 as a release speed. In the present embodiment, the second bonding tool lifting speed 75 is 5 mm / sec. By controlling the rising speed 75 of the second bonding tool in this way, the thermal shrinkage speed of the tape can be controlled, and the balance with the cooling and fixing force of the molten eutectic joint can be controlled. The peeling of the eutectic joint due to the shrinking force of 20 can be prevented. When bonding (thermocompression bonding) is performed by previously stretching the carrier tape 20 by forming as a measure against thermal expansion of the chip 10, the contraction force of the carrier tape 20 accompanying the release of the first bonding tool 35 after thermocompression bonding is reduced. Since it becomes large, it is particularly effective for suppressing the speed of generating the contraction force.
[0036]
As described above, when the plurality of inner leads 25 are collectively thermocompression-bonded to the plurality of bumps 15, factors other than the bonding temperature, the bonding load, and the load hold time are factors other than the touch speed of the bonding tool to the part to be bonded. By controlling the initial load application speed 64, the initial load search speed 65, the load change speed 68, the second load search speed 69, the load reduction speed 73, and the second bonding tool raising speed 75, the inner leads 25 and the bumps 15 The eutectic bonding strength can be increased, so that gang bonding can be properly performed even in the case of multiple pins and a narrow pitch such as 50 μm with 444 pins. That is, according to the present embodiment, an experiment was conducted in which 50 μm inner leads 25 and bumps 15 were collectively thermocompressed with 444 pins and gold-tin eutectic bonding was performed, and then carrier tape 20 was fixed and chip 10 was pulled. As a result, no peeling occurred at the gold-tin eutectic joint between the inner lead 25 and the bump 15, and peeling occurred between the outer lead 26 having a lower bonding (adhesion) strength and the tape body 21. did.
[0037]
According to the embodiment, the following effects can be obtained.
[0038]
1) When a plurality of inner leads are collectively bonded to a plurality of bumps by thermocompression bonding, factors other than a bonding temperature, a bonding load, and a load holding time are factors such as a touch speed of a bonding tool to a bonded portion and an initial load application speed. By controlling the initial load search speed, the load change speed, the second load search speed, the load reduction speed, and the second bonding tool raising speed, the eutectic bonding strength between the inner lead and the bump can be increased. Even in the case of a multi-pin, narrow-pitch COF IC having a pin size of 50 μm, gang bonding can be performed properly.
[0039]
2) By simultaneously gang bonding pads arranged in two rows to inner leads with a bonding tool, even COF ICs having high-density and narrow-pitch pads can be collectively subjected to inner lead bonding. The working time of the inner lead bonding step can be significantly reduced as compared with the case of performing by single point bonding or the case of using both gang bonding and single point bonding.
[0040]
3) Since the carrier tape of the COF / IC does not have a so-called flying inner lead, it is easy to increase the number of pins and narrow the pitch of the inner lead. In addition, it is advantageous in terms of yield from the viewpoint of molding and handling of the inner lead, so that the manufacturing cost of the COF / IC can be reduced.
[0041]
FIG. 7 is a graph showing a bonding load control sequence according to the second embodiment of the present invention.
[0042]
This embodiment is different from the above embodiment in that the initial load search speed 65 and the initial bonding load hold time 67 are not set. In the present embodiment, although the initial bonding load 66 slightly varies in height depending on the mechanism, the advantage that the total bonding time can be reduced can be obtained.
[0043]
FIG. 8 is a graph showing a bonding load control sequence according to the third embodiment of the present invention.
[0044]
This embodiment is different from the above embodiment in that the load change speed 68, the second load search speed 69, and the second bonding load hold time 71 are not set. In the above embodiment, even when the initial load application speed 64, the initial load search speed 65, and the initial bonding load hold time 67 are not set, the same bonding load sequence as that in FIG. According to the present embodiment, although the bonding strength is slightly reduced, bonding with a constant bonding strength can be performed in a short bonding time.
[0045]
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various changes can be made without departing from the gist of the invention. Needless to say.
[0046]
The bump is not limited to being provided on the pad side of the chip, but may be provided on the inner lead side of the carrier tape.
[0047]
The bumps are not limited to so-called stud bumps protruded by a wire bonding method, but may be bumps protruded by a plating method or the like.
[0048]
The COF / IC may be shipped separately or may be shipped in the form of a tape.
[0049]
In the above description, mainly the case where the invention made by the present inventor is applied to a method of manufacturing a COF / IC used for a driver of a liquid crystal display device, which is a background of application, is limited. However, the present invention can be applied to a method of manufacturing a TCP / IC, and is not limited to a method of manufacturing a COF / IC or a TCP / IC used for a driver of a liquid crystal display device. The present invention can be applied to all methods for manufacturing semiconductor devices such as COF ICs, TCP ICs, transistor arrays, and electronic components.
[0050]
【The invention's effect】
The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.
[0051]
Factors other than bonding temperature, bonding load, and load holding time are used as the factors other than bonding temperature, bonding load, and load holding time when multiple inner leads are collectively thermocompressed to multiple bumps. By controlling the change speed, the second load search speed, the load reduction speed, and the release speed, the pressure contact strength between the inner lead and the bump can be increased. However, gang bonding can be performed properly.
[Brief description of the drawings]
FIGS. 1A and 1B show a chip used in a method of manufacturing a COF IC according to an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is an enlarged cross section along line bb of FIG. FIG.
FIGS. 2A and 2B also show a carrier tape, wherein FIG. 2A is a partially omitted plan view, and FIG. 2B is a cross-sectional view taken along line bb of FIG.
FIG. 3 is a front view showing a die bonder used in a method of manufacturing a COF · IC according to an embodiment of the present invention.
FIGS. 4A and 4B are enlarged front views for explaining the operation, wherein FIG. 4A is an alignment step, FIG. 4B is a thermocompression bonding step, FIG. 4C is an ascending step of a second bonding tool, and FIG. Figure 4 shows the lowering step of the bonding tool.
5A and 5B show a state after the inner lead bonding step, in which FIG. 5A is a partially omitted plan view, and FIG. 5B is a cross-sectional view taken along line bb of FIG.
FIG. 6 is a graph showing a control sequence of a bonding load in a bonding step according to an embodiment of the present invention.
FIG. 7 is a graph showing a bonding load control sequence according to the second embodiment of the present invention.
FIG. 8 is a graph showing a control sequence of a bonding load according to a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... chip (semiconductor chip), 11 ... substrate, 12 ... 1st main surface (active area side main surface), 13 ... electrode pad, 14 ... passivation film, 15 ... bump, 20 ... carrier tape, 21 ... tape main body , 22 ... sending hole, 23 ... bonding area, 24 ... outer lead hole, 25 ... inner lead, 26 ... outer lead, 27 ... assembly, 30 ... die bonder (bonding device), 31 ... tape guide, 32 ... bonding station, 33A ... upper clamper, 33B ... lower clamper, 34 ... heat block, 35 ... first bonding tool, 36 ... heat insulating block, 37 ... Z table, 38 ... table, 39 ... X table, 40 ... Y table, 41 ... upper Y Table, 42: Upper X table, 43: Bracket, 44: Load applying device, 5: load cell, 46: tool flatness Θy adjustment unit, 47: Θx adjustment unit, 48: Θ adjustment unit, 49: heat insulation unit, 50: holding unit, 51: second bonding tool, 61: detected load at touch speed Straight line, 62: Landing detection load, 63: Impact waveform, 64: Initial load application speed, 65: Initial load search speed, 66: Initial bonding load, 67: Initial bonding load hold time, 68: Load change speed, 69: No. Two load search speed, 70: second bonding load, 71: second bonding load hold time, 72: bonding load hold total time, 73: load reduction speed, 74: speed switching load, 75: second bonding tool lifting speed ( Release speed).

Claims (5)

A method of manufacturing a semiconductor device, comprising: a bonding step in which a plurality of electrode pads of a semiconductor chip are thermocompression-bonded collectively to a plurality of inner leads laid on a carrier by a bonding tool,
A method of manufacturing a semiconductor device, wherein a touch speed, an initial load application speed, a load reduction speed, and a release speed of a bonding tool are controlled as factors other than a bonding temperature, a bonding load, and a load holding time. A method of manufacturing a semiconductor device, comprising: a bonding step in which a plurality of electrode pads of a semiconductor chip are thermocompression-bonded collectively to a plurality of inner leads laid on a carrier by a bonding tool,
A method of manufacturing a semiconductor device, wherein a touch speed, a load reduction speed, and a release speed of a bonding tool are controlled as factors other than a bonding temperature, a bonding load, and a load holding time. A method of manufacturing a semiconductor device, comprising: a bonding step in which a plurality of electrode pads of a semiconductor chip are thermocompression-bonded collectively to a plurality of inner leads laid on a carrier by a bonding tool,
As a factor other than the bonding temperature, the bonding load, and the load holding time, the touch speed, initial load application speed, load change speed, second load search speed, load reduction speed, and release speed of the bonding tool are controlled. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device, comprising: a bonding step in which a plurality of electrode pads of a semiconductor chip are thermocompression-bonded collectively to a plurality of inner leads laid on a carrier by a bonding tool,
Factors other than the bonding temperature, bonding load, and load hold time are controlled by the touch speed, initial load application speed, initial load search speed, load change speed, second load search speed, load reduction speed, and release speed of the bonding tool. A method for manufacturing a semiconductor device, comprising: The method according to claim 1, 2, 3, or 4, wherein the semiconductor device is a COF IC.

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