JP2004247647A - Photo-diode and image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of preventing an excess leakage current in the p-n junction section of a photo-diode. <P>SOLUTION: p-Wells 3 and the photo-diode D<SB>1</SB>separated from element isolation sections 2 formed to the main surface of a semiconductor substrate 1 and composed of an n<SP>+</SP>-type region 4a surrounded by the p-wells 3 are formed to an active region surrounded by the element isolation sections 2. A peripheral electrode 7a composed of a silicon polycrystalline film formed on the active region from the peripheral section of the region 4a to the element isolation section 2 through a silicon oxide film 6a is arranged at a specified distance from the region 4a, and a voltage higher than the voltage applied to the region 4a is applied to the peripheral electrode 7a. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a photodiode, and more particularly, to a technique effective when applied to a photodiode provided in a CMOS image sensor.
[0002]
[Prior art]
At present, an image sensor (solid-state imaging device) is used as an imaging device for converting an image into an electric signal instead of an imaging tube or a photomultiplier tube. The image sensor has a large number of two-dimensionally arranged photoelectric conversion elements such as photodiodes, sequentially scans or transfers signal charges obtained by each photoelectric conversion element to an output terminal, and reads out signal charges therefrom. . As an image sensor, various types of fields such as MOS (Metal Oxide Semiconductor), CCD (Charge Coupled Device), CPD (Charge Priming Device), and CSD (Charge Sweep Device) have been developed, and various types of fields requiring high speed have been developed. In this case, a CMOS (Complementary MOS) type has become mainstream.
[0003]
Although there are several types of CMOS image sensors, in general, a pixel of a light receiving section is formed by a combination of one photodiode and one field effect transistor (hereinafter, referred to as a MISFET). . Each pixel is arranged in an array and connected to a vertical and horizontal shift register.Light incident on each pixel is photoelectrically converted by a photodiode, and each pixel is sequentially scanned by a vertical and horizontal shift register. The signals of all the pixels are read out to the output terminals (for example, see Non-Patent Documents 1 and 2).
[0004]
Note that, in the pixel including the light receiving section area and the switch section area, the light receiving section area and the switch section area are arranged so as to be adjacent to each other, and the light receiving section area of each pixel is a pixel of the adjacent pixel in a predetermined one-dimensional direction. A configuration in which the light-receiving portion is arranged adjacent to the light-receiving portion region is disclosed (for example, see Patent Document 1).
[0005]
Further, the depth of the n-type region from the substrate surface of the photoelectric conversion unit such as a photodiode is formed to be deeper than the depth of the element isolation insulating layer from the substrate surface of the photoelectric conversion unit, so that a reproduced image due to leak current is remarkable. A method for preventing deterioration is disclosed (for example, see Patent Document 2).
[0006]
[Non-patent document 1]
Hiroo Takemura, "Introduction to CCD Camera Technology," Corona Publishing, December 15, 1997, pp. 37-41.
[0007]
[Non-patent document 2]
Kevin Ng, "Technology Review of Charge-Coupled Devices and CMOS Based Electronic Images", November 21, 2001, [Search October 10, 2002], Internet <URL: http: // www. eecg. toronto. edu / @ kpang / ece1352f / papers / ng_CCD. pdf>
[0008]
[Patent Document 1]
JP-A-10-326341
[0009]
[Patent Document 2]
JP-A-10-308507
[0010]
[Problems to be solved by the invention]
One pixel of the light receiving section of the CMOS image sensor is, for example, n ⁺ -Consists of a p-junction photodiode and an n-channel MISFET. N obtained by introducing an n-type impurity into a substrate ⁺ The n-type region and the p-type region into which the p-type impurity is introduced ⁺ -P junction photodiode is formed, but n ⁺ The type region is n which constitutes the source / drain of the n-channel MISFET. ⁺ The p-type region is formed in the same step as the p-well, and the p-type region is formed in the same step as the p-well. Further, adjacent photodiodes are electrically isolated by an element isolation portion.
[0011]
By the way, when a reverse bias is applied to the photodiode, a minute current, that is, a so-called leak current flows. If the leakage current flows though it is very small, problems such as an increase in the noise level of the image, an increase in the standby current and an increase in power consumption occur. For this reason, reduction of leakage current is an important issue for photodiodes.
[0012]
However, the present inventor studied that the photodiode n ⁺ It has been found that when the interface between the mold region and the p-type region (hereinafter referred to as a pn junction interface) directly contacts the element isolation portion or the insulating film formed on the surface of the substrate, the leak current increases.
[0013]
FIG. 17 shows a photodiode studied by the present inventors. FIG. 17A shows a photodiode D having a pn junction interface in contact with an element isolation portion. ₄ FIG. 2B shows a photodiode D in which the pn junction interface is in contact with the insulating film formed on the surface of the semiconductor substrate. ₅ FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, showing the structure of FIG.
[0014]
An active region surrounded by an element isolation portion 52 made of an insulating film is formed on a main surface of a semiconductor substrate 51 made of silicon single crystal, and a p well 53 doped with a p-type impurity is formed in this active region. ing. p well 53 is p ⁺ Connected to ground potential GND via mold region 54. Furthermore, n surrounded by p well 53 and having n-type impurities introduced therein ⁺ A mold region 55 is formed. ⁺ Photodiode D with the mold region 55 ₄ , D ₅ Of the pn junction. Also, the photodiode D ₄ , D ₅ An insulating film 56 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 51 on which is formed.
[0015]
Hereinafter, a leakage current in a low electric field will be considered. Photodiode D ₄ , D ₅ Bottom part L of pn junction interface ₁ In this case, it is considered that the generated current generated in the depletion layer 57 by the reverse bias Vr becomes the leak current. On the other hand, the peripheral portion L of the pn junction interface in contact with the insulating film or the insulating film 56 constituting the element isolation portion 52 ₂ Then, the current generated in the depletion layer 57 due to the reverse bias Vr is added to the current flowing at the interface (FIG. 17A) between the semiconductor substrate 51 and the insulating film constituting the element isolation portion 52, or the semiconductor substrate 51 and the insulating film. It is considered that the current obtained by adding the current flowing to the interface with the interface 56 (FIG. 17B) becomes the leak current. This is due to the fact that the silicon bond of the silicon single crystal constituting the semiconductor substrate 51 is broken at the interface, and the generation and recombination of electron-hole pairs occur due to the interface state. Furthermore, peripheral part L ₂ In this case, since the pn junction interface is in contact with the insulating film or the insulating film 56 forming the element isolation portion 52, the electric field locally increases, and the bottom portion L ₁ There is a possibility that the generated current will be larger than that.
[0016]
An object of the present invention is to provide a technique capable of preventing an excessive leakage current at a pn junction of a photodiode.
[0017]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0018]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0019]
According to the present invention, a p-well is formed in an active region surrounded by an element isolation portion formed on a main surface of a semiconductor substrate, and an n-region separated from the element isolation portion and surrounded by the p-well is formed. ⁺ Type region and n ⁺ And a peripheral electrode made of a conductive material provided on the active region between the peripheral portion of the mold region and the element isolation portion with an insulating film interposed therebetween. And the surrounding electrode and n ⁺ Is arranged at a predetermined distance from the mold region, and n ⁺ A voltage higher than the voltage applied to the mold region is applied to the surrounding electrodes.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0021]
(Embodiment 1)
FIG. 1 is an equivalent circuit of a photodiode cell in which a photodiode and a MISFET constituting a light receiving unit of the image sensor according to the first embodiment are combined.
[0022]
Each photodiode cell that constitutes the light receiving portion of the image sensor has a photodiode D ₁ And the photodiode D ₁ And a MISFET Qn functioning as a switch when transmitting the signal charge stored in the step S1 to the outside of the photodiode cell. Each photodiode cell is switched by a pulse applied to the gate of the MISFET Qn via a pixel selection line, and the photodiode D ₁ Is taken out to the output via the data line. When light enters each photodiode cell, the photodiode D ₁ The signal charge corresponding to the intensity of light is accumulated with time.
[0023]
FIG. 2 is a plan layout diagram of the photodiode cell according to the first embodiment, and FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate showing the photodiode cell of FIG.
[0024]
An active region surrounded by an element isolation portion 2 is formed on a main surface of a semiconductor substrate 1 made of a p-type silicon single crystal, and a p-well 3 into which a p-type impurity, for example, boron is introduced, is formed in the active region. Is formed. An n-type impurity such as phosphorus or arsenic is introduced on the surface of the semiconductor substrate 1. ⁺ A mold region 4a is formed, and the p well 3 and n ⁺ Photodiode D with the mold region 4a ₁ Of the pn junction. The p well 3 has a relatively high impurity concentration formed in another active region. ⁺ Connected to ground potential via mold region 5. And n ⁺ The mold region 4 a is formed at a distance of, for example, about 0.5 to 2.0 μm from the element isolation part 2.
[0025]
On the surface of the semiconductor substrate 1, a pair of n-type regions 4b forming the source / drain of the MISFET Qn into which n-type impurities are introduced are formed, and a part of the n-type region 4b is a photodiode D ₁ N ⁺ It is formed integrally with the mold region 4a.
[0026]
Although not shown, a threshold voltage control layer is formed between the pair of n-type regions 4b constituting the source / drain of the MISFET Qn. On this threshold voltage control layer, a gate insulating film 6 made of a silicon oxide film 6a is formed. Further, a gate electrode 7 made of a polycrystalline silicon film is formed on the gate insulating film 6, and a sidewall spacer 8 is formed on a side wall of the gate electrode 7. This gate electrode 7 functions as a pixel selection line. The gate electrode 7 may be formed of a laminated film in which a silicon polycrystalline film and a silicide film are sequentially deposited from a lower layer, or a laminated film in which a silicon polycrystalline film and a metal film are sequentially deposited from a lower layer.
[0027]
Also, the photodiode D ₁ Is formed on the element isolation portion 2 above the periphery of the active region where the gate electrode 7 of the MISFET Qn is formed of a conductive film in the same layer as the gate electrode 7 (hereinafter, referred to as a peripheral electrode) 7a. ⁺ It is provided at a predetermined distance from the mold region 4a. A silicon oxide film 6a of the same layer as the gate insulating film 6 of the MISFET Qn is formed in the active region below the peripheral electrode 7a, and a side wall of the peripheral electrode 7a is formed of an insulating film of the same layer as the sidewall spacer 8 of the MISFET Qn. Is formed. The peripheral electrode 7a is not formed all around the active region and is cut off near the MISFET Qn in order not to short-circuit the gate electrode 7 of the MISFET Qn.
[0028]
An insulating film 9 made of, for example, a silicon oxide film is formed on the gate electrode 7 of the MISFET Qn. A contact hole 10 is formed in the insulating film 9 to reach a required portion such as the n-type region 4b of the MISFET Qn. A plug 11 is formed by embedding a barrier film, for example, a titanium nitride film and a metal film, for example, a tungsten film, inside the contact hole 10, and through this plug 11, the wiring 12 is connected to the n-type region 4 b of the MISFET Qn or the like. Connected to the necessary parts.
[0029]
Next, a leakage current in the photodiode of the first embodiment will be described with reference to a schematic cross-sectional view in which the MISFET shown in FIG. 4 is omitted and only the photodiode is taken out.
[0030]
Photodiode D ₁ N ⁺ -P junction n ⁺ When applying the reverse bias Vr to the mold region 4a, a voltage Vg higher than the reverse bias Vr is applied to the peripheral electrode 7a. For example, assume that the reverse bias Vr is 1 V and the voltage Vg is 2 V. p ⁺ Although it depends on the impurity concentration of the mold region 5 and the work function of the peripheral electrode 7a, if the threshold voltage of the MISFET Qn is about 1 V, an n-layer 13 as an inversion layer is formed in the p well 3 immediately below the peripheral electrode 7a. . Since the n-layer 13 is isolated, n ⁺ No current flows from mold region 4a to n-layer 13.
[0031]
Further, n ⁺ The distance between the mold region 4a and the n-layer 13 is determined by the size of the side wall spacer 8a. ⁺ When a reverse bias of 1 V is applied to the mold region 4a, n ⁺ A depletion layer 14 is formed between mold region 4a and n-layer 13 (part A). The width of the depletion layer 14 in the horizontal direction is equal to the photodiode D shown in FIG. ₅ N ⁺ The width is smaller than the width of the depletion layer 57 formed around the mold region 55. And n ⁺ The depletion layer 14 generated in the peripheral portion (part B) of the mold region 4a is formed under the n-layer 13, so that the depletion layer 14 is hardly affected by the reverse bias Vr. (N ⁺ It becomes narrower than the width of the depletion layer at the bottom of the mold region 4a.
[0032]
The probability of generation of a generation current or generation and recombination of electron-hole pairs on the surface of the semiconductor substrate decreases in proportion to the width of the depletion layer. ₁ The leakage current at the peripheral portion of the pn junction interface is caused by the photodiode without the peripheral electrode 7a, for example, the photodiode D shown in FIG. ₅ Is smaller than the leakage current at the periphery of the pn junction junction interface. Thereby, the photodiode D ₁ Can be made smaller than the leak current in the entire pn junction of the photodiode without the peripheral electrode 7a.
[0033]
FIG. 5 shows a leakage current at the pn junction of the photodiode according to the first embodiment. The horizontal axis is n ⁺ The reverse bias Vr applied to the mold region and the vertical axis is the leak current Ir. The voltage Vg applied to the surrounding electrodes was used as a parameter.
[0034]
When the reverse bias Vr is about 1.2 V or less, the leak current when the voltage Vg is 2 V is about one digit smaller than the leak current when the voltage Vg is 0 V. Note that when the reverse bias Vr is larger than 1.2 V, the inversion layer disappears, so that the leak current Ir sharply increases even when the voltage Vg is applied. Since the transition voltage changes depending on the voltage Vg, the voltage Vg may be 2 V if the voltage applied when the photodiode is used is 1 V or less, and 3 V if the voltage applied is 2 V or less.
[0035]
Next, an example of a method for manufacturing a photodiode cell forming a light receiving portion of the image sensor according to the first embodiment will be described in the order of steps with reference to the cross-sectional views of main parts of the semiconductor substrate shown in FIGS.
[0036]
First, as shown in FIG. 6, a semiconductor substrate (semiconductor wafer processed into a circular thin plate) 1 made of, for example, a p-type silicon single crystal is prepared. Next, the semiconductor substrate 1 is thermally oxidized to form a thin silicon oxide film having a thickness of about 0.01 μm on the surface thereof, and then, a nitride film having a thickness of about 0.1 μm is formed thereon by a CVD (Chemical Vapor Deposition) method. A silicon film is deposited. Thereafter, the silicon nitride film, the silicon oxide film, and the semiconductor substrate 1 are sequentially etched using the resist pattern as a mask, thereby forming an element isolation groove 2a having a depth of about 0.35 μm in the semiconductor substrate 1 in the element isolation region.
[0037]
Next, a silicon oxide film 2b is deposited on the semiconductor substrate 1. Subsequently, the semiconductor substrate 1 is heat-treated at about 1000 ° C., and the silicon oxide film 2b buried in the element isolation trench 2a is hardened. Next, the silicon oxide film 2b is polished by etch-back or CMP (Chemical Mechanical Polishing) to leave the silicon oxide film 2b inside the isolation trench 2a. After that, the element isolation portion 2 is formed by removing the silicon nitride film by wet etching using hot phosphoric acid.
[0038]
Before depositing the silicon oxide film 2b on the semiconductor substrate 1, a step of forming a silicon oxide film by a thermal oxidation method is added to further clean the interface between the semiconductor substrate 1 and the silicon oxide film 2b. Good. Further, the LOCOS (Local Oxidation of Silicon) method may be used for forming the element isolation portion 2.
[0039]
Next, impurities are ion-implanted into the semiconductor substrate 1 to form a p-well 3. A p-type impurity, for example, boron is ion-implanted into the p-well 3. Implantation conditions for ion implantation of boron as a p-type impurity include an energy of 100 to 200 keV and a dose of 5 × 10 5 ¹² cm ^-2 Can be exemplified. Thereafter, an impurity for controlling the threshold value of the MISFET Qn may be ion-implanted into the p-well 3. Next, a silicon oxide film 6a having a thickness of about 10 nm to be a gate insulating film 6 in the MISFET Qn formation region is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method or a CVD method.
[0040]
Next, as shown in FIG. 7, after a silicon polycrystalline film having a thickness of about 200 nm into which an n-type impurity, for example, phosphorus is introduced, is deposited on the semiconductor substrate 1 by a CVD method, the silicon polycrystalline film is formed using the resist pattern as a mask. The film is etched to form a gate electrode 7 and a peripheral electrode 7a made of a polycrystalline silicon film. Thereafter, the semiconductor substrate 1 is subjected to, for example, a dry oxidation process at about 900 ° C.
[0041]
Next, a region where ion implantation is to be avoided is defined by a resist pattern RP. ₁ And an n-type impurity such as phosphorus or arsenic is ion-implanted into the semiconductor substrate 1 using the mask as a mask to form an n-type extension (extension) region 4b constituting a source / drain. ₁ To form Implantation conditions for ion implantation of phosphorus as an n-type impurity include an energy of 50 keV and a dose of 2 × 10 4. ^Thirteen cm ^-2 Can be exemplified. The region where the ion implantation is to be avoided is defined as a region that slightly overlaps the peripheral electrode 7a (a region in which the margin is added to the length of the sidewall spacer 8a to be formed later) and the p serving as the power supply portion of the p-well 3. ⁺ Mold region 5 and the like.
[0042]
Next, as shown in FIG. ₁ Is removed, a silicon oxide film having a thickness of about 150 nm is deposited on the semiconductor substrate 1. Subsequently, the silicon oxide film is anisotropically etched by, for example, RIE (Reactive Ion Etching) to form a sidewall spacer 8 on the side wall of the gate electrode 7 and a side wall spacer 8a on the side wall of the peripheral electrode 7a. Thereafter, a silicon oxide film (not shown) having a thickness of about 10 nm is formed by a thermal oxidation method or a CVD method.
[0043]
Next, a region where ion implantation is to be avoided is defined by a resist pattern RP. ₂ And n-type impurities, for example, phosphorus or arsenic are ion-implanted into the semiconductor substrate 1 using the mask as a mask. ₁ N ⁺ Region 4a and n-type diffusion region 4b forming the source / drain of MISFET Qn ₂ To form The region where the ion implantation is to be avoided is defined as p serving as a power supply portion of the p well 3. ⁺ Mold region 5 and the like. Implantation conditions for ion implantation of arsenic as an n-type impurity include an energy of 80 keV and a dose of 2 × 10 4. ^Fifteen cm ^-2 Can be exemplified. Thereby, the n-type extension region 4b ₁ And n-type diffusion region 4b ₂ Thus, an n-type region 4b constituting the source / drain of the MISFET Qn is formed. In this case, the n-type extension region 4b ₁ Impurity concentration of the n-type diffusion region 4b ₂ The source / drain having an LDD (Lightly Doped Drain) structure capable of relaxing the electric field at the end of the gate electrode 7 is formed by relatively increasing the impurity concentration of the gate electrode 7.
[0044]
Next, as shown in FIG. ₃ Is implanted into the semiconductor substrate 1 with a p-type impurity, for example, boron. ⁺ The mold region 5 is formed. After that, resist pattern RP ₃ Is removed, the semiconductor substrate 1 is subjected to a heat treatment at 900 to 1000 ° C. for about 10 seconds, for example, in a nitrogen atmosphere.
[0045]
Next, as shown in FIG. 10, after an insulating film 9 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1, the surface of the insulating film 9 is flattened by polishing the insulating film 9 by, for example, a CMP method. . Subsequently, a contact hole 10 is formed in the insulating film 9 by etching using the resist pattern as a mask. The contact hole 10 is formed in a necessary portion such as on the n-type region 4b constituting the source / drain of the MISFET Qn.
[0046]
Further, a titanium nitride film is formed on the entire surface of the semiconductor substrate 1 including the inside of the contact hole 10 by, for example, a CVD method, and a tungsten film for filling the contact hole 10 is formed by, for example, a CVD method. Then, the plug 11 is formed inside the contact hole 10 by removing the titanium nitride film and the tungsten film in the region other than the contact hole 10 by, for example, the CMP method.
[0047]
Next, after forming, for example, an aluminum alloy film on the semiconductor substrate 1, the aluminum alloy film is processed by etching using a resist pattern as a mask to form the wiring 12 shown in FIG. The aluminum alloy film can be formed by, for example, a sputtering method. Thereafter, by covering the entire surface of the semiconductor substrate 1 with a passivation film, the photodiode D ₁ And a MISFET Qn are almost completed.
[0048]
As described above, according to the first embodiment, the photodiode D ₁ Of the depletion layer in the peripheral portion of the pn junction interface can be suppressed, so that the generation probability of the generation current or the generation and recombination probability of the electron-hole pair on the surface of the semiconductor substrate 1 decreases, and the photodiode D ₁ Leakage current at the pn junction can be reduced.
[0049]
(Embodiment 2)
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate showing a photodiode cell according to the second embodiment.
[0050]
Photodiode D shown in Embodiment 1 ₁ Similarly, the p-type well 3 and the n-type well 3 ⁺ N composed of the mold region 4a ⁺ -P junction photodiode D ₂ Are formed, and the p well 3 has p ⁺ Connected to ground potential via mold region 5. However, the photodiode D ₂ Is formed on the active region where n is formed. ⁺ Surrounding the mold region 4a, there is provided a peripheral electrode 7a made of a conductor film of the same layer as the gate electrode 7 of the MISFET Qn. And n ⁺ The mold region 4a is formed inside the surrounding of the peripheral electrode 7b and on the surface of the p-well 3 in a self-aligned manner with respect to the side wall spacer 8a. It is not formed in the p well 3 between the portion 2.
[0051]
FIG. 12 is an example of a plan layout diagram of the photodiode cell according to the second embodiment. FIG. 12A shows a first photodiode cell, and FIG. 12B shows a second photodiode cell.
[0052]
In the first photodiode cell shown in FIG. ₂ Is provided only on the active region away from the end of the element isolation portion 2 and n ⁺ It surrounds the periphery of the mold region 4a. The peripheral electrode 7a is not closed, but is cut off near the MISFET Qn formation region. This is because the n-type region 4b constituting the source / drain of the MISFET Qn and the photodiode D ₂ N ⁺ This is for connecting the mold region 4a. The pn junction interface is near the location where the peripheral electrode 7a has been cut (opened).
[0053]
In the second photodiode cell shown in FIG. 12B, the peripheral electrode 7a has an opening near the MISFET Qn formation region in the same manner as in the first photodiode cell. Riding up. The boundary of the pn junction interface is defined by the surrounding electrode 7a.
[0054]
Next, a leakage current in the photodiode according to the second embodiment will be described with reference to a schematic sectional view shown in FIG.
[0055]
Photodiode D ₂ N ⁺ -P junction n ⁺ The conditions of the reverse bias Vr applied to the mold region 4a and the voltage Vg applied to the peripheral electrode 7a are the same as in the first embodiment. For example, when the reverse bias Vr is 1 V and the voltage Vg is 2 V, an n-layer 13 as an inversion layer is formed in the p-well 3 immediately below the peripheral electrode 7a. And n ⁺ Bottom part of mold region 4a, n ⁺ Between the mold region 4a and the n-layer 13 (part A), below the n-layer 13 (part B) and n ⁺ A depletion layer 14 is formed on the side surface (part C) of n layer 13 opposite to mold region 4a. The depletion layer 14 generated in the portions B and C is hardly affected by the reverse bias Vr, and has a width equal to the width of the depletion layer (n) due to the electric field of the reverse bias Vr. ⁺ It becomes narrower than the width of the depletion layer at the bottom of the mold region 4a.
[0056]
The photodiode D shown in FIG. ₂ Although some resist patterns are different, the photodiodes D shown in FIGS. ₁ Can be formed in substantially the same steps as in the method of manufacturing.
[0057]
As described above, according to the second embodiment, similarly to the first embodiment, the photodiode D ₂ Of the depletion layer 14 in the peripheral portion of the pn junction interface of the photodiode D ₂ Leakage current at the pn junction can be reduced. Also, the photodiode D ₂ N ⁺ The distance from the mold region 4a to the point where the end of the depletion layer 14 is in contact with the insulating film (point C in FIG. 13) is equal to the photodiode D described in the first embodiment. ₂ N ⁺ Since the distance from the mold region 4a to the point where the end of the depletion layer 14 contacts the insulating film (point B in FIG. 3) is longer, the photodiode D ₂ Then, photodiode D ₁ The electric field at the end of the depletion layer 14 in contact with the insulating film is weakened, and the surface leakage current can be reduced.
[0058]
(Embodiment 3)
FIG. 14 is a cross-sectional view of a main part of a semiconductor substrate showing a photodiode cell according to the third embodiment.
[0059]
Photodiode D shown in Embodiment 2 ₂ Similarly, the p-type well 3 and the n-type well 3 ⁺ N composed of the mold region 4a ⁺ -P junction photodiode D ₃ Are formed, and the photodiode D ₃ Is formed on the active region where n is formed. ⁺ Surrounding the mold region 4a, there is provided a peripheral electrode 7a made of a conductor film of the same layer as the gate electrode 7 of the MISFET Qn. However, the photodiode D ₃ Then, the n-well is formed in the p-well 3 outside the peripheral electrode 7a, that is, ⁺ The mold region 4c is formed. This n ⁺ The mold region 4c is formed on the inside of the peripheral electrode 7a. ⁺ It is electrically separated from the mold region 4a, and is floated without being connected to the wiring, or is connected to the wiring to be at the ground potential.
[0060]
FIG. 15 is an example of a plan layout diagram of the photodiode cell according to the third embodiment. FIG. 15A shows a first photodiode cell, and FIG. 15B shows a second photodiode cell.
[0061]
As shown in FIG. 15, the n-well is located outside the peripheral electrode 7 a, that is, in the p-well 3 between the peripheral electrode 7 a and the element isolation portion 2. ⁺ Except for forming the mold region 4c, it is the same as the plan layout diagram of the photodiode cell shown in the second embodiment. In the first photodiode cell shown in FIG. 15A, the pn junction interface is near the location where the peripheral electrode 7a has been cut (opened).
[0062]
Next, a leakage current in the photodiode of Embodiment 3 will be described with reference to a schematic cross-sectional view of the photodiode illustrated in FIG.
[0063]
Photodiode D ₃ N ⁺ -P junction n ⁺ The conditions of the reverse bias Vr applied to the mold region 4a and the voltage Vg applied to the peripheral electrode 7a are the same as in the first embodiment. For example, if the reverse bias Vr is 1 V and the voltage Vg is 2 V, an n-layer 13 as an inversion layer is formed in the p-well 3 immediately below the peripheral electrode 7a. And n ⁺ Bottom part of mold region 4a, n ⁺ Between the mold region 4a and the n-layer 13 (part A), below the n-layer 13 (part B), n ⁺ Side surface (part C) of n layer 13 opposite to mold region 4a and n ⁺ A depletion layer 14 is formed below (D portion) the mold region 4c. The depletion layer 14 generated in the B, C, and D portions is hardly affected by the reverse bias Vr, and has a width equal to the depletion layer (n) due to the electric field of the reverse bias Vr. ⁺ It becomes narrower than the width of the depletion layer at the bottom of the mold region 4a.
[0064]
The photodiode D shown in FIG. ₃ Although some resist patterns are different, the photodiodes D shown in FIGS. ₁ Can be formed in substantially the same steps as in the method of manufacturing.
[0065]
Thus, according to the third embodiment, as in the first embodiment, the photodiode D ₃ Of the depletion layer 14 in the peripheral portion of the pn junction interface of the photodiode D ₃ Leakage current at the pn junction can be reduced. Also, the photodiode D ₃ N ⁺ The distance from the mold region 4a to the point where the end of the depletion layer 14 contacts the insulating film (point D in FIG. 16) is the photodiode D described in the first embodiment. ₁ N ⁺ Since the distance from the mold region 4a to the point where the end of the depletion layer 14 contacts the insulating film (point B in FIG. 3) is longer, the photodiode D ₃ Then, photodiode D ₁ The electric field at the end of the depletion layer 14 in contact with the insulating film is weakened, and the surface leakage current can be reduced.
[0066]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say, there is.
[0067]
For example, in the above-described embodiment, a case where the present invention is applied to a CMOS image sensor has been described. However, the present invention can be applied to other imaging devices, for example, pixels of a CCD.
[0068]
In the above embodiment, the photodiode is n ⁺ -P junction, but the opposite conductivity type, ie, p ⁺ A -n junction may be used. In this case, the p-type and the n-type are reversed, but the same effect as in the above embodiment can be obtained.
[0069]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0070]
Photodiode n ⁺ N forming a p-junction ⁺ By reducing the width of the depletion layer at the periphery of the mold region and reducing the leakage current at the periphery of the pn junction interface, the leakage current at the pn junction can be reduced. Further, since the noise level can be reduced by reducing the leak current, a clear image can be obtained.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a photodiode cell in which a photodiode and a MISFET constituting a light receiving unit of the image sensor according to the first embodiment are combined.
FIG. 2 is a plan layout diagram of the photodiode cell according to the first embodiment.
FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate showing the photodiode cell according to the first embodiment;
FIG. 4 is a schematic cross-sectional view showing a photodiode for describing a leak current of the photodiode according to the first embodiment.
FIG. 5 is a graph showing a leakage current at a pn junction of the photodiode according to the first embodiment.
FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a photodiode cell according to Embodiment 1;
FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a photodiode cell according to Embodiment 1;
8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a photodiode cell according to Embodiment 1; FIG.
FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a photodiode cell according to Embodiment 1;
10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a photodiode cell according to Embodiment 1; FIG.
FIG. 11 is a sectional view of a principal part of a semiconductor substrate showing a photodiode cell according to the second embodiment;
FIG. 12 is an example of a plan layout diagram of a photodiode cell according to the second embodiment. FIG. 1A is a plan layout diagram of a first photodiode cell, and FIG. 2B is a plan layout diagram of a second photodiode cell.
FIG. 13 is a schematic cross-sectional view showing a photodiode for describing a leak current of the photodiode according to the second embodiment.
FIG. 14 is a sectional view of a principal part of a semiconductor substrate showing a photodiode cell according to the third embodiment;
FIG. 15 is an example of a plan layout diagram of a photodiode cell according to the third embodiment. FIG. 1A is a plan layout diagram of a first photodiode cell, and FIG. 2B is a plan layout diagram of a second photodiode cell.
FIG. 16 is a schematic cross-sectional view showing a photodiode for describing a leak current of the photodiode according to the third embodiment.
FIGS. 17A and 17B are cross-sectional views of main parts of a semiconductor substrate showing a photodiode studied by the present inventors.
[Explanation of symbols]
1 semiconductor substrate
2 Element separation unit
2a Element isolation groove
2b Silicon oxide film
3 p-well
4an ⁺ Type area
4b n-type region
4b ₁ n-type extension region
4b ₂ n-type diffusion region
4c n ⁺ Type area
5 p ⁺ Type area
6 Gate insulating film
6a Silicon oxide film
7 Gate electrode
7a Surrounding electrode
8 Side wall spacer
8a sidewall spacer
9 Insulating film
10 Contact hole
11 plug
12 Wiring
13 n layers
14 Depletion layer
51 Semiconductor substrate
52 Element separation unit
53 p-well
54 p ⁺ Type area
55 n ⁺ Type area
56 Insulating film
57 Depletion layer
D ₁ Photodiode
D ₂ Photodiode
D ₃ Photodiode
D ₄ Photodiode
D ₅ Photodiode
Qn MISFET
L ₁ Bottom
L ₂ Peripheral part
Vr reverse bias
Vg voltage
GND Ground potential
RP ₁ Resist pattern
RP ₂ Resist pattern
RP ₃ Resist pattern

Claims (5)

An active region surrounded by an isolation portion formed on a main surface of the substrate, a first region of a first conductivity type, and a first conductivity type separated from the isolation portion and surrounded by the first region; A second region of a second conductivity type different from the first region, and a peripheral electrode made of a conductive material provided on the active region between the peripheral portion of the second region and the element isolation portion via an insulating film. Has,
A part of the peripheral electrode rises on the element isolation portion, the peripheral electrode and the second region are arranged at a predetermined distance, and a voltage higher than a voltage applied to the second region is applied to the peripheral region. A photodiode which is applied to an electrode. An active region surrounded by an isolation portion formed on a main surface of the substrate, a first region of a first conductivity type, and a first conductivity type separated from the isolation portion and surrounded by the first region; A second region of a second conductivity type different from the first region, and a peripheral electrode made of a conductive material provided on the active region between the peripheral portion of the second region and the element isolation portion via an insulating film. Has,
The peripheral electrode and the second region, and the peripheral electrode and the element isolation portion are respectively arranged at predetermined distances, and a voltage higher than a voltage applied to the second region is applied to the peripheral electrode. A photodiode characterized by the above-mentioned. An active region surrounded by an isolation portion formed on a main surface of the substrate, a first region of a first conductivity type, and a first conductivity type separated from the isolation portion and surrounded by the first region; A second region of a second conductivity type different from the first region, and a peripheral electrode made of a conductive material provided on the active region between the peripheral portion of the second region and the element isolation portion via an insulating film. Has,
The peripheral electrode and the second region, and the peripheral electrode and the element isolation portion are arranged at a predetermined distance from each other, and the active region between the peripheral electrode and the element isolation portion is provided with the second conductive layer. A photodiode, wherein a third region of a mold is formed, and a voltage higher than a voltage applied to the second region is applied to the peripheral electrode. An active region surrounded by an isolation portion formed on a main surface of the substrate, a first region of a first conductivity type, and a first conductivity type separated from the isolation portion and surrounded by the first region; A second region of a second conductivity type different from the first region, and a peripheral electrode made of a conductive material provided on the active region between the peripheral portion of the second region and the element isolation portion via an insulating film. A part of the peripheral electrode is mounted on the element isolation portion, the peripheral electrode and the second region are arranged at a predetermined distance, and is higher than a voltage applied to the second region. A photodiode, wherein a voltage is applied to the surrounding electrodes;
An image sensor, characterized in that one of the second regions of the second conductivity type constituting a source / drain includes a field effect transistor connected to the second region of the photodiode. An active region surrounded by an isolation portion formed on a main surface of the substrate, a first region of a first conductivity type, and a first conductivity type separated from the isolation portion and surrounded by the first region; A second region of a second conductivity type different from the first region, and a peripheral electrode made of a conductive material provided on the active region between the peripheral portion of the second region and the element isolation portion via an insulating film. A part of the peripheral electrode is mounted on the element isolation portion, the peripheral electrode and the second region are arranged at a predetermined distance, and is higher than a voltage applied to the second region. A photodiode, wherein a voltage is applied to the surrounding electrodes;
An image sensor comprising: a field-effect transistor in which one of the second regions of the second conductivity type forming a source / drain is connected to the second region of the photodiode;
An image sensor, wherein a conductive material forming the peripheral electrode and a conductive material forming a gate electrode of the field effect transistor are in the same layer.

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