JP2004247450A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the deterioration of characteristics due to an electric field, in a semiconductor device such as an MESFET, a PHEMT or the like. <P>SOLUTION: The semiconductor device is provided with a channel layer 7 formed on a semiconductor substrate 10, Schottky layers 5a, 5b formed on the channel layer, a gate electrode 1 provided on the Schottky layers, and a source electrode 2 as well as a drain electrode 3 provided at two places apart from each other into the opposite directions from the gate electrode respectively through n<SP>+</SP>-layers 4. A first layer 12 having a band gap narrower than the Schottky layers, and a second layer 11 provided on the first layer and having a band discontinuation with respect to the Schottky layers, are inserted into the Schottky layers. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device such as a MESFET and a PHEMT.
[0002]
[Prior art]
As a high-frequency transistor in a microwave band to a millimeter-wave band, a schottky gate field effect transistor (MESFET) using GaAs or InP, a strained high electron mobility transistor (MESFET), and the like. Are used. It is known that these devices cause element degradation due to an electric field when operated in a high-output RF (radio frequency) output (for example, see Non-Patent Documents 1 and 2). In particular, high-frequency transistors are required to have high-frequency characteristics, and therefore are designed to have small device dimensions such as gate length and channel depth. When such an element is operated at a high voltage, the electric field becomes extremely high, and characteristic deterioration due to the electric field is likely to occur. For example, it has been reported that the GaAs PHEMT has a reduced output in an RF reliability test at room temperature and has a higher temperature during operation (for example, Non-Patent Document 3).
[0003]
A first semiconductor layer having a narrow band gap and a second semiconductor layer having a wide band gap; and a two-dimensional electron gas channel is formed at an interface between the first semiconductor layer and the second semiconductor layer. In the high electron mobility transistor to be formed, a pn junction is formed with the second semiconductor layer, and in the energy band structure, the conductor lower end is higher than the conductor lower end of the second semiconductor layer. A third semiconductor layer serving as a gate portion forming a barrier is provided over the second semiconductor layer (see, for example, Patent Document 1). Further, an energy barrier for carriers is formed by inserting a compound semiconductor layer (energy barrier layer) having a larger band gap than the carrier supply layer and the buffer layer into the carrier supply layer and the buffer layer, thereby reducing leakage current and further improving low noise performance. There is a compound semiconductor device for improvement (for example, see Patent Document 2). Furthermore, there is a high electron mobility transistor in which a layer having a large forbidden band is formed in a carrier supply layer to prevent holes from flowing (for example, see Patent Document 3).
[0004]
[Patent Document 1]
JP-A-64-36080 [Patent Document 2]
Japanese Patent Laid-Open Publication No. 6-244218 [Patent Document 3]
JP 9-205196 A [Non-Patent Document 1]
GaAs IC symposium (1995), pp. 81-84 [Non-Patent Document 2]
GaAs IC symposium (1994), pp. 259-262 [Non-Patent Document 3]
GaAs Mantech (1997), pp. 42-45.
[Problems to be solved by the invention]
The degradation mechanism of PHEMT is considered as follows. First, hot electrons or hot holes having high energy having high energy are generated by impact ionization during high electric field operation, and the hot carriers reach the surface of the semiconductor device and deteriorate the surface. When the hot carriers are hot electrons, they are trapped in the surface passivation film, and the negative charges cause the depletion layer to extend, thereby causing channel narrowing. As a result, it is considered that the I _max value decreases and the characteristics of PHEMT deteriorate. This deterioration mechanism becomes more prominent as the electric field increases. In addition, in the case of an InP-based HEMT or a metamorphic HEMT for improving high-frequency characteristics, the energy of impact ionization is increased, so that the characteristics are significantly deteriorated.
[0006]
An object of the present invention is to suppress characteristic deterioration due to an electric field in a semiconductor device such as a MESFET or a PHEMT.
[0007]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a channel layer formed on a semiconductor substrate,
A Schottky layer formed on the channel layer,
A gate electrode provided on the Schottky layer;
A source electrode and a drain electrode provided on the Schottky layer at two locations separated from the gate electrode in opposite directions via an n + layer, respectively;
A first layer having a band gap narrower than the Schottky layer, and a second layer having a band discontinuity with respect to the Schottky layer is inserted into the Schottky layer on the first layer. It is characterized by having.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
A semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the drawings, substantially the same members are denoted by the same reference numerals.
[0009]
Embodiment 1 FIG.
First Embodiment A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of the semiconductor device. This semiconductor device is a strained high electron mobility transistor (PHEMT) using an InGaAs layer for a channel layer. In this semiconductor device, an AlGaAs buffer layer 9, a Si-doped lower electron supply layer 8, an InGaAs channel layer 7, an Si-doped upper electron supply layer 6, and AlGaAs Schottky layers 5a and 5b are sequentially formed on a GaAs substrate 10. It is laminated. Furthermore, in this semiconductor device, the recombination layer 12 and the barrier layer 11 provided on the recombination layer 12 are sandwiched between the two Schottky layers 5a and 5b. It is characterized by. The gate electrode 1 is provided on the Schottky layer 5b. Further, on the Schottky layer 5 b, a source electrode 2 and a drain electrode 3 are provided via an n + GaAs layer 4, separated from the gate electrode 1 in opposite directions.
[0010]
Here, the Schottky layer 5 is usually an AlGaAs layer having a molar ratio of Al of 0.24 or less. The barrier layer 11 is made of a semiconductor material having band discontinuity (ΔEc, ΔEv) with respect to the Schottky layer 5, and has a barrier effect on carriers such as holes or electrons. As the barrier layer 11, for example, an AlGaAs layer having an Al molar ratio higher than that of the Schottky layer 5 of 0.4 or more, or an InGaP layer can be used. Further, the recombination layer 12 is made of a material having a narrower band gap than the Schottky layer 5. As the recombination layer 12, for example, a layer in which InGaAs is doped with oxygen can be used. Further, as the recombination layer 12, a layer having lattice defects at the interface or in the layer may be used.
[0011]
Next, the effect of the recombination layer 12 provided between the Schottky layers 5a and 5b and the barrier layer 11 in this semiconductor device will be described with reference to FIG. FIG. 2 is a schematic diagram illustrating a process in which hot carriers generated in the channel layer 4 due to a high electric field disappear in the recombination layer 12 during RF high output operation. The hot carriers generated due to the high electric field do not reach the surface above the barrier layer 11 because of the presence of the barrier layer 11. For this reason, surface deterioration due to hot carriers is suppressed. The hot carriers stopped by the barrier layer 11 disappear in the recombination layer 12 provided below the barrier layer 11 due to recombination of holes and electrons. When the recombination layer 12 is not provided, when hot carriers stopped by the barrier layer 11, for example, hot holes are accumulated under the barrier layer, it is considered that the potential decreases and Ids increases to generate a kink waveform. In this semiconductor device, by providing the barrier layer 11 and the recombination layer 12 under the barrier layer, surface deterioration due to hot carriers can be prevented, and accumulation of hot carriers can be prevented.
[0012]
Embodiment 2 FIG.
Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a sectional view of the semiconductor device. This semiconductor device is characterized in that a recombination layer 12 and a barrier layer 11 provided on the recombination layer 12 are sandwiched between two Schottky layers 5a and 5b. And Further, under the source electrode 2, ap + contact layer 15 is provided penetrating the n + layer 4, the Schottky layer 5a, the barrier layer 11, and the recombination layer 12, and connecting the source electrode 2 and the Schottky layer 5b. It is characterized by having. This p + contact layer 15 is formed by ion implantation of a p-type dopant such as Mg or C.
[0013]
Next, the effect of the p + contact layer 15 will be described with reference to FIG. FIG. 4 is a schematic view showing a process in which a hot hole 26 below the barrier layer 11 is caused to flow through the source electrode 2 by the p + contact layer 15 provided below the source electrode 2. Therefore, accumulation of holes under the barrier layer 11 is suppressed.
[0014]
Embodiment 3 FIG.
Third Embodiment A semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a sectional view of the semiconductor device. This semiconductor device is characterized in that an n-type doped layer 13 is provided between the Schottky layers 5a and 5b, and a p-type doped layer 14 is provided below the n-type doped layer 13. Due to the lamination of the n-type doped layer 13 and the p-type doped layer 14, the potential is reduced in the n-type doped layer 13 and the potential is increased in the p-type doped layer 14, so that band discontinuity occurs. Therefore, this semiconductor device has a barrier effect against hot holes.
[0015]
Embodiment 4 FIG.
Fourth Embodiment A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a sectional view of the semiconductor device. In this semiconductor device, an n-type doped layer 13 and a p-type doped layer 14 provided on the n-type doped layer 13 are sandwiched between two Schottky layers 5a and 5b. It is characterized by having. Further, a via hole 16 penetrating from the source electrode 2 to the GaAs substrate 10 is provided. The holes blocked by the n-type doped layer 13 and the p-type doped layer 14 by the via hole 16 flow from the via hole 16 to the source electrode. Thereby, accumulation of hot holes is suppressed.
[0016]
In this example, the via hole 16 is opened from the surface of the GaAs substrate 10 and penetrated to the source electrode 2, but may be opened from the source electrode 2 and penetrated to the GaAs substrate 10.
[0017]
Embodiment 5 FIG.
A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a sectional view of the semiconductor device. In this semiconductor device, an AlGaAs buffer layer 9, an Si-doped lower electron supply layer 8, an InGaAs channel layer 7, an Si-doped upper electron supply layer 6, and an AlGaAs Schottky layer 5 are sequentially stacked on a GaAs substrate 10. . The gate electrode 1 is provided on the Schottky layer 5. Further, on the Schottky layer 5, the source electrode 2 and the drain electrode 3 are separated from each other in the opposite direction from the gate electrode 1 via the n + GaAs layer 4 sandwiched between the two InGaP layers 17 and 18. Is provided. Note that the InGaAs layer 18 covers the surface of the Schottky layer 5.
[0018]
Next, the effect of sandwiching the n + GaAs layer 4 between the two InGaP layers 17 and 18 will be described. The surface degradation due to the electric field occurs on the surface of the Schottky layer 5 and the surface of the n + GaAs layer 4. On the other hand, compound semiconductors such as P-based InGaP are less likely to be oxidized than compound semiconductors such as As-based GaAs and AlGaAs. InGaP has a large band discontinuity (ΔEv) in the valence band and has a barrier effect against hot holes. Further, InGaP hardly causes surface oxidation. Therefore, the surface degradation is suppressed by covering the surface of the Schottky layer 5 where the surface degradation is likely to occur and the n + GaAs layer with the InGaP layers 17 and 18. In the manufacture of this semiconductor device, InGaP having a predetermined shape shown in FIG. 7 is formed by selectively etching InGaP with respect to GaAs or AlGaAs.
[0019]
Embodiment 6 FIG.
A semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a sectional view of the semiconductor device. In this semiconductor device, an AlGaAs buffer layer 9, an Si-doped lower electron supply layer 8, an InGaAs channel layer 7, an Si-doped upper electron supply layer 6, and an AlGaAs Schottky layer 5 are sequentially stacked on a GaAs substrate 10. . The gate electrode 1 is provided on the Schottky layer 5. Further, on the Schottky layer 5, at a position separated from the gate electrode 1 in the opposite direction, via the n-GaAs layer 4 and the n + GaAs layer 4 sandwiched between the two InGaP layers 17 and 18, A source electrode 2 and a drain electrode 3 are provided, respectively. Note that the InGaAs layer 18 covers the surface of the Schottky layer 5.
[0020]
The effect of providing the n-GaAs layer 4 and the n + GaAs layer 4 sandwiched between the two InGaP layers 17 and 18 will be described. As described in the fifth embodiment, by covering the surface of the Schottky layer 5 and the surface of the n-GaAs layer 19 with the InGaP layers 17 and 18, surface degradation due to a high electric field is suppressed.
[0021]
In the above embodiment, the GaAs PHEMT has been described as an example. However, the present invention is not limited to this. Is also applicable.
[0022]
【The invention's effect】
The semiconductor device according to the present invention includes the recombination layer between the two Schottky layers, and the barrier layer provided on the recombination layer. During RF high-power operation, hot carriers generated in the channel layer due to a high electric field are blocked by the barrier layer and do not reach the surface above it. For this reason, surface deterioration due to hot carriers is suppressed. Further, the hot carriers stopped by the barrier layer disappear by recombination of holes and electrons in the recombination layer provided below the barrier layer. Therefore, accumulation of hot carriers can be prevented.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a schematic view showing a process in which hot carriers are recombined and eliminated by a barrier layer and a recombination layer in the semiconductor device of FIG. 1;
FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram showing a process of flowing hot holes under a barrier layer to a source electrode by a p + layer provided under a source electrode in the semiconductor device of FIG. 3;
FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention;
FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 8 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 gate electrode, 2 source electrode, 3 drain electrode, 4 n + GaAs layer, 5 5 a, 5 b AlGaAs layer (Schottky layer), 6 upper electron supply layer, 7 channel layer, 8 lower electron supply layer, 9 buffer layer, 10 GaAs substrate, 11 barrier layer, 12 recombination layer, 13 n-type doped layer, 14 p-type doped layer, 15 p + contact layer, 16 via hole, 17, 18 InGaP layer, 19 n-GaAs layer, 20 electrons, 22 holes, 24 Hot Hole, 26 Hot Hole Route

Claims (10)

A channel layer formed on a semiconductor substrate;
A Schottky layer formed on the channel layer,
A gate electrode provided on the Schottky layer;
A source electrode and a drain electrode provided on the Schottky layer at two locations separated from the gate electrode in opposite directions via an n + layer, respectively;
A first layer having a band gap narrower than the Schottky layer, and a second layer having a band discontinuity with respect to the Schottky layer is inserted into the Schottky layer on the first layer. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the first layer is made of a material having lattice defects. A channel layer formed on a semiconductor substrate;
A Schottky layer formed on the channel layer,
A gate electrode provided on the Schottky layer;
A source electrode and a drain electrode provided on the Schottky layer at two locations separated from the gate electrode in opposite directions via an n + layer, respectively;
A semiconductor device, wherein a p-type doped layer and an n-type doped layer on the p-type doped layer are inserted in the Schottky layer. 4. The semiconductor device according to claim 1, further comprising a p + contact layer connecting the source electrode and the first Schottky layer below the source electrode. 5. The semiconductor device according to claim 1, further comprising a via hole penetrating from the source electrode to the semiconductor substrate. A channel layer formed on a semiconductor substrate;
A Schottky layer formed on the channel layer,
A gate electrode provided on the Schottky layer;
A source electrode and a drain electrode provided on the Schottky layer at two locations separated from the gate electrode in opposite directions via an n + layer, respectively;
A semiconductor device, wherein the surface of the Schottky layer is covered with a P-based compound semiconductor layer. First and second P-type compound semiconductor layers sandwiching the n + layer between the source electrode and the Schottky layer and the n + layer between the drain electrode and the Schottky layer from above and below, respectively. The semiconductor device according to claim 6, further comprising: An n− layer and third and fourth P-based compound semiconductor layers sandwiching the n− layer from above and below, respectively, are sandwiched between the n + layer and the Schottky layer. The semiconductor device according to claim 6. 9. The semiconductor device according to claim 6, wherein the P-based compound semiconductor layer is an InGaP layer. The semiconductor device according to claim 1, further comprising first and second electron supply layers sandwiching the channel layer from above and below.

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