JP2004247229A

JP2004247229A - Image display device

Info

Publication number: JP2004247229A
Application number: JP2003037603A
Authority: JP
Inventors: Toshiaki Kusunoki; 敏明楠; Masakazu Sagawa; 雅一佐川; Mutsumi Suzuki; 睦三鈴木
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2003-02-17
Filing date: 2003-02-17
Publication date: 2004-09-02

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device capable of enhancing insulation between a spacer electrode and the electrode wiring of an electron source array by anodizing the surface of a lower electrode or an upper electrode three-dimensionally intersecting with the spacer electrode, and by covering it with a double or triple insulation layer by using an interlayer insulation film formed by a sputtering method. <P>SOLUTION: This image display device has: a thin film type electron source array having the lower electrode, the upper electrode and an electron acceleration layer caught between them, and used for emitting electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode; and a phosphor surface. The electrode of the thin film type electron source and the spacer electrode are insulated from each other with a stacked insulation film formed by using different film formation methods. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、薄膜型電子源を利用した自発光型フラットパネルディスプレイに係わるものである。
【０００２】
【従来の技術】
微少で集積可能な冷陰極を利用するディスプレイは、ＦＥＤ（ＦｉｅｌｄＥｍｉｓｓｉｏｎＤｉｓｐｌａｙ）と呼称される。冷陰極には、電界放出型電子源とホットエレクトロン型電子源に分類され、前者には、スピント型電子源、表面伝導型電子源、カーボンナノチューブ型電子源等が属し、後者には金属―絶縁体―金属を積層したＭＩＭ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ）型、金属―絶縁体―半導体を積層したＭＩＳ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）型、金属―絶縁体―半導体−金属型等の薄膜型電子源がある。
【特許文献１】
特開平７−６５７１０号公報
【特許文献２】
特開平１０−１５３９７９号公報
【非特許文献１】
Ｊ．Ｖａｃ．Ｓｃｉ．Ｔｅｃｈｏｎｏｌ．Ｂ１１（２）ｐ．４２９−４３２（１９９３）
【非特許文献２】
ｈｉｇｈ−ｅｆｆｉｃｉｅｎｃｙ−ｅｌｅｃｔｒｏ−ｅｍｉｓｓｉｏｎｄｅｖｉｃｅ、Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．、ｖｏｌ３６、ｐＬ９３９
【非特許文献３】
Ｅｌｅｃｔｒｏｌｕｍｉｎｅｓｃｅｎｃｅ、応用物理第６３巻、第６号、５９２頁
【非特許文献４】
応用物理第６６巻、第５号、４３７頁
ＭＩＭ型については例えば特許文献１、金属―絶縁体―半導体型についてはＭＯＳ型（非特許文献１）、金属―絶縁体―半導体−金属型ではＨＥＥＤ型（非特許文献２などに記載）、ＥＬ型（非特許文献３などに記載）、ポーラスシリコン型（非特許文献４などに記載）などが報告されている。
【０００３】
ＭＩＭ型電子源については、例えば特許文献２に開示されている。ＭＩＭ型電子源の構造と動作原理を図２に示す。上部電極１３と下部電極１１との間に駆動電圧Ｖ_ｄを印加して、絶縁層１２内の電界を１〜１０ＭＶ／ｃｍ程度にすると、下部電極１１中のフェルミ準位近傍の電子はトンネル現象により障壁を透過し、電子加速層である絶縁層１２の伝導帯へ注入されホットエレクトロンとなり、上部電極１３の伝導帯へ流入する。これらのホットエレクトロンのうち、上部電極１３の仕事関数φ以上のエネルギーをもって上部電極１３表面に達したものが真空２０中に放出される。
【０００４】
【発明が解決しようとする課題】
薄膜型電子源アレイと蛍光面を用いたフラットパネルディスプレイでは、真空を保持するため、電子源アレイ基板と蛍光面との間にスペーサを配置する。スペーサは電子源アレイ基板と蛍光面に印加する高電圧を絶縁するため、基本的に絶縁性が必要であるが、電子線照射などによる帯電で電子線が曲がるのを防止するため若干の導電性を有する。その電位を安定させるため、電子源アレイ基板上でスペーサに接地または低電圧の電位を与えるスペーサ電極を設ける。スペーサはそのスペーサ電極上に配置されるが、パネル内を真空排気した際は大気圧がかかるため、電子源アレイ基板にはスペーサから強い圧力がかかり、薄膜型電子源が損傷しやすい。特にスペーサ電極と薄膜型電子源の下部または上部電極の交差部の絶縁膜が破壊されると、スペーサ電極と電子源の電極配線が短絡する不良が生じる。
【０００５】
したがって、薄膜型電子源にはスペーサからの圧力で破壊されない構造が必要である。
【０００６】
【課題を解決するための手段】
本発明の目的は、スペーサ電極と立体交差する部分の薄膜型電子源の電極配線を、異なる成膜法で形成する少なくとも２層の絶縁膜で被覆することにより実現できる。さらに、その上にめっきなどで形成した厚膜でスペーサ電極を形成することにより、より有効に実現できる。
【０００７】
【発明の実施の形態】
（実施例）
上記目的を実現する本発明の実施の形態をＭＩＭ電子源を例に図１〜１５で説明する。
【０００８】
はじめにガラス等の絶縁性の基板１０上に下部電極１１用の金属膜を成膜する。下部電極１１の材料としてはＡｌやＡｌ合金を用いる。ＡｌやＡｌ合金を用いたのは、陽極酸化により良質の絶縁膜を形成できるからである。ここでは、Ｎｄを２原子量％ドープしたＡｌ−Ｎｄ合金を用いた。成膜には例えば、スパッタリング法を用いる。膜厚は５００ｎｍとした（図３）。成膜後はホト工程、エッチング工程によりストライプ形状の下部電極１１を形成した。エッチングは例えば燐酸、酢酸、硝酸の混合水溶液でのウェットエッチングを用いる（図４）。
【０００９】
次に、電子放出部を制限し、下部電極１１のエッジへの電界集中を防止する保護絶縁層１４を形成する。まず下部電極１１上の電子放出部となる部分をレジスト２５でマスクし、その他の部分を選択的に厚く陽極酸化し，保護絶縁層１４とする（図５）。化成電圧を１００Ｖとすれば、厚さ約１３６ｎｍの保護絶縁層１４が形成される。陽極酸化後、レジスト２５を剥離する。
【００１０】
続いて電子放出部に絶縁層１２を陽極酸化で形成する。化成電圧を６Ｖとすれば、厚さ約１１ｎｍの絶縁層１２が形成される。本工程は省略し、上部電極１３の成膜前に行うことも可能である。
【００１１】
次に第１の層間絶縁膜１５と、上部電極１３への給電線となる上部バス電極１６を例えばスパッタリング法等で成膜する。第１の層間絶縁膜１５としては、例えばシリコン酸化物やシリコン窒化膜などを用いることができる。ここでは、シリコン窒化膜を用い膜厚は３００ｎｍとした。この第１の層間絶縁膜１５は、陽極酸化で形成する保護絶縁層１４にピンホールがあった場合、その欠陥を埋め、下部電極１１と上部バス電極１６間の絶縁を保つ役割を果たす。上部バス電極１６の材料としては、ＡｌやＡｌ合金、Ｔａなど、表面に陽極酸化膜が形成できるバルブ金属を用いる。本実施例では下部電極１１と同様、Ｎｄを２原子量％ドープしたＡｌ−Ｎｄ合金を用いた（図６）。
【００１２】
続いて、ホトエッチング工程により上部バス電極１６をエッチングし配線形状に加工する（図７）。続いて上部バス電極１６のうち、少なくとも後程形成する上部電極１３との接続部となる部分や、回路への接続部などをレジスト２５で被覆し、その他の部分の表面を陽極酸化する。さらに下部電極１１もレジスト２５で被覆しておくと、化成液を介して下部電極１１が陰極と同電位になることが防止できるので、上部バス電極１６と下部電極１１間の絶縁破壊を防止でき、本工程の歩留まりを高めることができる。ここでは、下部電極１１の配線間に位置する上部バス電極１６の表面のみ選択的に陽極酸化膜１７を形成した（図８）。
【００１３】
続いて第２の層間絶縁膜１８を成膜する。第２の層間絶縁膜１８としては例えば窒化シリコンや酸化シリコン、あるいはその積層膜などを用いればよい。ここでは窒化シリコン、酸化シリコンの順に積層した膜を用いた（図９）。
【００１４】
続いてスペーサ電極１９を形成する。スペーサ電極１９としては例えばスパッタ法やめっき法により形成する。めっきをする場合は、スパッタ法などで種膜を成膜し、電気めっきで形成する方法や無電解めっき、あるいはその組み合わせをもちいればよい。めっきとしてはＡｕなどの貴金属めっき、ＣｕやＮｉ、Ｃｒ、Ａｌめっきなどを用いることが可能である。
【００１５】
この際、スペーサ電極１９はできるだけ厚く形成しておくことが好ましい。厚膜化することでスペーサからの圧力を吸収する緩衝材として機能させることができる。このような厚膜を形成するには特に電気めっき法が有効である。本発明では、上部バス電極１６上に陽極酸化膜１７とスパッタ法で形成した第２の層間絶縁膜１８の異なる成膜法で形成した二重の絶縁膜を用いているため、それぞれの絶縁層のピンホール欠陥を補償し、上部バス電極１６とスペーサ電極１９間の絶縁が確実になるため、電気めっきなどを用いても電極間の絶縁破壊などの副作用がなく厚いスペーサ電極１９を形成することができる（図１０）。
【００１６】
続いて第２の層間絶縁膜１８の電子放出部をドライエッチングで開口する。加工は例えばＣＦ_４やＳＦ_６を主成分とする用いたドライエッチングによって行うことができる。本実施例では第２の層間絶縁膜１８をエッチング速度の遅い酸化シリコン膜と速い窒化シリコンの積層膜で構成しているため、逆テーパー加工が可能である（図１１）。
【００１７】
続いて上部バス電極１６の電子放出部をウェットエッチングにより開口する。加工は電子放出部に向かってテーパー状に膜厚が減少するように行う。これにより後程形成する上部電極１３を段切れさせずに接続することが可能である（図１２）。
【００１８】
続いて第１の層間絶縁膜１５をドライエッチングで加工する。加工は例えばＣＦ_４やＳＦ_６を主成分とする用いたドライエッチングによって行うことができる。この加工も電子放出部に向かってテーパー状に膜厚が減少するように行う。テーパー加工はエッチングガスに酸素を添加し、レジストが後退するようにして行うことができる。（図１３）。
【００１９】
次に絶縁層１２を修復するため、再度陽極酸化する。最初に陽極酸化しない場合は、本工程で始めて絶縁層１２を形成することになる（図１４）。
【００２０】
最後に上部電極１３膜の成膜を行う。成膜法は例えばスパッタ成膜を用いる。上部電極１３としては例えばＩｒ、Ｐｔ，Ａｕの積層膜を用い膜厚は例えば６ｎｍとした。本実施例では、第２の層間絶縁膜１８の逆テーパー形状を利用して上部電極１３を自動分離した（図１）。
【００２１】
図１５は本発明の薄膜型電子源を用いたディスプレイの一部を示したものである。説明の便宜上、蛍光面基板は一部のみ図示している。
【００２２】
表示側基板はコントラストを上げる目的のブラックマトリクス１２０、色蛍光体１１１、緑色蛍光体１１２と青色蛍光体１１３とからなる。蛍光体としては，例えば赤色にＹ_２Ｏ_２Ｓ：Ｅｕ（Ｐ２２−Ｒ），緑色にＺｎＳ：Ｃｕ，Ａｌ（Ｐ２２−Ｇ），青色にＺｎＳ：Ａｇ，Ｃｌ（Ｐ２２−Ｂ）を用いる。スペーサ３０は、陰極基板のスペーサ電極１８上に配置し、蛍光面基板のブラックマトリクス１２０の下に隠れるように配置する。下部電極１１は走査線回路５０へ結線し，上部バス電極１６は信号線回路６０に結線する。本実施例ではスペーサ電極１９は下部電極１１配線間、上部バス電極１６とは立体交差するように配置され、接地されている。
【００２３】
以上のように本発明では、上部バス電極１６と、スペーサ電極１９の立体交差する部分が陽極酸化膜１７と第２の層間絶縁膜１８の異なる成膜法で形成された二重の絶縁膜に被覆されている。そのためまず第１の効果として、絶縁膜の厚膜化の効果でスペーサからの圧力への耐性が向上する。さらに第２の効果として、成膜法の異なる二重の絶縁膜の積層膜を用いることで、それぞれの絶縁層のピンホール欠陥を補償されるので、上部バス電極１６とスペーサ電極１９間の絶縁が確実になる。そのため、電気めっきを用いても電極間の絶縁破壊などの副作用がなく厚いスペーサ電極１９を形成することができる。この厚膜がスペーサの圧力を吸収する緩衝材として機能するため、薄膜型電子源アレイ基板の損傷を防止することができる。
【００２４】
なお、本実施例では上部バス電極１６とスペーサ電極１９が交差する場合について述べたが、本構造の薄膜型電子源の下部電極１１は陽極酸化で形成した保護絶縁層１４を有しており、その上に第１の層間絶縁膜１５、第２の層間絶縁膜１８が被覆されているため、スペーサ電極１９が下部電極１１と交差するように配置しても上記実施例と同様の効果を得ることが可能である。
【００２５】
【発明の効果】
以上のように、スペーサ電極と立体交差する下部電極または上部バス電極の表面を陽極酸化し、さらにスパッタ法で形成した層間絶縁膜で二重、三重の絶縁層で被覆することにより、スペーサ電極と電子源アレイの電極配線間の絶縁を強化することができる。それによりスペーサ電極からの圧力への耐性を強化し、電気めっきを用いても電極間絶縁破壊などの副作用がなく厚いスペーサ電極１９で形成でき、スペーサからの圧力を吸収する緩衝材を設けることができる。
【図面の簡単な説明】
【図１】本発明の薄膜型電子源の構造を示す図である。
【図２】薄膜型電子源の動作原理を示す図である。
【図３】本発明の薄膜型電子源の製法を示す図である。
【図４】本発明の薄膜型電子源の製法を示す図である。
【図５】本発明の薄膜型電子源の製法を示す図である。
【図６】本発明の薄膜型電子源の製法を示す図である。
【図７】本発明の薄膜型電子源の製法を示す図である。
【図８】本発明の薄膜型電子源の製法を示す図である。
【図９】本発明の薄膜型電子源の製法を示す図である。
【図１０】本発明の薄膜型電子源の製法を示す図である。
【図１１】本発明の薄膜型電子源の製法を示す図である。
【図１２】本発明の薄膜型電子源の製法を示す図である。
【図１３】本発明の薄膜型電子源の製法を示す図である。
【図１４】本発明の薄膜型電子源の製法を示す図である。
【図１５】本発明の薄膜型電子源を用いた表示装置を示す図である。
【符号の説明】
１０・・・基板，１１・・・下部電極，１２・・・絶縁層，１３・・・上部電極，１４・・・保護絶縁層，１５・・・層間絶縁膜、１６・・・上部バス電極、１７・・・陽極酸化膜、１８・・・第２の層間絶縁膜、１９・・・スペーサ電極、２０・・・真空、２５・・・レジスト、３０・・・スペーサ，５０・・・下部電極駆動回路，６０・・・上部電極駆動回路，１１１・・・赤色蛍光体，１１２・・・緑色蛍光体，１１３・・・青色蛍光体，１２０・・・ブラックマトリクス。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a self-luminous flat panel display using a thin-film electron source.
[0002]
[Prior art]
A display using a small and integrable cold cathode is referred to as an FED (Field Emission Display). Cold cathodes are classified into field-emission electron sources and hot-electron electron sources.The former includes Spindt-type electron sources, surface-conduction electron sources, carbon nanotube-type electron sources, etc. Thin-film electron sources such as MIM (Metal-Insulator-Metal) type in which body-metal is laminated, MIS (Metal-Insulator-Semiconductor) type in which metal-insulator-semiconductor is laminated, and metal-insulator-semiconductor-metal type There is.
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[Non-Patent Document 3]
Electroluminescence, Applied Physics Vol. 63, No. 6, page 592 [Non-Patent Document 4]
Applied Physics Vol. 66, No. 5, page 437 For example, Patent Document 1 for the MIM type, MOS type for the metal-insulator-semiconductor type (Non-Patent Document 1), and HEED for the metal-insulator-semiconductor-metal type Types (described in Non-Patent Document 2 and the like), EL types (described in Non-Patent Document 3 and the like), and porous silicon types (described in Non-Patent Document 4 and the like) have been reported.
[0003]
The MIM type electron source is disclosed in Patent Document 2, for example. FIG. 2 shows the structure and operating principle of the MIM type electron source. By applying a driving voltage V _d between the upper electrode 13 and the lower electrode 11, when the electric field of the insulating layer 12 to about 1~10MV / cm, the neighborhood of the Fermi level in the lower electrode 11 electron tunneling As a result, the electrons pass through the barrier, are injected into the conduction band of the insulating layer 12 as the electron acceleration layer, become hot electrons, and flow into the conduction band of the upper electrode 13. Of these hot electrons, those that have reached the surface of the upper electrode 13 with energy equal to or higher than the work function φ of the upper electrode 13 are released into the vacuum 20.
[0004]
[Problems to be solved by the invention]
In a flat panel display using a thin-film type electron source array and a phosphor screen, a spacer is disposed between the electron source array substrate and the phosphor screen to maintain a vacuum. The spacer basically needs to be insulated to insulate the high voltage applied to the electron source array substrate and the phosphor screen, but it needs to be slightly conductive to prevent the electron beam from being bent by charging by electron beam irradiation. Having. In order to stabilize the potential, a spacer electrode is provided on the electron source array substrate to apply a ground or low-voltage potential to the spacer. The spacer is arranged on the spacer electrode. However, when the inside of the panel is evacuated to vacuum, a high pressure is applied to the electron source array substrate from the spacer, and the thin-film electron source is easily damaged. In particular, when the insulating film at the intersection of the spacer electrode and the lower or upper electrode of the thin film type electron source is broken, a short circuit between the spacer electrode and the electrode wiring of the electron source occurs.
[0005]
Therefore, the thin film type electron source needs a structure that is not broken by the pressure from the spacer.
[0006]
[Means for Solving the Problems]
The object of the present invention can be realized by covering at least two layers of insulating films formed by different film forming methods on the electrode wiring of the thin film type electron source at a portion which three-dimensionally intersects with the spacer electrode. Further, by forming a spacer electrode with a thick film formed by plating or the like on the spacer electrode, it can be more effectively realized.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example)
An embodiment of the present invention for achieving the above object will be described with reference to FIGS.
[0008]
First, a metal film for the lower electrode 11 is formed on an insulating substrate 10 such as glass. As a material of the lower electrode 11, Al or an Al alloy is used. The reason why Al or Al alloy is used is that a high-quality insulating film can be formed by anodic oxidation. Here, an Al—Nd alloy doped with 2 atomic% of Nd was used. For example, a sputtering method is used for film formation. The film thickness was 500 nm (FIG. 3). After the film formation, a stripe-shaped lower electrode 11 was formed by a photo process and an etching process. For the etching, for example, wet etching with a mixed aqueous solution of phosphoric acid, acetic acid and nitric acid is used (FIG. 4).
[0009]
Next, a protective insulating layer 14 for limiting an electron emission portion and preventing electric field concentration on the edge of the lower electrode 11 is formed. First, a portion serving as an electron emission portion on the lower electrode 11 is masked with a resist 25, and the other portion is selectively anodized thickly to form a protective insulating layer 14 (FIG. 5). If the formation voltage is 100 V, the protective insulating layer 14 having a thickness of about 136 nm is formed. After the anodic oxidation, the resist 25 is peeled off.
[0010]
Subsequently, an insulating layer 12 is formed on the electron emitting portion by anodic oxidation. If the formation voltage is 6 V, an insulating layer 12 having a thickness of about 11 nm is formed. This step can be omitted and performed before the film formation of the upper electrode 13.
[0011]
Next, a first interlayer insulating film 15 and an upper bus electrode 16 serving as a power supply line to the upper electrode 13 are formed by, for example, a sputtering method. As the first interlayer insulating film 15, for example, a silicon oxide or silicon nitride film can be used. Here, a silicon nitride film was used and the film thickness was 300 nm. The first interlayer insulating film 15 fills the defect when the protective insulating layer 14 formed by anodic oxidation has a pinhole, and plays a role of maintaining insulation between the lower electrode 11 and the upper bus electrode 16. As a material for the upper bus electrode 16, a valve metal such as Al, an Al alloy, or Ta that can form an anodic oxide film on the surface is used. In the present embodiment, similarly to the lower electrode 11, an Al—Nd alloy doped with 2 atomic% of Nd was used (FIG. 6).
[0012]
Subsequently, the upper bus electrode 16 is etched by a photo-etching process and processed into a wiring shape (FIG. 7). Subsequently, of the upper bus electrode 16, at least a portion to be connected to the upper electrode 13 to be formed later, a portion to be connected to a circuit, and the like are covered with a resist 25, and the surfaces of other portions are anodized. Further, if the lower electrode 11 is also covered with the resist 25, the lower electrode 11 can be prevented from having the same potential as the cathode through the chemical conversion solution, so that dielectric breakdown between the upper bus electrode 16 and the lower electrode 11 can be prevented. Thus, the yield of this step can be increased. Here, the anodic oxide film 17 was selectively formed only on the surface of the upper bus electrode 16 located between the wirings of the lower electrode 11 (FIG. 8).
[0013]
Subsequently, a second interlayer insulating film 18 is formed. As the second interlayer insulating film 18, for example, silicon nitride, silicon oxide, or a stacked film thereof may be used. Here, a film laminated in the order of silicon nitride and silicon oxide was used (FIG. 9).
[0014]
Subsequently, a spacer electrode 19 is formed. The spacer electrode 19 is formed by, for example, a sputtering method or a plating method. In the case of plating, a method in which a seed film is formed by a sputtering method or the like and formed by electroplating, electroless plating, or a combination thereof may be used. As plating, noble metal plating such as Au, Cu, Ni, Cr, Al plating or the like can be used.
[0015]
At this time, it is preferable that the spacer electrode 19 be formed as thick as possible. By making the film thicker, it can function as a buffer material that absorbs pressure from the spacer. In order to form such a thick film, an electroplating method is particularly effective. In the present invention, a double insulating film formed by a different film forming method of the anodic oxide film 17 and the second interlayer insulating film 18 formed by the sputtering method on the upper bus electrode 16 is used. To form a thick spacer electrode 19 without any side effects such as dielectric breakdown between the electrodes even when using electroplating, because the pinhole defect of the above is compensated and the insulation between the upper bus electrode 16 and the spacer electrode 19 is ensured. (FIG. 10).
[0016]
Subsequently, the electron emission portion of the second interlayer insulating film 18 is opened by dry etching. The processing can be performed, for example, by dry etching using CF ₄ or SF ₆ as a main component. In this embodiment, since the second interlayer insulating film 18 is composed of a stacked film of a silicon oxide film having a low etching rate and a silicon nitride film having a high etching rate, reverse taper processing is possible (FIG. 11).
[0017]
Subsequently, the electron emission portion of the upper bus electrode 16 is opened by wet etching. The processing is performed so that the film thickness is tapered toward the electron emission portion. This makes it possible to connect the upper electrode 13 to be formed later without disconnection (FIG. 12).
[0018]
Subsequently, the first interlayer insulating film 15 is processed by dry etching. The processing can be performed, for example, by dry etching using CF ₄ or SF ₆ as a main component. This processing is also performed so that the film thickness is tapered toward the electron emission portion. The tapering can be performed by adding oxygen to the etching gas so that the resist recedes. (FIG. 13).
[0019]
Next, in order to repair the insulating layer 12, anodic oxidation is performed again. If the anodic oxidation is not performed first, the insulating layer 12 is formed for the first time in this step (FIG. 14).
[0020]
Finally, a film of the upper electrode 13 is formed. As a film forming method, for example, sputtering film forming is used. The upper electrode 13 is, for example, a laminated film of Ir, Pt, and Au, and has a thickness of, for example, 6 nm. In the present embodiment, the upper electrode 13 was automatically separated using the reverse tapered shape of the second interlayer insulating film 18 (FIG. 1).
[0021]
FIG. 15 shows a part of a display using the thin-film electron source of the present invention. For convenience of explanation, only a part of the phosphor screen substrate is shown.
[0022]
The display-side substrate includes a black matrix 120, a color phosphor 111, a green phosphor 112, and a blue phosphor 113 for the purpose of increasing the contrast. As the phosphor, for example, Y ₂ O ₂ S: Eu (P22-R) is used for red, ZnS: Cu, Al (P22-G) is used for green, and ZnS: Ag, Cl (P22-B) is used for blue. The spacer 30 is disposed on the spacer electrode 18 on the cathode substrate, and is disposed so as to be hidden under the black matrix 120 on the phosphor screen substrate. The lower electrode 11 is connected to the scanning line circuit 50, and the upper bus electrode 16 is connected to the signal line circuit 60. In this embodiment, the spacer electrode 19 is arranged between the wirings of the lower electrode 11 and at a three-dimensional intersection with the upper bus electrode 16 and is grounded.
[0023]
As described above, in the present invention, the portion where the upper bus electrode 16 and the spacer electrode 19 intersect three-dimensionally is formed by a double insulating film formed by different film forming methods of the anodic oxide film 17 and the second interlayer insulating film 18. Coated. Therefore, as a first effect, the resistance to the pressure from the spacer is improved by the effect of increasing the thickness of the insulating film. Furthermore, as a second effect, the pinhole defect of each insulating layer can be compensated by using a laminated film of double insulating films having different film forming methods. Will be sure. Therefore, even if electroplating is used, a thick spacer electrode 19 can be formed without side effects such as dielectric breakdown between the electrodes. Since this thick film functions as a buffer absorbing the pressure of the spacer, it is possible to prevent the thin film type electron source array substrate from being damaged.
[0024]
In this embodiment, the case where the upper bus electrode 16 and the spacer electrode 19 intersect has been described. However, the lower electrode 11 of the thin film type electron source having this structure has the protective insulating layer 14 formed by anodic oxidation. Since the first interlayer insulating film 15 and the second interlayer insulating film 18 are coated thereon, even if the spacer electrode 19 is arranged so as to intersect the lower electrode 11, the same effect as in the above embodiment can be obtained. It is possible.
[0025]
【The invention's effect】
As described above, the surface of the lower electrode or the upper bus electrode that three-dimensionally intersects with the spacer electrode is anodized, and is further covered with a double or triple insulating layer with an interlayer insulating film formed by a sputtering method. The insulation between the electrode wires of the electron source array can be enhanced. Thereby, the resistance to the pressure from the spacer electrode is strengthened, and even if the electroplating is used, the thick spacer electrode 19 can be formed without side effects such as dielectric breakdown between electrodes, and a buffer material absorbing the pressure from the spacer can be provided. it can.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a thin film type electron source of the present invention.
FIG. 2 is a diagram illustrating the operation principle of a thin-film electron source.
FIG. 3 is a diagram illustrating a method for producing a thin-film electron source according to the present invention.
FIG. 4 is a view showing a method for producing a thin-film electron source of the present invention.
FIG. 5 is a diagram showing a method for producing a thin-film electron source of the present invention.
FIG. 6 is a view showing a method for producing a thin-film electron source of the present invention.
FIG. 7 is a diagram showing a method for producing a thin-film electron source of the present invention.
FIG. 8 is a diagram showing a method for producing a thin-film electron source according to the present invention.
FIG. 9 is a diagram showing a method for producing a thin-film electron source of the present invention.
FIG. 10 is a diagram showing a method for producing a thin-film electron source of the present invention.
FIG. 11 is a diagram showing a method for producing a thin-film electron source of the present invention.
FIG. 12 is a diagram illustrating a method for producing a thin-film electron source according to the present invention.
FIG. 13 is a view showing a method for producing a thin-film electron source of the present invention.
FIG. 14 is a diagram illustrating a method for producing a thin-film electron source according to the present invention.
FIG. 15 is a view showing a display device using the thin-film electron source of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... board | substrate, 11 ... lower electrode, 12 ... insulating layer, 13 ... upper electrode, 14 ... protective insulating layer, 15 ... interlayer insulating film, 16 ... upper bus electrode , 17: anodized film, 18: second interlayer insulating film, 19: spacer electrode, 20: vacuum, 25: resist, 30: spacer, 50: lower part Electrode drive circuit, 60: Upper electrode drive circuit, 111: Red phosphor, 112: Green phosphor, 113: Blue phosphor, 120: Black matrix.

Claims

A thin-film type electron source array having a lower electrode and an upper electrode, an electron acceleration layer sandwiched therebetween, and emitting electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode; In the image display device having a surface, the thin film type electron source array has an upper bus electrode serving as a power supply line to the upper electrode, and an interlayer insulating film covering the thin film type electron source array other than the electron emission portion and the circuit connection portion. And a spacer electrode formed on the interlayer insulating film, and a lower or upper bus electrode, which three-dimensionally intersects the spacer electrode, is insulated by at least a double insulating film formed by a different film forming method. An image display device using a thin film type electron source array.

A thin-film type electron source array having a lower electrode and an upper electrode, an electron acceleration layer sandwiched therebetween, and emitting electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode; In the image display device having a surface, the thin film type electron source array has an upper bus electrode serving as a power supply line to the upper electrode, and an interlayer insulating film covering the thin film type electron source array other than the electron emission portion and the circuit connection portion. And a spacer electrode formed on the interlayer insulating film. The surface of the lower or upper bus electrode, which three-dimensionally intersects with the spacer electrode, is anodized, and is further formed by another film forming method. An image display device using a thin-film type electron source array, characterized by being coated with a thin film type electron source array.

A thin-film type electron source array having a lower electrode and an upper electrode, an electron acceleration layer sandwiched therebetween, and emitting electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode; In the image display device having a surface, the thin film type electron source array has an upper bus electrode serving as a power supply line to the upper electrode, and an interlayer insulating film covering the thin film type electron source array other than the electron emission portion and the circuit connection portion. And a spacer electrode formed on the interlayer insulating film, and the surface of the lower or upper bus electrode at the portion that three-dimensionally intersects with the spacer electrode is selectively anodized. An image display device using a thin-film type electron source array, characterized by being formed with an interlayer insulating film.

4. The image display device according to claim 1, wherein said upper bus electrode is made of a valve metal such as aluminum, an aluminum alloy, and tantalum on which an anodic oxide film can be formed.

4. The image display device according to claim 1, wherein said spacer electrode is a plating film.