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JP2004128259A - Joint structure and electronic equipment equipped with the same - Google Patents

Joint structure and electronic equipment equipped with the same Download PDF

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Publication number
JP2004128259A
JP2004128259A JP2002291108A JP2002291108A JP2004128259A JP 2004128259 A JP2004128259 A JP 2004128259A JP 2002291108 A JP2002291108 A JP 2002291108A JP 2002291108 A JP2002291108 A JP 2002291108A JP 2004128259 A JP2004128259 A JP 2004128259A
Authority
JP
Japan
Prior art keywords
substrate
electronic component
organic material
electrodes
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002291108A
Other languages
Japanese (ja)
Inventor
Yasushi Takeuchi
竹内 靖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2002291108A priority Critical patent/JP2004128259A/en
Publication of JP2004128259A publication Critical patent/JP2004128259A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve connection reliability by reducing a uniform load and providing a mounting connection structure which is free of bending and a recess when an electronic component and a substrate are pressed and electrically connected by using an organic material. <P>SOLUTION: On the organic material represented by an ACF, a structure member is previously arranged at a position corresponding to between bumps of electronic components and electrodes of the substrate, and pressed and joined. In such constitution, the structure member is present between the bumps of the electronic components and electrodes of the substrate, so a structure having columns formed between the bumps and electrodes by pressure application is obtained to reduce the uniform load, and consequently a join having neither flexure nor a recess is obtained. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、電子部品と基板、電子部品と電子部品、基板と基板の接合構造に係り、接合部の高信頼性を図る手法に関する。
【0002】
【従来の技術】
電子部品を異方導電性フィルム(ACF)、異方導電性ペースト(ACP)、非導電性フィルム(NCF)、非導電性ペースト(NCP)に代表される熱硬化性有機材料、あるいは光硬化性有機材料を用いて基板に接合する場合、前記フィルムを電子部品と基板の間に挟んで加熱、加圧接合、光照射、加圧接合を行い電気的に接続していた。
【0003】
有機材料を加熱、加圧接合する場合や光照射、加圧して電子部品と基板を接合する場合、電子部品のバンプと基板の電極間の有機材料を流動排出させて電子部品のバンプと基板の電極を相互に接触させ、バンプと電極間に有機材料を残さずに有機材料の接着力により電子部品と基板を電気的に接続する構造としていた。
【0004】
さらに、電子部品と基板の加圧接合時に等分布荷重を低減するために、電子部品や基板上に本来の電気的接続以外の目的でダミーのバンプと電極を形成し、接合後に電子部品や基板の部分的撓みや凹みを低減すると同時に、接合部の信頼性向上を図っていた(例えば、特許文献1参照)。
【0005】
【特許文献1】
特開平9−68715号公報
【0006】
【発明が解決しようとする課題】
しかしながら上記従来例では、電子部品や基板にダミーのバンプや電極を形成するため、電子部品上に部品の機能とは関係ないエリアを設ける必要があり、電子部品や基板が大きくなりコストが上昇するという問題があった。
【0007】
又、電子部品や基板にダミーのバンプや電極を形成する自由度が低い場合は、接合時に等分布荷重が低減されず部分的撓みや凹みが発生し、電子部品のバンプや基板の電極の塑性変形量がばらついた状態で接合され、最悪の場合電子部品と基板の電気接合部が剥離して電気的にオープンになるという問題があった。
【0008】
本発明は上記の問題点を解決する為になされたもので、電子部品を有機材料を挟んで基板に加熱、加圧接合する場合や、光照射、加圧接合する場合に、電子部品や基板にダミーバンプや電極を形成することなく電子部品と基板の接合信頼性向上を図るとともに、コスト上昇を抑える接合構造とこの接合構造を備えた電子機器を提供することを目的とする。
【0009】
【課題を解決するための手段】
上記目的を達成する為本出願に係る第1の発明は、電子部品と基板を加熱、加圧接合する有機材料中に、電子部品のバンプや基板の電極間に位置するように構造部材を設けたことを特徴とする。特に電子部品のバンプと基板の電極の接続点同士が離れている場合に構造部材を設けると効果が大きい。
【0010】
上記構成において、有機材料中に配置した構造部材がバンプ間、電極間に存在するので、電子部品と基板を加熱、加圧接合する場合や、光照射、加圧接合する場合に構造部材による支柱が形成されるので等分布荷重が著しく低減される。
【0011】
従って、電子部品や基板に撓みや凹みが発生し難い接合構造となり、バンプと電極の塑性変形量のばらつきが低減され、電子部品と基板との電気接合部の剥離は発生しない。
【0012】
又、電子部品や基板にダミーのバンプや電極を形成する場合に比べ、電子部品や基板のサイズを小さくすることが可能となる。
【0013】
その結果、電子部品と基板の接合信頼性が向上し、同時にコストの上昇も抑えることが可能となる。
【0014】
なお、さらに詳細に説明すれば、本発明は下記の構成によって前記課題を解決できた。
【0015】
(1)電子部品と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と基板を加熱、加圧接合したことを特徴とする接合構造。
【0016】
(2)電子部品と電子部品が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と電子部品を加熱、加圧接合したことを特徴とする接合構造。
【0017】
(3)基板と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて基板と基板を加熱、加圧接合したことを特徴とする接合構造。
【0018】
(4)前記(1)または(2)記載の接合構造を持った電子部品と基板を搭載したことを特徴とする電子機器。
【0019】
【発明の実施の形態】
(第1の実施例)
図1−aが本発明の特徴を最もよく表した図であり、シリコン基板1にベアチップIC2がACF3で熱圧着接合され、ベアチップIC2のバンプ5とシリコン基板1の電極6間からACF3が排出されバンプ5と電極6が接触し電気的に導通した状態を、横断面から示したものであり、図1−bは上面から示したものである。
【0020】
図1において、7で示した構造部材がACF3に予め形成された構造部材で、高耐熱性の樹脂ボールを用いている。構造部材7の高さは、ベアチップIC2のバンプ5の厚みとシリコン基板1の電極6の厚みに合わせて決めればよいが、バンプ5と電極6が熱圧着されて塑性変形して決まるギャップ量に合わせる事が望ましい。
【0021】
また、構造部材7を配置する間隔は、加圧されるベアチップICの剛性により決めればよいが、剛性が低い場合は構造部材7の間隔を狭める事が望ましい。
【0022】
このような構成をとることによって、構造部材7がバンプ5と電極6の接合個所の間に配置され支柱として機能するので、ベアチップIC2が加圧された時に等分布荷重が著しく低減された。
【0023】
その結果、加圧時の等分布荷重に起因したベアチップIC2の凹みがなくなり、ベアチップIC2のバンプ5とシリコン基板1の電極6の塑性変形量ばらつきが低減され、接合部の剥離が発生しなくなり、電気的接合信頼性が向上した。
【0024】
(第2の実施例)
図2−a、図2−bは、本発明の第2の実施形態を説明する図である。この実施形態は、第1の実施の形態において、構造部材7に、高耐熱性樹脂ボールの代わりに金属ボールの周りを高耐熱樹脂で被覆したボールを用いた以外は、第1の実施の形態と同じ構成である。
【0025】
このような構成でも第1の実施例と同様、構造部材7がバンプ5と電極6の接合個所の間に配置され支柱として機能するので、ベアチップIC2が加圧された時に等分布荷重が著しく低減された。
【0026】
その結果、加圧時の等分布荷重に起因したベアチップIC2の凹みがなくなり、ベアチップIC2のバンプ5とシリコン基板1の電極6の塑性変形量ばらつきが低減され、接合部の剥離が発生しなくなり、電気的接合信頼性が向上した。
【0027】
(第3の実施例)
図3−a、図3−bは、本発明の第3の実施形態を説明する図である。この実施形態は、第1の実施の形態において、構造部材7の形状がボールではなく、円柱であること以外は第1の実施の形態と同じ構成である。
【0028】
このような構成でも第1の実施例と同様、構造部材7がバンプ5と電極6の接合個所の間に配置され支柱として機能するので、ベアチップIC2が加圧された時に等分布荷重が著しく低減された。
【0029】
その結果、加圧時の等分布荷重に起因したベアチップIC2の凹みがなくなり、ベアチップIC2のバンプ5とシリコン基板1の電極6の塑性変形量ばらつきが低減され、接合部の剥離が発生しなくなり、電気的接合信頼性が向上した。
【0030】
以上、本発明の実施の形態について説明したが、本発明はこれに限定されるものではなく、基板としては、ガラスエポキシ基板、ガラス基板、セラミック基板など有機基板、無機基板で電子部品を搭載するものであれば全てに適用できる。同様に電子部品としては、能動部品、受動部品いずれであっても本発明を適用することができる。併せて、基板同士、電子部品同士の接合にも適用できる。
【0031】
また有機材料としては、NCF、ACP、NCPなど熱硬化性有機材料、あるいは光硬化性有機材料のいずれであっても本発明を適用することができる。
【0032】
【発明の効果】
以上説明したように、本発明は電子部品を有機材料を用いて基板に加熱、加圧接合、あるいは光照射、加圧接合する場合、電子部品のバンプと基板の電極による接続個所の間に位置するように、有機材料に予め構造部材を設けて接合することにより等分布荷重を著しく低減することが可能となった。
【0033】
その結果、電子部品や基板に撓みや凹みが発生しない接合構造となり、電子部品のバンプと基板の電極の塑性変形量ばらつきが低減され、電子部品と基板との電気接合部の剥離による接続不良が発生しなくなり接合信頼性が向上した。
【0034】
又、電子部品や基板にダミーのバンプや電極を形成する場合に比べ、電子部品や基板のサイズを小さくすることが可能となり、その結果電子部品と基板のコスト上昇も抑えることが可能となった。
【図面の簡単な説明】
【図1−a】本発明の第1の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す断面図である。
【図1−b】本発明の第1の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す上面図である。
【図2−a】本発明の第2の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す断面図である。
【図2−b】本発明の第2の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す上面図である。
【図3−a】本発明の第3の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す断面図である。
【図3−b】本発明の第3の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す上面図である。
【符号の説明】
1 シリコン基板
2 ベアチップIC
3 ACF
4 ACFに配置された構造部材(高耐熱性樹脂)
5 ベアチップICのバンプ
6 シリコン基板の電極
7 金属コアボール(構造部材)
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a joint structure between an electronic component and a substrate, an electronic component and an electronic component, and a substrate and a substrate, and relates to a technique for increasing the reliability of a joint.
[0002]
[Prior art]
For electronic components, thermosetting organic materials such as anisotropic conductive film (ACF), anisotropic conductive paste (ACP), non-conductive film (NCF) and non-conductive paste (NCP), or photo-curing When bonding to a substrate using an organic material, the film is sandwiched between the electronic component and the substrate, and is electrically connected by performing heating, pressure bonding, light irradiation, and pressure bonding.
[0003]
When joining an electronic component and a substrate by applying heat and pressure to the organic material or by applying light and pressure, the organic material between the bumps of the electronic component and the electrodes of the substrate is discharged and the bumps of the electronic component and the substrate are The electrodes are in contact with each other, and the electronic component and the substrate are electrically connected by the adhesive force of the organic material without leaving the organic material between the bump and the electrode.
[0004]
Furthermore, in order to reduce the evenly distributed load at the time of pressure bonding between the electronic component and the substrate, dummy bumps and electrodes are formed on the electronic component or the substrate for a purpose other than the original electrical connection. (See, for example, Patent Document 1).
[0005]
[Patent Document 1]
JP-A-9-68715
[Problems to be solved by the invention]
However, in the above conventional example, since dummy bumps and electrodes are formed on the electronic component and the substrate, it is necessary to provide an area irrelevant to the function of the component on the electronic component, and the electronic component and the substrate increase in size and the cost increases. There was a problem.
[0007]
If the degree of freedom in forming dummy bumps and electrodes on electronic components and substrates is low, the uniform distribution load will not be reduced during bonding, causing partial bending and dents, and the plasticity of electronic component bumps and electrodes on substrates will be reduced. Joining is performed in a state where the amount of deformation varies, and in the worst case, there is a problem that an electrical joint between the electronic component and the substrate is peeled off and becomes electrically open.
[0008]
The present invention has been made in order to solve the above-described problems, and when an electronic component is heated and pressed and bonded to a substrate with an organic material interposed therebetween, or when light irradiation and pressure bonding are performed, the electronic component and the substrate are bonded. It is an object of the present invention to provide a bonding structure that suppresses a rise in cost while improving the bonding reliability of an electronic component and a substrate without forming dummy bumps and electrodes, and an electronic device provided with the bonding structure.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a first invention according to the present application provides a structural member in an organic material for heating and pressure bonding an electronic component and a substrate so as to be located between bumps of the electronic component and electrodes of the substrate. It is characterized by having. In particular, when the connection point between the bump of the electronic component and the electrode of the substrate is apart from each other, providing the structural member has a great effect.
[0010]
In the above configuration, since the structural member disposed in the organic material is present between the bumps and the electrodes, the support by the structural member is used in the case where the electronic component and the substrate are joined by heating and pressure, or in the case of light irradiation and pressure joining. Are formed, the uniform distribution load is significantly reduced.
[0011]
Accordingly, a bonding structure in which bending or dent is unlikely to occur in the electronic component or the substrate is obtained, the variation in the amount of plastic deformation between the bump and the electrode is reduced, and the electrical bonding portion between the electronic component and the substrate does not peel.
[0012]
Further, the size of the electronic component or the substrate can be reduced as compared with the case where dummy bumps or electrodes are formed on the electronic component or the substrate.
[0013]
As a result, the bonding reliability between the electronic component and the substrate is improved, and at the same time, it is possible to suppress an increase in cost.
[0014]
In addition, if it explains in more detail, this invention could solve the said subject by the following structures.
[0015]
(1) In a joining structure in which an electronic component and a substrate are joined by a curing shrinkage force and a heat shrinkage force of an organic material, the electronic component and the substrate are heated and pressed by using an organic material in which a structural member is arranged in a predetermined position in advance. A joining structure characterized by joining.
[0016]
(2) In a joining structure in which the electronic component and the electronic component are joined by the curing shrinkage force and the heat shrinkage force of the organic material, the electronic component and the electronic component are heated by using an organic material in which a structural member is arranged in a predetermined position in advance. A joining structure characterized by pressure joining.
[0017]
(3) In a bonding structure in which the substrate and the substrate are bonded by the curing shrinkage force and the heat shrinkage force of the organic material, the substrate and the substrate are heated and pressed by using an organic material in which a structural member is arranged at a predetermined position in advance. A joint structure characterized by the above.
[0018]
(4) An electronic device comprising an electronic component and a substrate having the joint structure according to (1) or (2).
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
FIG. 1A is a view best showing the features of the present invention. A bare chip IC 2 is thermocompression-bonded to a silicon substrate 1 with an ACF 3, and ACF 3 is discharged from between a bump 5 of the bare chip IC 2 and an electrode 6 of the silicon substrate 1. A state in which the bumps 5 and the electrodes 6 are in contact with each other and are electrically connected is shown from a cross section, and FIG. 1B is shown from the top.
[0020]
In FIG. 1, a structural member indicated by 7 is a structural member formed in advance on the ACF 3 and uses a resin ball having high heat resistance. The height of the structural member 7 may be determined in accordance with the thickness of the bump 5 of the bare chip IC 2 and the thickness of the electrode 6 of the silicon substrate 1. However, the height of the gap 5 is determined by thermocompression bonding of the bump 5 and the electrode 6 and plastic deformation. It is desirable to match.
[0021]
The interval at which the structural members 7 are arranged may be determined according to the rigidity of the bare chip IC to be pressed. However, if the rigidity is low, it is desirable to reduce the interval between the structural members 7.
[0022]
By adopting such a configuration, the structural member 7 is disposed between the joining portions of the bumps 5 and the electrodes 6 and functions as a support. Therefore, when the bare chip IC 2 is pressed, the uniform distribution load is significantly reduced.
[0023]
As a result, the dent of the bare chip IC 2 due to the uniform distribution load at the time of pressurization is eliminated, the variation in the amount of plastic deformation between the bump 5 of the bare chip IC 2 and the electrode 6 of the silicon substrate 1 is reduced, and the peeling of the joint does not occur. The electrical connection reliability has been improved.
[0024]
(Second embodiment)
FIG. 2A and FIG. 2B are diagrams illustrating a second embodiment of the present invention. This embodiment is the same as the first embodiment except that a ball having a metal ball covered with a high heat-resistant resin is used for the structural member 7 instead of the high heat-resistant resin ball in the first embodiment. It has the same configuration as.
[0025]
Even in such a configuration, similarly to the first embodiment, the structural member 7 is disposed between the joints of the bumps 5 and the electrodes 6 and functions as a support. Therefore, when the bare chip IC 2 is pressed, the uniformly distributed load is significantly reduced. Was done.
[0026]
As a result, the dent of the bare chip IC 2 due to the uniform distribution load at the time of pressurization is eliminated, the variation in the amount of plastic deformation between the bump 5 of the bare chip IC 2 and the electrode 6 of the silicon substrate 1 is reduced, and the peeling of the joint does not occur. The electrical connection reliability has been improved.
[0027]
(Third embodiment)
FIGS. 3A and 3B are diagrams illustrating a third embodiment of the present invention. This embodiment has the same configuration as the first embodiment, except that the shape of the structural member 7 is not a ball but a cylinder.
[0028]
Even in such a configuration, similarly to the first embodiment, the structural member 7 is disposed between the joints of the bumps 5 and the electrodes 6 and functions as a support. Therefore, when the bare chip IC 2 is pressed, the uniformly distributed load is significantly reduced. Was done.
[0029]
As a result, the dent of the bare chip IC 2 due to the uniformly distributed load at the time of pressurization is eliminated, the variation in the amount of plastic deformation between the bumps 5 of the bare chip IC 2 and the electrodes 6 of the silicon substrate 1 is reduced, and the peeling of the joint does not occur. The electrical connection reliability has been improved.
[0030]
As described above, the embodiments of the present invention have been described, but the present invention is not limited to this, and as the substrate, an organic substrate such as a glass epoxy substrate, a glass substrate, a ceramic substrate, and an electronic component mounted on an inorganic substrate are mounted. It can be applied to all things. Similarly, the present invention can be applied to an electronic component whether it is an active component or a passive component. In addition, the present invention can be applied to bonding between substrates and between electronic components.
[0031]
In addition, the present invention can be applied to any organic material such as a thermosetting organic material such as NCF, ACP, and NCP, or a photocurable organic material.
[0032]
【The invention's effect】
As described above, according to the present invention, when an electronic component is heated, press-bonded, or irradiated with light or press-bonded to a substrate using an organic material, the electronic component is located between the bumps of the electronic component and the connection points of the electrodes of the substrate. As described above, by providing a structural member in advance on an organic material and joining the same, it is possible to significantly reduce an evenly distributed load.
[0033]
As a result, a bonding structure in which no bending or dent is generated in the electronic component or the substrate is obtained, the variation in the amount of plastic deformation between the bump of the electronic component and the electrode of the substrate is reduced, and the connection failure due to the separation of the electrical bonding portion between the electronic component and the substrate is reduced. No longer occurs, and the bonding reliability is improved.
[0034]
Also, compared to the case where dummy bumps or electrodes are formed on an electronic component or a substrate, the size of the electronic component or the substrate can be reduced, and as a result, it is possible to suppress an increase in the cost of the electronic component and the substrate. .
[Brief description of the drawings]
FIG. 1A is a diagram illustrating a first embodiment of the present invention, and is a cross-sectional view showing a state in which a bare chip IC and a silicon substrate are joined via an ACF.
FIG. 1B is a view for explaining the first embodiment of the present invention, and is a top view showing a state in which a bare chip IC and a silicon substrate are joined via an ACF.
FIG. 2A is a diagram illustrating a second embodiment of the present invention, and is a cross-sectional view illustrating a state in which a bare chip IC and a silicon substrate are joined via an ACF.
FIG. 2B is a view for explaining the second embodiment of the present invention, and is a top view showing a state where the bare chip IC and the silicon substrate are joined via the ACF.
FIG. 3A is a diagram illustrating a third embodiment of the present invention, and is a cross-sectional view illustrating a state in which a bare chip IC and a silicon substrate are joined via an ACF.
FIG. 3B is a view for explaining the third embodiment of the present invention, and is a top view showing a state in which the bare chip IC and the silicon substrate are joined via the ACF.
[Explanation of symbols]
1 silicon substrate 2 bare chip IC
3 ACF
4 Structural members arranged on ACF (high heat resistant resin)
5 Bump of bare chip IC 6 Electrode of silicon substrate 7 Metal core ball (structural member)

Claims (4)

電子部品と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と基板を加熱、加圧接合したことを特徴とする接合構造。In a joining structure in which the electronic component and the substrate are joined by the curing shrinkage force and the heat shrinkage force of the organic material, the electronic component and the substrate are heated and pressed by using an organic material in which a structural member is arranged in a predetermined position in advance. A joining structure characterized by: 電子部品と電子部品が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と電子部品を加熱、加圧接合したことを特徴とする接合構造。In a joining structure in which an electronic component and an electronic component are joined by a curing shrinkage force and a heat shrinkage force of the organic material, the electronic component and the electronic component are heated and pressed by using an organic material in which a structural member is arranged in a predetermined position in advance. Bonding structure characterized by doing. 基板と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて基板と基板を加熱、加圧接合したことを特徴とする接合構造。In a bonding structure in which the substrate and the substrate are bonded by the curing shrinkage force and the heat shrinkage force of the organic material, the substrate and the substrate are heated and pressed by using an organic material in which a structural member is arranged in a predetermined position in advance. And joining structure. 請求項1または請求項2記載の接合構造を持った電子部品と基板を搭載したことを特徴とする電子機器。An electronic device comprising an electronic component having the joint structure according to claim 1 and a substrate.
JP2002291108A 2002-10-03 2002-10-03 Joint structure and electronic equipment equipped with the same Withdrawn JP2004128259A (en)

Priority Applications (1)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007039959A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
WO2007039960A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
JP2011176143A (en) * 2010-02-24 2011-09-08 Sumitomo Bakelite Co Ltd Conductive connection sheet, method of connecting between terminals, method of forming connection terminal, semiconductor device, and electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007039959A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
WO2007039960A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
US8013454B2 (en) 2005-10-05 2011-09-06 Sharp Kabushiki Kaisha Wiring substrate and display device including the same
JP2011176143A (en) * 2010-02-24 2011-09-08 Sumitomo Bakelite Co Ltd Conductive connection sheet, method of connecting between terminals, method of forming connection terminal, semiconductor device, and electronic device

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