JP2004112836A - System and method of receiving orthogonal frequency division multiplexing signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a receiver side to easily receive an accurate synchronizing signal, when the receiver side receives an OFDM signal. <P>SOLUTION: A transmitter side of an OFDM signal has an IFFT circuit for generating a multilevel QAM signal, a guard interval setting circuit, and a clock signal generating circuit for driving both circuits. Phases are set at predetermined values at starting points of a plurality of symbol sections by the IFFT circuit, a pilot signal having a high order frequency having a predetermined frequency ratio with a clock signal. The pilot signal is continuously sent out over a plurality of symbol sections including guard interval sections. A receiver side obtains the pilot signal by demodulation to generate an accurate clock signal for driving the system. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to an OFDM (Orthogonal Frequency Division Multiplexing) signal receiving apparatus, and more particularly to a receiving apparatus for receiving an OFDM signal suitable for digital mobile communication and an OFDM signal receiving method.

  A conventional OFDM signal transmitting apparatus will be described with reference to FIG.

  First, a digital information data signal is supplied to a serial-parallel conversion circuit 70 via an input terminal, and an error correction code is added as necessary.

  The output signal of this circuit 70 is supplied to an IFFT circuit 71, and the output signal is supplied to a D / A converter 73 via a guard interval circuit 72 for reducing multipath distortion.

  Here, the signal is converted into an analog signal, and only components in a necessary frequency band are passed by the next LPF 74.

  Output signals of the analog real and imaginary parts are supplied to a quadrature modulator 75, and an OFDM signal is output.

  This OFDM signal is frequency-converted by a frequency converter 76 into a frequency band to be transmitted, supplied to the next transmitting unit 77, and transmitted via a linear amplifier and a transmitting antenna constituting the same.

  The output signal of the intermediate frequency generation circuit 78 and the signal via the 90 ° shift circuit 78A are supplied to the quadrature modulator 75, respectively.

  The output signal of the circuit 78 is supplied to a clock signal generation circuit 79.

  The output clock signal of the circuit 79 is supplied to the serial-parallel conversion circuit 70, the IFFT circuit 71, the guard interval circuit 72, and the D / A converter 73, respectively.

  Next, a conventional OFDM signal receiving apparatus will be described with reference to FIG.

  A receiving unit 80 amplifies a signal from the transmitting unit 77 obtained by a receiving antenna constituting the same by a high frequency amplifier, and converts the carrier frequency to an intermediate frequency via a frequency converter 81, thereby providing an intermediate frequency amplifying circuit. 82, and further supplied to a quadrature demodulator 83.

  An output signal of the circuit 82 is supplied to an intermediate frequency generation circuit 89 via a carrier detection circuit 90.

  The output signal of the circuit 89 and the signal passed through the 90 ° shift circuit 89A are respectively supplied to the quadrature demodulator 83, and the output signals of the real and imaginary parts are decoded.

  The output signal of the quadrature demodulator 83 is supplied to an A / D converter 85 via an LPF 84 and is converted into a digital signal. The output signal of the quadrature demodulator 83 is also supplied to a synchronization signal generation circuit 91. .

  The output of the A / D converter 85 is supplied to the FFT / QAM decoding circuit 87 via the next guard interval circuit 86.

  The FFT / QAM decoding circuit 87 performs a complex Fourier operation based on the supplied synchronization signal of the synchronization signal generation circuit 91, and outputs a real part and an imaginary part signal (real part, imaginary part) for each frequency of the input signal. , The level of the quantized digital signal transmitted by the digital information transmission carrier is determined, and the digital information is decoded.

  The output signal of the FFT / QAM decoding circuit 87 is output via the parallel / serial conversion circuit 88.

  Here, if the intermediate frequency of the transmitting device and the intermediate frequency of the receiving device completely match, only the modulation component can be obtained, and there is no problem. However, the intermediate frequency generating circuit and the local oscillator of the frequency converter (not shown) ), If the frequency stability is not high, or if there is a phase error between the two output signals, the subsequent demodulation operation will be affected, and the probability of occurrence of a symbol error will increase.

  In a receiving apparatus that receives a transmitted OFDM signal, it is very difficult to completely reproduce the phases of all the received carriers without having a time-axis fluctuation component. A guard interval circuit is set on the transmission side to reduce the transmission.When receiving a transmission signal under such conditions, the phase of the transmission signal between the transmission side and the effective symbol period part and the guard interval part is set. There is a problem that it is more difficult to reproduce in exactly the same state.

  The present invention has been made in view of the above points, and an OFDM signal receiving apparatus in which a specific carrier of OFDM is set as a pilot signal carrier so that a synchronization relationship on a receiving side can be kept constant. And an OFDM signal receiving method.

  The present invention comprises the means described in the following 1) or 2).

That is,
1) An orthogonal frequency division multiplexed signal receiving apparatus for receiving a multilevel QAM modulated digital information signal that is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added,
The guard interval has a higher-order frequency which is present as a discontinuous waveform at the head, is multiplied by 4 and exists as a signal of a single frequency, and is held in opposite phases in adjacent effective symbol sections. A pilot signal demodulation means for obtaining information on the polarity of the pilot signal by phase demodulating the pilot signal transmitted as a constant signal, and a driving signal based on the polarity information obtained by the pilot signal demodulation means. Signal generating means for generating, and FFT means driven by the driving signal generated by the signal generating means and converting the multi-level QAM modulated signal to the digital information signal;
An orthogonal frequency division multiplexed signal receiving apparatus comprising:
2) A method for receiving an orthogonal frequency division multiplexed signal which receives a multilevel QAM modulated digital information signal which is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added,
In the guard interval, a high-order frequency that is present as a discontinuous waveform at the head and is present as a signal of a single frequency after being quadrupled and held in opposite phases in adjacent effective symbol sections, and A first step of phase demodulating the pilot signal transmitted as a constant signal to obtain information on the polarity of the pilot signal,
A second step of generating a drive signal based on the polarity information obtained in the first step;
A third step of being driven by the driving signal generated in the second step and performing an FFT on the multi-level QAM modulated signal to obtain the digital information signal;
A method for receiving an orthogonal frequency division multiplexed signal.

In the OFDM signal receiving apparatus and the OFDM signal receiving method according to the present invention, the guard interval has a discontinuous waveform at the head and a quadruple frequency as a signal of a single frequency. The phase information of the pilot signal transmitted as a signal having a constant amplitude and a higher frequency having an integer frequency ratio relationship with the clock signal held in the phase demodulation is obtained to obtain the polarity information of the pilot signal. , A FFT is performed using the driving signal, and it is easy to set the same time relationship between the IFFT circuit that operates on the transmitting side and the FFT circuit that operates on the receiving side. That is, the FFT operation having the same time relationship as the IFFT operation can be performed, and more accurate information can be received.

Furthermore, since the symbol synchronization information is inserted into the pilot signal transmitted as the information signal, the synchronization signal can be decoded before the time division synchronization signal arrives. Has the effect of being able to perform decryption.

  Embodiments of an orthogonal frequency division multiplexing signal receiving apparatus and an OFDM signal transmitting / receiving apparatus adapted to a method of receiving an orthogonal frequency division multiplexing signal according to the present invention will be described below with reference to FIGS.

  FIG. 1 shows an embodiment of an OFDM signal transmitting apparatus applied to the present invention. Digital data transmitted here is compressed audio and video signals.

  An OFDM signal transmitting apparatus arranges a large number of carriers orthogonally, and transmits independent digital information on each carrier. Since the carriers are orthogonal, the spectrum of the adjacent carrier is determined by the frequency position of the carrier. Becomes zero.

  IFFT circuit technology is used to create this orthogonal carrier. If an inverse DFT (Discrete Fourier Transform) using N complex numbers is performed during a time interval T which is a window section in the IFFT, an OFDM signal can be generated, and each point of the inverse DFT corresponds to a modulation signal output. The N is also referred to as an IFFT or FFT cycle. For details, see pages 74 to 75 of "Television Society of Japan, edited by Seiji Imai, Signal Processing Engineering" published by Corona Corporation (issued on May 20, 1993). It is explained in.

The basic specifications of the apparatus according to the present embodiment shown in FIGS. 1 and 2 are as shown below.
(a) Center carrier frequency: 100 MHz (b) Number of transmission carriers: 248 waves
(c) Modulation method: 256QAM OFDM (d) Number of carriers used: 257 waves
(e) Transmission bandwidth: 100 kHz, bandwidth used: 99 kHz
(f) Transfer rate: 750 kbps (g) Guard interval: 60.6 μsec
As shown in FIG. 1, for example, a digital information signal, which is an audio or video signal in which an information signal is compressed by an encoding method such as MPEG, is supplied to a serial-parallel conversion circuit 2 via an input terminal 1. An error correction code is assigned accordingly.

  In this circuit 2, the input signal is arranged as a signal for 256QAM modulation and output.

  The 256 QAM modulation is a system in which 16 levels are defined in the amplitude direction and 16 levels in the angle direction for each carrier to transmit information, and 256 values of 16 × 16 are specified and transmitted.

  In this embodiment, information is transmitted using 248 waves out of 257 carriers, and the remaining 9 waves are used for calibration and for transmitting other auxiliary signals.

  The serial-parallel conversion circuit 2 is configured to output 248 bytes of digital data during one symbol period, that is, 248 sets of 4-bit parallel data during one symbol period.

  The output signal of the serial-parallel conversion circuit 2 is supplied to an IFFT / pilot signal generation circuit 3. The circuit 3 operates by the clock signal output from the clock signal generation circuit 10, performs 256 QAM modulation on the 248 wave carrier, and outputs each output signal as a real and imaginary component.

In the IFFT / pilot signal generation circuit 3, an IFFT circuit having a period of N is used, and discrete frequency point information corresponding to N discrete frequency points (sample points) in each effective symbol period set by the IFFT circuit. Is output from the IFFT and pilot signal generation circuit 3.

The Nyquist frequency corresponds to １ ／ of the sample clock frequency in the IFFT of the period N, and the pilot signal is transmitted as information of the Nyquist frequency, that is, Nyquist frequency information. Since the Nyquist frequency is の of the sample clock frequency, the receiving device can decode and multiply the Nyquist frequency information to generate a sampling position signal (sample clock signal) for operating the FFT circuit. .

  The Nyquist frequency information is obtained by applying a signal of a constant level to the N / 2-th frequency terminal of the real part input terminal R (imaginary part input terminal I) of the IFFT of the IFFT and pilot signal generation circuit 3.

  The output signals of these IFFT and pilot signal generation circuits 3 are supplied to a guard interval setting circuit 4 having the following RAM (random access memory) 4A, and the guard interval setting circuit 4 reduces multipath distortion in the transmission path. A guard interval gi of a predetermined section for performing the setting is set as shown in FIG.

  The guard interval setting circuit 4 operates by the clock signal output from the clock signal generation circuit 10 and sets the last part in the window section (effective symbol period ts) obtained from the IFFT and pilot signal generation circuit 3 to the window section. Place it just before.

In order to set the guard interval, the guard interval setting circuit 4 reads the signal from the IFFT / pilot signal generation circuit 3 which is taken into the RAM (4A) of the guard interval setting circuit 4 and reads the last period of the effective symbol period ( This period is set to be equal to gi.), the process returns to the beginning of the effective symbol period, the data of the effective symbol period ts is read, and the signal of the symbol period ta is transmitted.

  The Nyquist frequency information (pilot signal) is transmitted even within the guard interval, but in order to maintain continuity with the preceding and following IFFT window section signals, the transmitted pilot signal has an integer wavelength within the guard interval. Let

Although the case where the Nyquist frequency is used as the pilot signal has been described, the Nyquist frequency does not necessarily have to be used as long as it has a simple integer ratio relationship with the sample clock signal. You may.

When considering an IFFT with a period M, a pilot signal is arranged at a position １ ／ of the Nyquist frequency, that is, at the M / 4th frequency, and the carrier transmitted by OFDM is the M / 4th from the first in the IFFT. , And signals output as 3M / 4th to Mth.

  As described above, even if an IFFT with a period M = 2N is used, an output signal of an IFFT equivalent to the case of using an IFFT with a period N can be obtained. Therefore, a continuous pilot signal including a guard interval can be transmitted, and a sample clock signal can be obtained by decoding the pilot signal and quadrupling the pilot signal.

  If the window section signal information of the FFT can be separately decoded, the FFT operation of the OFDM signal can be performed in combination with the sample clock signal obtained according to the present embodiment, and the OFDM signal can be decoded.

  Next, the symbol period set by the guard interval setting circuit 4 will be described with reference to FIG.

  First, when the used bandwidth is 99 kHz and the IFFT cycle is N = 256, the effective symbol frequency fs and the effective symbol period ts are as follows, respectively.

fs = 99,000 / 256 = 387Hz
ts = 1 / fs = 2586 μsec
If the guard interval period gi, which is a multipath distortion removal section, is determined to be equal to three wavelengths of the pilot signal, gi is set as follows.

gi = (1 / 49,500) × 3 = 60.6 μsec
At this time, the symbol period ta and the symbol frequency fa are respectively as follows.

ta = ts + gi = 2586 + 60.6 = 2646.6 μsec
fa = 1 / ta = 378 Hz
The output signals of the guard interval setting circuit 4 are supplied to a D / A converter 5, where they are converted into analog signals, and only components in a required frequency band are passed by the next LPF 6.

  The real and imaginary output signals of the analog value are supplied to the next quadrature modulator 7, which outputs the output signal of the 10.7 MHz intermediate frequency generation circuit 9 and the signal via the 90 ° shift circuit 8. Are supplied, and an OFDM signal is output.

  The OFDM signal is frequency-converted by the frequency converter 11 into a frequency band to be transmitted, supplied to the next transmission unit 12, and transmitted via the linear amplifier and the transmission antenna constituting the transmission unit.

  The output signal of the 10.7 MHz intermediate frequency generation circuit 9 is also supplied to the clock signal generation circuit 10. In the clock signal generation circuit 10, a clock signal for driving the IFFT and pilot signal generation circuit 3 and a clock signal for driving the guard interval setting circuit 4 are a common clock signal supplied from the intermediate frequency generation circuit 9. Generated based on

  Since the 248 sets of 4 + 4 bit parallel data are transmitted by 248 wave carriers, the transmission speed of this apparatus is 248 bytes per symbol period. Therefore, the transmission rate per second is approximately 750 Kbits.

  Next, the phase relationship between the guard interval, the symbol period and the synchronization signal (pilot signal) will be described below with reference to the drawings.

Here, the description according to FIGS. 7 to 9 is described as a reference example of the present embodiment.

In FIG. 7 shown as a reference example, a case where a synchronization signal (pilot signal) having the same phase is generated in each symbol period and a synchronization signal having an integer wavelength exists in a guard interval will be described. (This is a first example of generating a continuous synchronization signal without inverting the polarity.)
The IFFT shown in FIG. 7 is synonymous with the effective symbol period and the IFFT period, and one cycle at the end (right part) of the IFFT period is used as it is as a signal of the guard interval G before (left part) of the IFFT period. .

  In this example, a synchronization signal (pilot signal) having the same phase is generated every IFFT period, and the synchronization signal (pilot signal) has an integer wave in the guard interval section, so that the pilot signal is generated over a plurality of symbol periods. Generated continuously.

  The case of FIG. 3 described above is the same as the case of FIG. 7, and since the synchronization signal (pilot signal) has an integer wave in the guard interval, the pilot signal is continuously generated over a plurality of symbol periods. I have.

In FIG. 8 shown as a reference example, a case will be described where a synchronization signal (pilot signal) having the same phase is generated in every other symbol period and a synchronization signal having an odd multiple of a half wavelength exists in the guard interval. (This is a second example of generating a continuous synchronization signal without inverting the polarity.)
The IFFT is synonymous with the effective symbol period and the IFFT period, and a half cycle at the end (right) of the IFFT period is used as it is as a signal of the guard interval before (left) the IFFT period.

  In this example, a synchronization signal (pilot signal) of reverse polarity is generated for each IFFT period, and a synchronization signal having an odd multiple of a half wavelength exists in the guard interval, so that a plurality of symbol periods (symbol periods) are present. The pilot signal is continuously generated.

In FIG. 9 shown as a reference example, a case where a synchronization signal exists in the guard interval G at an odd multiple of a half wavelength will be described. (This is a first example of generating a synchronization signal with inverted polarity.)
In this case, the polarity of the pilot signal is inverted at the start point of the guard interval, and the phase of the pilot signal in each symbol period is the same.

  That is, the terminal voltage corresponding to the frequency at which the IFFT synchronization signal for generating the frequency division multiplex signal is generated is fixed for each symbol, and the synchronization signal having the same phase is always generated.

  Therefore, when the guard interval is an odd multiple of half a wavelength, the synchronization signal becomes a continuous signal if the polarity of the synchronization signal is inverted every other symbol period on the receiving device side.

  In this case, a synchronization signal can be detected using a PLL circuit in a phase synchronization circuit as shown in FIG.

In FIG. 10 according to the embodiment of the present invention, a case where a synchronization signal (pilot signal) exists in the guard interval, which is an even multiple of a half wavelength, will be described. (This is a second example of generating a synchronization signal with inverted polarity.)
As shown in FIG. 10, even when the synchronization signal (pilot signal) existing in the guard interval is an integer wave (an even multiple of half a wavelength), the synchronization signal is transmitted in the symbol period 1 as in the case of FIG. If the output is inverted every other time, a synchronous output whose polarity is inverted for each symbol is obtained.

  Also in this case, the synchronization signal can be detected using a PLL circuit as shown in FIG.

  FIG. 11 is an example of a phase synchronization circuit applied to the present invention that detects a synchronization signal inverted every other symbol period.

  This phase-locked loop circuit switches the VCO output of a PLL circuit composed of a phase comparator PD2 (112), Amp (amplifier # 113), LPF (114), and VCO circuit (115) by an exclusive OR. In this configuration, the container 116 is inserted.

  The phase comparator PD1 (111) forms a synchronous detection circuit that receives the VCO output of the phase synchronous circuit as an input. The frequency division multiplexed signal including the synchronization signal applied to the input terminal 110 is input to both the phase synchronization circuit and the synchronization detection circuit PD1 (111). This phase synchronization circuit is composed of a PLL composed of a phase comparator PD2 (112), an amplifier (113), an LPF (114), a VCO (115), and a signal switch (116).

  The output of the VCO circuit 115 of the PLL is inverted by the signal switch (116) in accordance with the output of the PD1 (111) that has been synchronously detected. Since the VCO output whose polarity has been inverted is supplied to the phase comparator PD2 (112) which is detected by the detection circuit and constitutes the PLL, the lock operation is continuously performed even for the synchronization signal whose polarity has been inverted.

  FIG. 12 shows output waveforms at terminals B and A in FIG. Output A is a synchronization signal output waveform, and output B is a symbol synchronization signal transmitted with its polarity inverted for each symbol period (symbol period).

  FIG. 13 is another circuit example corresponding to FIG. 11, in which the signal switch 136 is inserted between the phase comparator PD2 (132) and the amplifier 133.

  The synchronous signal is detected at the same time as the synchronous signal is inverted, and the polarity of the error signal is inverted. The operation is performed in the same manner as in FIG. In any case, even if the synchronization signal is inverted every other symbol period (symbol period), it is detected and the characteristics of the PLL loop are inverted, so that the VCO continues continuous operation without being inverted. . Therefore, decoding of the synchronization signal can be performed normally.

  Next, an embodiment of an OFDM signal receiving apparatus applied to the present invention will be described with reference to FIGS.

Each component of the receiving device is constituted by a circuit that operates in the opposite direction to the transmitting device.
The receiving unit 20 amplifies the signal from the transmitting unit 12 obtained by the receiving antenna constituting the receiving unit 20 with a high-frequency amplifier and supplies the amplified signal to the frequency converter 21.

  This output signal is supplied to the intermediate frequency amplifier circuit 22, and is output from the intermediate frequency amplifier circuit 22 as a reception signal of a predetermined level.

  The output signal of the intermediate frequency amplification circuit 22 is supplied to a quadrature demodulator 23 and a carrier detection (carrier extraction) circuit 29, respectively.

  The carrier detection circuit 29 has a PLL circuit including a phase comparator (multiplier) 41, an LPF 42, a VCO circuit 43, and a 1/4 frequency dividing circuit 45 illustrated in FIG. The intermediate frequency oscillation circuit 31 is a circuit that extracts the center carrier with a small phase error.

  In the present embodiment, carriers for transmitting information are arranged adjacent to each other at every 378 Hz which is a symbol frequency, and constitute an OFDM signal. The information carrier adjacent to the center carrier is also separated by only 378 Hz. The center carrier needs to transmit information without being affected by the adjacent information carrier, and a circuit with high selectivity is used.

  In this embodiment, the center carrier is extracted by using a PLL circuit. A quartz oscillator (VCXO) oscillating at about ± 200 Hz, which is approximately の of the interval between adjacent carrier frequencies, is connected to a voltage controlled oscillator (VCO) 43. To operate the circuit. The LPF used in the PLL circuit has a cutoff frequency sufficiently lower than 378 Hz.

  The output signal of the intermediate frequency generating circuit 31 and the signal passed through the 90 ° shift circuit 30 are supplied to a quadrature demodulator 23 having multipliers 40 and 41, respectively, to output real and imaginary parts (real part and imaginary part). The output signal is decoded.

  The real part and imaginary part output signals are supplied to the LPF 24, pass through signals of a required frequency band transmitted as OFDM signal information, sample input analog signals, and A / D convert the output signals. (Sampling circuit) 25 to convert the signal into a digital signal.

  In the sample synchronizing signal generating circuit 32, a sample clock signal before frequency multiplication is generated by a PLL circuit which is phase-synchronized with a pilot signal, and an analog output signal of the quadrature demodulator 23 is supplied to this circuit. The PLL is phase-synchronized with the pilot signal transmitted as a continuous signal in each symbol section including the guard interval period, and a demodulated pilot signal is obtained.

  In the transmitting apparatus, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and performs frequency multiplication according to the frequency ratio to obtain a sample clock signal.

  The guard interval processing circuit 26 can obtain an effective symbol period signal of the period ts at an arbitrary timing within the symbol period ta from the transmitted signal, and from the effective symbol period signal of which the influence of the multipath distortion is smaller, Then, the output signal is supplied to the FFT / QAM decoding circuit 27.

  The symbol synchronization signal generation circuit 33 for detecting the symbol period detects the symbol period.

  The next FFT / QAM decoding circuit 27 is supplied with the obtained clock synchronization signal and symbol synchronization signal, performs a complex Fourier operation, and outputs a real part and imaginary part signal (real part, imaginary part signal) for each frequency of the input signal. Imaginary part) level.

  The real part of each frequency obtained in this way, the imaginary part signal level, and the real part of each carrier to be transmitted, comparing the demodulated output of the reference carrier for transmitting the reference value of the imaginary part, The level of the quantized digital signal transmitted by the digital information transmission carrier is determined, and the digital information is decoded.

  The output signal of this circuit 27 is output via a parallel / serial conversion circuit 28.

  Next, the carrier detection circuit 29 and the sample synchronization (sample clock) signal generation circuit 32 will be described below with reference to FIG.

  The purpose of this circuit is to extract a pilot signal transmitted at a certain level and to generate an accurate sample synchronization (sample clock) signal based on the extracted pilot signal.

  First, the VCO circuit 43 constituting the carrier detection circuit 29 is oscillated at a frequency of 42.8 MHz which is four times the intermediate frequency 10.7 MHz. The output signal of the VCO circuit 43 is supplied to multipliers 40 and 41 via quarter frequency divider circuits 44 and 45, respectively.

  An output signal from one of the multipliers 41 is supplied to an LPF 42 to extract a component equal to or lower than a symbol frequency, and the output signal controls a VCO circuit 43.

  A loop including the multiplier 41, the LPF 42, the VCO circuit 43, and the frequency divider 45 forms a PLL circuit.

  The intermediate frequency-amplified signal is applied to the input terminals of the multipliers 40 and 41, and orthogonal decoding is performed by this circuit, and output signals of a real part and an imaginary part are obtained.

  The sample synchronization signal generation circuit 32 is supplied with the real part output signal from the quadrature demodulator 23 and detects a Nyquist frequency component transmitted as a pilot signal.

  The output signal of the VCO circuit 43 is supplied to the frequency division ratio variable circuit (VCO circuit) 50, and the frequency division ratio is set to be from 1/426 to 1/438. The multiplier 52 in the sample synchronization signal generating circuit 32 is supplied with the output signal from the quadrature demodulator 23 and the signal of the VCO circuit through the 1/2 frequency dividing circuit 51, and operates as a phase comparator. Do.

  The output signal of the multiplier 52 is passed by the LPF circuit 53 only through an error signal relating to frequency control. The delay circuit 54 and the addition circuit 55 are circuits for attenuating adjacent carrier components, and have a characteristic of giving a dip to the symbol frequency of 387 Hz.

  In a PLL circuit composed of a VCO circuit (division ratio variable circuit) 50, a multiplier 52, and an LPF 53, a VCO output synchronized with a continuous pilot signal included in a real part output signal of a quadrature demodulator 23 of a carrier extraction unit. The signal is oscillated and output as a 99 kHz sample clock output signal.

  In the above embodiment, the case where an IFFT having a period of 256 is used to generate carriers of 257 waves has been described. However, as another embodiment, an example in which an IFFT having a period of 512 is used will be described below.

  In the embodiment using the IFFT having a period of 512, the Nyquist frequency is not used as the pilot frequency, but a high-order frequency having a simple integer ratio relationship with the sample clock signal is used.

  That is, when considering an IFFT with a period M, a pilot signal is arranged at a position of 1/2 of the Nyquist frequency, that is, at the M / 4th frequency, and the carrier to be transmitted by OFDM is M / Mth than the first in the IFFT. The signals output up to the fourth and from the 3M / 4th to the Mth are used.

  As described above, even if an IFFT with a period M = 2N is used, an output signal of an IFFT equivalent to the case of using an IFFT with a period N can be obtained. Therefore, a continuous pilot signal including a guard interval can be transmitted, and a sample clock signal can be obtained by decoding the pilot signal and quadrupling the pilot signal.

  In the sample synchronization signal generating circuit used at this time, the frequency of the pilot signal is the same as that of the embodiment in which the period N is 256, but the sample clock frequency for driving the FFT / QAM decoding circuit 27 shown in FIG. This is twice as long as the period N is 256. In accordance therewith, a double 198 kHz sample clock signal is output.

  Therefore, in this sample synchronization signal generating circuit, the dividing ratio of the dividing ratio variable circuit 50 is 1/213 to 1/219, and the dividing ratio of the 1/2 dividing circuit 51 is 1 / 4, and the other configuration is the same as that of FIG. 4, and the description thereof is omitted.

FIG. 3 is a block diagram of an embodiment of an OFDM signal transmission device applied to the present invention. It is a block diagram of an example of an OFDM signal receiving device of the present invention. FIG. 5 is a diagram illustrating a relationship between a symbol period of an OFDM signal and a guard interval according to an embodiment of the present invention. FIG. 4 is a block diagram of a carrier extraction unit and a sample synchronization signal generation unit of the OFDM signal receiving device according to an embodiment of the present invention. FIG. 11 is a block diagram of a conventional OFDM signal transmission device. FIG. 11 is a block diagram of a conventional OFDM signal receiving device. FIG. 3 is a diagram illustrating a relationship between a synchronization signal and a symbol period. FIG. 3 is a diagram illustrating a relationship between a synchronization signal and a symbol period. FIG. 3 is a diagram illustrating a relationship between a synchronization signal and a symbol period. FIG. 4 is a diagram illustrating a relationship between a synchronization signal and a symbol period according to the embodiment of the present invention. FIG. 2 is a diagram showing an example of a phase locked loop circuit applied to the present invention. FIG. 3 is an output waveform diagram of the phase locked loop. FIG. 6 is a diagram illustrating another example of the phase locked loop circuit.

Explanation of reference numerals

2 serial-parallel conversion circuit 3 IFFT, pilot signal generation circuit 4 guard interval setting circuit 4A RAM (random access memory)
5 D / A translator 6,24,42,53,114,134 LPF
7 Quadrature modulator 8, 30 90 ° shift circuit 9, 31 Intermediate frequency generation circuit 10 Clock signal generation circuit 11, 21 Frequency converter 12 Transmitter 20 Receiver 23 Quadrature demodulator 25 A / D converter (sampling circuit)
26 guard interval processing circuit 27 FFT, QAM decoding circuit 28 parallel-serial conversion circuit 29 carrier detection circuit 32 sample synchronization signal generation circuit 33 symbol synchronization signal generation circuit 40, 41, 52 Multiplier (phase comparator)
43, 50, 115, 135 VCO circuit 44, 45 1/4 frequency divider 51 1/2 frequency divider 111, 112, 131, 132 Phase comparator (PD)
116,136 Signal switch

Claims (2)

An orthogonal frequency division multiplexed signal receiving apparatus for receiving a multilevel QAM modulated digital information signal that is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added,
The guard interval has a higher-order frequency which is present as a discontinuous waveform at the head, is multiplied by 4 and exists as a signal of a single frequency, and is held in opposite phases in adjacent effective symbol sections. A pilot signal demodulation means for obtaining information on the polarity of the pilot signal by phase demodulating the pilot signal transmitted as a constant signal, and a driving signal based on the polarity information obtained by the pilot signal demodulation means. Signal generating means for generating, and FFT means driven by the driving signal generated by the signal generating means and converting the multi-level QAM modulated signal to the digital information signal;
An orthogonal frequency division multiplexed signal receiving apparatus comprising: A method for receiving an orthogonal frequency division multiplexed signal that receives a multilevel QAM-modulated digital information signal that is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added,
In the guard interval, a high-order frequency that is present as a discontinuous waveform at the head and is present as a signal of a single frequency after being quadrupled and held in opposite phases in adjacent effective symbol sections, and A first step of phase demodulating the pilot signal transmitted as a constant signal to obtain information on the polarity of the pilot signal,
A second step of generating a drive signal based on the polarity information obtained in the first step;
A third step of being driven by the driving signal generated in the second step and performing an FFT on the multi-level QAM modulated signal to obtain the digital information signal;
A method for receiving an orthogonal frequency division multiplexed signal.

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