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JP2004103751A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2004103751A
JP2004103751A JP2002262275A JP2002262275A JP2004103751A JP 2004103751 A JP2004103751 A JP 2004103751A JP 2002262275 A JP2002262275 A JP 2002262275A JP 2002262275 A JP2002262275 A JP 2002262275A JP 2004103751 A JP2004103751 A JP 2004103751A
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area
pads
pad
semiconductor chip
semiconductor device
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Tatsuya Oki
沖　達哉
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/05553—Shape in top view being rectangular
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device whose chip is reducible in area without generating any unnecessary area as to the area for arranging pads and the area for arranging an internal resource. <P>SOLUTION: In the four corners of the semiconductor chip 1, the pads 2 serving as input/output interfaces are arranged. Here, the pads 2 are nearly square. The pads 2 arranged in the four corners are arranged in a concentrated state although a semiconductor chip of a conventional technology has pads arranged around the four sides. Regions of a plurality of pads 2 arranged in the respective corners are named pad regions 3. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に係る発明であって、特に、半導体チップ内のパッドの配置に関するものである。
【０００２】
【従来の技術】
図７に、従来の技術の半導体装置の平面図を示す。半導体チップ１０１の外周の四辺には、入出力インターフェイスとなるパッド１０２が配置されている。半導体チップ１０１の四隅には、ウェハプロセスやアセンブリ工程等で必要に応じて使用されるアライメントマーク等の特殊マーク１０３が設けられる。ここで、パッド１０２や特殊マーク１０３が配置される領域をパッド領域Ａとする。このパッド領域Ａに囲まれた領域には、ＣＰＵ、ＲＯＭやＲＡＭ等の内部資源１０４が配置されている。この内部資源１０４は、パッド１０２に接続され必要な信号が入出力されている。この内部資源１０４が配置される領域を内部資源領域Ｂとする。
【０００３】
図７のような構成を採る半導体装置として、例えばシングルチップマイクロコンピュータなどがある。このシングルチップマイクロコンピュータの四辺に配置されたパッド１０２は、主にＬＱＦＰ（Ｌｏｗ　ｐｒｏｆｉｌｅ　Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）パッケージなどの多ピンアセンブリパッケージに対応している。近年、プロセスルールの微細化に伴い内部資源１０４の集積化が進み、半導体チップ１０１の面積を小さくすることが望まれている。
【０００４】
この半導体チップ１０１の面積は、パッド領域Ａの面積に内部資源領域Ｂの面積を加えた面積である。そして、パッド領域Ａの面積は、内部資源領域Ｂの面積を囲むように設けられているため、内部資源領域Ｂの面積により制限を受ける。逆に、内部資源領域Ｂの面積もパッド領域Ａの面積により制限を受ける。
【０００５】
例えば、内部資源領域Ｂの面積が小さい半導体チップ１０１に比べて、内部資源領域Ｂの面積が大きい半導体チップ１０１の方が、その周りに設けられるパッド領域Ａの面積も大きくなる。このときパッド１０２の数が同数であれば、内部資源領域Ｂの面積が大きい半導体チップ１０１では、パッド領域Ａの面積にパッド１０２等が配置されない無駄な面積が多くなる。よって、内部資源領域Ｂの面積が大きい半導体チップ１０１では、半導体チップ１０１の面積を小さく最適化することが困難となる。
【０００６】
また、パッド１０２の数が少ない半導体チップ１０１に比べて、パッド１０２の数が多い半導体チップ１０１では、パッド領域Ａの面積を大きくする必要があり、それ囲まれる内部資源領域Ｂの面積も大きくなる。このとき内部資源１０４の面積（実際に配置される内部資源１０４の面積）が同じであれば、パッド１０２の数が多い半導体チップ１０１では、内部資源領域Ｂの面積に内部資源１０４が配置されない無駄な面積が多くなる。そのため、パッド１０２の数が多い半導体チップ１０１では、半導体チップ１０１の面積を小さく最適化することは困難となる。
【０００７】
上記のような制限を回避するパッド１０２の配置として、パッド１０２の数が多い半導体チップ１０１であっても、内部資源領域Ｂの面積が小さくできるパッド１０２の配置を図８に示す。図８では、複数列（２列）のパッド１０２を配置した半導体チップ１０１である。このように複数列のパッド配置とすることにより、１列にパッド１０２を配置する場合に比べて、パッド１０２が配置される領域の四辺の長さを短くできる。そのため、パッド領域Ａに囲まれた、内部資源領域Ｂの面積を小さくすることができる。
【０００８】
また、図９に複数列のパッド１０２が配置された半導体チップ１０１の平面図を示す。図９では、図８のパッド１０２の配置に比べて、外側のパッド形状が、半導体チップの四辺に沿って長い形状の矩形である点が異なる。このようなパッド形状とすることにより、外側のパッド１０２に接続される金線１０５の位置に自由度が増し、複数列のパッド１０２間で金線１０５が接触しないようにボンディングすることが可能となる。図８及び図９に示したパッドの配置及び形状についての内容は、特許文献１に詳しい。
【０００９】
さらに、複数列のパッド配置とした場合、パッドの形状を矩形とするよりも五角形以上の多角形とする方が、パッド領域Ａの面積を小さくすることができる。これは図１０に示すように形状が矩形のパッド１０２の場合、列間のパッド間のショートを防止する必要があるため対角方向に隣接したパッド間の対角距離１０６を十分取らなければならない。一方、図１０に示すように形状が五角形以上の多角形のパッド１０７の場合、パッド１０７の形状から対角方向に隣接したパッド間のショートを考える必要がなくなる。そのため、形状が矩形のパッド１０２とする場合に比べて五角形以上の多角形のパッド１０７とする場合の方が、列間のパッド間距離１０８を短くすることができ、パッド領域Ａの面積を小さくすることができる。よって、半導体チップ１０１の面積を小さくすることができる。図１０に示した内容については、特許文献２に詳しい。
【００１０】
【特許文献１】特開平１１−４５９０３号公報
【特許文献２】特開昭６０−３５５２４号公報
【００１１】
【発明が解決しようとする課題】
しかし、図８又は図９のように複数列のパッド配置であっても、パッド領域Ａが内部資源領域Ｂを囲む構成には変わりがない。そのため、内部資源領域Ｂの面積とパッド領域Ａの面積とが、互いに制限される関係は残ることになる。
【００１２】
そのため、複数列のパッド配置としてパッド領域Ａの面積を小さくすることができても、内部資源領域Ｂに配置される内部資源１０４の面積により制限されるため、パッド１０２が配置されない無駄な面積をパッド領域Ａから完全に排除できない問題点がある。逆に、内部資源１０４の面積が大きい場合には、それに伴いパッド領域Ａの面積も大きくなるため、複数列のパッド配置としなくとも十分にパッド１０２を配置することができる場合もある。その場合に、仮にパッド１０２の配置を複数列にすると、パッド領域Ａにパッド１０２が配置されない無駄な面積が生じてしまう。
【００１３】
一方、図１０に示したパッドの形状を五角形以上の多角形とする構成も、パッド領域Ａの面積自体を小さくする点においては貢献するが、パッド領域Ａの面積と内部資源領域Ｂの面積とが互いに制限される関係を解消できない。そのため、上記の複数列のパッド配置と同様の問題点が残る。
【００１４】
そこで、本発明は、パッドを配置するための面積や内部資源を配置するための面積に無駄な面積を生じさせず、半導体チップの面積を小さくすることが可能な半導体装置を提供することを目的とする。
【００１５】
【課題を解決するための手段】
本発明の請求項１に係る解決手段は、半導体チップの四隅に配置される入出力インターフェイスのパッドと、パッドに接続され、半導体チップのパッドが配置された四隅以外に配置される内部資源とを備え、一の隅に配置されたパッドと隣接する他の隅に配置されるパッドの間にも内部資源が配置させている。
【００１６】
本発明の請求項２に係る解決手段は、請求項１記載の半導体装置であって、パッドは、半導体チップの四隅に複数列配置されている。
【００１７】
本発明の請求項３に係る解決手段は、請求項２記載の半導体装置であって、複数列のパッドは、半導体チップの内側のパッドより外側のパッドの方が半導体チップの四辺に沿って長い形状の矩形である。
【００１８】
本発明の請求項４に係る解決手段は、請求項１乃至請求項３のいずれかに記載の半導体装置であって、パッドは、形状が円に近い多角形である。
【００１９】
【発明の実施の形態】
以下、本発明をその実施の形態を示す図面に基づいて具体的に説明する。
【００２０】
（実施の形態１）
図１に本実施の形態に係る半導体装置の平面図を示す。半導体チップ１の四隅には、入出力インターフェイスとなるパッド２が配置されている。ここで、パッド２の形状はほぼ正方形である。この四隅に配置されたパッド２は、従来の技術の半導体チップにおいて四辺を囲むように配置されていたパッドを四隅に集約して配置されている。それぞれの隅に配置された複数のパッド２の領域を、パッド領域３とする。なお、図１のパッド領域３には、それぞれ１列のパッド２が配置されている例が図示されている。
【００２１】
さらに、パッド領域３には、ウェハプロセスやアセンブリ工程等で必要に応じて使用されるアライメントマーク等の特殊マーク４も設けられている。半導体チップ１でパッド領域３以外の領域には、ＣＰＵ、ＲＯＭやＲＡＭ等の内部資源５が配置されている。この内部資源５は、パッド２に接続され必要な信号が入出力されている。ここで、半導体チップ１でパッド領域３以外の領域を内部資源領域６とする。なお、図１では、内部資源領域６に設けられた一部の内部資源５について図示している。
【００２２】
本実施の形態では、パッド２が半導体チップ１の四隅に配置されているため、半導体チップ１の四辺の中央部にはそれぞれ内部資源領域６が設けられている。しかし、電源配線（図示せず）が、この中央部も含め半導体チップ１の四辺に沿って設けられており、この中央部の内部資源領域６に内部資源５を配置すると電源配線と内部資源５の配線とがショートする場合も考えられる。そこで、半導体チップ１では多層配線構造を採用し、電源配線は上層に内部資源５の配線は下層に配線して、電源配線と内部資源５の配線とのショートを回避している。これにより、半導体チップ１の四辺の中央部にも、何の問題もなく内部資源５を配置することができる。
【００２３】
また、本実施の形態でも半導体チップ１の面積は、パッド領域３の面積に内部資源領域６の面積を加えた面積である。しかし、従来の技術のようにパッド領域の面積は、内部資源領域６の面積を囲むように設けられておらず、内部資源領域６の面積とパッド領域３の面積とはお互いに制限されることはない。
【００２４】
例えば、内部資源領域６の面積が小さい半導体チップ１であっても、内部資源領域６の面積が大きい半導体チップ１であっても、パッド２の数が同じであればパッド領域３の面積は同じになる。そのため、パッド領域３の面積には無駄な面積が生じず、半導体チップ１の面積を最適化することができる。また、パッド２の数が少ない半導体チップ１であっても、パッド２の数が多い半導体チップ１であっても、実際に配置される内部資源５の面積が同じであれば内部資源領域６の面積も同じになる。そのため、内部資源領域６の面積には無駄な面積が生じず、半導体チップ１の面積を最適化することができる。
【００２５】
従って、本実施の形態では、パッド２の配置を最適化し、内部資源５の配置を最適化すれば、トータルとしての半導体チップ１の面積が最適化される。従来の技術のようなパッド領域３の面積と内部資源領域６の面積とがお互いに制限される場合に比べて、本実施の形態の半導体チップ１の面積は、小さくすることが可能となる。なお、本実施の形態では、あらかじめパッド２の直下に出力ドライバトランジスタ等の回路を配置しておくことにより、パッドと出力ドライバ間の配線を不要にでき、よりパッドの間隔を詰めて配置することができ、パッド領域３の面積を小さくすることができる。
【００２６】
以下に、本実施の形態に係る具体例について説明する。図２に、本実施の形態のパッド配置を利用したシングルチップマイクロコンピュータの平面図を示す。
【００２７】
図２の内部資源５を配置するための内部資源領域６の面積は、約２７ｍｍ２必要である。しかし、本実施の形態では、シングルチップマイクロコンピュータである半導体チップ１の四辺の中央部にも内部資源５を配置することができ、パッド領域３を含めた半導体チップ１の面積は約３７ｍｍ２にすることが可能である。図２では、左右の半導体チップ１の四辺の中央部のみに内部資源５が配置され、上下部分には配置されていない。そのため、内部資源５の配置の方法によっては、さらに半導体チップ１の面積を小さくすることが可能である。
【００２８】
図３に、従来の技術のパッド配置を利用したシングルチップマイクロコンピュータの平面図を示す。図３の内部資源５を配置するための内部資源領域６の面積も、図２と同様に約２７ｍｍ２必要であるとすると、従来の技術のパッド配置では、内部資源領域６を囲むようにパッド領域３を設けなければならないため、図３に示すシングルチップマイクロコンピュータである半導体チップ１の面積は、約４１ｍｍ２必要となる。つまり、本実施の形態を利用し、図２に示すようなシングルチップマイクロコンピュータを作製すれば、約１割程度半導体チップ１の面積を小さくすることが可能となる。
【００２９】
（実施の形態２）
図４に、本実施の形態に係る半導体チップ１のパッド領域の平面図を示す。半導体チップ１の四隅に設けられたパッド２は、千鳥状に２列に配置されている。ここで、パッド２の形状はほぼ正方形である。それぞれの隅に配置された複数のパッド２の領域を、パッド領域３とする。これらのパッド２には、外部から入出力が可能なように金線７がそれぞれに接続されている。
【００３０】
さらに、パッド領域３には、ウェハプロセスやアセンブリ工程等で必要に応じて使用されるアライメントマーク等の特殊マーク４も設けられている。半導体チップ１でパッド領域３以外の領域には、ＣＰＵ、ＲＯＭやＲＡＭ等の内部資源５が配置されている。この内部資源５は、パッド２に接続され必要な信号が入出力されている。ここで、半導体チップ１でパッド領域３以外の領域を内部資源領域６とする。なお、図４では、内部資源領域６に設けられた一部の内部資源５について図示している。
【００３１】
実施の形態１では、従来の半導体チップにおいて四辺を囲むように配置されていたパッドが四隅に集約して配置されているが、パッドの数が多いと１列配置のままでは四隅に集約するにも限界がある。そこで、本実施の形態では、パッド２を配列を千鳥状に２列に配置して、より多数のパッド２を四隅に集約することが可能にしている。パッド２が千鳥状に２列に配置されている点以外は、本実施の形態は、実施の形態１と同じ構成である。
【００３２】
なお、上記において説明した本実施の形態では、パッド２が千鳥状に２列に配置されている場合について説明したが、本発明は、これに限られず、パッド２が千鳥状に３列以上の複数列に配置されている場合であっても良い。また、本実施の形態でも、あらかじめパッド２の直下に出力ドライバトランジスタ等の回路を配置しておくことにより、パッドと出力ドライバ間の配線を不要にでき、よりパッドの間隔を詰めて配置することができる。
【００３３】
（変形例１）
図５に、本実施の形態の変形例に係る半導体チップ１のパッド領域の平面図を示す。半導体チップ１の四隅に設けられたパッドは、外側の列に配置されたパッド８と内側の列に配置されたパッド９が千鳥状に２列に配置されている。このパッド８は、半導体チップ１の四辺に沿って長い形状の矩形である。一方、パッド９は、実施の形態２のパッド２と同じくほぼ正方形である。それぞれの隅に配置された複数のパッド８及びパッド９の領域を、パッド領域３とする。これらのパッド８及びパッド９には、外部から入出力が可能なように金線７がそれぞれに接続されている。
【００３４】
さらに、パッド領域３には、ウェハプロセスやアセンブリ工程等で必要に応じて使用されるアライメントマーク等の特殊マーク４も設けられている。半導体チップ１でパッド領域３以外の領域には、ＣＰＵ、ＲＯＭやＲＡＭ等の内部資源５が配置されている。この内部資源５は、パッド８及びパッド９に接続され必要な信号が入出力されている。ここで、半導体チップ１でパッド領域３以外の領域を内部資源領域６とする。なお、図５では、内部資源領域６に設けられた一部の内部資源５について図示している。
【００３５】
実施の形態２では、ほぼ正方形であるパッド２が千鳥状に２列に配置されている。しかし、ほぼ正方形の形状では、金線７の接続位置に自由度がなく、金線７が互いにオーバーラップして電気的に不良が起こる場合も考えられる。そこで、本変形例のように半導体チップ１の外側の列に配置されたパッド８は、半導体チップ１の四辺に沿って長い形状の矩形にする。これにより、パッド８に接続される金線７は、半導体チップ１の四辺に沿った方向に接続位置の自由度を持つことになり、金線７が互いにオーバーラップして電気的に不良が起こる不具合も回避することができる。パッド８の形状以外は、本変形例は、実施の形態２と同じ構成である。
【００３６】
なお、上記において説明した本実施の形態では、パッド８及びパッド９が千鳥状に２列に配置されている場合について説明したが、本発明は、これに限られず、パッドが千鳥状に３列以上の複数列に配置されている場合であっても良い。この場合、より半導体チップ１の外側の列に配置されるパッドの形状は、半導体チップ１の四辺に沿ってより長い形状の矩形となる。これにより、半導体チップ１のより外側の列に配置されたパッドに接続される金線７が、半導体チップ１の四辺に沿った方向に接続位置の自由度を持つことになる。また、本変形例でも、あらかじめパッド８及びパッド９の直下に出力ドライバトランジスタ等の回路を配置しておくことにより、パッドと出力ドライバ間の配線を不要にでき、よりパッドの間隔を詰めて配置することができる。
【００３７】
（変形例２）
図６に、本実施の形態の変形例に係る半導体チップ１のパッド領域の平面図を示す。半導体チップ１の四隅に設けられたパッド１０は、千鳥状に２列に配置されている。このパッド１０は、実施の形態２のパッド２の形状と異なり円に近い多角形である。それぞれの隅に配置された複数のパッド１０の領域を、パッド領域３とする。これらのパッド１０には、外部から入出力が可能なように金線７がそれぞれに接続されている。
【００３８】
さらに、パッド領域３には、ウェハプロセスやアセンブリ工程等で必要に応じて使用されるアライメントマーク等の特殊マーク４も設けられている。半導体チップ１でパッド領域３以外の領域には、ＣＰＵ、ＲＯＭやＲＡＭ等の内部資源５が配置されている。この内部資源５は、パッド１０に接続され必要な信号が入出力されている。ここで、半導体チップ１でパッド領域３以外の領域を内部資源領域６とする。なお、図６では、内部資源領域６に設けられた一部の内部資源５について図示している。
【００３９】
実施の形態２では、ほぼ正方形であるパッド２が千鳥状に２列に配置されている。しかし、ほぼ正方形の形状では、パッド間のショートを防止する必要があるため対角方向に隣接したパッド間の対角距離を十分取らなければならなかった。この制約により、半導体チップ１の外側と内側に設けられたパッドのパッド間距離を短くすることができなかった。そこで、本変形例のように、パッド１０の形状を円に近い多角形にすることで、対角方向に隣接したパッド間のショートを考える必要がなくなり、パッド間の対角距離の制約を受けずに半導体チップ１の外側と内側に設けられたパッドのパッド間距離を短くすることができる。従って、本変形例では、より多数のパッド１０を四隅に集約することが可能にしている。パッド１０の形状以外は、本変形例は、実施の形態２と同じ構成である。
【００４０】
なお、上記において説明した本実施の形態では、パッド１０が千鳥状に２列に配置されている場合について説明したが、本発明は、これに限られず、パッド１０が千鳥状に３列以上の複数列に配置されている場合であっても良い。また、本変形例でも、あらかじめパッド１０の直下に出力ドライバトランジスタ等の回路を配置しておくことにより、パッドと出力ドライバ間の配線を不要にでき、よりパッドの間隔を詰めて配置することができる。
【００４１】
【発明の効果】
本発明の請求項１に記載の半導体装置は、半導体チップの四隅に配置された入出力インターフェイスのパッドを備えるので、トータルとしての半導体装置の面積が最適化できる効果がある。
【００４２】
本発明の請求項２に記載の半導体装置は、半導体チップの四隅に複数列配置されているので、より多数のパッドを四隅に集約することが可能にする効果がある。
【００４３】
本発明の請求項３に記載の半導体装置は、半導体チップの内側のパッドより外側のパッドの方が半導体チップの四辺に沿って長い形状の矩形であるので、パッドに接続される金線が、半導体チップの四辺に沿った方向に接続位置の自由度を持つことができる効果がある。
【００４４】
本発明の請求項４に記載の半導体装置は、パッド形状が円に近い多角形であるので、パッド間のショートを回避しつつ、より多数のパッドを四隅に集約することが可能にする効果がある。
【図面の簡単な説明】
【図１】本発明の実施の形態１に係る半導体装置の平面図である。
【図２】本発明の実施の形態１に係る半導体装置の平面図である。
【図３】従来の技術に係る半導体装置の平面図である。
【図４】本発明の実施の形態２に係る半導体装置の平面図である。
【図５】本発明の実施の形態２に係る半導体装置の平面図である。
【図６】本発明の実施の形態２に係る半導体装置の平面図である。
【図７】従来の技術に係る半導体装置の平面図である。
【図８】従来の技術に係る半導体装置の平面図である。
【図９】従来の技術に係る半導体装置の平面図である。
【図１０】従来の技術に係るパッド部分の平面図である。
【符号の説明】
１，１０１　半導体チップ、２，８，９，１０，１０２，１０７　パッド、３パッド領域、４，１０３　特殊マーク、５，１０４　内部資源、６　内部資源領域、７，１０５　金線、１０６　対角距離、１０８　パッド間距離。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to an arrangement of pads in a semiconductor chip.
[0002]
[Prior art]
FIG. 7 shows a plan view of a conventional semiconductor device. Pads 102 serving as input / output interfaces are arranged on the four sides on the outer periphery of the semiconductor chip 101. At four corners of the semiconductor chip 101, special marks 103 such as alignment marks used as needed in a wafer process, an assembly process, and the like are provided. Here, a region where the pad 102 and the special mark 103 are arranged is referred to as a pad region A. In an area surrounded by the pad area A, internal resources 104 such as a CPU, a ROM and a RAM are arranged. This internal resource 104 is connected to the pad 102 and inputs and outputs necessary signals. The area where the internal resources 104 are located is referred to as an internal resource area B.
[0003]
As a semiconductor device having the configuration shown in FIG. 7, for example, there is a single-chip microcomputer or the like. The pads 102 arranged on the four sides of the single-chip microcomputer mainly correspond to a multi-pin assembly package such as an LQFP (Low profile Quad Flat Package) package. In recent years, the integration of the internal resources 104 has progressed with the miniaturization of process rules, and it has been desired to reduce the area of the semiconductor chip 101.
[0004]
The area of the semiconductor chip 101 is the area obtained by adding the area of the internal resource area B to the area of the pad area A. Since the area of the pad region A is provided to surround the area of the internal resource region B, it is limited by the area of the internal resource region B. Conversely, the area of the internal resource area B is also limited by the area of the pad area A.
[0005]
For example, the area of the pad region A provided around the semiconductor chip 101 having a larger area of the internal resource region B is larger than that of the semiconductor chip 101 having a smaller area of the internal resource region B. At this time, if the number of the pads 102 is the same, in the semiconductor chip 101 in which the area of the internal resource region B is large, the useless area in which the pads 102 and the like are not arranged in the area of the pad region A increases. Therefore, in the semiconductor chip 101 in which the area of the internal resource region B is large, it is difficult to optimize the semiconductor chip 101 in a small area.
[0006]
Further, in the semiconductor chip 101 having a large number of pads 102, the area of the pad area A needs to be larger than that of the semiconductor chip 101 having a small number of pads 102, and the area of the internal resource area B surrounded by the pad area A also needs to be large. . At this time, if the area of the internal resources 104 (the area of the actually arranged internal resources 104) is the same, in the semiconductor chip 101 having a large number of pads 102, the internal resources 104 are not arranged in the area of the internal resource area B. Large area. Therefore, in the semiconductor chip 101 having a large number of pads 102, it is difficult to optimize the semiconductor chip 101 in a small area.
[0007]
FIG. 8 shows an arrangement of the pads 102 that can reduce the area of the internal resource region B even in the semiconductor chip 101 having a large number of pads 102 as an arrangement of the pads 102 that avoids the above-described limitation. FIG. 8 shows a semiconductor chip 101 on which a plurality of rows (two rows) of pads 102 are arranged. By arranging the pads in a plurality of rows in this manner, the lengths of the four sides of the region where the pads 102 are arranged can be shorter than when the pads 102 are arranged in one row. Therefore, the area of the internal resource region B surrounded by the pad region A can be reduced.
[0008]
FIG. 9 is a plan view of the semiconductor chip 101 on which a plurality of rows of pads 102 are arranged. 9 is different from the arrangement of the pads 102 in FIG. 8 in that the outer pad shape is a rectangle having a long shape along the four sides of the semiconductor chip. With such a pad shape, the position of the gold wire 105 connected to the outer pad 102 is increased in degree of freedom, and bonding can be performed between the pads 102 in a plurality of rows so that the gold wire 105 does not contact. Become. The contents of the arrangement and shape of the pads shown in FIGS. 8 and 9 are described in detail in Patent Document 1.
[0009]
Further, when a plurality of rows of pads are arranged, it is possible to reduce the area of the pad region A by setting the shape of the pad to be a pentagon or more polygon rather than a rectangle. This is because in the case of the pad 102 having a rectangular shape as shown in FIG. 10, it is necessary to prevent a short circuit between pads between rows, so that a diagonal distance 106 between diagonally adjacent pads must be sufficiently taken. . On the other hand, in the case of a polygonal pad 107 having a shape of a pentagon or more as shown in FIG. 10, it is not necessary to consider a short circuit between diagonally adjacent pads from the shape of the pad 107. Therefore, when the pad 107 is a pentagonal or more polygonal pad, the inter-pad distance 108 between rows can be shortened, and the area of the pad region A can be reduced as compared with the case where the pad is rectangular in shape. can do. Therefore, the area of the semiconductor chip 101 can be reduced. The contents shown in FIG. 10 are described in detail in Patent Document 2.
[0010]
[Patent Document 1] JP-A-11-45903 [Patent Document 2] JP-A-60-35524
[Problems to be solved by the invention]
However, the pad area A surrounds the internal resource area B even when the pads are arranged in a plurality of rows as shown in FIG. 8 or FIG. Therefore, the relationship that the area of the internal resource region B and the area of the pad region A are mutually restricted remains.
[0012]
Therefore, even if the area of the pad area A can be reduced as the pad arrangement in a plurality of rows, the area is limited by the area of the internal resources 104 arranged in the internal resource area B. There is a problem that it cannot be completely excluded from the pad area A. Conversely, when the area of the internal resource 104 is large, the area of the pad region A is also increased accordingly, so that the pad 102 can be sufficiently arranged in some cases without arranging a plurality of rows of pads. In this case, if the pads 102 are arranged in a plurality of rows, an unnecessary area in which the pads 102 are not disposed in the pad area A occurs.
[0013]
On the other hand, the configuration in which the shape of the pad shown in FIG. 10 is a polygon of five or more pentagons also contributes in reducing the area itself of the pad area A, but the area of the pad area A and the area of the internal resource area B are reduced. Cannot eliminate the relation that is restricted by each other. For this reason, the same problem as the above-described pad arrangement in a plurality of rows remains.
[0014]
Therefore, an object of the present invention is to provide a semiconductor device capable of reducing the area of a semiconductor chip without causing useless area for arranging pads and arranging internal resources. And
[0015]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor device comprising: an input / output interface pad disposed at four corners of a semiconductor chip; and internal resources connected to the pad and disposed at other than the four corners at which the semiconductor chip pad is disposed. In addition, internal resources are also arranged between a pad arranged in one corner and a pad arranged in another adjacent corner.
[0016]
According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the pads are arranged in a plurality of rows at four corners of the semiconductor chip.
[0017]
According to a third aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein pads in a plurality of rows are longer along four sides of the semiconductor chip than pads inside the semiconductor chip. It is a rectangular shape.
[0018]
A solution according to claim 4 of the present invention is the semiconductor device according to any one of claims 1 to 3, wherein the pad has a polygonal shape close to a circle.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments.
[0020]
(Embodiment 1)
FIG. 1 shows a plan view of the semiconductor device according to the present embodiment. At the four corners of the semiconductor chip 1, pads 2 serving as input / output interfaces are arranged. Here, the shape of the pad 2 is substantially square. The pads 2 arranged at the four corners are arranged such that the pads arranged so as to surround the four sides in the semiconductor chip of the prior art are gathered at the four corners. A region of the plurality of pads 2 arranged at each corner is referred to as a pad region 3. Note that an example in which one row of pads 2 is arranged in the pad area 3 of FIG. 1 is illustrated.
[0021]
Further, the pad area 3 is provided with a special mark 4 such as an alignment mark used as necessary in a wafer process, an assembly process, or the like. In an area other than the pad area 3 of the semiconductor chip 1, internal resources 5 such as a CPU, a ROM and a RAM are arranged. This internal resource 5 is connected to the pad 2 and inputs and outputs necessary signals. Here, a region other than the pad region 3 in the semiconductor chip 1 is defined as an internal resource region 6. FIG. 1 illustrates a part of the internal resources 5 provided in the internal resource area 6.
[0022]
In the present embodiment, since the pads 2 are arranged at the four corners of the semiconductor chip 1, the internal resource regions 6 are provided at the center of the four sides of the semiconductor chip 1, respectively. However, power supply wires (not shown) are provided along the four sides of the semiconductor chip 1 including the central portion. When the internal resources 5 are arranged in the internal resource region 6 in the central portion, the power supply wires and the internal resources 5 It is also conceivable that the wiring is short-circuited. Therefore, the semiconductor chip 1 employs a multi-layer wiring structure, in which the power supply wiring is provided in the upper layer and the wiring of the internal resources 5 is provided in the lower layer, thereby avoiding a short circuit between the power supply wiring and the wiring of the internal resources 5. As a result, the internal resources 5 can be arranged at the center of the four sides of the semiconductor chip 1 without any problem.
[0023]
Also in this embodiment, the area of the semiconductor chip 1 is the area obtained by adding the area of the internal resource region 6 to the area of the pad region 3. However, unlike the prior art, the area of the pad region is not provided so as to surround the area of the internal resource region 6, and the area of the internal resource region 6 and the area of the pad region 3 are limited to each other. There is no.
[0024]
For example, even if the semiconductor chip 1 has a small area of the internal resource region 6 or the semiconductor chip 1 has a large area of the internal resource region 6, the area of the pad region 3 is the same if the number of pads 2 is the same. become. Therefore, no useless area is generated in the area of the pad region 3, and the area of the semiconductor chip 1 can be optimized. Even if the semiconductor chip 1 has a small number of pads 2 or the semiconductor chip 1 has a large number of pads 2, if the area of the actually arranged internal resources 5 is the same, The area is the same. Therefore, no useless area is generated in the area of the internal resource region 6, and the area of the semiconductor chip 1 can be optimized.
[0025]
Therefore, in this embodiment, the area of the semiconductor chip 1 as a whole is optimized by optimizing the arrangement of the pads 2 and optimizing the arrangement of the internal resources 5. The area of the semiconductor chip 1 according to the present embodiment can be reduced as compared with the case where the area of the pad region 3 and the area of the internal resource region 6 are limited to each other as in the related art. In the present embodiment, by arranging a circuit such as an output driver transistor immediately below the pad 2 in advance, wiring between the pad and the output driver can be made unnecessary, and the pad spacing can be reduced. Thus, the area of the pad region 3 can be reduced.
[0026]
Hereinafter, a specific example according to the present embodiment will be described. FIG. 2 shows a plan view of a single-chip microcomputer using the pad arrangement of the present embodiment.
[0027]
The area of the internal resource area 6 for arranging the internal resources 5 in FIG. 2 needs to be about 27 mm 2 . However, in the present embodiment, the internal resources 5 can also be arranged at the center of the four sides of the semiconductor chip 1 which is a single-chip microcomputer, and the area of the semiconductor chip 1 including the pad region 3 is about 37 mm 2 . It is possible to do. In FIG. 2, the internal resources 5 are arranged only in the central portions of the four sides of the left and right semiconductor chips 1, and are not arranged in the upper and lower portions. Therefore, the area of the semiconductor chip 1 can be further reduced depending on the method of arranging the internal resources 5.
[0028]
FIG. 3 is a plan view of a single-chip microcomputer using a conventional pad arrangement. Assuming that the area of the internal resource area 6 for arranging the internal resources 5 in FIG. 3 also needs to be about 27 mm 2 similarly to FIG. 2, in the pad arrangement of the related art, the pad is arranged so as to surround the internal resource area 6. Since the region 3 must be provided, the area of the semiconductor chip 1 which is a single-chip microcomputer shown in FIG. 3 requires about 41 mm 2 . That is, if a single-chip microcomputer as shown in FIG. 2 is manufactured using this embodiment, the area of the semiconductor chip 1 can be reduced by about 10%.
[0029]
(Embodiment 2)
FIG. 4 is a plan view of a pad region of the semiconductor chip 1 according to the present embodiment. The pads 2 provided at the four corners of the semiconductor chip 1 are arranged in two rows in a staggered manner. Here, the shape of the pad 2 is substantially square. A region of the plurality of pads 2 arranged at each corner is referred to as a pad region 3. Gold wires 7 are connected to these pads 2 so that input and output can be performed from the outside.
[0030]
Further, the pad area 3 is provided with a special mark 4 such as an alignment mark used as necessary in a wafer process, an assembly process, or the like. In an area other than the pad area 3 of the semiconductor chip 1, internal resources 5 such as a CPU, a ROM and a RAM are arranged. This internal resource 5 is connected to the pad 2 and inputs and outputs necessary signals. Here, a region other than the pad region 3 in the semiconductor chip 1 is defined as an internal resource region 6. FIG. 4 illustrates a part of the internal resources 5 provided in the internal resource area 6.
[0031]
In the first embodiment, the pads arranged so as to surround the four sides in the conventional semiconductor chip are arranged at the four corners. However, if the number of pads is large, the pads are arranged at the four corners if they are arranged in one row. Have limitations. Therefore, in the present embodiment, the pads 2 are arranged in two rows in a staggered manner, so that a larger number of pads 2 can be collected at four corners. The present embodiment has the same configuration as the first embodiment except that the pads 2 are arranged in two rows in a staggered manner.
[0032]
In the present embodiment described above, a case has been described in which the pads 2 are arranged in two rows in a staggered manner. However, the present invention is not limited to this, and the pads 2 are arranged in three or more rows in a staggered manner. It may be a case in which they are arranged in a plurality of rows. Also in the present embodiment, by arranging a circuit such as an output driver transistor immediately below the pad 2 in advance, wiring between the pad and the output driver can be made unnecessary, and the pad spacing can be reduced. Can be.
[0033]
(Modification 1)
FIG. 5 shows a plan view of a pad region of a semiconductor chip 1 according to a modification of the present embodiment. The pads provided at the four corners of the semiconductor chip 1 are such that pads 8 arranged in an outer row and pads 9 arranged in an inner row are arranged in two rows in a staggered manner. The pad 8 is a rectangle having a long shape along four sides of the semiconductor chip 1. On the other hand, the pad 9 is substantially square like the pad 2 of the second embodiment. The area of the plurality of pads 8 and pads 9 arranged at each corner is referred to as a pad area 3. A gold wire 7 is connected to each of the pads 8 and 9 so that input and output can be performed from the outside.
[0034]
Further, the pad area 3 is provided with a special mark 4 such as an alignment mark used as necessary in a wafer process, an assembly process, or the like. In an area other than the pad area 3 of the semiconductor chip 1, internal resources 5 such as a CPU, a ROM and a RAM are arranged. The internal resources 5 are connected to the pads 8 and 9 to input and output necessary signals. Here, a region other than the pad region 3 in the semiconductor chip 1 is defined as an internal resource region 6. Note that FIG. 5 illustrates some internal resources 5 provided in the internal resource area 6.
[0035]
In the second embodiment, the pads 2 each having a substantially square shape are arranged in two rows in a staggered manner. However, in the case of a substantially square shape, the connection position of the gold wires 7 does not have a degree of freedom, and the gold wires 7 may overlap each other to cause an electrical failure. Therefore, the pads 8 arranged in the outer row of the semiconductor chip 1 as in the present modification are formed into a rectangular shape having a long shape along the four sides of the semiconductor chip 1. As a result, the gold wires 7 connected to the pads 8 have a degree of freedom in connection positions in the direction along the four sides of the semiconductor chip 1, and the gold wires 7 overlap with each other to cause an electrical failure. Problems can also be avoided. Except for the shape of the pad 8, this modification has the same configuration as the second embodiment.
[0036]
In the present embodiment described above, the case where the pads 8 and the pads 9 are arranged in two rows in a staggered manner has been described. However, the present invention is not limited to this, and the pads may be arranged in three rows in a staggered manner. The above arrangement may be applied to a case where the plurality of columns are arranged. In this case, the shape of the pads arranged in a row outside the semiconductor chip 1 is a rectangle having a longer shape along the four sides of the semiconductor chip 1. As a result, the gold wire 7 connected to the pads arranged in the outermost row of the semiconductor chip 1 has a degree of freedom of the connection position in the direction along the four sides of the semiconductor chip 1. Also in this modification, by arranging a circuit such as an output driver transistor immediately below the pad 8 and the pad 9 in advance, wiring between the pad and the output driver can be eliminated, and the pad spacing can be reduced. can do.
[0037]
(Modification 2)
FIG. 6 is a plan view of a pad region of a semiconductor chip 1 according to a modification of the present embodiment. The pads 10 provided at the four corners of the semiconductor chip 1 are arranged in two rows in a staggered manner. This pad 10 is a polygon close to a circle unlike the shape of the pad 2 of the second embodiment. A region of the plurality of pads 10 arranged at each corner is referred to as a pad region 3. Gold wires 7 are connected to these pads 10 so that input and output can be performed from the outside.
[0038]
Further, the pad area 3 is provided with a special mark 4 such as an alignment mark used as necessary in a wafer process, an assembly process, or the like. In an area other than the pad area 3 of the semiconductor chip 1, internal resources 5 such as a CPU, a ROM and a RAM are arranged. The internal resources 5 are connected to the pads 10 to input and output necessary signals. Here, a region other than the pad region 3 in the semiconductor chip 1 is defined as an internal resource region 6. FIG. 6 shows a part of the internal resources 5 provided in the internal resource area 6.
[0039]
In the second embodiment, the pads 2 each having a substantially square shape are arranged in two rows in a staggered manner. However, in the case of a substantially square shape, it is necessary to prevent a short circuit between pads, so that a sufficient diagonal distance between pads adjacent in a diagonal direction has to be provided. Due to this restriction, the distance between the pads provided on the outside and inside of the semiconductor chip 1 cannot be reduced. Therefore, by making the shape of the pad 10 a polygon close to a circle as in the present modification, it is not necessary to consider a short circuit between pads adjacent to each other in a diagonal direction. Instead, the distance between the pads provided on the outside and inside of the semiconductor chip 1 can be reduced. Therefore, in the present modification, a larger number of pads 10 can be collected at the four corners. Except for the shape of the pad 10, the present modification has the same configuration as that of the second embodiment.
[0040]
In the present embodiment described above, the case where the pads 10 are arranged in two rows in a staggered manner has been described. However, the present invention is not limited to this, and the pads 10 are arranged in three or more rows in a staggered manner. It may be a case in which they are arranged in a plurality of rows. Also in this modification, by arranging a circuit such as an output driver transistor immediately below the pad 10 in advance, wiring between the pad and the output driver can be made unnecessary, and the pad spacing can be reduced. it can.
[0041]
【The invention's effect】
Since the semiconductor device according to the first aspect of the present invention includes the pads of the input / output interface arranged at the four corners of the semiconductor chip, there is an effect that the total area of the semiconductor device can be optimized.
[0042]
Since the semiconductor device according to the second aspect of the present invention is arranged in a plurality of rows at the four corners of the semiconductor chip, there is an effect that a larger number of pads can be integrated at the four corners.
[0043]
In the semiconductor device according to the third aspect of the present invention, since the outer pads are longer rectangles along the four sides of the semiconductor chip than the inner pads, the gold wires connected to the pads are: There is an effect that the degree of freedom of the connection position can be increased in the direction along the four sides of the semiconductor chip.
[0044]
In the semiconductor device according to the fourth aspect of the present invention, since the pad shape is a polygon close to a circle, it is possible to avoid a short circuit between the pads and to collect more pads at the four corners. is there.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a plan view of a semiconductor device according to a conventional technique.
FIG. 4 is a plan view of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a plan view of a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a plan view of a semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a plan view of a semiconductor device according to a conventional technique.
FIG. 8 is a plan view of a semiconductor device according to a conventional technique.
FIG. 9 is a plan view of a semiconductor device according to a conventional technique.
FIG. 10 is a plan view of a pad portion according to a conventional technique.
[Explanation of symbols]
1,101 semiconductor chip, 2,8,9,10,102,107 pad, 3 pad area, 4,103 special mark, 5,104 internal resource, 6 internal resource area, 7,105 gold wire, 106 diagonal distance , 108 Distance between pads.

Claims (4)

半導体チップの四隅に配置される入出力インターフェイスのパッドと、
前記パッドに接続され、前記半導体チップの前記パッドが配置された四隅以外に配置される内部資源とを備え、
一の隅に配置された前記パッドと隣接する他の隅に配置される前記パッドの間にも前記内部資源が配置させていることを特徴とする半導体装置。Input / output interface pads arranged at the four corners of the semiconductor chip,
Connected to the pad, comprising an internal resource arranged at other than the four corners where the pad of the semiconductor chip is arranged,
The semiconductor device, wherein the internal resources are also arranged between the pad arranged in one corner and the pad arranged in another adjacent corner. 請求項１記載の半導体装置であって、
前記パッドは、前記半導体チップの四隅に複数列配置されていることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the pads are arranged in a plurality of rows at four corners of the semiconductor chip. 請求項２記載の半導体装置であって、
前記複数列のパッドは、前記半導体チップの内側の前記パッドより外側の前記パッドの方が前記半導体チップの四辺に沿って長い形状の矩形であることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein
The semiconductor device, wherein the plurality of rows of pads have a rectangular shape in which the pads outside the pads inside the semiconductor chip are longer along four sides of the semiconductor chip. 請求項１乃至請求項３のいずれかに記載の半導体装置であって、
前記パッドは、形状が円に近い多角形であることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein:
The semiconductor device according to claim 1, wherein the pad has a polygonal shape close to a circle.
JP2002262275A 2002-09-09 2002-09-09 Semiconductor device Pending JP2004103751A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006013035A (en) * 2004-06-24 2006-01-12 Fujitsu Ltd Semiconductor integrated circuit and method for designing the same
EP2153460A1 (en) * 2007-06-07 2010-02-17 Silicon Works Co., Ltd. Pad layout structure of semiconductor chip
JP2011096889A (en) * 2009-10-30 2011-05-12 Elpida Memory Inc Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006013035A (en) * 2004-06-24 2006-01-12 Fujitsu Ltd Semiconductor integrated circuit and method for designing the same
EP2153460A1 (en) * 2007-06-07 2010-02-17 Silicon Works Co., Ltd. Pad layout structure of semiconductor chip
EP2153460A4 (en) * 2007-06-07 2014-05-07 Silicon Works Co Ltd Pad layout structure of semiconductor chip
JP2011096889A (en) * 2009-10-30 2011-05-12 Elpida Memory Inc Semiconductor device

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