JP2004198671A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem in which when test terminals are prepared by driving circuits mounted on a display panel to test operations of the driving circuits, the number of the test terminals is very large. <P>SOLUTION: A driving circuit integrated type liquid crystal display device constituted by integrally forming driving circuits at peripheries of pixel parts 12 on a glass substrate 11 together with the pixel parts 12 is so configured to input a plurality of operation result signals to a selecting circuit 31 during an operation test of driving circuits and selecting and outputting one of them to outside the substrate by the selecting circuit 31 through a single test terminal 33. Consequently, the number of terminals of the display panel can greatly be decreased. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device such as a liquid crystal display device or an EL (electroluminescence) display device, and more particularly to a so-called drive circuit integrated type display device in which a pixel portion and a peripheral drive circuit are integrally formed on the same transparent insulating substrate. About.
[0002]
[Prior art]
In the field of flat panel display devices represented by liquid crystal display devices and EL display devices, in recent years, in order to reduce the size and thickness of the display device, the same transparent insulation as that of a pixel portion in which pixels are arranged in a matrix is used. On a substrate, for example, a glass substrate (display panel), a peripheral driving circuit for driving the pixel portion, specifically, a vertical driving circuit for selectively scanning each pixel of the pixel portion in a row unit, or a vertical driving circuit for selecting The development of a drive circuit integrated type display device in which a horizontal drive circuit for writing a display signal to the pixels in the specified row and the like are integrally formed has been advanced.
[0003]
In the drive circuit integrated type display device, in the final stage of the manufacturing process, a functional test of each of the drive circuits mounted on the display panel is performed. For example, a digital interface driving circuit is mounted as a horizontal driving circuit, and a reference voltage (gradation voltage) selection type DA converting circuit is used as a digital-to-analog converting circuit (hereinafter, referred to as a “DA converting circuit”) in the driving circuit. In an integrated drive circuit type liquid crystal display device, at least a part or all of a plurality of reference voltage lines are electrically disconnected from a reference voltage generation circuit during an operation test, so that the reference voltage lines are set to an arbitrary voltage level and tested. This makes it possible to easily and reliably perform an operation test of the DA conversion circuit in a short time (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-2002-32053
[0005]
[Problems to be solved by the invention]
By the way, when performing an operation test of a drive circuit mounted on a display panel, it is usually necessary to take out a signal indicating the operation result outside the panel and determine whether the circuit operation is normal or not to a test circuit. To verify that signal. Therefore, in the case of the above-described DA conversion circuit, for example, test terminals are required in a number corresponding to the number of output lines of the DA conversion circuit, and it is necessary to provide a huge number of test terminals on the display panel. .
[0006]
In addition, actually, not only the DA conversion circuit but also various other drive circuits are mounted on the display panel. Therefore, the more drive circuits are mounted, the more the signals to be verified are required. The greater the number of test terminals, the greater the number of test terminals for extracting a signal indicating the operation result of the drive circuit to the outside of the panel, which hinders the downsizing of the display panel and the downsizing of the entire display device.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to perform an operation test when a peripheral driving circuit for driving a pixel portion is mounted on the same transparent insulating substrate as the pixel portion. It is an object of the present invention to provide a display device capable of extracting a signal indicating an operation result of each drive circuit to the outside of a panel with a smaller number of terminals.
[0008]
[Means for Solving the Problems]
A display device according to the present invention includes a pixel portion in which pixels are arranged in a matrix on a transparent insulating substrate, a driving circuit formed on the same transparent insulating substrate as the pixel portion and driving the pixel portion, A control terminal for taking in a control signal for designating one of a plurality of signals indicating an operation result during an operation test of the circuit from outside the transparent insulating substrate; and the control signal input via the control terminal And a test terminal for outputting a signal selected by the selection circuit to the outside of the transparent insulating substrate. I have.
[0009]
In the display device having the above structure, when a control signal is input from the outside of the substrate via a control terminal during an operation test of the drive circuit, the selection circuit generates a plurality of signals indicating an operation result of the drive circuit based on the control signal. And outputs the selected one. This selected signal is output to the outside of the board via the test terminal. Then, outside the board, a test circuit is used to verify whether one circuit operation is normal based on a signal output to the outside of the board. Then, when verifying another circuit operation, a control signal indicating that is input to the inside of the substrate via the control terminal, so that the selection circuit selects and outputs a signal indicating another circuit operation. By repeatedly performing these series of operations, a plurality of signals indicating the operation results of the drive circuit are sequentially selected by the selection circuit and output to the outside of the substrate via a single test terminal.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0011]
FIG. 1 is a block diagram showing a configuration example of a drive circuit integrated display device, for example, a liquid crystal display device according to an embodiment of the present invention. In FIG. 1, on a transparent insulating substrate, for example, a glass substrate 11, a large number of pixels are arranged in a matrix (matrix) to form a pixel portion (effective pixel region) 12. The glass substrate 11 is opposed to another glass substrate (not shown) with a predetermined gap, and forms a display panel by sealing a liquid crystal material between the two substrates.
[0012]
FIG. 2 illustrates an example of a configuration of a pixel circuit in the pixel portion 12. Each of the pixels 20 arranged in a matrix has a TFT (Thin Film Transistor) 21 serving as a pixel transistor, a liquid crystal cell 22 having a pixel electrode (first electrode) connected to a drain electrode of the TFT 21, The liquid crystal cell 22 has a configuration including a pixel electrode and a storage capacitor 23 to which one electrode is connected. Here, the liquid crystal cell 22 means a liquid crystal capacitance generated between a pixel electrode and a counter electrode formed to face the pixel electrode.
[0013]
In this pixel structure, the TFT 21 has a gate electrode connected to a scanning line (gate line) 24 and a source electrode connected to a signal line (source line) 25. The liquid crystal cell 22 has a common electrode connected to a common line 26 for each pixel. Then, a common potential Vcom is commonly applied to the counter electrode of the liquid crystal cell 22 via the common line 26 for each pixel. The other electrode of the storage capacitor 23 is commonly connected to the CS line 27 for each pixel.
[0014]
Here, in the case of performing 1H (H is a horizontal period) inversion drive or 1F (F is a field period) inversion drive, the display signal written to each pixel performs the polarity inversion based on the common potential Vcom. . When common inversion driving for inverting the polarity of the common potential Vcom at a fixed period, for example, 1H or 1F period is used together with 1H inversion driving or 1F inversion driving, the potential of the CS line 57 (hereinafter referred to as “CS potential”) ) Is also AC-inverted in synchronization with the common potential Vcom. Note that the CS potential is a potential having substantially the same amplitude and the same phase as the common potential Vcom.
[0015]
Referring to FIG. 1 again, on the same glass substrate 11 as the pixel unit 12, for example, an interface (IF) circuit 13, a timing generator (TG) circuit 14, and a CS driver 15 are provided on the left side of the pixel unit 12. A vertical (V) driver (vertical drive circuit) 16 is mounted above and below the pixel section 12, and horizontal (H) drivers (horizontal drive circuits) 17A and 17B are mounted as peripheral drive circuits. However, here, only a part is illustrated as a peripheral driving circuit, and the present invention is not limited to these. These peripheral drive circuits are manufactured using a TFT having an active layer of CG (Continuous Grain Crystal) silicon or low-temperature polysilicon together with the pixel transistors of the pixel section 12.
[0016]
In the drive circuit integrated liquid crystal display device having the above configuration, a master clock MCK having a low voltage amplitude (for example, 3.3 V amplitude), a horizontal synchronization pulse Hsync, a vertical synchronization pulse Vsync, and R (red) G are applied to the glass substrate 11. (Green) B (blue) parallel input display data Data is input from outside the substrate. The interface circuit 13 performs a level shift (level conversion) from a low voltage amplitude signal level input from outside the substrate to a high voltage amplitude (for example, 6.0 V) signal level.
[0017]
The level-shifted master clock MCK, horizontal synchronization pulse Hsync, and vertical synchronization pulse Vsync are supplied to the timing generator circuit 14. The timing generator circuit 14 generates various timing pulses necessary for driving the CS driver 15, the vertical driver 16, and the horizontal drivers 17A and 17B based on the master clock MCK, the horizontal synchronization pulse Hsync, and the vertical synchronization pulse Vsync. The level-shifted display data Data is supplied to the horizontal drivers 17A and 17B.
[0018]
The CS driver 15 generates a CS potential to be applied to the counter electrode side terminal of the storage capacitor 23 of the pixel 20 and applies the same to the other electrode of the storage capacitor 23 via the CS line 27 in FIG. Here, assuming that the amplitude of the display signal is, for example, 0 to 3.3 V, when the above-described common inversion driving is employed, the CS potential is set such that the low level is 0 V (ground level) and the high level is between 3.3 V. Inversion will be repeated.
[0019]
The vertical driver 16 includes a vertical shift register and a gate buffer. In the vertical driver 16, the vertical shift register starts a shift operation in response to a vertical start pulse VST supplied from the timing generator circuit 14, and synchronizes with the vertical clock pulse VCK also supplied from the timing generator circuit 14. A scan pulse sequentially transferred in one vertical period is generated. The generated scanning pulses are sequentially output to the scanning lines 24-1 to 24-y wired according to the number y of pixels in the vertical direction of the pixel unit 12 through the gate buffer. When the scanning pulse is sequentially output to the scanning lines 24-1 to 24-y by the vertical scanning by the vertical driver 13, each pixel of the pixel unit 12 is sequentially selected in units of rows (lines).
[0020]
The horizontal drivers 17A and 17B operate based on the horizontal start pulse HST and the horizontal clock pulse HCK supplied from the timing generator circuit 14, and display each pixel of a row sequentially selected by vertical scanning by the vertical driver 13. The signal is written dot-sequentially (pixel unit) or line-sequentially (row unit) via signal lines 25-1 to 25-x wired corresponding to the number x of pixels in the horizontal direction of the pixel unit 12. As a role of each of the horizontal drivers 17A and 17B, for example, the horizontal driver 17A is responsible for writing to odd pixels, and the horizontal driver 17B is responsible for writing to even pixels.
[0021]
On the glass substrate 11, other than the above-described drive circuits, a selection circuit 31 for use in an operation test of these drive circuits is mounted. The selection circuit 31 receives from the interface circuit 13, the timing generator circuit 14, the CS driver 15, the vertical driver and the horizontal driver 17A, 17B, a signal indicating the operation result at the time of their operation test (hereinafter referred to as "operation result signal"). Is entered. Here, for simplicity of the drawing, as an example, two operation result signals are output from the interface circuit 13 and the timing generator circuit 14, and one operation result signal is output from the CS driver 15, the vertical driver and the horizontal drivers 17A and 17B, respectively. It is assumed that a total of eight operation result signals are input to the selection circuit 31.
[0022]
Here, the operation test will be specifically described by taking, for example, the case of the interface circuit 13 as an example. In this operation test, when a horizontal synchronization pulse Hsync is applied to the interface circuit 13 from outside the substrate, it is determined whether or not the horizontal synchronization pulse Hsync is normally output from the interface circuit 13 at a predetermined timing. When a vertical synchronization pulse Vsync is applied to the circuit 13 from the outside of the substrate, it is verified whether the vertical synchronization pulse Vsync is normally output from the interface circuit 13 at a predetermined timing.
[0023]
The selection circuit 31 selects and outputs one of a plurality of operation result signals based on an input control signal provided from outside the glass substrate 11. Here, since the number of operation result signals input to the selection circuit 31 is eight, a 3-bit input control signal is supplied to the selection circuit 31 via the control terminals 32-1, 32-2, and 32-3. Provided from outside the substrate. The operation result signal selected by the selection circuit 31 is output to the outside of the board via the single test terminal 33.
[0024]
The operation result signal output to the outside of the board via the single test terminal 33 is supplied to a test circuit (not shown), and the test circuit verifies the operation test. That is, taking the case of the above-described interface circuit 13 as an example, when the horizontal synchronization pulse Hsync is given, it is determined whether or not the horizontal synchronization pulse Hsync is normally output at a predetermined timing, or the vertical synchronization pulse Vsync is given. At this time, the test circuit verifies whether the vertical synchronization pulse Vsync is normally output at a predetermined timing.
[0025]
As described above, at the time of the operation test of the drive circuit, the input control signals C1, C2, and C3 are supplied to the selection circuit 31 from the outside of the board via the control terminals 32-1, 32-2, and 32-3. In response to this, the selection circuit 31 selects one of the plurality of operation result signals S1 to S8 according to the logic states of the input control signals C1, C2, and C3. The selected operation result signal is output to the outside of the board via the single test terminal 33. Then, outside the board, a test circuit is used to verify whether one circuit operation is normal based on the operation result signal output outside the board.
[0026]
Then, when verifying another circuit operation, input control signals C1, C2, and C3 in a logical state indicating the fact are input to the inside of the board through the control terminals 32-1, 32-2, and 32-3. Thus, the selection circuit 31 selects and outputs an operation result signal indicating another circuit operation. By repeatedly executing these series of operations, a plurality of operation result signals indicating operation results of the drive circuit, in this example, operation result signals S1 to S8, are changed according to the logic states of the input control signals C1, C2, and C3. Is selected by the selection circuit 31 and output to the outside of the substrate via the single test terminal 33.
[0027]
FIG. 3 is an equivalent circuit diagram showing an example of the configuration of the selection circuit 31. Here, a case where one of eight operation result signals S1 to S8 is selected by 3-bit input control signals C1 to C3. Is shown.
[0028]
As shown in FIG. 3, the selection circuit 31 is connected between each of the eight input terminals 34-1 to 34-8 to which the operation result signals S1 to S8 are input and the output line 35 connected to the test terminal 33. A configuration in which three switches SW1-1, SW1-2, SW1-3 to SW8-1, SW8-2, SW8-3 corresponding to the number of bits of the input control signals C1 to C3 are connected in series. Has become. These switches are turned on (closed) when the logic of the input control signals C1 to C3 is "0", that is, at a low (L) level, and when the logic is "1", that is, at a high (H) level. To the off (open) state.
[0029]
During normal driving, it is preferable that the input control signals C1 to C3 are set to L level (GND input), and the L level is output to the output line 35 (GND output) at this time. This is because unnecessary signals do not need to be output to the outside of the board, so that power consumption can be suppressed. Further, since the signal is at the GND level, noise is added to other signal lines due to the addition of the selection circuit 31. Not even.
[0030]
FIG. 4 is a state diagram according to the input control signals C1 to C3 of the selection circuit 31 having the above configuration. The selection circuit 31 selects the operation result signal S1 when the input control signals C1 to C3 are all at L level, and selects the operation result signal when the input control signals C1 and C2 are at L level and the input control signal C3 is at H level. S2 is selected, the operation result signal S3 is selected when the input control signals C1 and C3 are at L level and the input control signal C2 is at H level, and the input control signal C1 is at L level and the input control signals C2 and C3 are The operation result signal S4 is selected when it is at the H level, the operation result signal S5 is selected when the input control signal C1 is at the H level, and the input control signals C2 and C3 are at the L level, and the input control signals C1 and C3 are at the H level. The operation result signal S6 is selected when the input control signal C2 is at the L level, and the operation result signal S7 is selected when the input control signals C1 and C2 are at the H level and the input control signal C3 is at the L level. input Control signal C1~C3 selects the operation result signal S8 when all H level.
[0031]
5 and 6 are circuit diagrams showing specific examples of the selection circuit 31 having the above configuration. FIG. 5 shows a circuit example in which the switches SW1-1, SW1-2, SW1-3 to SW8-1, SW8-2, and SW8-3 are configured by MOS switches. FIG. 6 shows a circuit example in which the switches SW1-1, SW1-2, SW1-3 to SW8-1, SW8-2, and SW8-3 are configured by C-MOS transmission gates.
[0032]
As described above, in the driving circuit integrated type liquid crystal display device in which the pixel portion 12 and the peripheral driving circuit are integrally formed on the same glass substrate 11, a plurality of operation result signals are selected during the operation test of the driving circuit. By adopting a configuration in which one of the operation result signals is input to the circuit 31 and one of them is selected by the selection circuit 31 and output to the outside of the substrate via the single test terminal 33, the operation result signal corresponding to each of the plurality of operation result signals is obtained. Since there is no need to provide test terminals, the number of terminals on the display panel can be minimized. As a result, the size of the display panel can be reduced, and the size of the entire display device can be reduced.
[0033]
In the above-described embodiment, an example has been described in which one selection circuit 31 is mounted, and operation result signals are input to the selection circuit 31 from a plurality of drive circuits. However, the present invention is not limited to this. Absent. For example, when there is room in the terminal arrangement space, it is possible to adopt a configuration in which a large number of operation result signals supplied from a plurality of drive circuits are grouped and a selection circuit is provided for each group. According to this, although the number of test terminals needs to be provided by the number of selection circuits, the number of terminals is slightly increased. However, by performing parallel processing by a plurality of selection circuits, a large number of operation result signals can be processed by one selection circuit. The time required for the operation test can be shortened as compared with the case of performing the operation test.
[0034]
Further, when one selection circuit is arranged for one driving circuit, or when there are many operation result signals output from one driving circuit, the operation result signals output from the one driving circuit are grouped. It is also possible to adopt a configuration in which a selection circuit is provided for each group. Also in this case, the time required for the operation test can be reduced by the parallel processing by the plurality of selection circuits. As a case where the number of operation result signals output from one drive circuit is large, for example, a case where an operation test of a DA converter described later is performed can be considered.
[0035]
FIG. 7 is a block diagram showing a specific configuration example of the horizontal drivers 17A and 17B. Here, a configuration in the case of a digital interface drive circuit configuration including a DA conversion circuit is shown. As is clear from FIG. 7, the horizontal driver 17A has, for example, a digital driver configuration including a horizontal shift register 171, a data sampling latch 172, a second latch 173, a level shifter 174, and a DA conversion (DAC) circuit 175. I have. The horizontal driver 17B has exactly the same configuration as the horizontal driver 17A.
[0036]
The horizontal shift register 171 starts the shift operation in response to the horizontal start pulse HST supplied from the timing generator circuit 14 (see FIG. 1), and synchronizes with the horizontal clock pulse HCK supplied from the timing generator circuit 14. A sampling pulse to be sequentially transferred in one horizontal period is generated. The data sampling latch section 172 samples and latches display data Data, which is input from outside the substrate and is sequentially input through the interface circuit 13 (see 1) in one horizontal period in synchronization with the sampling pulse generated by the horizontal shift register 171. I do.
[0037]
The latched digital display data for one line is collectively transferred to the second latch section 173 during the horizontal blanking period. From the second latch unit 173, digital display data for one line is output all at once. The output digital display data for one line is leveled up by a level shifter 174 and provided to a DA conversion circuit 175, where it is converted into an analog display signal. The analog display signal for one line output from the DA conversion circuit 175 is output to the signal lines 25-1 to 25-x of the pixel unit 12.
[0038]
Here, as the DA conversion circuit 175, a reference voltage selection type DA conversion circuit that selects a reference voltage corresponding to a digital display signal from a plurality of reference voltages and outputs the selected reference voltage as an analog display signal is used. FIG. 8 shows an example of the configuration of this reference voltage selection type DA conversion circuit.
[0039]
As shown in FIG. 8, the reference voltage selection type DA conversion circuit includes x DA conversion circuits 175-1 and 175 -x provided corresponding to each of the signal lines 25-1 to 25 -x of the pixel unit 12. And a reference voltage generating circuit 176 for generating a plurality of reference voltages. The reference voltage generation circuit 176 generates eight reference voltages V0 to V7 corresponding to the number of bits of digital display data, in this example, three bits d2 (MSB), d1, d0 (LSB), and a DA conversion circuit 175- 1, 175-2, 175-3,... Here, the reference voltage V0 is a black signal reference voltage, and the reference voltage V7 is a white signal reference voltage.
[0040]
Each of the D / A conversion circuits 175-1, 175-2, 175-3,... Has the same circuit configuration, and each output terminal is connected to the signal lines 25-1 to 25-x of the pixel unit 12, respectively. Then, one of the reference voltages V0 to V7 provided from the reference voltage generation circuit 176 is selected from among the reference voltages V0 to V7 corresponding to the digital display data d2, d1, and d0, and the signal lines 25-1 to 25-1 of the pixel unit 12 are used as analog display signals. 25-x.
[0041]
Among the transmission lines transmitting the reference voltages V0 to V7 from the reference voltage generation circuit 176 to the first DA conversion circuit 175-1, for example, a switch SW is inserted in the transmission line L1 transmitting the reference voltage V0. In addition, a test line L2 is provided between a terminal on the DA converter circuit side of the switch SW and the test terminal 33A. The operation of the switch SW and the test line L2 will be described later.
[0042]
Next, specific circuit configurations of the DA conversion circuit 175 (175-1, 175-2, 175-3,...) And the reference voltage generation circuit 176 will be described.
[0043]
FIG. 9 is a circuit diagram showing an example of the configuration of the DA conversion circuit 175. As is clear from FIG. 9, the DA conversion circuit 175 includes, for example, eight gradation selection units 41-provided corresponding to the reference voltages V0 to V7 for eight gradations generated by the reference voltage generation circuit 176. 1 to 41-8. Each of the gradation selection units 41-1 to 41-8 is connected to each of the input lines 42-1 to 42-8 to which eight reference voltages V0 to V7 are applied and the signal lines 25-1 to 25-x, respectively. Three transistor switches corresponding to the digital display data d2, d1, and d0, for example, MOS switches are connected in series between the output lines 43 connected to the respective output lines 43.
[0044]
In the DA conversion circuit 175 having the above configuration, the MOS switches of the gradation selection units 41-1 to 41-8 perform on / off operations in accordance with the logical states of the digital display data d2, d1, and d0. Then, among the gradation selection units 41-1 to 41-8, all the MOS switches of any one of the gradation selection units are turned on according to the combination of the logics of the digital display data d2, d1, and d0. As a result, one of the eight reference voltages V0 to V8 is selected and output to the corresponding signal line 25 (25-1 to 25-x) via the output line 43 as an analog display signal.
[0045]
FIG. 10 is a circuit diagram showing an example of a circuit configuration of the reference voltage generation circuit 176. As is apparent from FIG. 10, the reference voltage generation circuit 176 has a configuration including a resistance division (resistance division) circuit. That is, in this example, since the number of gradations is 8, the voltage between the first reference potential VA and the second reference potential VB is divided by seven resistors R1 to R7 connected in series. Thereby, six reference voltages V1 to V6 are obtained from each voltage dividing point. By setting the reference potential VA to the reference voltage V0 and the reference potential VB to the reference voltage V7, the reference voltage generation circuit 176 generates a total of eight reference voltages V0 to V7.
[0046]
By the way, in the liquid crystal display device, as described above, the polarity of the display signal is changed in order to prevent the specific resistance (specific resistance value of the material) of the liquid crystal from deteriorating due to the continuous application of the same polarity DC voltage to the liquid crystal. AC inversion driving (1H inversion driving or 1F inversion driving) for inverting at a certain cycle is employed. Therefore, in the reference voltage generation circuit 176, the switches SW11 to SW14 are turned on (closed) / off (opened) by timing pulses φ1 and φ2 that are generated alternately in synchronization with the AC inversion.
[0047]
In the reference voltage generation circuit 176, when the timing pulse φ1 is generated at an inversion timing with AC inversion, the switches SW11 and SW14 are turned on, so that the positive power supply voltage VCC is used as the first reference potential VA, and the second reference potential VB is used as the first reference potential VA. A negative power supply voltage VSS (for example, a ground level) is provided. When the timing pulse φ2 is generated at the next inversion timing, the switches SW12 and SW13 are turned on, so that the negative power supply voltage VSS is supplied as the first reference potential VA and the positive power supply voltage VCC is supplied as the second reference potential VB.
[0048]
The DA conversion circuit 175 and the reference voltage generation circuit 176 having the above configuration are also subjected to the operation test described above. For example, when the DA conversion circuit 175 is an operation test target, the operation test is performed on each of the DA conversion circuits 175-1, 175-2, 175-3,... Provided corresponding to the number of pixels in the horizontal direction. Is required, the operation result signals corresponding to the number of pixels in the horizontal direction are output from the DA conversion circuit 175, and the number of operation result signals becomes extremely large.
[0049]
It is possible to provide one selection circuit 31 for these many operation result signals. In this case, however, there is an advantage that only one test terminal is required, but the operation test takes time. Therefore, when there is a margin in the number of terminals of the display panel, many operation result signals may be grouped, one selection circuit 31 may be provided for each group, and operation tests may be performed in parallel. By doing so, although the number of test terminals increases slightly, the time required for the operation test can be significantly reduced.
[0050]
By the way, in a display device represented by a liquid crystal display device, an operation test of a driving circuit can be performed as described above, but an output test (inspection) of the signal lines 25-1 to 25-x of the pixel unit 12 is performed. Has not been considered before. Therefore, in the liquid crystal display device according to the present embodiment, in the reference voltage selection type DA conversion circuit, as described above, the transmission line for transmitting, for example, the reference voltage V0 from the reference voltage generation circuit 176 to the first stage D / A conversion circuit 175-1. The switch SW is inserted into L1 and the test line L2 is wired between the terminal of the switch SW on the DA conversion circuit side and the test terminal 33A, so that the output of the signal lines 25-1 to 25-x is obtained. Testing is possible.
[0051]
Here, the output test of the signal lines 25-1 to 25-x will be specifically described. First, in the normal operation, the switch SW is in the ON state, and the reference voltage is supplied from the reference voltage generation circuit 176 to the DA conversion circuits 175-1, 175-2, 175-3,. It is transmitted by L1.
[0052]
On the other hand, at the time of the output test, the switch SW is first turned on under the control by the input control signal C supplied from the outside of the glass substrate 11, and the transmission line L1 and the DA conversion circuits 175-1, 175-2, and 175- The reference voltage V0 is written to the signal lines 25-1 to 25-x via 3,. Next, the switch SW is turned off, and the written reference voltage V0 is read from the test terminal 33A via the DA conversion circuits 175-1, 175-2, 175-3,... And the test line L2.
[0053]
As described above, a specific potential (in this example, the reference voltage V0) is written to the signal lines 25-1 to 25-x, and this is taken out of the substrate. An output test (inspection) of 25-1 to 25-x can be performed. Any of the above-described input control signals C1 to C3 may be used as the input control signal C for controlling the switch SW. Considering the on-resistance of the switch SW, a transmission line for a black signal or a transmission line for a white signal having a lower impedance than other transfer lines having a divided resistor is used as a transmission line into which the switch SW is inserted. Is good.
[0054]
As the test terminal 33A, a terminal different from the test terminal 33 used in the operation test of the drive circuit described above may be used, or the same terminal may be used and the test line L2 may be connected to the input line of the selection circuit 31. It is also possible to wire them as one and perform an output test (inspection) of the signal lines 25-1 to 25-x as one of the operation tests of the drive circuit.
[0055]
In the present embodiment, a case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as a display element of a pixel has been described as an example. However, the present invention is not limited to application to a liquid crystal display device. The present invention can be applied to all driving circuit integrated display devices such as an EL display device using an electroluminescence (EL) element as an element.
[0056]
【The invention's effect】
As described above, according to the present invention, in a drive circuit-integrated display device in which a pixel portion and a peripheral drive circuit are integrally formed on the same transparent insulating substrate, a plurality of drive circuits are provided during an operation test of the drive circuit. It is necessary to provide a test terminal corresponding to each of a plurality of operation result signals by adopting a configuration in which one of the operation result signals is selected by a selection circuit and output to the outside of the board via a single test terminal. Since the number of terminals of the display panel can be reduced to a minimum, the size of the display panel can be reduced, and the size of the entire display device can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a drive circuit integrated type liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a configuration of a pixel circuit.
FIG. 3 is an equivalent circuit diagram illustrating an example of a configuration of a selection circuit.
FIG. 4 is a state diagram according to input control signals C1 to C3 of a selection circuit.
FIG. 5 is a circuit diagram showing a specific example of a selection circuit.
FIG. 6 is a circuit diagram showing another specific example of the selection circuit.
FIG. 7 is a block diagram illustrating an example of a configuration of a horizontal driver.
FIG. 8 is a block diagram illustrating an example of a configuration of a reference voltage selection type DA conversion circuit.
FIG. 9 is a circuit diagram illustrating an example of a specific circuit configuration of a DA conversion circuit.
FIG. 10 is a circuit diagram showing an example of a specific circuit configuration of a reference voltage generation circuit.
[Explanation of symbols]
11: glass substrate, 12 pixel section, 13: interface (IF) circuit, 14: timing generator (TG) circuit, 15: CS driver, 16: vertical driver, 17A, 17B: horizontal driver, 20: pixel, 21: TFT (Thin film transistor), 22: liquid crystal cell, 23: storage capacitor, 24, 24-1 to 24-y: scanning line, 25, 25-1 to 25-x: signal line, 31: selection circuit, 33: test terminal

Claims (4)

A pixel portion in which pixels are arranged in a matrix on a transparent insulating substrate,
A driving circuit formed on the same transparent insulating substrate as the pixel portion and driving the pixel portion;
A control terminal for taking in a control signal for designating one of a plurality of signals indicating the operation result from outside the transparent insulating substrate during an operation test of the drive circuit,
A selection circuit that selects and outputs one of the plurality of signals based on the control signal input through the control terminal;
A display terminal for outputting a signal selected by the selection circuit to the outside of the transparent insulating substrate. There are a plurality of the driving circuits,
2. The display device according to claim 1, wherein the selection circuit selects and outputs one of a plurality of signals indicating respective operation results of the plurality of drive circuits. The display device according to claim 1, wherein the display element of the pixel is a liquid crystal cell. 2. The display device according to claim 1, wherein the pixel portion, the drive circuit, and the selection circuit are formed on the transparent insulating substrate using low-temperature polysilicon or continuous grain silicon.

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