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JP2004193457A - Method for forming two-layer bump - Google Patents

Method for forming two-layer bump Download PDF

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Publication number
JP2004193457A
JP2004193457A JP2002361893A JP2002361893A JP2004193457A JP 2004193457 A JP2004193457 A JP 2004193457A JP 2002361893 A JP2002361893 A JP 2002361893A JP 2002361893 A JP2002361893 A JP 2002361893A JP 2004193457 A JP2004193457 A JP 2004193457A
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JP
Japan
Prior art keywords
resist
forming
layer
plating
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002361893A
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Japanese (ja)
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JP3703455B2 (en
Inventor
Seiji Okaji
成治 岡治
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Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
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Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP2002361893A priority Critical patent/JP3703455B2/en
Publication of JP2004193457A publication Critical patent/JP2004193457A/en
Application granted granted Critical
Publication of JP3703455B2 publication Critical patent/JP3703455B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To apply a resist once in a method for forming a two-layer bump for an electrode of a semiconductor by plating. <P>SOLUTION: In the method for forming the two-layer bump 20, the first time a small hole 16 is formed in a resist 15A to use the resist to plate a copper bump 17, and a hole 18 is widened to use the same resist used for the second time to plate a gold skin 19. The same resist 15A is used twice, while the holes 16 and 18 are formed different in sizes, to reduce the consumption of the resist to a half as large as before. Also resist coating processes can be reduced by one. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は二層バンプの形成方法に関し、特にめっきによる半導体の電極用二層バンプの形成方法に関する。
【０００２】
【従来の技術】
半導体ウェハの電極部分にめっきでバンプを形成する技術は昔からあった。しかし昔のバンプは金または半田の単層バンプであった。金バンプは作りやすく抵抗が低く接続の信頼性が高いが、材料費が非常に高い。一方半田バンプは材料費が安いが、作りにくく抵抗が高く接続の信頼性が低い。このため金バンプも半田バンプも一長一短であった。
【０００３】
これを改良するため二層のバンプが発明された。二層バンプでよく使われる材料は銅と金である。銅は材料費が安く抵抗が低いが、表面が酸化しやすい。表面が酸化すると接続の信頼性がなくなる。そこでバンプのコアを銅でつくり、バンプ表面を金で覆うようにした。銅の表面を金で覆えば銅が酸化することがない。
【０００４】
当初は特開平２−２５３６２８号公報、第３図のように単純に銅めっきの上に金めっきを積んでいた。これでも接続に必要な面は金めっきできるからである。ところがこの二層バンプは銅バンプの側面が露出しているため、そこが腐食することが分かった。すなわちこの構造は信頼性に欠ける。
【０００５】
そこで次に特開平２−２５３６２８号公報、第４図のように、銅バンプを形成したところでいったんレジストを除去し、再度銅バンプより一回り大きいレジストパターンを作り、それを用いて金めっきする方法が考えられた。こうすれば銅バンプの側面も金めっきで覆われるので、銅バンプが腐食することがない。こうして二層バンプの信頼性が確保できるようになった。
【０００６】
本発明のもとになる従来技術はこの二層バンプである。ただし特開平２−２５３６２８号公報、第４図の説明は簡単すぎて理解しにくい。また第４図の二回目のレジスト（６Ａ）の高さが銅バンプ（７）より低いのは不適当である。そのためここで従来の二層バンプを詳しく説明する。なお第４図の二回目のレジスト（６Ａ）の高さが銅バンプ（７）より低いのは不適当であるとは、もしそうであると、金めっき（８）が第４図のように一様な厚さにならず、レジストのないところは厚くついてキノコ形になるからである。バンプのピッチが以前のように広い場合はキノコ形でも差し支えないが、現在のようにピッチを極力狭くしなければならないときにキノコ形は都合が悪い。
【０００７】
図６（ａ）〜図１０（ｊ）は従来の二層バンプの形成方法を工程順に図解した斜視図である。図６（ａ）はバンプを形成する直前の半導体基板であり、シリコン基板３１の上面にアルミニウム配線３２を設けている。
【０００８】
次に図６（ｂ）のようにシリコン基板３１およびアルミニウム配線３２の上面を絶縁膜３３で覆う。ただしアルミニウム配線上３２の、後にバンプを形成する部分３２Ａは絶縁膜３３を除去しておく。
【０００９】
次に図６（ｃ）のように絶縁膜３３およびアルミニウム配線３２の上面に全面的にめっき用電極３４を形成する。めっき用電極３４はチタンなどをスパッタリングして形成し、後にバンプを電気めっきするのに使う。めっき用電極３４の厚さは１μｍ以下である。
【００１０】
次に図７（ｄ）のようにめっき用電極３４の上面に厚いレジスト３５を塗布する。このときバンプを形成する部分だけはフォトリソグラフィーによりレジスト３５に孔３６をあけておく。レジスト３５の厚さは２０μｍ程度必要である。レジスト３５として現在はポジレジストが普通であるがネガレジストでもよい。
【００１１】
次に図７（ｅ）のように銅バンプ３７を銅の電気めっきで形成する。レジスト３５の上に電気めっきはつかないから、レジスト３５の孔３６の中だけに電気めっきが成長する。レジスト３５の孔３６が四角柱であるので、出来上がった銅バンプ３７も四角柱になる。
【００１２】
次に図８（ｆ）のようにレジスト３５を除去して銅バンプ３７を露出させる。
【００１３】
次に図８（ｇ）のように一回目より厚いレジスト３８を全面に塗布する。しかし銅バンプ３７の所だけは、銅バンプ３７より一回り大きい孔３９をフォトリソグラフィーによりあけておく。二回目のレジスト３８の種類は一回目と同じでよい。
【００１４】
次に図９（ｈ）のように銅バンプ３７の側面と上面を覆うように金４０の電気めっきをおこない、コアが銅バンプ３７で表皮が金４０の二層バンプ４１を形成する。側面の金４０めっきはレジスト３８によって周囲を規制されているので一様な厚さになり、キノコ形にならない。前述のように、このとき二回目のレジスト３８が銅バンプ３７より低いと、レジスト３８より上の部分は金４０めっきが厚くついてキノコ形になり具合が悪い。
【００１５】
次に図９（ｉ）のように二回目のレジスト３８を除去して銅コア／金表皮の二層バンプ４１を露出させる。この段階ではめっき用電極３４により各二層バンプ４１（図示しないが二層バンプ４１は多数ある）がショートしている。
【００１６】
最後に図１０（ｊ）のようにめっき用電極３４をエッチングして取り除き、各二層バンプ４１を電気的に独立させ、半導体の電極として使えるようにする。
【００１７】
【特許文献１】
特開平２−２５３６２８号公報
【００１８】
【発明が解決しようとする課題】
前述の従来の方法により完成した二層バンプ４１の特性・信頼性には問題ない。しかしコストには問題がある。その理由は、レジスト塗布を二度するため（図７（ｄ）、図８（ｇ））、工程が長く、またレジスト３５、３８の費用が高くつくからである。めっき用のレジスト３５、３８は他の工程のレジストに比べて１０倍〜２０倍も厚いため材料費がかさむ。
【００１９】
レジスト３５、３８はめっきが終われば捨ててしまう。本願発明者は厚いレジスト３５、３８を二度も塗布することに大きな無駄を感じ、レジスト塗布を一度に減らせないか鋭意検討した結果本願発明をするに至った。
【００２０】
【課題を解決するための手段】
本発明の、めっきによる半導体の電極用二層バンプの形成方法においては、同じレジストに、一回目は小さい孔をあけて銅バンプのめっきに使い、二回目は孔を広げて金表皮をめっきするのに使うようにした。このように同一のレジストを孔のサイズを変えて二回使うようにしたのが本発明の特徴である。従来は孔のサイズを変えるたびにレジストを塗布し直していたから、本発明によりレジストの消費量が従来の約半分で済むことになる。めっき用のレジストは通常の工程のレジストの１０倍〜２０倍も厚いから材料費がかさむ。したがってレジストの消費量が半分になることはコストダウンに大きく寄与する。またレジスト塗布工程が一回減るから、それもコストダウンに寄与する。従来の方法によっても本発明の方法によっても、完成した二層バンプ自体に差はない。
【００２１】
請求項１記載の発明は、半導体基板上にめっき用の厚いポジレジストと保護用の薄いポジレジストの二層レジストを塗布し、次に前記の厚いポジレジストと前記の薄いポジレジストの両方を貫通した孔を形成し、次に前記の孔の中に金属のコアをめっきで形成し、次に前記の薄いポジレジストを除去し、次に前記の金属コアを含む一回り大きい孔を前記の厚いポジレジストに形成し、次に前記の孔の中に金属表皮をめっきで形成する工程を少なくとも含むことを特徴とする二層バンプの形成方法である。
【００２２】
請求項２記載の発明は、請求項１記載の二層バンプの形成方法において、前記の厚いポジレジストの厚さが２０μｍ以上、前記の薄いポジレジストの厚さが２μｍ以下であることを特徴とする二層バンプの形成方法である。
【００２３】
請求項３記載の発明は、半導体基板上にめっき用の厚いポジレジストを塗布し、次に前記の厚いポジレジストに孔を形成し、次に前記の孔の中に金属のコアをめっきで形成し、次に前記の厚いポジレジストの表面を除去し、次に前記の金属コアを含む一回り大きい孔を前記の厚いポジレジストに形成し、次に前記の孔の中に金属表皮をめっきで形成する工程を少なくとも含むことを特徴とする二層バンプの形成方法である。
【００２４】
請求項４記載の発明は、請求項３記載の二層バンプの形成方法において、前記の厚いポジレジストの厚さが２０μｍ以上であることを特徴とする二層バンプの形成方法である。
【００２５】
請求項５記載の発明は、請求項３記載の二層バンプの形成方法において、前記の厚いポジレジストの表面を除去する厚さが２μｍ以下であることを特徴とする二層バンプの形成方法である。
【００２６】
請求項６記載の発明は、請求項３記載の二層バンプの形成方法において、前記の厚いポジレジストの表面を除去する方法が酸素プラズマによるエッチングであることを特徴とする二層バンプの形成方法である。
【００２７】
請求項７記載の発明は、請求項１または請求項３記載の二層バンプの形成方法において、前記のコアの金属が銅であり、前記の表皮の金属が金であることを特徴とする二層バンプの形成方法である。
【００２８】
【発明の実施の形態】
図１（ａ）〜図５（ｊ）は本発明の二層バンプの形成方法を工程順に図解した斜視図である。図１（ａ）はバンプを形成する直前の半導体基板であり、シリコン基板１１の上面にアルミニウム配線１２を設けている。
【００２９】
次に図１（ｂ）のようにシリコン基板１１およびアルミニウム配線１２の上面を絶縁膜１３（ＳｉＯ２またはＳｉＮｘ）で覆う。ただしアルミニウム配線１２上の、後にバンプを形成する部分１２Ａは絶縁膜１３を除去しておく。
【００３０】
次に図１（ｃ）のように絶縁膜１３およびアルミニウム配線１２の上面に全面的にめっき用電極１４を形成する。めっき用電極１４はチタンなどをスパッタリングして形成し、後にバンプを電気めっきするときの電極に使う。めっき用電極１４の厚さは１μｍ以下である。
【００３１】
次に図２（ｄ）のようにめっき用電極１４の上面にレジスト１５を二層塗布する。一層目（下側）のレジスト１５Ａの役割は、めっきの形状を規制することである。そのため一層目のレジスト１５Ａは厚く、その厚さは従来の方法の二回目のレジストと同じ厚さ、つまり最終的な（銅コア＋金表皮）の高さを超える２０μｍ以上の厚さが必要である。二層目（上側）のレジスト１５Ｂは、銅めっきの最中に一層目のレジスト１５Ａがめっき液により荒れたり変質したりするのを防ぐための保護カバーである。そのため二層目のレジスト１５Ｂは薄くてよい（２μｍ以下、１μｍ程度）。
【００３２】
一層目のレジスト１５Ａの種類は従来の方法のレジストと同じでよいが、但しポジレジストでなければならない（ネガレジストは使えない）。二層目のレジスト１５Ｂは銅めっき後に一層目のレジスト１５Ａから容易に剥離させられるものが適当である。従来の方法ではこのような種類のレジストは使わない。また二層目のレジスト１５Ｂもポジレジストでなければならない。
【００３３】
そしてバンプを形成する部分だけはフォトリソグラフィーにより一層目のレジスト１５Ａと二層目のレジスト１５Ｂを貫通した孔１６をあけておく。この孔１６のサイズが後に銅バンプのサイズになる。
【００３４】
次に図２（ｅ）のように銅バンプ１７を銅の電気めっきで形成する。レジスト１５の上に電気めっきはつかないから、レジスト１５の孔１６の中だけに電気めっきが成長する。レジスト１５の孔１６が四角柱であるので、出来上がった銅バンプ１７も四角柱になる。二層目のレジスト１５Ｂはめっき中にめっき液により荒れたり変質したりするが、一層目のレジスト１５Ａは二層目のレジスト１５Ｂで保護されているので、荒れたり変質したりしない。
【００３５】
次に図３（ｆ）のように荒れた二層目のレジスト１５Ｂを酸素プラズマにより剥離除去すると、荒れていない新鮮な一層目のレジスト１５Ａが現われる。
【００３６】
次に図３（ｇ）のようにフォトリソグラフィーにより一回目（図２（ｄ））の孔１６より一回り大きい孔１８を一層目のレジスト１５Ａに形成する。すなわち二回目の孔１８は銅バンプ１７より一回り大きいようにする。二回目の孔１８は次工程で金めっきに使う。本発明では同じ（一層目の）レジスト１５Ａに、一回目は小さい孔１６をあけて銅バンプ１７のめっきに使い、二回目は孔１８を広げて金表皮をめっきするのに使う。このように同一のレジスト１５Ａを孔１６、１８のサイズを変えて二回使うのが本発明の特徴である。従来は孔のサイズを変えるたびに新しくレジストを塗布していたから、本発明によりレジストの消費量が従来の約半分で済むことになる。めっき用のレジストは通常の工程のレジストの１０倍〜２０倍も厚いから材料費がかさむ。したがってレジストの消費量が半分になることはコストダウンに大きく寄与する。またレジスト塗布工程が一回減るから、それもコストダウンに寄与する。
【００３７】
本発明のように同一のレジスト１５Ａを孔１６、１８のサイズを変えて二回使うためには次の条件を満たさないといけない。
（１）レジスト１５がポジ形であること。ポジレジストは光の当った部分が溶解するようになるため、一回目は狭い範囲を露光して狭い範囲を溶解し、二回目には一回目を含む広い範囲を露光して広い範囲を溶解することができる。一方ネガレジストは光の当った部分が溶解しなくなるため、このようなことができない。
（２）二回目の露光の前にめっき工程があるが、めっき工程でレジストの表面が荒れたり変質したりすると、二回目の露光範囲通りにレジストが溶解できなくなる。したがってめっき工程ではレジストの保護をする必要がある。確実なのは図２（ｄ）のように薄い二層目のレジスト１５Ｂを保護カバーとして塗布することである（請求項１〜請求項２の方法）。しかし簡易な方法として、二層目のレジストを使わず、レジストを一層目１５Ａだけとし、二回目の露光の前にレジスト１５Ａの表面を酸素プラズマなどで１μｍ〜２μｍ削り新鮮な表面を出す方法もある（請求項３〜請求項６の方法、この方法は図示しない）。もちろんこの方がコストが安い。どちらを選ぶかはバンプのサイズ、数、密度、必要な信頼度などにより決める。
【００３８】
次に図４（ｈ）のように銅バンプ１７の側面、上面を覆うように金１９の電気めっきをおこない、コアが銅バンプ１７で表皮が金１９の二層バンプ２０を形成する。側面の金１９めっきはレジストによって周囲を規制されているので一様な厚さになり、キノコ形にならない。
【００３９】
次に図４（ｉ）のようにレジスト１５Ａを除去して銅コア／金表皮の二層バンプ２０を露出させる。この段階ではめっき用電極１４により各二層バンプ２０（図示しないが二層バンプ２０は多数ある）がショートしている。
【００４０】
最後に図５（ｊ）のようにめっき用電極１４をエッチングして取り除き、各二層バンプ２０を電気的に独立させ、半導体の電極として使えるようにする。
【００４１】
従来の方法によっても本発明の方法によっても、完成した二層バンプ２０自体に差はないが、コストは大きく異なる。その理由は、従来は高価な厚いレジストを二度も塗布しているが、本発明では一度の塗布で済むからである。
【００４２】
上の説明ではコアが銅、表皮が金であった。これに対しコアに鉛系半田などを、表皮にニッケル系合金などを使うことも考えられるが、あまりメリットが無いようである。したがって今のところ銅コア／金表皮が最適な組み合わせと思われる。
【００４３】
【発明の効果】
本発明の二層バンプ２０の形成方法においては、同じレジスト１５Ａに、一回目は小さい孔１６をあけて銅バンプ１７のめっきに使い、二回目は孔１８を広げて金表皮１９をめっきするのに使うようにした。このように同一のレジスト１５Ａを孔１６、１８のサイズを変えて二回使うようにしたのでレジストの消費量が従来の約半分で済むことになる。またレジスト塗布工程を一回減らすことができる。
【図面の簡単な説明】
【図１】本発明の二層バンプの形成方法を工程順に図解した斜視図
【図２】本発明の二層バンプの形成方法を工程順に図解した斜視図
【図３】本発明の二層バンプの形成方法を工程順に図解した斜視図
【図４】本発明の二層バンプの形成方法を工程順に図解した斜視図
【図５】本発明の二層バンプの形成方法を工程順に図解した斜視図
【図６】従来の二層バンプの形成方法を工程順に図解した斜視図
【図７】従来の二層バンプの形成方法を工程順に図解した斜視図
【図８】従来の二層バンプの形成方法を工程順に図解した斜視図
【図９】従来の二層バンプの形成方法を工程順に図解した斜視図
【図１０】従来の二層バンプの形成方法を工程順に図解した斜視図
【符号の説明】
１１ シリコン基板
１２ アルミニウム配線
１２Ａ アルミニウム配線の露出部分
１３ 絶縁膜
１４ めっき用電極
１５ レジスト
１５Ａ 一層目のレジスト
１５Ｂ 二層目のレジスト
１６ 小さい孔
１７ 銅バンプ
１８ 大きい孔
１９ 金
２０ 二層バンプ
３１ シリコン基板
３２ アルミニウム配線
３２Ａ アルミニウム配線の露出部分
３３ 絶縁膜
３４ めっき用電極
３５ 一回目のレジスト
３６ 小さい孔
３７ 銅バンプ
３８ 二回目のレジスト
３９ 大きい孔
４０ 金
４１ 二層バンプ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a two-layer bump, and more particularly to a method for forming a two-layer bump for a semiconductor electrode by plating.
[0002]
[Prior art]
The technology for forming bumps on the electrode portions of a semiconductor wafer by plating has long existed. However, the old bumps were gold or solder single layer bumps. Gold bumps are easy to make, have low resistance and high connection reliability, but have a very high material cost. Solder bumps, on the other hand, have low material costs, but are difficult to make and have high resistance and low connection reliability. For this reason, both gold bumps and solder bumps have their merits and demerits.
[0003]
To improve this, a two-layer bump was invented. Commonly used materials for double-layer bumps are copper and gold. Copper has low material cost and low resistance, but its surface is easily oxidized. If the surface is oxidized, the connection reliability is lost. Therefore, the bump core was made of copper and the bump surface was covered with gold. If the copper surface is covered with gold, the copper will not be oxidized.
[0004]
Initially, gold plating was simply stacked on copper plating as disclosed in Japanese Patent Laid-Open No. 2-253628 and FIG. This is because the surface necessary for the connection can still be gold-plated. However, this two-layer bump was found to corrode because the side surface of the copper bump was exposed. That is, this structure lacks reliability.
[0005]
Then, as shown in Japanese Patent Application Laid-Open No. 2-253628, FIG. 4, when the copper bump is formed, the resist is once removed, and a resist pattern that is one size larger than the copper bump is formed again, and gold plating is performed using the resist pattern. Was considered. By doing so, the side surfaces of the copper bumps are also covered with the gold plating, so that the copper bumps are not corroded. Thus, the reliability of the two-layer bump can be secured.
[0006]
The prior art on which the present invention is based is this two-layer bump. However, the description of JP-A-2-253628 and FIG. 4 is too simple to understand. Also, it is inappropriate that the height of the second resist (6A) in FIG. 4 is lower than that of the copper bump (7). Therefore, the conventional two-layer bump will be described in detail here. Note that it is inappropriate that the height of the second resist (6A) in FIG. 4 is lower than that of the copper bump (7). If so, the gold plating (8) is as shown in FIG. This is because the thickness is not uniform, and the portion without the resist is thick and becomes a mushroom shape. If the bump pitch is as wide as before, the mushroom shape may be used, but the mushroom shape is inconvenient when the pitch needs to be as narrow as possible.
[0007]
FIG. 6A to FIG. 10J are perspective views illustrating a conventional two-layer bump forming method in the order of steps. FIG. 6A shows a semiconductor substrate just before the bump is formed, and an aluminum wiring 32 is provided on the upper surface of the silicon substrate 31.
[0008]
Next, the upper surfaces of the silicon substrate 31 and the aluminum wiring 32 are covered with an insulating film 33 as shown in FIG. However, the insulating film 33 is removed from a portion 32A on the aluminum wiring 32 where bumps will be formed later.
[0009]
Next, as shown in FIG. 6C, a plating electrode 34 is formed on the entire upper surface of the insulating film 33 and the aluminum wiring 32. The plating electrode 34 is formed by sputtering titanium or the like, and is used for electroplating bumps later. The thickness of the plating electrode 34 is 1 μm or less.
[0010]
Next, a thick resist 35 is applied to the upper surface of the plating electrode 34 as shown in FIG. At this time, a hole 36 is formed in the resist 35 only by a portion where the bump is formed by photolithography. The thickness of the resist 35 needs to be about 20 μm. Currently, a positive resist is generally used as the resist 35, but a negative resist may be used.
[0011]
Next, as shown in FIG. 7E, copper bumps 37 are formed by copper electroplating. Since electroplating is not applied on the resist 35, electroplating grows only in the holes 36 of the resist 35. Since the hole 36 of the resist 35 is a square pole, the completed copper bump 37 is also a square pole.
[0012]
Next, as shown in FIG. 8F, the resist 35 is removed to expose the copper bumps 37.
[0013]
Next, as shown in FIG. 8G, a resist 38 thicker than the first time is applied to the entire surface. However, a hole 39 that is slightly larger than the copper bump 37 is formed only by the photolithography at the copper bump 37. The type of resist 38 for the second time may be the same as that for the first time.
[0014]
Next, as shown in FIG. 9H, electroplating of the gold 40 is performed so as to cover the side surface and the upper surface of the copper bump 37, and the two-layer bump 41 having the core of the copper bump 37 and the skin of the gold 40 is formed. Since the periphery of the gold 40 plating on the side surface is regulated by the resist 38, it has a uniform thickness and does not have a mushroom shape. As described above, if the resist 38 at the second time is lower than the copper bump 37 at this time, the portion above the resist 38 is thickly plated with gold 40 and becomes a mushroom shape, which is not good.
[0015]
Next, as shown in FIG. 9I, the resist 38 for the second time is removed to expose the two-layer bump 41 of the copper core / gold skin. At this stage, each of the two-layer bumps 41 (not shown, but there are many two-layer bumps 41) is short-circuited by the plating electrode.
[0016]
Finally, as shown in FIG. 10 (j), the plating electrode 34 is removed by etching so that each double-layer bump 41 is electrically independent and can be used as a semiconductor electrode.
[0017]
[Patent Document 1]
JP-A-2-253628
[Problems to be solved by the invention]
There is no problem in the characteristics and reliability of the double-layer bump 41 completed by the above-described conventional method. However, there is a problem with cost. The reason is that the resist coating is performed twice (FIGS. 7 (d) and 8 (g)), the process is long, and the costs of the resists 35 and 38 are high. Since the resists 35 and 38 for plating are 10 to 20 times thicker than resists in other processes, the material cost is increased.
[0019]
The resists 35 and 38 are discarded after plating. The inventor of the present application felt a great waste of applying the thick resists 35 and 38 twice, and as a result of earnestly examining whether the resist application could be reduced at a time, the present inventor came to make the present invention.
[0020]
[Means for Solving the Problems]
In the method of forming a two-layer bump for semiconductor electrodes by plating according to the present invention, a small hole is first formed in the same resist to be used for plating a copper bump, and the second time is used for plating a gold skin by expanding the hole. I used it. Thus, the feature of the present invention is that the same resist is used twice with the hole size changed. Conventionally, the resist is reapplied every time the size of the hole is changed. Therefore, according to the present invention, the resist consumption can be reduced to about half that of the conventional method. Since the resist for plating is 10 to 20 times thicker than the resist in the normal process, the material cost is increased. Therefore, halving the resist consumption greatly contributes to cost reduction. Moreover, since the resist coating process is reduced once, it also contributes to cost reduction. There is no difference in the completed two-layer bump itself by either the conventional method or the method of the present invention.
[0021]
According to the first aspect of the present invention, a two-layer resist of a thick positive resist for plating and a thin positive resist for protection is applied on a semiconductor substrate, and then penetrates both the thick positive resist and the thin positive resist. And then forming a metal core in the hole by plating, then removing the thin positive resist, and then making the larger hole containing the metal core into the thicker hole. A method for forming a two-layer bump, comprising forming at least a positive resist and then forming a metal skin by plating in the hole.
[0022]
The invention according to claim 2 is the method for forming a double-layer bump according to claim 1, wherein the thickness of the thick positive resist is 20 μm or more, and the thickness of the thin positive resist is 2 μm or less. This is a method for forming a two-layer bump.
[0023]
According to a third aspect of the present invention, a thick positive resist for plating is applied on a semiconductor substrate, then a hole is formed in the thick positive resist, and then a metal core is formed in the hole by plating. Next, the surface of the thick positive resist is removed, and then a hole that is slightly larger including the metal core is formed in the thick positive resist, and then a metal skin is plated in the hole. It is a formation method of the double layer bump characterized by including the process of forming at least.
[0024]
The invention according to claim 4 is the method for forming a double-layer bump according to claim 3, wherein the thickness of the thick positive resist is 20 μm or more.
[0025]
The invention according to claim 5 is the method for forming a double-layer bump according to claim 3, wherein the thickness for removing the surface of the thick positive resist is 2 μm or less. is there.
[0026]
The invention according to claim 6 is the method for forming a double-layer bump according to claim 3, wherein the method for removing the surface of the thick positive resist is etching by oxygen plasma. It is.
[0027]
The invention according to claim 7 is the method for forming a double-layer bump according to claim 1 or 3, wherein the metal of the core is copper and the metal of the skin is gold. This is a method for forming a layer bump.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1A to FIG. 5J are perspective views illustrating the two-layer bump forming method of the present invention in the order of steps. FIG. 1A shows a semiconductor substrate immediately before bump formation, and an aluminum wiring 12 is provided on the upper surface of a silicon substrate 11.
[0029]
Next, as shown in FIG. 1B, the upper surfaces of the silicon substrate 11 and the aluminum wiring 12 are covered with an insulating film 13 (SiO 2 or SiNx). However, the insulating film 13 is removed from the aluminum wiring 12 where a bump 12A is to be formed later.
[0030]
Next, as shown in FIG. 1C, a plating electrode 14 is formed on the entire upper surface of the insulating film 13 and the aluminum wiring 12. The plating electrode 14 is formed by sputtering titanium or the like, and is used as an electrode for later electroplating bumps. The thickness of the plating electrode 14 is 1 μm or less.
[0031]
Next, as shown in FIG. 2D, two layers of resist 15 are applied to the upper surface of the plating electrode 14. The role of the first layer (lower side) resist 15A is to regulate the shape of plating. Therefore, the first layer resist 15A is thick, and the thickness is the same as the second resist of the conventional method, that is, a thickness of 20 μm or more exceeding the final (copper core + gold skin) height. is there. The second-layer (upper) resist 15B is a protective cover for preventing the first-layer resist 15A from being roughened or altered by the plating solution during copper plating. Therefore, the second-layer resist 15B may be thin (2 μm or less, about 1 μm).
[0032]
The type of the resist 15A for the first layer may be the same as the resist of the conventional method, but it must be a positive resist (a negative resist cannot be used). The second-layer resist 15B is suitably one that can be easily removed from the first-layer resist 15A after copper plating. Conventional methods do not use this type of resist. The second layer resist 15B must also be a positive resist.
[0033]
Then, a hole 16 penetrating through the first-layer resist 15A and the second-layer resist 15B is opened only at the portion where the bump is formed by photolithography. The size of the hole 16 will later become the size of the copper bump.
[0034]
Next, as shown in FIG. 2E, copper bumps 17 are formed by copper electroplating. Since electroplating is not applied on the resist 15, electroplating grows only in the holes 16 of the resist 15. Since the hole 16 of the resist 15 is a quadrangular prism, the completed copper bump 17 is also a quadrangular prism. The second-layer resist 15B is roughened or deteriorated by the plating solution during plating, but the first-layer resist 15A is protected by the second-layer resist 15B, so that it is not roughened or deteriorated.
[0035]
Next, when the rough second-layer resist 15B is peeled and removed by oxygen plasma as shown in FIG. 3F, a fresh first-layer resist 15A that is not rough appears.
[0036]
Next, as shown in FIG. 3G, a hole 18 that is slightly larger than the hole 16 in the first time (FIG. 2D) is formed in the first resist 15A by photolithography. That is, the second hole 18 is made slightly larger than the copper bump 17. The second hole 18 is used for gold plating in the next step. In the present invention, the same (first layer) resist 15A is first used for plating the copper bumps 17 by opening a small hole 16 and the second time is used for plating the gold skin by expanding the holes 18. Thus, the feature of the present invention is that the same resist 15A is used twice while changing the sizes of the holes 16 and 18. Conventionally, a new resist is applied every time the size of the hole is changed. Therefore, according to the present invention, the resist consumption can be reduced to about half that of the conventional one. Since the resist for plating is 10 to 20 times thicker than the resist in the normal process, the material cost is increased. Therefore, halving the resist consumption greatly contributes to cost reduction. Moreover, since the resist coating process is reduced once, it also contributes to cost reduction.
[0037]
In order to use the same resist 15A twice while changing the size of the holes 16 and 18 as in the present invention, the following conditions must be satisfied.
(1) The resist 15 is positive. The positive resist dissolves in the lighted part, so the first time exposes a narrow area and dissolves the narrow area, and the second time exposes the wide area including the first and dissolves the wide area. be able to. On the other hand, the negative resist can not do this because the lighted part does not dissolve.
(2) Although there is a plating step before the second exposure, if the resist surface is roughened or deteriorated in the plating step, the resist cannot be dissolved in the second exposure range. Therefore, it is necessary to protect the resist in the plating process. As shown in FIG. 2D, a thin second layer of resist 15B is applied as a protective cover (methods of claims 1 and 2). However, as a simple method, the resist of the second layer is not used, the resist is only the first layer 15A, and the surface of the resist 15A is scraped by 1 μm to 2 μm with oxygen plasma or the like before the second exposure to give a fresh surface. There is a method according to claims 3 to 6 (this method is not shown). Of course, this is cheaper. Which to choose depends on the size, number, density, and required reliability of the bumps.
[0038]
Next, as shown in FIG. 4H, electroplating of the gold 19 is performed so as to cover the side surface and the upper surface of the copper bump 17 to form a two-layer bump 20 having a core of the copper bump 17 and a skin of the gold 19. Since the periphery of the gold 19 plating on the side surface is restricted by the resist, it has a uniform thickness and does not have a mushroom shape.
[0039]
Next, as shown in FIG. 4I, the resist 15A is removed to expose the two-layer bump 20 of the copper core / gold skin. At this stage, each of the two-layer bumps 20 (there are a large number of two-layer bumps 20 although not shown) is short-circuited by the electrode 14 for plating.
[0040]
Finally, as shown in FIG. 5 (j), the plating electrode 14 is removed by etching so that each two-layer bump 20 is electrically independent and can be used as a semiconductor electrode.
[0041]
There is no difference in the completed two-layer bump 20 itself according to the conventional method and the method of the present invention, but the cost is greatly different. The reason is that, conventionally, an expensive thick resist is applied twice, but in the present invention, only one application is required.
[0042]
In the above explanation, the core was copper and the skin was gold. On the other hand, it is possible to use lead-based solder for the core and nickel-based alloy for the skin, but there seems to be no merit. Therefore, for now, the copper core / gold skin seems to be the optimal combination.
[0043]
【The invention's effect】
In the method of forming the two-layer bump 20 of the present invention, the same resist 15A is first plated with a small hole 16 to be used for plating the copper bump 17, and the second time the hole 18 is widened and the gold skin 19 is plated. I used it. As described above, the same resist 15A is used twice by changing the sizes of the holes 16 and 18, so that the consumption of the resist can be reduced to about half of the conventional amount. Moreover, the resist coating process can be reduced once.
[Brief description of the drawings]
FIG. 1 is a perspective view illustrating a method of forming a double-layer bump according to the present invention in the order of steps. FIG. 2 is a perspective view illustrating a method of forming a double-layer bump according to the present invention in the order of steps. FIG. 4 is a perspective view illustrating a method for forming a two-layer bump according to the present invention in order of steps. FIG. 5 is a perspective view illustrating a method for forming a two-layer bump according to the present invention in order of steps. FIG. 6 is a perspective view illustrating a conventional two-layer bump forming method in the order of steps. FIG. 7 is a perspective view illustrating a conventional two-layer bump forming method in the order of steps. FIG. FIG. 9 is a perspective view illustrating a conventional two-layer bump forming method in the order of steps. FIG. 10 is a perspective view illustrating a conventional two-layer bump forming method in the order of steps.
11 Silicon substrate 12 Aluminum wiring 12A Exposed portion of aluminum wiring 13 Insulating film 14 Electrode for plating 15 Resist 15A First resist 15B Second resist 16 Small hole 17 Copper bump 18 Large hole 19 Gold 20 Two-layer bump 31 Silicon substrate 32 Aluminum wiring 32A Exposed portion of aluminum wiring 33 Insulating film 34 Electrode for plating 35 First resist 36 Small hole 37 Copper bump 38 Second resist 39 Large hole 40 Gold 41 Double layer bump

Claims (7)

半導体基板上にめっき用の厚いポジレジストと保護用の薄いポジレジストの二層レジストを塗布し、次に前記の厚いポジレジストと前記の薄いポジレジストの両方を貫通した孔を形成し、次に前記の孔の中に金属のコアをめっきで形成し、次に前記の薄いポジレジストを除去し、次に前記の金属コアを含む一回り大きい孔を前記の厚いポジレジストに形成し、次に前記の孔の中に金属表皮をめっきで形成する工程を少なくとも含むことを特徴とする二層バンプの形成方法。A two-layer resist of a thick positive resist for plating and a thin positive resist for protection is applied on a semiconductor substrate, and then a hole penetrating both the thick positive resist and the thin positive resist is formed. Forming a metal core in the hole by plating, then removing the thin positive resist, and then forming a one-larger hole in the thick positive resist containing the metal core; A method for forming a two-layer bump, comprising at least a step of forming a metal skin by plating in the hole. 請求項１記載の二層バンプの形成方法において、前記の厚いポジレジストの厚さが２０μｍ以上、前記の薄いポジレジストの厚さが２μｍ以下であることを特徴とする二層バンプの形成方法。2. The method for forming a double-layer bump according to claim 1, wherein the thickness of the thick positive resist is 20 [mu] m or more and the thickness of the thin positive resist is 2 [mu] m or less. 半導体基板上にめっき用の厚いポジレジストを塗布し、次に前記の厚いポジレジストに孔を形成し、次に前記の孔の中に金属のコアをめっきで形成し、次に前記の厚いポジレジストの表面を除去し、次に前記の金属コアを含む一回り大きい孔を前記の厚いポジレジストに形成し、次に前記の孔の中に金属表皮をめっきで形成する工程を少なくとも含むことを特徴とする二層バンプの形成方法。A thick positive resist for plating is applied on a semiconductor substrate, then a hole is formed in the thick positive resist, and then a metal core is formed by plating in the hole, and then the thick positive resist is formed. Removing at least the surface of the resist, and then forming at least one large hole including the metal core in the thick positive resist and then forming a metal skin in the hole by plating. A method for forming a two-layer bump, which is characterized. 請求項３記載の二層バンプの形成方法において、前記の厚いポジレジストの厚さが２０μｍ以上であることを特徴とする二層バンプの形成方法。4. The method for forming a double-layer bump according to claim 3, wherein the thickness of the thick positive resist is 20 [mu] m or more. 請求項３記載の二層バンプの形成方法において、前記の厚いポジレジストの表面を除去する厚さが２μｍ以下であることを特徴とする二層バンプの形成方法4. The method for forming a double-layer bump according to claim 3, wherein a thickness for removing the surface of the thick positive resist is 2 [mu] m or less. 請求項３記載の二層バンプの形成方法において、前記の厚いポジレジストの表面を除去する方法が酸素プラズマによるエッチングであることを特徴とする二層バンプの形成方法。4. The method for forming a double-layer bump according to claim 3, wherein the method for removing the surface of the thick positive resist is etching by oxygen plasma. 請求項１または請求項３記載の二層バンプの形成方法において、前記のコアの金属が銅であり、前記の表皮の金属が金であることを特徴とする二層バンプの形成方法。4. The method for forming a double-layer bump according to claim 1 or 3, wherein the metal of the core is copper and the metal of the skin is gold.
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JP2006128457A (en) * 2004-10-29 2006-05-18 Toyoda Gosei Co Ltd Light-emitting element and device thereof
JP2007165671A (en) * 2005-12-15 2007-06-28 Renesas Technology Corp Method for manufacturing semiconductor device
JP2010171365A (en) * 2008-12-26 2010-08-05 Toshiba Corp Semiconductor device and method of manufacturing the same
US8017967B2 (en) 2004-09-09 2011-09-13 Toyoda Gosei Co., Ltd. Light-emitting element including a fusion-bonding portion on contact electrodes
EP2879173A3 (en) * 2013-11-06 2015-08-26 Chipmos Technologies Inc. Electroplated silver alloy bump for a semiconductor structure
JP2015195382A (en) * 2013-11-12 2015-11-05 チップモス テクノロジーズ インコーポレイテッドＣｈｉｐｍｏｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｉｎｃ． Semiconductor structure and manufacturing method thereof
JP2015216344A (en) * 2014-04-21 2015-12-03 新光電気工業株式会社 Wiring board and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
US8017967B2 (en) 2004-09-09 2011-09-13 Toyoda Gosei Co., Ltd. Light-emitting element including a fusion-bonding portion on contact electrodes
JP2006128457A (en) * 2004-10-29 2006-05-18 Toyoda Gosei Co Ltd Light-emitting element and device thereof
JP2007165671A (en) * 2005-12-15 2007-06-28 Renesas Technology Corp Method for manufacturing semiconductor device
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JP2015195382A (en) * 2013-11-12 2015-11-05 チップモス テクノロジーズ インコーポレイテッドＣｈｉｐｍｏｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｉｎｃ． Semiconductor structure and manufacturing method thereof
JP2015216344A (en) * 2014-04-21 2015-12-03 新光電気工業株式会社 Wiring board and method of manufacturing the same

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