JP2004193352A - Layered capacitor and its mounted product - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layered capacitor which can reduce the extension and contraction due to the piezoelectric effect as much as possible. <P>SOLUTION: A part 12a which is constituted of only dielectric material exists between a first capacitor C11 and a second capacitor C12. Parts 12b which are constituted of only dielectric material surrounding the first and the second capacitor parts C11, C12 exist at both ends in lengthwise direction and at both ends in height direction. Parts 12c which are mostly constituted of dielectric material exist at both ends of a chip 12 in the widthwise direction. A pair of external electrodes 14 cover both ends of the chip 12 in the widthwise direction. Suppression effect to the change in the length, width and height directions is obtained by the dielectric materials 12a, 12b and 12c and the external electrode 14. The extension and contraction in the layered capacitor 11 by the piezoelectric effect can be reduced as much as possible. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer capacitor having a capacitor portion composed of a predetermined number of internal electrodes stacked via a dielectric portion in a rectangular parallelepiped dielectric chip, and a multilayer capacitor formed by mounting the multilayer capacitor on a substrate Regarding the mounting body.
[0002]
[Prior art]
1A to 1C show an example of a conventional multilayer capacitor. FIG. 1A is a top view of the multilayer capacitor, and FIG. 1B is z1-z1 of FIG. 1A. 1C is a sectional view taken along line z2-z2 of FIG. 1A. In the following description, the horizontal direction in FIG. 1A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 1B is referred to as a height direction.
[0003]
The multilayer capacitor 1 has a rectangular parallelepiped dielectric chip 2 having a dimension relationship of length> width = height, a predetermined number of internal electrodes 3 embedded in the chip 2, and both ends in the length direction of the chip 2. And a pair of external electrodes 4 provided on the side. A predetermined number of internal electrodes 3 stacked via the dielectric portion constitute a capacitor portion C1 capable of securing a predetermined capacitance.
[0004]
The chip 2 is formed by alternately laminating and compressing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing a metal powder, and then firing. The unfired internal electrode layer becomes the internal electrode 3 by firing. The external electrode 4 is formed by applying and baking an electrode paste containing metal powder on each end surface of the chip 2 in the longitudinal direction so as to cover four surrounding surfaces.
[0005]
The internal electrodes 3 are arranged so that two adjacent internal electrodes 3 face each other in the height direction via the dielectric portion, and each edge is alternately exposed on two end faces in the longitudinal direction of the chip 2. ing. The edge of the internal electrode 3 exposed from one end face in the longitudinal direction of the chip 2 is electrically connected to one external electrode 4, and the edge of the internal electrode 3 exposed from the other end face is connected to the other external electrode 4. Is electrically connected to
[0006]
Since the capacitor portion C1 in the chip 2 is separated from the both end surfaces in the width direction and both end surfaces in the height direction of the chip 2 by a predetermined distance, the capacitor portions C1 are provided at both end portions in the width direction and both end portions in the height direction of the chip 2. There is a portion 2a composed of only a dielectric material so as to surround C1.
[0007]
Since the multilayer capacitor 1 has a dielectric portion between each of the internal electrodes 3 constituting the capacitor portion C1, when charging and discharging are repeated with a DC voltage applied to the pair of external electrodes 4, When a DC voltage or a DC current containing a ripple component is applied, the dielectric portion sandwiched between the internal electrodes 3 expands and contracts due to the piezoelectric effect. Occurs. The expansion and contraction increase as the dielectric constant of the dielectric material forming the chip 2 increases and as the voltage or current applied to the external electrode 4 increases.
[0008]
The expansion and contraction due to the piezoelectric effect does not appear in a specific direction, and when the external electrode 4 is excluded, the chip 2 appears in all of the length direction, the width direction and the height direction in a complex manner. It is known that in the case of the multilayer capacitor 1 as shown in FIG. 1C, the amount of expansion and contraction in the length direction is the largest compared to the amount of expansion and contraction in other directions.
[0009]
Therefore, as shown in FIG. 2, if the above-described expansion and contraction occurs when the multilayer capacitor 1 is mounted on the substrate SB by bonding the external electrodes 4 thereof to the lands RD via the bonding material CM such as solder or the like. Mainly, the force caused by expansion and contraction in the largest length direction is transmitted to the substrate SB, and the substrate SB is bent, and the bending and the restoration thereof are repeated to generate vertical vibrations on the substrate SB, and this vertical vibration generates an unpleasant audible sound. I do.
[0010]
[Patent Document 1]
JP 2002-232110 A
[0011]
[Problems to be solved by the invention]
In the multilayer capacitor 1 shown in FIGS. 1 (A) to 1 (C), a portion 2a composed of only a dielectric material is formed at both ends in the width direction and both ends in the height direction of the chip 2 so as to surround the capacitor portion C1. Since it is present and has a structure in which a pair of external electrodes 4 cover both ends in the length direction of the chip 2, the effect of suppressing expansion and contraction in the width direction and the height direction is equal to that of the dielectric material portion 2a. It can be obtained by the external electrode 4, and the effect of suppressing the expansion and contraction in the length direction can be obtained by the dielectric material portion 2a.
[0012]
However, as described above, in the case of the multilayer capacitor 1 as shown in FIGS. 1A to 1C, the amount of expansion and contraction in the length direction generated in the capacitor portion C1 is smaller than the amount of expansion and contraction in other directions. Therefore, it is difficult to obtain the effect of suppressing the expansion and contraction in the length direction by the dielectric material portion 2a. Therefore, in the mounting state shown in FIG. 2, since the largest force caused by expansion and contraction in the length direction is transmitted from the multilayer capacitor 1 to the substrate 2, the substrate SB easily vibrates up and down, and the audible sound due to this vibration is also reduced. Easy to occur.
[0013]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a multilayer capacitor capable of reducing expansion and contraction due to a piezoelectric effect as much as possible, and a multilayer capacitor capable of reducing generation of audible sound caused by expansion and contraction of the multilayer capacitor as much as possible. It is to provide a capacitor mounting body.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is characterized in that, in a rectangular parallelepiped dielectric chip having the largest length among length, width and height, two adjacent internal electrodes are interposed via a dielectric portion. A multilayer capacitor having a capacitor portion composed of a predetermined number of internal electrodes arranged so as to face each other in the height direction, wherein two or more capacitor portions are provided in the chip at intervals in the length direction. The edges of the internal electrodes constituting the capacitor portion are alternately exposed at two end faces in the width direction of the chip. A pair of external electrodes are formed so as to extend over the surface, and the edges of the internal electrodes exposed from one end face of each capacitor portion are electrically connected to one external electrode and the internal electrodes exposed from the other end face. The edge of the electrode is connected to the other external electrode There is a portion made of only a dielectric material so as to surround each capacitor portion at both ends in the length direction and both ends in the height direction of the chip, and a dielectric material is provided between each capacitor portion. It is characterized by the fact that there is a portion composed of only the
[0015]
According to this multilayer capacitor, there is a portion made of only a dielectric material so as to surround each capacitor portion at both ends in the length direction and both ends in the height direction of the chip, and only the dielectric material is provided between each capacitor portion. And a structure in which a pair of external electrodes covers both ends in the width direction of the chip. It can be obtained by the electrode, and the effect of suppressing the expansion and contraction in the width direction can be obtained by the dielectric material portion, and the effect of suppressing the expansion and contraction in the height direction can be obtained by the dielectric material portion and the external electrode. Therefore, expansion and contraction caused in the multilayer capacitor due to the piezoelectric effect can be reduced as much as possible.
[0016]
The features, functions and effects of the invention according to the other claims will become apparent from the following description and the accompanying drawings.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
3 (A) to 3 (C) show a first embodiment of the multilayer capacitor according to the present invention. FIG. 3 (A) is a top view of the multilayer capacitor, and FIG. 3 (B) is FIG. 3 (A). 3) is a sectional view taken along line a1-a1, and FIG. 3 (C) is a sectional view taken along line a2-a2 in FIG. 3 (A). In the following description, the horizontal direction in FIG. 3A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 3B is referred to as a height direction.
[0018]
The multilayer capacitor 11 includes a rectangular chip 12 having a dimension relationship of length>width> height, a predetermined number of first internal electrodes 13 embedded in the chip 12, and a first internal electrode 13 in the chip 12. The chip 12 includes the same number of second internal electrodes 13 buried at a predetermined interval in the length direction from 13, and a pair of external electrodes 14 provided at both ends in the width direction of the chip 12. A predetermined number of first internal electrodes 13 on the left side of FIG. 3A stacked via the dielectric portion constitute a first capacitor portion C11 capable of securing a predetermined capacitance, and are stacked via the dielectric portion. A predetermined number of the second internal electrodes 13 on the right side of FIG. 3A constitute a second capacitor section C12 capable of securing the same capacitance.
[0019]
The chip 12 is formed by alternately laminating and pressing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing a metal powder, and firing the resultant. The unfired internal electrode layers become the first and second internal electrodes 13 by firing. The external electrode 14 may be formed by applying an electrode paste containing a metal powder to each end face in the width direction of the chip 12 so as to cover four surrounding surfaces, or by baking the electrode paste after applying the electrode paste. It is created by firing at the same time.
[0020]
The first internal electrodes 13 are arranged so that two adjacent first internal electrodes 13 face each other in the height direction via a dielectric portion, and the edge of a narrow portion 13a formed at one end in each width direction. Are alternately exposed at two end faces in the width direction of the chip 12. The second internal electrode 13 is also arranged such that two adjacent internal electrodes 13 face each other in the height direction via the dielectric portion. The edge of the narrow portion 13a formed at one end in the width direction is a chip. Twelve end faces in the width direction are alternately exposed. The edges of the first and second internal electrodes 13 exposed from one end face in the width direction of the chip 12 are electrically connected to one external electrode 14 and the first and second internal electrodes 13 exposed from the other end face. Is electrically connected to the other external electrode 14.
[0021]
Since the first capacitor section C11 and the second capacitor section C12 are connected in parallel to the pair of external electrodes 14, the capacitance obtained by the multilayer capacitor 11 is equal to the capacitance of the first capacitor section C11. And the capacitance of the second capacitor section C12.
[0022]
Since the first capacitor portion C11 and the second capacitor portion C12 in the chip 12 are separated from each other at a predetermined interval in the length direction, the distance between the first capacitor portion C11 and the second capacitor portion C12 of the chip 12 is large. There is a portion 12a composed of only a dielectric material. Further, since the first and second capacitor portions C11 and C12 in the chip 12 are separated from the both end surfaces in the longitudinal direction and both end surfaces in the height direction of the chip 12 by a predetermined distance, both ends in the longitudinal direction of the chip 12 are provided. There is a portion 12b made of only a dielectric material so as to surround the first and second capacitor portions C11 and C12 at both ends of the portion and the height direction. Furthermore, since the internal electrodes 13 constituting the first and second capacitor portions C11 and C12 are connected to the external electrodes 14 via the narrow portions 13a, most of the internal electrodes 13 are located at both ends in the width direction of the chip 12. There is a portion 12c made of body material.
[0023]
In the multilayer capacitor 11, since a dielectric portion exists between the internal electrodes 13 constituting the first and second capacitor portions C11 and C12, charging and discharging are performed in a state where a DC voltage is applied to the pair of external electrodes 14. Is repeated, or when a DC voltage or DC current including a ripple component is applied, the dielectric portion sandwiched between the first internal electrodes 13 and the dielectric portion sandwiched between the second internal electrodes 13 each have a piezoelectric effect. Causes expansion and contraction.
[0024]
However, in the multilayer capacitor 11, there is a portion 12a made of only a dielectric material between the first and second capacitor portions C11 and C12, and both ends in the length direction and both ends in the height direction of the chip 12 are provided. There is a portion 12b made of only a dielectric material surrounding the first and second capacitor portions C11 and C12, and portions 12c mostly made of a dielectric material at both ends in the width direction of the chip 12. In addition, since the pair of external electrodes 14 has a structure covering both end portions in the width direction of the chip 12, the effect of suppressing the expansion and contraction in the length direction is reduced by the dielectric material portions 12a, 12b and 12c and the outside. The dielectric material portions 12a, 12b, and 12c can obtain the effect of suppressing the expansion and contraction in the width direction by the electrode 14, and can further obtain the effect of suppressing the expansion and contraction in the width direction. An inhibitory effect on expansion the dielectric material portion 12a, can be obtained by 12b and 12c and the external electrodes 14, thereby can be significantly reduced stretch occurring in the multilayer capacitor 11 by the piezoelectric effect.
[0025]
Therefore, even when the pair of external electrodes 14 of the multilayer capacitor 11 are bonded to the lands RD of the substrate SB via the bonding material CM such as solder, the force transmitted to the substrate SB as the multilayer capacitor 11 expands and contracts is small. As a result, the vertical vibration of the substrate SB is also reduced, and the generation of audible sound due to this vibration is extremely small or almost inaudible.
[0026]
Further, since a pair of external electrodes 14 are provided at both ends in the width direction of the chip 12 whose degree of expansion and contraction is smaller than the length direction, expansion and contraction of the multilayer capacitor 11 occurs when the multilayer capacitor 11 is mounted on the substrate SB. In this case, it is possible to prevent the force accompanying the expansion and contraction in the length direction from being transmitted to the substrate SB as much as possible.
[0027]
In order to make it difficult for the force caused by the expansion and contraction of the multilayer capacitor 11 to be transmitted to the substrate SB, the bonding area between the external electrode 14 and the land RD is reduced by minimizing the land RD as shown in FIG. Alternatively, as shown in FIG. 4B, the bonding area between the external electrode 14 and the land RD is reduced by partially bonding the external electrode 14 and the land RD with the bonding material CM in the length direction. It is good to do. Further, if a material having low hardness, for example, a conductive resin or the like is used as the bonding material CM, the propagation of the force is reduced by the bonding material CM, so that the force accompanying expansion and contraction of the multilayer capacitor 11 is hardly transmitted to the substrate SB. it can.
[0028]
In the above-described embodiment, the chip 12 having the dimensional relationship of length>width> height is shown as the rectangular parallelepiped chip 12, but the chip 12 has the dimension of length> width = height or length>height> width. They may have a relationship.
[0029]
Further, in the above-described embodiment, the narrow portion 13a is provided at one end in the width direction of the internal electrode 13 constituting each of the capacitor portions C11 and C12, but the internal electrode 13 having no narrow portion 13 is used. Alternatively, the edges of the internal electrodes 13 may be used so as to be alternately exposed at two end faces in the width direction of the chip 12.
[0030]
Further, in the above-described embodiment, two capacitors C11 and C12 are provided in the chip 12 at intervals in the length direction. However, three or more capacitors are provided at intervals in the length direction. You may do so.
[0031]
Furthermore, in the above-described embodiment, a pair of external electrodes 14 is provided at both ends in the width direction of the chip 12, but as shown in FIG. A pair or more dummy electrodes 15 may be further provided. The dummy electrode 15 is coated with an electrode paste containing a metal powder on each end surface in the length direction of the chip 12 so as to cover two surrounding surfaces (both end surfaces in the height direction) and baked. It is prepared by firing simultaneously with the unfired internal electrode layer after application of the electrode paste. According to the multilayer capacitor 11 shown in FIG. 5, in addition to the above, an effect of suppressing the expansion and contraction in the width direction and the height direction can be obtained by the dummy electrode 15. Can be more reliably reduced.
[0032]
[Second embodiment]
6 (A) to 6 (C) show a second embodiment of the multilayer capacitor according to the present invention. FIG. 6 (A) is a top view of the multilayer capacitor, and FIG. 6 (B) is FIG. 6 (A). 6) is a sectional view taken along line b1-b1, and FIG. 6C is a sectional view taken along line b2-b2 in FIG. 6A. In the following description, the horizontal direction in FIG. 6A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 6B is referred to as a height direction.
[0033]
The multilayer capacitor 21 has a rectangular parallelepiped chip 22 having a dimension relationship of length>width> height, a predetermined number of first internal electrodes 23 embedded in the chip 22, and a first internal electrode 23 in the chip 22. The chip 22 includes the same number of second internal electrodes 23 buried at a predetermined interval in the width direction from 23, and a pair of external electrodes 24 provided at both ends in the length direction of the chip 22. A predetermined number of first internal electrodes 23 on the upper side in FIG. 6A stacked via the dielectric portion constitute a first capacitor portion C21 capable of securing a predetermined capacitance, and are stacked via the dielectric portion. A predetermined number of the second internal electrodes 23 on the lower side of FIG. 6A constitute a second capacitor portion C22 capable of securing the same capacitance.
[0034]
The chip 22 is formed by alternately laminating and compressing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing metal powder, and then firing the chip. The unfired internal electrode layers become the first and second internal electrodes 23 by firing. The external electrode 24 may be coated with an electrode paste containing metal powder on each end surface of the chip 22 in the longitudinal direction so as to cover four surrounding surfaces, or may be a non-fired internal electrode after application of the electrode paste. It is created by firing simultaneously with the layers.
[0035]
The first internal electrode 23 is disposed such that two adjacent internal electrodes 23 face each other in the height direction via the dielectric portion, and each edge is alternately provided on two end surfaces in the length direction of the chip 22. It is exposed. The second internal electrode 23 is also arranged so that two adjacent internal electrodes 23 face each other in the height direction via the dielectric portion, and each edge is alternately formed on two end surfaces in the longitudinal direction of the chip 22. It is exposed. The edges of the first and second internal electrodes 23 exposed from one end surface in the length direction of the chip 22 are electrically connected to one external electrode 24 and the first and second internal electrodes exposed from the other end surface. The edge of 23 is electrically connected to the other external electrode 24.
[0036]
Since the first capacitor portion C21 and the second capacitor portion C22 are connected in parallel to the pair of external electrodes 24, the capacitance obtained by the multilayer capacitor 21 is equal to the capacitance of the first capacitor portion C21. And the capacitance of the second capacitor section C22.
[0037]
Since the first capacitor portion C21 and the second capacitor portion C22 group in the chip 22 are separated from each other at a predetermined interval in the width direction, there is a gap between the first capacitor portion C21 and the second capacitor portion C22 of the chip 22. There is a portion 22a composed of only a dielectric material. Further, since the first and second capacitor portions C21 and C22 in the chip 22 are separated from the both end surfaces in the width direction and both end surfaces in the height direction of the chip 22 by a predetermined distance, respectively, the two end portions in the width direction of the chip 22 are separated from each other. At both ends in the height direction, there are portions 22b made of only a dielectric material so as to surround the first and second capacitor portions C21 and C22.
[0038]
The multilayer capacitor 21 has a dielectric portion between the internal electrodes 23 constituting the first and second capacitor portions C21 and C22. Therefore, the multilayer capacitor 21 is charged and discharged while a DC voltage is applied to the pair of external electrodes 24. Is repeated, or when a DC voltage or DC current including a ripple component is applied, the dielectric portion sandwiched between the first internal electrodes 23 and the dielectric portion sandwiched between the second internal electrodes 23 each have a piezoelectric effect. Causes expansion and contraction.
[0039]
However, in the multilayer capacitor 21, there is a portion 22a made of only a dielectric material between the first and second capacitor portions C21 and C22, and at both ends in the width direction and both ends in the height direction of the chip 22. There is a portion 22b made of only a dielectric material so as to surround the first and second capacitor portions C21 and C22, and has a structure in which a pair of external electrodes 24 cover both ends in the longitudinal direction of the chip 22. Therefore, the effect of suppressing the expansion and contraction in the length direction can be obtained by the dielectric material portions 22a and 22b, and the effect of suppressing the expansion and contraction in the width direction can be obtained by the dielectric material portions 22a and 22b and the external electrode. 24, and the effect of suppressing expansion and contraction in the height direction can be obtained by the dielectric material portions 22a and 22b and the external electrode 24. , Thereby it can be significantly reduced stretch occurring in the multilayer capacitor 21 by the piezoelectric effect.
[0040]
Accordingly, even when the pair of external electrodes 24 of the multilayer capacitor 21 are joined to the lands RD of the substrate SB via the joining material CM such as solder, the force transmitted to the substrate SB as the multilayer capacitor 21 expands and contracts is small. As a result, the vertical vibration of the substrate SB is also reduced, and the generation of audible sound due to this vibration is extremely small or almost inaudible.
[0041]
In order to make it difficult for the force accompanying the expansion and contraction of the multilayer capacitor 21 to be transmitted to the substrate SB, the bonding area between the external electrode 24 and the land RD is reduced by minimizing the land RD as shown in FIG. Alternatively, as shown in FIG. 7A, the bonding area between the external electrode 24 and the land RD is reduced by partially bonding the external electrode 24 and the land RD by the bonding material CM in the width direction. It is good to Further, if a material having a low hardness, for example, a conductive resin or the like is used as the bonding material CM, the propagation of the force can be reduced by the bonding material CM, and the force accompanying expansion and contraction of the multilayer capacitor 21 can be hardly transmitted to the substrate SB. it can.
[0042]
In the above-described embodiment, the chip 22 having a length>width> height dimension is shown as the rectangular parallelepiped chip 22. However, the chip 22 has a length> width = height or length>height> width dimension. They may have a relationship.
[0043]
In the above embodiment, the two capacitor portions C21 and C22 are provided in the chip 22 at intervals in the width direction. However, three or more capacitor portions are provided at intervals in the width direction. You may.
[0044]
Further, in the above-described embodiment, a pair of external electrodes 24 is provided at both ends in the length direction of the chip 22. However, as shown in FIG. A pair or more dummy electrodes 25 may be further provided. The dummy electrode 25 is coated with an electrode paste containing a metal powder on each end surface in the width direction of the chip 22 in a band shape so as to cover two surrounding surfaces (both end surfaces in the height direction), or baked. It is created by firing simultaneously with the unfired internal electrode layer after application of the electrode paste. According to the multilayer capacitor 21 shown in FIG. 8, in addition to the above, an effect of suppressing the expansion and contraction in the length direction and the height direction can be obtained by the dummy electrode 25. Expansion and contraction can be reduced more reliably.
[0045]
[Third embodiment]
9 (A) to 9 (C) show a third embodiment of the multilayer capacitor according to the present invention. FIG. 9 (A) is a top view of the multilayer capacitor, and FIG. 9 (B) is FIG. 9 (A). 9) is a sectional view taken along line c1-c1, and FIG. 9 (C) is a sectional view taken along line c2-c2 in FIG. 9 (A). In the following description, the horizontal direction in FIG. 9A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 9B is referred to as a height direction.
[0046]
The multilayer capacitor 31 has a rectangular parallelepiped chip 32 having a dimension relationship of length>width> height, a predetermined number of internal electrodes 33 embedded in the chip 32, and both ends in the width direction of the chip 32. And two pairs of external electrodes 34. The internal electrodes 33 stacked via the dielectric portion constitute a capacitor portion C31 capable of securing a predetermined capacitance.
[0047]
The chip 32 is formed by alternately laminating and compressing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing a metal powder. The unfired internal electrode layer becomes the internal electrode 33 by firing. In addition, the external electrode 34 is coated with an electrode paste containing metal powder in a band shape so as to cover two end surfaces in the width direction of the chip 32 (both end surfaces in the height direction), and is baked. It is prepared by firing simultaneously with the unfired internal electrode layer after application of the electrode paste. The external electrodes 34 have a width slightly larger than a narrow portion 33a to be described later, and two external electrodes are provided at both ends in the width direction of the chip 32 at intervals in the length direction.
[0048]
The internal electrodes 33 are arranged such that two adjacent internal electrodes 33 face each other in the height direction via a dielectric portion, and the edges of two narrow portions 33a formed at one end in the width direction are formed by a chip. 32 are alternately exposed at two end faces in the width direction. The two edges of the internal electrode 33 exposed from one end surface in the width direction of the chip 32 are electrically connected to the corresponding two external electrodes 34, respectively, and the internal electrode 33 exposed from the other end surface. The two edges are electrically connected to the other two corresponding external electrodes 34, respectively.
[0049]
Two narrow portions 33a are provided on each of the internal electrodes 33 constituting the capacitor portion C31, and the exposed edges of each of the narrow portions 33a are connected to separate external electrodes 34. The capacitance obtained between the external electrode 34 and the two external electrodes 34 at the other end in the width direction, and the capacitance between one external electrode 34 at one end in the width direction and one external electrode 34 at the other end in the width direction The capacitance obtained between them is the same.
[0050]
Since the capacitor portion C31 in the chip 32 is separated from the both ends in the length direction and both ends in the height direction of the chip 32 by a predetermined distance, respectively, both ends in the length direction and both ends in the height direction of the chip 32 There is a portion 32a made of only a dielectric material so as to surround the capacitor portion C31. Further, since each of the internal electrodes 33 constituting the capacitor portion C31 is connected to the external electrode 34 via the narrow portion 33a, the both ends of the chip 32 in the width direction are almost entirely made of a dielectric material. 32b exists.
[0051]
Since the multilayer capacitor 31 has a dielectric portion between the internal electrodes 33 forming the capacitor portion C31, a DC voltage is applied to the two pairs of external electrodes 32 or the external electrodes 32 addressed to one side. When charging / discharging is repeated, or when a DC voltage or DC current including a ripple component is applied, the dielectric portion sandwiched between the internal electrodes 33 expands and contracts due to a piezoelectric effect.
[0052]
However, in the above-mentioned multilayer capacitor 31, portions 32 a made of only a dielectric material are present at both ends in the length direction and both ends in the height direction of the chip 32 so as to surround the capacitor portion C 31, and both ends in the width direction of the chip 32 are provided. A portion 32b, which is mostly made of a dielectric material, exists in the portion, and two pairs of external electrodes 34 have a structure that partially covers both ends in the width direction of the chip 32. Can be obtained by the dielectric material portions 32a and 32b and the external electrode 34, and the effect of suppressing expansion and contraction in the width direction can be obtained by the dielectric material portions 32a and 32b. Further, the effect of suppressing expansion and contraction in the height direction can be obtained by the above-mentioned dielectric material portions 32a and 32b and the external electrode 34. It can be significantly reduced stretch occurring in the multilayer capacitor 31 by.
[0053]
Therefore, even when the two pairs of external electrodes 34 of the multilayer capacitor 31 are joined to the lands RD of the substrate SB via the joining material CM such as solder, the force transmitted to the substrate SB as the multilayer capacitor 31 expands and contracts is small. As a result, the vertical vibration of the substrate SB is also reduced, and the generation of audible sound due to this vibration is extremely small or almost inaudible.
[0054]
Further, since two pairs of external electrodes 34 are provided at both ends in the width direction of the chip 32 whose degree of expansion and contraction is smaller than that in the length direction, expansion and contraction of the multilayer capacitor 31 occurs when the multilayer capacitor 31 is mounted on the substrate SB. In this case, it is possible to prevent the force accompanying the expansion and contraction in the length direction from being transmitted to the substrate SB as much as possible.
[0055]
In order to make it difficult for the force caused by the expansion and contraction of the multilayer capacitor 31 to be transmitted to the substrate SB, the bonding area between the external electrode 34 and the land RD is reduced by minimizing the land RD as shown in FIG. Alternatively, as shown in FIG. 10B, the bonding area between the external electrode 34 and the land RD is reduced by partially bonding the external electrode 34 and the land RD by the bonding material CM in the length direction. It is good to do. When a material having low hardness, for example, a conductive resin or the like is used as the bonding material CM, the propagation of the force is reduced by the bonding material CM, so that the force accompanying expansion and contraction of the multilayer capacitor 31 is hardly transmitted to the substrate SB. it can.
[0056]
In the above-described embodiment, the chip 32 having a length>width> height dimension is shown as the rectangular parallelepiped chip 32. However, the chip 32 has a length> width = height or length>height> width dimension. They may have a relationship.
[0057]
In the above-described embodiment, two narrow portions 33a are provided at one end in the width direction of each internal electrode 33 constituting the capacitor portion C31. However, three or more narrow portions are provided in each internal electrode 33. Thus, the external electrode 34 may be provided to correspond to this.
[0058]
Furthermore, in the above-described embodiment, two pairs of external electrodes 34 are provided at both ends in the width direction of the chip 32. However, as shown in FIG. The electrode 35 may be provided. The dummy electrode 35 is formed by applying an electrode paste containing metal powder to each end surface of the chip 32 in the longitudinal direction so as to cover four peripheral surfaces thereof, or by sintering the electrode paste, or by applying an unfired internal electrode layer after applying the electrode paste. It is created by firing at the same time. According to the multilayer capacitor 31 shown in FIG. 11, in addition to the above, an effect of suppressing expansion and contraction in the width direction and the height direction can be obtained by the dummy electrode 35. Can be more reliably reduced.
[0059]
[Fourth embodiment]
FIGS. 12A to 12C show a multilayer capacitor according to a fourth embodiment of the present invention. FIG. 12A is a top view of the multilayer capacitor, and FIG. 12) is a sectional view taken along line d1-d1, and FIG. 12 (C) is a sectional view taken along line d2-d2 in FIG. 12 (A). In the following description, the horizontal direction in FIG. 12A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 12B is referred to as a height direction.
[0060]
The multilayer capacitor 41 includes a rectangular chip 42 having a dimension relationship of length>width> height, a predetermined number of first internal electrodes 43a embedded in the chip 42 at intervals in the length direction, and A predetermined number of internal electrodes 43 b buried from one end face to the other end face in the longitudinal direction inside the chip 42, two pairs of first external electrodes 44 provided at both ends in the width direction of the chip 42, And a pair of second external electrodes 45 provided at both ends in the length direction. Since the first internal electrodes 43a and the second internal electrodes have a structure in which the first internal electrodes 43a and the second internal electrodes are alternately overlapped with a dielectric portion interposed therebetween, a part of a predetermined number of the second internal electrodes 43b and a part thereof facing FIG. A predetermined number of first internal electrodes 43b on the left side constitute a first capacitor portion C41 capable of securing a predetermined capacitance, and a part of the predetermined number of second internal electrodes 43b and a part thereof facing the right side of FIG. A predetermined number of second internal electrodes 13 constitute a second capacitor section C42 capable of ensuring the same capacitance.
[0061]
The chip 42 includes two types of unfired dielectric layers made of ceramic slurry containing dielectric ceramic powder and two types of unfired internal electrode layers made of an electrode paste containing metal powder (for the first internal electrode 43a and the second internal electrode layer). And an unfired internal electrode layer for the electrode 43b) are alternately laminated and pressed, and then fired. The unfired internal electrode layer is formed by firing the first and second internal electrodes 43a and 43b. Become. The first external electrode 44 may be formed by applying an electrode paste containing metal powder in a band shape to each end face in the width direction of the chip 42 so as to cover two surrounding surfaces (both end faces in the height direction) and baking. Alternatively, the electrode paste is formed by firing simultaneously with the unfired internal electrode layer after the application of the electrode paste, while the second external electrode 45 is formed by applying an electrode paste containing metal powder to each end surface of the chip 42 in the length direction. It is formed by applying and baking so as to cover the four surrounding surfaces, or by baking simultaneously with the unfired internal electrode layer after applying the electrode paste.
[0062]
The first internal electrodes 43a and the second internal electrodes 43b are alternately arranged so as to face each other in the height direction via a dielectric portion, and the narrow portions 43a1 formed at both ends in the width direction of each first internal electrode 43a. Are exposed at two end surfaces in the width direction of the chip 42, and the longitudinal edges of each second internal electrode 43b are exposed at two end surfaces in the longitudinal direction of the chip 42. Two edges of each first internal electrode 43a exposed from one end face in the width direction of the chip 42 are electrically connected to one corresponding two first external electrodes 44, respectively, and are exposed from the other end face. The two edges of each of the first internal electrodes 43a are electrically connected to the corresponding two other first external electrodes 44, respectively. The edge of each second internal electrode 43b exposed from one end face in the length direction of the chip 42 is electrically connected to one second external electrode 45, and each edge exposed from the other end face in the length direction. The edge of the second internal electrode 43b is electrically connected to the other second external electrode 45.
[0063]
When two pairs of first external electrodes 44 are used as one of plus and minus and one pair of second external electrodes 45 are used as the other of plus and minus, the capacitance obtained by the multilayer capacitor 41 is the first capacitor. It is the sum of the capacitance of the portion C41 and the capacitance of the second capacitor portion C42. Of course, if the pair of first external electrodes 44 on the left side of FIG. 12A is used as one of positive and negative and the pair of second external electrodes 45 is used as the other of positive and negative, the static electricity obtained by the multilayer capacitor 41 can be obtained. The capacitance is the capacitance of the first capacitor portion C41, and the pair of first external electrodes 44 on the right side of FIG. 12A is one of plus and minus, and the pair of second external electrodes 45 is plus. If used as the other, the capacitance obtained by the multilayer capacitor 41 becomes the capacitance of the second capacitor unit C41.
[0064]
Since the first and second capacitor portions C41 and C42 in the chip 42 are separated from the both end surfaces in the height direction of the chip 42 by a predetermined interval, both ends of the chip 42 in the height direction are made of only a dielectric material. There is a configured portion 42a. Further, since each first internal electrode 43a is connected to the first external electrode 44 via the narrow portion 43a1, a portion 42b, which is mostly made of a dielectric material, is provided at both ends in the width direction of the chip 42. Exists.
[0065]
The multilayer capacitor 41 is provided between the first and second internal electrodes 43a and 43b forming the first capacitor portion C41 and between the first and second internal electrodes 43a and 43b forming the second capacitor portion C42. Due to the presence of the dielectric portion, for example, when charge / discharge is repeated in a state where a DC voltage is applied using two pairs of first external electrodes 44 as plus and one pair of second external electrodes 45 as minus, or When a DC voltage or a DC current containing a ripple component is applied, the dielectric portion sandwiched between the first and second internal electrodes 43a and 43b of the first capacitor portion C41 and the first and second internal portions of the second capacitor portion C42 Each of the dielectric portions sandwiched between the electrodes 43a and 43b expands and contracts due to the piezoelectric effect.
[0066]
However, in the above-described multilayer capacitor 41, portions 42a made of only a dielectric material are present at both ends in the height direction of the chip 42, and almost all of them are made of the dielectric material at both end portions in the width direction of the chip 42. And a pair of first external electrodes 44 has a structure that partially covers both ends in the width direction of the chip 42 and a pair of second external electrodes 45 Since it has a structure that covers both ends, the effect of suppressing the expansion and contraction in the length direction can be obtained by the dielectric material portions 42a and 42b and the first external electrode 44, and the effect of suppressing the expansion and contraction in the width direction can be obtained. The effect can be obtained by the dielectric material portions 42a and 42b and the second external electrode 45. Further, the effect of suppressing the expansion and contraction in the height direction can be obtained by the dielectric material portions 42a and 42b. It can be obtained by the second external electrode 45, thereby can be significantly reduced stretch occurring in the multilayer capacitor 41 by the piezoelectric effect.
[0067]
Therefore, the two pairs of first external electrodes 44 of the multilayer capacitor 41 are joined to the lands RD of the substrate SB via the joining material CM such as solder, and the pair of second external electrodes 45 are joined to the joining material CM such as solder. Even in the state of being bonded to the land RD of the substrate SB via the CM, the force transmitted to the substrate SB with the expansion and contraction of the multilayer capacitor 41 is small, and as a result, the vertical vibration of the substrate SB is also reduced, and the audible sound due to this vibration is reduced. The occurrence is extremely small or almost inaudible.
[0068]
In order to make it difficult for the force accompanying expansion and contraction of the multilayer capacitor 41 to be transmitted to the substrate SB, the first and second external electrodes are reduced by minimizing the land RD as shown in FIGS. 13 (A) and 13 (B). The bonding area between the lands RD and the lands RD is reduced, or the bonding between the first external electrodes 44 and the lands RD by the bonding material CM is partially performed in the length direction as shown in FIG. This may reduce the bonding area between the first external electrode 44 and the land RD. When a material having low hardness, for example, a conductive resin or the like is used as the bonding material CM, the propagation of the force is reduced by the bonding material CM, so that the force accompanying expansion and contraction of the multilayer capacitor 41 is hardly transmitted to the substrate SB. it can.
[0069]
In the above-described embodiment, the cuboid-shaped chip 42 having the dimension relationship of length>width> height is shown. However, the chip 42 has the dimension of length> width = height or length>height> width. They may have a relationship.
[0070]
In the above-described embodiment, two first internal electrodes 43a are provided at intervals in the length direction in the chip 42. However, three or more first internal electrodes 43a are provided at intervals in the length direction. And three or more pairs of the first external electrodes 44 may be provided accordingly.
[0071]
[Fifth Embodiment]
14 (A) to 14 (C) show a fifth embodiment of the multilayer capacitor according to the present invention. FIG. 14 (A) is a top view of the multilayer capacitor, and FIG. 14 (B) is FIG. 14 (A). 14) is a sectional view taken along line e1-e1, and FIG. 14 (C) is a sectional view taken along line e2-e2 in FIG. 14 (A). In the following description, the horizontal direction in FIG. 14A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 14B is referred to as a height direction.
[0072]
The multilayer capacitor 51 includes a rectangular chip 52 having a dimension relationship of length>width> height, a predetermined number of first internal electrodes 53 embedded in the chip 52, and a first internal electrode 53 in the chip 52. The chip includes the same number of second internal electrodes 53 buried at a predetermined interval in the length direction from 53, and two pairs of external electrodes 54 provided at both ends in the width direction of the chip 52. A predetermined number of first internal electrodes 53 on the left side of FIG. 14A stacked via the dielectric portion constitute a first capacitor portion C51 capable of securing a predetermined capacitance, and are stacked via the dielectric portion. A predetermined number of the second internal electrodes 53 on the right side of FIG. 14A constitute a second capacitor section C52 capable of securing the same capacitance.
[0073]
The chip 52 is formed by alternately laminating and firing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing a metal powder, and firing the resultant. The unfired internal electrode layers become the first and second internal electrodes 53 by firing. The external electrode 54 is coated with an electrode paste containing a metal powder on each end face in the width direction of the chip 52 so as to cover two surrounding surfaces (both end faces in the height direction), and is baked, or It is prepared by firing simultaneously with the unfired internal electrode layer after application of the electrode paste. The external electrodes 54 have a width slightly larger than the narrow width portion 53a described later, and are provided at two ends in the width direction of the chip 52 at intervals in the length direction.
[0074]
The first internal electrode 53 is disposed such that two adjacent internal electrodes 53 face each other in the height direction via the dielectric portion. The edge of the narrow portion 53a formed at one end in the width direction is a chip. 52 are alternately exposed at two end faces in the width direction. The second internal electrode 53 is also arranged such that two adjacent internal electrodes 53 face each other in the height direction via the dielectric portion. The edge of the narrow portion 53a formed at one end in the width direction is a chip. 52 are alternately exposed at two end faces in the width direction. The edges of the first and second internal electrodes 53 exposed from one end face in the width direction of the chip 52 are electrically connected to the two external electrodes 54 respectively, and the first and second edges exposed from the other end face. The edge of the internal electrode 53 is electrically connected to the other two external electrodes 54, respectively.
[0075]
Since the first capacitor portion C51 is connected to the pair of external electrodes 54 and the second capacitor portion C51 is also connected to the pair of external electrodes 54, the first capacitor portion C51 is connected to the two external electrodes 54 at one end in the width direction. The capacitance obtained between the two external electrodes 54 at the other end in the width direction is the sum of the capacitance of the first capacitor C51 and the capacitance of the second capacitor C52.
[0076]
Since the first capacitor portion C51 and the second capacitor portion C52 in the chip 52 are separated from each other at a predetermined interval in the length direction, there is a gap between the first capacitor portion C51 and the second capacitor portion C52 of the chip 52. There is a portion 52a composed of only a dielectric material. Further, since the first and second capacitor portions C51 and C52 in the chip 52 are separated from the both end surfaces in the longitudinal direction and both end surfaces in the height direction of the chip 52 by a predetermined interval, both ends in the longitudinal direction of the chip 52. There is a portion 52b made of only a dielectric material so as to surround the first and second capacitor portions C51, C52 at both ends of the portion and the height direction. Further, since each of the internal electrodes 53 constituting the first and second capacitor portions C51 and C52 is connected to the external electrode 54 via the narrow portion 53a, most of the both ends of the chip 52 in the width direction are dielectric. There is a portion 52c made of body material.
[0077]
In the multilayer capacitor 51, since a dielectric portion exists between the internal electrodes 53 constituting the first and second capacitor portions C51 and C52, charging and discharging are performed with a DC voltage applied to the two pairs of external electrodes 54. Is repeated, or when a DC voltage or DC current containing a ripple component is applied, the dielectric portion sandwiched between the internal electrodes 53 of the first capacitor portion C51 and the internal electrode 53 of the second capacitor portion C52 sandwich the same. Each of the dielectric portions expands and contracts due to the piezoelectric effect.
[0078]
However, in the multilayer capacitor 51, there is a portion 52a made of only a dielectric material between the first and second capacitor portions C51 and C52, and both ends in the length direction and both ends in the height direction of the chip 52 are provided. There is a portion 52b made of only a dielectric material surrounding the first and second capacitor portions C51 and C52, and portions 52c mostly made of a dielectric material are present at both ends in the width direction of the chip 52. In addition, since the two pairs of external electrodes 54 have a structure that partially covers both ends in the width direction of the chip 52, the effect of suppressing the expansion and contraction in the length direction is reduced by the dielectric material portions 52a and 52b and 52c and the external electrode 54, and the effect of suppressing expansion and contraction in the width direction can be obtained by the dielectric material portions 52a, 52b and 52c. Is an inhibitory effect on the direction of expansion and contraction of the dielectric material portion 52a, it can be obtained by 52b and 52c and the external electrodes 54, thereby can be significantly reduced stretch occurring in the multilayer capacitor 51 by the piezoelectric effect.
[0079]
Therefore, even when the two pairs of external electrodes 54 of the multilayer capacitor 51 are joined to the lands RD of the substrate SB via the joining material CM such as solder, the force transmitted to the substrate SB as the multilayer capacitor 51 expands and contracts is small. As a result, the vertical vibration of the substrate SB is also reduced, and the generation of audible sound due to this vibration is extremely small or almost inaudible.
[0080]
Further, since two pairs of external electrodes 54 are provided at both ends in the width direction of the chip 52 whose degree of expansion and contraction is smaller than that in the length direction, expansion and contraction of the multilayer capacitor 51 occurs when the multilayer capacitor 51 is mounted on the substrate SB. In this case, it is possible to prevent the force accompanying the expansion and contraction in the length direction from being transmitted to the substrate SB as much as possible.
[0081]
In order to make it difficult for the force caused by the expansion and contraction of the multilayer capacitor 51 to be transmitted to the substrate SB, the bonding area between the external electrode 54 and the land RD is reduced by minimizing the land RD as shown in FIG. Alternatively, as shown in FIG. 15B, the bonding area between the external electrode 54 and the land RD is reduced by partially bonding the external electrode 54 and the land RD with the bonding material CM in the length direction. It is good to do. Further, if a material having low hardness, for example, a conductive resin or the like is used as the bonding material CM, the propagation of the force is alleviated by the bonding material CM, so that the force accompanying expansion and contraction of the multilayer capacitor 51 is hardly transmitted to the substrate SB. it can.
[0082]
In the above-described embodiment, the cuboid-shaped chip 52 having the dimension relation of length>width> height is shown. However, the chip 52 has the dimension of length> width = height or length>height> width. They may have a relationship.
[0083]
In the above-described embodiment, the two capacitor portions C51 and C52 are provided in the chip 52 at intervals in the length direction. However, three or more capacitor portions are provided at intervals in the length direction. According to this, three or more pairs of external electrodes 54 may be provided.
[0084]
Further, in the above-described embodiment, two pairs of external electrodes 54 are provided at both ends in the width direction of the chip 52. However, as shown in FIG. The electrode 55 may be provided. The dummy electrode 55 is coated with an electrode paste containing metal powder on each end surface in the length direction of the chip 52 so as to cover four peripheral surfaces thereof, or is baked, or the unfired internal electrode layer is formed after the electrode paste is applied. It is created by firing at the same time. According to the multilayer capacitor 51 shown in FIG. 16, in addition to the above, an effect of suppressing expansion and contraction in the width direction and the height direction can be obtained by the dummy electrode 55.
[0085]
[Sixth embodiment]
FIGS. 17 (A) to 17 (C) show a sixth embodiment of the multilayer capacitor according to the present invention. FIG. 17 (A) is a top view of the multilayer capacitor, and FIG. 17 (B) is FIG. 17) is a sectional view taken along line f1-f1, and FIG. 17C is a sectional view taken along line f2-f2 in FIG. In the following description, the horizontal direction in FIG. 17A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 17B is referred to as a height direction.
[0086]
The multilayer capacitor 61 is provided with a rectangular parallelepiped chip 62 having a dimension relationship of length> width = height, a predetermined number of internal electrodes 63 embedded in the chip 62, and both ends in the width direction of the chip 62. And a pair of external electrodes 64. A predetermined number of internal electrodes 63 stacked via the dielectric portion constitute a capacitor portion C61 capable of ensuring a predetermined capacitance.
[0087]
The chip 62 is formed by alternately laminating and compressing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing a metal powder, and firing the resultant. The unfired internal electrode layer becomes the internal electrode 63 by firing. The external electrode 64 may be formed by applying an electrode paste containing a metal powder to each end surface in the width direction of the chip 62 so as to cover four surrounding surfaces, or by baking the electrode paste after applying the electrode paste. It is created by firing at the same time.
[0088]
The internal electrodes 63 are arranged such that two adjacent internal electrodes 63 face each other in the height direction via the dielectric portion, and each edge is alternately exposed to two end surfaces in the width direction of the chip 62. I have. The edge of the internal electrode 63 exposed from one end face in the width direction of the chip 62 is electrically connected to one external electrode 64, and the edge of the internal electrode 63 exposed from the other end face is connected to the other external electrode 64. It is electrically connected.
[0089]
Since the capacitor portion C61 in the chip 62 is separated from the both end surfaces of the chip 62 in the longitudinal direction and both end surfaces in the height direction by a predetermined distance, both ends in the longitudinal direction and both end portions in the height direction of the chip 62 are provided. There is a portion 62a made of only a dielectric material so as to surround the capacitor portion C61.
[0090]
Since the multilayer capacitor 61 has a dielectric portion between the internal electrodes 63 constituting the capacitor portion C61, when charging and discharging are repeated with a DC voltage applied to the pair of external electrodes 64, or When a DC voltage or a DC current containing a ripple component is applied, the dielectric portion sandwiched between the internal electrodes 63 expands and contracts due to a piezoelectric effect.
[0091]
However, in the multilayer capacitor 61, there are portions 62a made of only a dielectric material so as to surround the capacitor portion C61 at both ends in the length direction and both ends in the height direction of the chip 63. Since the electrode 64 has a structure that covers both ends in the width direction of the chip 62, the effect of suppressing the expansion and contraction in the length direction can be obtained by the dielectric material portion 62 a and the external electrode 64. The effect of suppressing the expansion and contraction of the piezoelectric material can be obtained by the dielectric material portion 62a, and the effect of suppressing the expansion and contraction in the height direction can be obtained by the dielectric material portion 62a and the external electrode 64. Due to the effect, expansion and contraction occurring in the multilayer capacitor 61 can be reduced as much as possible.
[0092]
Therefore, even when the pair of external electrodes 64 of the multilayer capacitor 61 are bonded to the land RD of the substrate SB via the bonding material CM such as solder, the force transmitted to the substrate SB as the multilayer capacitor 61 expands and contracts is small. As a result, the vertical vibration of the substrate SB is also reduced, and the generation of audible sound due to this vibration is extremely small or almost inaudible.
[0093]
Further, since a pair of external electrodes 64 is provided at both ends in the width direction of the chip 62 whose degree of expansion and contraction is smaller than the length direction, expansion and contraction of the multilayer capacitor 61 occurs when the multilayer capacitor 61 is mounted on the substrate SB. In this case, it is possible to prevent the force accompanying the expansion and contraction in the length direction from being transmitted to the substrate SB as much as possible.
[0094]
In order to make it difficult for the force caused by the expansion and contraction of the multilayer capacitor 61 to be transmitted to the substrate SB, the bonding area between the external electrode 64 and the land RD is reduced by minimizing the land RD as shown in FIG. Alternatively, as shown in FIG. 18B, the bonding area between the external electrode 64 and the land RD is reduced by partially bonding the external electrode 64 and the land RD with the bonding material CM in the length direction. It is good to do. Further, if a material having low hardness, for example, a conductive resin or the like is used as the bonding material CM, the propagation of force can be reduced by the bonding material CM so that the force accompanying expansion and contraction of the multilayer capacitor 61 is hardly transmitted to the substrate SB. it can.
[0095]
In the above-described embodiment, the rectangular parallelepiped chip 62 having the dimension relationship of length>width> height is shown. However, the chip 62 has the dimension of length> width = height or length>height> width. They may have a relationship.
[0096]
In the above embodiment, a pair of external electrodes 64 is provided at both ends in the width direction of the chip 62. However, as shown in FIG. A pair or more dummy electrodes 65 may be provided. The dummy electrode 65 is coated with an electrode paste containing a metal powder on each end surface in the length direction of the chip 62 in a band shape so as to cover two surrounding surfaces (both end surfaces in the height direction), or is baked. It is prepared by firing simultaneously with the unfired internal electrode layer after application of the electrode paste. According to the multilayer capacitor 61 shown in FIG. 19, in addition to the above, an effect of suppressing expansion and contraction in the width direction and the height direction can be obtained by the dummy electrode 65.
[0097]
Further, in the multilayer capacitor 61 shown in FIG. 19, external electrodes 64 are provided so as to cover both ends in the width direction of the chip 62, and dummy electrodes 65 are provided to partially cover both ends in the length direction of the chip 62. However, as shown in FIG. 20, the external electrode 64 ′ may be formed to partially cover both ends in the width direction of the chip 62, and the dummy electrode 65 ′ may be formed to cover both ends in the length direction of the chip 62. Similar functions and effects can be obtained.
[0098]
[Seventh embodiment]
FIGS. 21A to 21C show a seventh embodiment of the multilayer capacitor according to the present invention. FIG. 21A is a top view of the multilayer capacitor, and FIG. FIG. 21A is a sectional view taken along line g1-g1, and FIG. 21C is a sectional view taken along line g2-g2 in FIG. In the following description, the horizontal direction in FIG. 21A is described as a length direction, the vertical direction is described as a width direction, and the vertical direction in FIG. 21B is described as a height direction.
[0099]
The multilayer capacitor 71 is provided with a rectangular parallelepiped chip 72 having a dimension relationship of length> width = height, a predetermined number of internal electrodes 73 embedded in the chip 72, and provided at both ends in the length direction of the chip 72. And a pair of dummy electrodes 75 provided on both ends of the chip 72 in the width direction. A predetermined number of internal electrodes 73 stacked via the dielectric portion constitute a capacitor portion (without reference numeral) capable of securing a predetermined capacitance.
[0100]
The chip 72 is formed by alternately laminating and compressing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing metal powder, and then firing the chip. The unfired internal electrode layer becomes the internal electrode 73 by firing. Further, the external electrode 74 is formed by applying and baking an electrode paste containing metal powder to each end surface in the length direction of the chip 72 so as to cover four surrounding surfaces. Further, the dummy electrode 75 is formed by applying and baking an electrode paste containing metal powder on each end surface in the width direction of the chip 72 so as to cover two surrounding surfaces (both end surfaces in the height direction). I have.
[0101]
The internal electrodes 73 are arranged such that two adjacent internal electrodes 73 face each other in the height direction via the dielectric portion, and each edge is alternately exposed to two end surfaces in the longitudinal direction of the chip 72. ing. The edge of the internal electrode 73 exposed from one end face in the longitudinal direction of the chip 72 is electrically connected to one external electrode 74, and the edge of the internal electrode 73 exposed from the other end face is connected to the other external electrode 74. Is electrically connected to
[0102]
Since the capacitor portions in the chip 72 are separated from the both end surfaces in the width direction and the both end surfaces in the height direction of the chip 72 by a predetermined distance, capacitor portions are provided at both end portions in the width direction and both end portions in the height direction of the chip 72. There is a portion 72a made of only a dielectric material so as to surround it.
[0103]
Since the multilayer capacitor 71 has a dielectric portion between the internal electrodes 73 constituting the capacitor portion, if charging and discharging are repeated while a DC voltage is applied to the pair of external electrodes 74, or a ripple occurs. When a DC voltage or DC current containing components is applied, the dielectric portion sandwiched between the internal electrodes 73 expands and contracts due to the piezoelectric effect.
[0104]
However, in the above-described multilayer capacitor 71, there are portions 72 a made of only a dielectric material so as to surround the capacitor portion at both ends in the width direction and both ends in the height direction of the chip 72. Has a structure that covers both ends in the longitudinal direction of the chip 72 and has a structure in which the pair of dummy electrodes 75 partially covers both ends in the width direction of the chip 72. Can be obtained by the above-mentioned dielectric material portion 72a and the dummy electrode 75, and the effect of suppressing expansion and contraction in the width direction can be obtained by the above-mentioned dielectric material portion 72a and the external electrode 74. Can be obtained by the dielectric material portion 72a, the external electrode 74, and the dummy electrode 75, whereby the multilayer capacitor is formed by the piezoelectric effect. Stretch occurring in sub 71 can be significantly reduced.
[0105]
Therefore, even when the pair of external electrodes 74 of the multilayer capacitor 71 are joined to the land RD of the substrate SB via the joining material CM such as solder, the force transmitted to the substrate SB as the multilayer capacitor 71 expands and contracts is small. As a result, the vertical vibration of the substrate SB is also reduced, and the generation of audible sound due to this vibration is extremely small or almost inaudible.
[0106]
In order to make it difficult for the force caused by the expansion and contraction of the multilayer capacitor 71 to be transmitted to the substrate SB, the bonding area between the external electrode 74 and the land RD is reduced by minimizing the land RD as shown in FIG. Alternatively, as shown in FIG. 22A, the bonding area between the external electrode 74 and the land RD is reduced by partially bonding the external electrode 74 and the land RD by the bonding material CM in the width direction. It is good to Further, if a material having low hardness, for example, a conductive resin or the like is used as the bonding material CM, the transmission of the force can be reduced by the bonding material CM so that the force accompanying expansion and contraction of the multilayer capacitor 71 is hardly transmitted to the substrate SB. it can.
[0107]
In the above-described embodiment, a rectangular parallelepiped chip 72 having a length>width> height dimension relationship has been described. However, the chip 72 has a length> width = height or length>height> width dimension. They may have a relationship.
[0108]
In the above-described embodiment, a pair of dummy electrodes 75 is provided at both ends in the width direction of the chip 72. However, as shown in FIG. 23, two pairs or three pairs are provided at both ends in the width direction of the chip 72. Even when the dummy electrode 75 'described above is provided, the same operation and effect can be obtained.
[0109]
[Eighth Embodiment]
FIGS. 24A to 24C show an eighth embodiment of the multilayer capacitor according to the present invention. FIG. 24A is a top view of the multilayer capacitor, and FIG. 24A is a cross-sectional view taken along the line h1-h1, and FIG. 24C is a cross-sectional view taken along the line h2-h2 in FIG. In the following description, the horizontal direction in FIG. 24A is referred to as a length direction, the vertical direction is referred to as a width direction, and the vertical direction in FIG. 24B is referred to as a height direction.
[0110]
The multilayer capacitor 81 is provided with a rectangular parallelepiped chip 82 having a dimensional relationship of length> width = height, a predetermined number of internal electrodes 83 embedded in the chip 82, and both ends of the chip 82 in the length direction. And a pair of external electrodes 84 provided. A predetermined number of the internal electrodes 83 stacked via the dielectric portion constitute a capacitor portion (no symbol) capable of securing a predetermined capacitance.
[0111]
The chip 82 is formed by alternately laminating and compressing an unfired dielectric layer made of a ceramic slurry containing dielectric ceramic powder and an unfired internal electrode layer made of an electrode paste containing a metal powder, and then firing. The unfired internal electrode layer becomes the internal electrode 83 by firing. Further, the external electrode 84 is formed by applying and baking an electrode paste containing metal powder on each end surface in the length direction of the chip 82 so as to cover four surrounding surfaces.
[0112]
Here, the length of each external electrode 84 is set to be at least １ ／ of the length of the multilayer capacitor 81 and within a range in which both are not short-circuited. Incidentally, the lengths of the external electrodes 84 in the drawing are equal to each other, and each length is about ／ of the length of the multilayer capacitor 81.
[0113]
The internal electrodes 83 are arranged such that two adjacent internal electrodes 83 face each other in the height direction via the dielectric portion, and each edge is alternately exposed on two end surfaces in the longitudinal direction of the chip 82. ing. The edge of the internal electrode 83 exposed from one end face in the length direction of the chip 82 is electrically connected to one external electrode 84, and the edge of the internal electrode 83 exposed from the other end face is connected to the other external electrode 84. Is electrically connected to
[0114]
Since the capacitor portion in the chip 82 is separated from the both ends in the width direction and both ends in the height direction of the chip 82 by a predetermined distance, capacitor portions are provided at both ends in the width direction and both ends in the height direction of the chip 82. There is a portion 82a made of only a dielectric material so as to surround it.
[0115]
In the multilayer capacitor 81, since a dielectric portion exists between the internal electrodes 83 constituting the capacitor portion, when charging and discharging are repeated with a DC voltage applied to the pair of external electrodes 84, ripples occur. When a DC voltage or DC current containing components is applied, the dielectric portion sandwiched between the internal electrodes 83 expands and contracts due to the piezoelectric effect.
[0116]
However, in the above-mentioned multilayer capacitor 81, there are portions 82a made of only a dielectric material so as to surround the capacitor portion at both ends in the width direction and both ends in the height direction of the chip 82. Has a structure that covers both ends of the chip 82 in the length direction, and the length dimension of each external electrode 84 is set to be at least の of the length dimension of the multilayer capacitor 81 and not to short-circuit the two. The effect of suppressing expansion and contraction in the length direction can be obtained by the dielectric material portion 82a and the external electrode 84, and the effect of suppressing expansion and contraction in the width direction can be obtained by the dielectric material portion 82a and the external electrode 84. Further, the effect of suppressing the expansion and contraction in the height direction can be obtained by the above-described dielectric material portion 82a and the external electrode 84. Stretch occurring in the capacitor 81 can be significantly reduced.
[0117]
Therefore, even when the pair of external electrodes 84 of the multilayer capacitor 81 are bonded to the land RD of the substrate SB via the bonding material CM such as solder, the force transmitted to the substrate SB as the multilayer capacitor 81 expands and contracts is small. As a result, the vertical vibration of the substrate SB is also reduced, and the generation of audible sound due to this vibration is extremely small or almost inaudible.
[0118]
In order to make it difficult for the force caused by the expansion and contraction of the multilayer capacitor 81 to be transmitted to the substrate SB, the bonding area between the external electrode 84 and the land RD is reduced by minimizing the land RD as shown in FIG. Alternatively, as shown in FIG. 25A, the bonding area between the external electrode 84 and the land RD is reduced by partially bonding the external electrode 84 and the land RD with the bonding material CM in the width direction. It is good to Also, as shown in FIG. 25 (B), when the joint between the external electrode 84 and the land RD is set at the innermost position of each external electrode 84 and the fixed end distance is made as small as possible, the length of the multilayer capacitor 81 in the length direction can be expanded and contracted. , The vertical vibration hardly occurs on the substrate SB. Furthermore, if a material having low hardness, for example, a conductive resin or the like is used as the bonding material CM, the propagation of force can be reduced by the bonding material CM, and the force accompanying expansion and contraction of the multilayer capacitor 81 can be hardly transmitted to the substrate SB. it can.
[0119]
In the above-described embodiment, the chip 82 having the dimension relationship of length>width> height is shown as the rectangular parallelepiped chip 82, but the chip 82 has the dimension of length> width = height or length>height> width. They may have a relationship.
[0120]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to provide a multilayer capacitor capable of reducing expansion and contraction due to a piezoelectric effect as much as possible, and a multilayer capacitor mounting body capable of minimizing generation of audible sound caused by expansion and contraction of the multilayer capacitor. it can.
[Brief description of the drawings]
FIG. 1 shows an example of a conventional multilayer capacitor.
FIG. 2 is a view showing a state in which the multilayer capacitor shown in FIG. 1 is mounted on a substrate;
FIG. 3 is a view showing a first embodiment of the multilayer capacitor according to the present invention;
FIG. 4 is a diagram showing a state in which the multilayer capacitor shown in FIG. 3 is mounted on a substrate;
FIG. 5 is a diagram showing a modification of the multilayer capacitor shown in FIG. 3;
FIG. 6 is a view showing a second embodiment of the multilayer capacitor according to the present invention;
FIG. 7 is a view showing a state in which the multilayer capacitor shown in FIG. 6 is mounted on a substrate;
FIG. 8 is a view showing a modification of the multilayer capacitor shown in FIG. 6;
FIG. 9 is a diagram showing a third embodiment of the multilayer capacitor according to the present invention.
FIG. 10 is a diagram showing a state in which the multilayer capacitor shown in FIG. 9 is mounted on a substrate.
FIG. 11 is a view showing a modification of the multilayer capacitor shown in FIG. 9;
FIG. 12 is a view showing a multilayer capacitor according to a fourth embodiment of the present invention;
FIG. 13 is a view showing a state where the multilayer capacitor shown in FIG. 12 is mounted on a substrate.
FIG. 14 is a diagram showing a fifth embodiment of the multilayer capacitor according to the present invention;
FIG. 15 is a diagram showing a state in which the multilayer capacitor shown in FIG. 14 is mounted on a substrate.
FIG. 16 is a view showing a modification of the multilayer capacitor shown in FIG. 14;
FIG. 17 is a view showing a sixth embodiment of the multilayer capacitor according to the present invention;
18 is a view showing a state in which the multilayer capacitor shown in FIG. 17 is mounted on a substrate.
FIG. 19 is a view showing a modification of the multilayer capacitor shown in FIG. 17;
FIG. 20 is a view showing a modification of the multilayer capacitor shown in FIG. 17;
FIG. 21 is a view showing a seventh embodiment of the multilayer capacitor according to the present invention;
FIG. 22 is a view showing a state in which the multilayer capacitor shown in FIG. 21 is mounted on a substrate.
FIG. 23 is a view showing a modification of the multilayer capacitor shown in FIG. 21;
FIG. 24 is a diagram showing an eighth embodiment of the multilayer capacitor according to the present invention.
FIG. 25 is a diagram showing a state in which the multilayer capacitor shown in FIG. 24 is mounted on a substrate.
[Explanation of symbols]
SB: substrate, RD: land, CM: bonding material, 11: multilayer capacitor, 12: chip, 12a, 12b, 12c: dielectric material portion, 13: internal electrode, 13a: narrow portion, 14: external electrode, 15 ... Dummy electrode, 21 ... Multilayer capacitor, 22 ... Chip, 22a, 22b ... Dielectric material part, 23 ... Internal electrode, 24 ... External electrode, 25 ... Dummy electrode, 31 ... Multilayer capacitor, 32 ... Chip, 32a, 32b ... Dielectric material portion, 33 internal electrode, 33a narrow portion, 34 external electrode, 35 dummy electrode, 41 multilayer capacitor, 42 chip, 42a, 42b dielectric material portion, 43a first internal electrode 43a1 narrow width portion, 43b second internal electrode, 44 first external electrode, 45 second external electrode, 51 multilayer capacitor, 52 chip, 52a, 52b, 52c. Body material part, 53 ... Internal electrode, 53a ... Narrow width part, 54 ... External electrode, 55 ... Dummy electrode, 61 ... Multilayer capacitor, 62 ... Chip, 62a ... Dielectric material part, 63 ... Internal electrode, 64, 64 ' ... external electrodes, 65, 65 'dummy electrodes, 71 multilayer capacitors, 72 chips, 72a dielectric material portion, 73 internal electrodes, 74 external electrodes, 75, 75' dummy electrodes, 81 multilayer capacitors 82, a chip, 82a, a dielectric material portion, 83, an internal electrode, 84, an external electrode.

Claims (23)

Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
Two or more capacitor portions are provided in the chip at intervals in the length direction, and the internal electrodes constituting each capacitor portion have their edges exposed alternately on two end surfaces in the width direction of the chip,
Further, a pair of external electrodes is formed at both ends in the width direction of the chip so as to extend over each end surface in the width direction of the chip and four surrounding surfaces thereof, and internal electrodes exposed from one end surface of each capacitor portion. Edge is electrically connected to one external electrode, the edge of the internal electrode exposed from the other end surface is electrically connected to the other external electrode,
At both ends of the chip in the length direction and at both ends in the height direction, there is a part made of only dielectric material surrounding each capacitor part, and a part made of only dielectric material exists between each capacitor part Do
A multilayer capacitor characterized by the above-mentioned. The internal electrode constituting each capacitor portion has a narrow portion at one end in the width direction, and the edges of the narrow portion are alternately exposed at two end surfaces in the width direction of the chip. There is a part that is mostly composed of a dielectric material in the part,
The multilayer capacitor according to claim 1, wherein: At least one pair of dummy electrodes is provided at both ends in the longitudinal direction of the chip so as to cover each end surface in the longitudinal direction of the chip and two peripheral surfaces thereof.
The multilayer capacitor according to claim 1, wherein: The multilayer capacitor according to any one of claims 1 to 3, wherein a pair of external electrodes is bonded to a land of a substrate via a bonding material.
A multilayer capacitor mounted body characterized in that: Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
Two or more capacitor portions are provided in the chip at intervals in the width direction, and the internal electrodes constituting each capacitor portion have their edges exposed alternately on two end surfaces in the length direction of the chip.
Further, a pair of external electrodes is formed at both ends in the length direction of the chip so as to extend to each end surface in the length direction of the chip and four surrounding surfaces thereof, and is exposed from one end surface of each capacitor portion. The edge of the internal electrode is electrically connected to one external electrode, the edge of the internal electrode exposed from the other end surface is electrically connected to the other external electrode,
At both ends in the width direction and both ends in the height direction of the chip, there is a portion made of only the dielectric material so as to surround each capacitor portion, and there is a portion made of only the dielectric material between each capacitor portion. ,
A multilayer capacitor characterized by the above-mentioned. At least one pair of dummy electrodes is provided at both ends in the width direction of the chip so as to cover each end surface in the width direction of the chip and two surrounding surfaces thereof.
The multilayer capacitor according to claim 5, wherein: The multilayer capacitor according to claim 5 or 6, wherein a pair of external electrodes is bonded to a land of the substrate via a bonding material.
A multilayer capacitor mounted body characterized in that: Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
One capacitor portion is provided in the chip, and the internal electrode constituting the capacitor portion has two or more narrow portions at one end in the width direction, and the edge of the narrow portion is divided into two in the width direction of the chip. It is exposed alternately on the end face,
Further, at both ends in the width direction of the chip, two or more pairs of external electrodes corresponding to the number of the narrow portions are formed so as to cover each end face in the width direction of the chip and the two surrounding surfaces thereof. Two or more edges of the internal electrode exposed from one end face are electrically connected to one corresponding external electrode, respectively, and two or more edges of the internal electrode exposed from the other end face correspond to each. Each is electrically connected to the other external electrode,
There is a portion composed of only dielectric material surrounding both ends of the chip in the length direction and both ends in the height direction so as to surround the capacitor portion, and a portion composed mostly of dielectric material at both ends in the width direction of the chip. Exists,
A multilayer capacitor characterized by the above-mentioned. A pair of dummy electrodes is formed at both ends in the longitudinal direction of the chip so as to extend over each end surface in the longitudinal direction of the chip and four peripheral surfaces thereof.
The multilayer capacitor according to claim 8, wherein: 10. The multilayer capacitor according to claim 8, wherein two or more pairs of external electrodes are bonded to a land of the substrate via a bonding material.
A multilayer capacitor mounted body characterized in that: Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
In the chip, two or more first internal electrodes provided at intervals in the length direction and second internal electrodes provided over the length direction are alternately arranged so as to face each other via a dielectric portion. The first internal electrode has narrow portions at both ends in the width direction, and the edges of the narrow portion are exposed at two end faces in the width direction of the chip, and the second internal electrode has ends in the length direction. The edges are exposed at the two end faces in the longitudinal direction of the chip,
Further, at least two pairs of first external electrodes corresponding to the number of narrow portions are formed at both ends in the width direction of the chip so as to cover each end surface in the width direction of the chip and two surrounding surfaces thereof, and A pair of second external electrodes is formed at both ends in the length direction of the chip so as to extend over each end surface in the length direction of the chip and four surrounding surfaces thereof, and one exposed edge of the first internal electrode is The other exposed edge is electrically connected to one corresponding first external electrode, and the other exposed edge is electrically connected to the corresponding other first external electrode. One exposed edge is electrically connected to one second external electrode, and the other exposed edge is electrically connected to the other second external electrode.
At both ends in the height direction of the chip, there is a portion made of only a dielectric material, and at both ends in the width direction of the chip, there are portions mostly made of a dielectric material.
A multilayer capacitor characterized by the above-mentioned. The multilayer capacitor according to claim 11, wherein the first external electrode and the second external electrode are bonded to a land of a substrate via a bonding material.
A multilayer capacitor mounted body characterized in that: Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
Two or more capacitor portions are provided in the chip at intervals in the length direction, and the internal electrodes constituting each capacitor portion have a narrow portion at one end in the width direction, and the edge of the narrow portion is formed. It is exposed alternately on the two end faces in the width direction of the chip,
Further, two or more pairs of external electrodes corresponding to the number of narrow portions are formed at both ends in the width direction of the chip so as to cover each end surface in the width direction of the chip and two surrounding surfaces thereof. The edge of the internal electrode exposed from one end surface of the internal electrode is electrically connected to one corresponding external electrode, and the edge of the internal electrode exposed from the other end surface is connected to the corresponding external electrode. Each is electrically connected,
At both ends of the chip in the length direction and at both ends in the height direction, there is a part made of only dielectric material surrounding each capacitor part, and a part made of only dielectric material exists between each capacitor part At the same time, there are portions made of a dielectric material at both ends in the width direction of the chip,
A multilayer capacitor characterized by the above-mentioned. A pair of dummy electrodes is formed at both ends in the longitudinal direction of the chip so as to extend over each end surface in the longitudinal direction of the chip and four peripheral surfaces thereof.
14. The multilayer capacitor according to claim 13, wherein: The multilayer capacitor according to claim 13 or 14, wherein at least two pairs of external electrodes are bonded to a land of the substrate via a bonding material.
A multilayer capacitor mounted body characterized in that: Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
One capacitor portion is provided in the chip, and the inner electrodes constituting the capacitor portion have their edges alternately exposed on two end surfaces in the width direction of the chip,
Further, a pair of external electrodes is formed at both ends in the width direction of the chip so as to extend to each end surface in the width direction of the chip and four surrounding surfaces thereof, and a pair of internal electrodes exposed from one end surface of the capacitor portion. The edge is electrically connected to one external electrode, the edge of the internal electrode exposed from the other end is electrically connected to the other external electrode,
At both ends in the length direction and both ends in the height direction of the chip, there is a portion composed of only a dielectric material so as to surround the capacitor portion,
A multilayer capacitor characterized by the above-mentioned. At least one pair of dummy electrodes is formed at both ends in the longitudinal direction of the chip so as to cover each end surface in the longitudinal direction of the chip and two peripheral surfaces thereof.
The multilayer capacitor according to claim 16, wherein: A pair of external electrodes are formed at both ends in the width direction of the chip so as to extend over each end surface in the width direction of the chip and two surrounding surfaces thereof. A pair of dummy electrodes is formed so as to cover the end face and four surrounding faces;
The multilayer capacitor according to claim 16, wherein: A pair of external electrodes of the multilayer capacitor according to any one of claims 16 to 18, which is bonded to a land of a substrate via a bonding material.
A multilayer capacitor mounted body characterized in that: Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
One capacitor portion is provided in the chip, and the internal electrodes constituting the capacitor portion have their edges exposed alternately on two end surfaces in the length direction of the chip.
Further, a pair of external electrodes is formed at both ends in the length direction of the chip so as to extend to each end face in the length direction of the chip and four surrounding surfaces thereof, and an inner electrode exposed from one end face of the capacitor portion. The edge of the electrode is electrically connected to one external electrode, the edge of the internal electrode exposed from the other end surface is electrically connected to the other external electrode,
At both ends in the width direction and both ends in the height direction of the chip, there is a portion made of only a dielectric material so as to surround the capacitor portion,
At least one pair of dummy electrodes is provided at both ends in the width direction of the chip so as to cover each end surface in the width direction of the chip and two peripheral surfaces thereof.
A multilayer capacitor characterized by the above-mentioned. 21. A pair of external electrodes of the multilayer capacitor according to claim 20 joined to a land of a substrate via a joining material.
A multilayer capacitor mounted body characterized in that: Within a rectangular parallelepiped dielectric chip having the largest length among length, width and height, a predetermined number of internal electrodes are arranged such that two adjacent internal electrodes face each other in the height direction via the dielectric portion. A multilayer capacitor having a capacitor portion composed of electrodes,
One capacitor portion is provided in the chip, and the internal electrodes constituting the capacitor portion have their edges exposed alternately on two end surfaces in the length direction of the chip.
Further, a pair of external electrodes is formed at both ends in the length direction of the chip so as to extend to each end face in the length direction of the chip and four surrounding surfaces thereof, and an inner electrode exposed from one end face of the capacitor portion. The edge of the electrode is electrically connected to one external electrode, the edge of the internal electrode exposed from the other end surface is electrically connected to the other external electrode,
At both ends in the width direction and both ends in the height direction of the chip, there is a portion made of only a dielectric material so as to surround the capacitor portion,
The length dimension of each external electrode is set to be at least 1/4 of the length dimension of the multilayer capacitor and in a range in which both are not short-circuited,
A multilayer capacitor characterized by the above-mentioned. A pair of external electrodes of the multilayer capacitor according to claim 22, which is bonded to a land of a substrate via a bonding material.
A multilayer capacitor mounted body characterized in that:

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