JP2004186463A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has an excellent reliability and a high integration and can be manufactured at a high manufacturing efficiency, and also to provide a method for manufacturing the semiconductor device. <P>SOLUTION: A vertical MOS transistor has a structure wherein a gate insulating film 32 and a gate part of a gate electrode 41 are buried in part of a structure of a bipolar transistor, and a base layer 13 between a drain layer 2 and a source layer 24 forms a channel. A method for manufacturing the transistor is also provided. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a vertical MOS transistor and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, semiconductor devices have been required to be miniaturized, increased in speed, reduced in power consumption, and the like. For example, a BiCMOS transistor in which a bipolar transistor and a MOS transistor are formed on the same substrate has attracted attention because it can simultaneously realize the advantages of the high speed of the bipolar transistor and the low power consumption of the MOS transistor.
However, with further demands for miniaturization and the like, the manufacturing process of the semiconductor device has become more complicated, and the equipment cost has increased, the yield of the semiconductor device has decreased, and the reliability has decreased. For example, in BiCMOS transistors, pair characteristics such as ΔVth (difference in threshold Vth characteristics between adjacent transistors) may deteriorate with miniaturization. In order to cope with such a problem, attention has been paid to a vertical MOS transistor (for example, see Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-23001
[Problems to be solved by the invention]
Hereinafter, a conventional method for manufacturing a vertical MOS transistor will be described with reference to FIGS. As shown in FIG. 11, an n-type epitaxial layer 102 having a specific resistance of about 0.6 to 2 Ω · cm and a thickness of about 10 μm is formed on the entire surface of a main surface of an n-type semiconductor substrate 101. Next, B (boron) is ion-implanted over the entire surface of the n-type epitaxial layer 102 at an ion energy of 100 keV and a dose of 7 × 10 ¹³ cm ⁻² to form a base layer 103 having a thickness of 2 μm. Next, As (arsenic) is ion-implanted into the entire surface of the base layer 103 at an ion energy of 40 keV and a dose of 2 × 10 ¹⁵ cm ⁻² to obtain a 0.4 μm thick source layer 104.
[0005]
Next, as shown in FIG. 12, an opening for burying the gate electrode is etched by RIE (Reactive Ion Etching) to a depth reaching the n-type epitaxial layer 102. Next, a gate insulating film 111 is formed over the surface of the opening formed by etching. Next, a conductive material is deposited in the opening where the gate insulating film 111 is formed, and then heat treatment is performed to bury the conductive material in the opening to form the gate electrode 112.
[0006]
Next, as shown in FIG. 13, an insulating film 121 is formed on the entire surface. Next, a contact hole 122 is formed in the insulating film 121 to form a wiring 131 connecting the back gate, the source, and the gate electrode. Next, as shown in FIG. 14, a wiring 131bs connecting the back gate and the source and a wiring 131g connecting the gate electrode are formed. As described above, a conventional n-type vertical MOS transistor whose effective gate length is the thickness of the base layer 103 can be formed.
[0007]
Since the above-mentioned pair characteristics are affected by the gate length of the gate electrode, the pair characteristics are good when the variation in the gate length is small. The gate length of a general lateral MOS transistor is equal to the length of the gate electrode. On the other hand, since the gate electrode of the vertical MOS transistor is formed so as to be buried, the effective gate length corresponding to the gate length of the horizontal MOS transistor is the thickness of the base layer 103. The base layer 103 can be formed as desired by controlling the ion implantation conditions, and the thickness of the layer is less varied. As described above, the effective gate length of the vertical MOS transistor can be formed with a small variation because the variation in the gate length does not occur due to the lithography process of a general horizontal MOS transistor, so that good pair characteristics can be obtained. it can.
[0008]
However, in the conventional method of manufacturing a vertical MOS transistor, since a single transistor element is manufactured, a semiconductor device having a plurality of elements such as BiCMOS is formed with high integration and high manufacturing efficiency. It is not possible. Further, the reliability due to the hot carrier effect or the like accompanying miniaturization is not sufficient. Further, the conventional vertical MOS transistor has insufficient high-speed performance because the gate portion penetrates to the substrate and the gate-drain capacitance increases. Since the back gate and the source are taken out through the same wiring, they cannot be used for controlling the back gate and the source to different potentials. The above problems exist in the conventional vertical MOS transistor and the manufacturing method thereof.
[0009]
Accordingly, the present invention provides a semiconductor device capable of improving pair characteristics and preventing a hot carrier effect, having excellent reliability, having a high degree of integration, and being manufactured with high manufacturing efficiency, and a method of manufacturing the same. With the goal. Still another object of the present invention is to provide a semiconductor device having excellent high-speed performance and capable of controlling each diffusion layer at a different potential, and a method of manufacturing the same.
[0010]
[Means for Solving the Problems]
The present invention includes a first step of forming a second conductive type first diffusion layer having a conductivity type opposite to that of the first conductive type semiconductor substrate in a predetermined region of the first conductivity type semiconductor substrate; A second step of forming a second conductive type semiconductor layer on the one diffusion layer, a third step of providing a first insulating layer on the second conductive type semiconductor layer to form a first region and a second region, A fourth step of forming a second conductivity type second diffusion layer connected to the second conductivity type first diffusion layer in a region, and a fifth step of forming a first conductivity type third diffusion layer in the second region. Forming a fourth diffusion layer of a second conductivity type on a part of the third diffusion layer of the first conductivity type in the second region; and forming a fourth diffusion layer of the second conductivity type in the second region. The second conductivity type semiconductor layer exposes a part of the portion where the second conductivity type fourth diffusion layer and the first conductivity type third diffusion layer and the second conductivity type semiconductor layer are stacked. A seventh step of forming an opening by etching to a depth, and a second step on the surface of the second conductivity type fourth diffusion layer, the first conductivity type third diffusion layer and the second conductivity type semiconductor layer in the opening. A method of manufacturing a semiconductor device, comprising: an eighth step of forming an insulating layer; and a ninth step of burying a conductive layer in the opening in which the second insulating layer is formed on the surface.
[0011]
As described above, the method for manufacturing a semiconductor device of the present invention can manufacture a vertical MOS transistor having a structure in which a gate portion is embedded in a part of a bipolar transistor structure. Therefore, when manufacturing a BiCMOS transistor, the vertical MOS transistor of the present invention can be formed in the same process as a bipolar transistor on the same substrate, and can be manufactured with high manufacturing efficiency.
[0012]
In addition, the present invention provides a first conductivity type semiconductor substrate, a second conductivity type first diffusion layer formed in a predetermined region of the first conductivity type semiconductor substrate and having a conductivity type opposite to the first conductivity type semiconductor substrate. A second conductive type semiconductor layer formed on the second conductive type first diffusion layer, and a first insulating layer provided for forming a first region and a second region in the second conductive type semiconductor layer. A second conductivity type second diffusion layer formed in the first region and connected to the second conductivity type first diffusion layer; a first conductivity type third diffusion layer formed in the second region; A second conductive type fourth diffusion layer formed on a part of the first conductive type third diffusion layer in two regions; and a second conductive type fourth diffusion contacting the first insulating layer in the second region. The second conductivity type semiconductor layer exposes a part of a portion where the layer and the first conductivity type third diffusion layer and the second conductivity type semiconductor layer are stacked. An opening formed by etching, and a second insulating layer formed on the surface of the second conductive type fourth diffusion layer, the first conductive type third diffusion layer, and the second conductive type semiconductor layer in the opening. A semiconductor device comprising: a layer; and a conductive layer embedded in the second insulating layer in the opening.
[0013]
As described above, the method for manufacturing a semiconductor device of the present invention can manufacture a semiconductor device in which a gate portion is embedded in a part of a bipolar transistor structure and can be used as a vertical MOS transistor. Therefore, when manufacturing a BiCMOS transistor, the method of manufacturing a vertical MOS transistor according to the present invention can use the same manufacturing steps as a bipolar transistor on the same substrate, and can be manufactured with high manufacturing efficiency.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0015]
FIG. 1 is a schematic sectional view showing the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment includes a p-type substrate 1, an n-type drain buried layer 21 formed in a predetermined region of the p-type substrate 1, and an n-type drain layer 2 formed in the n-type drain buried layer 21. And a region separation layer 31 provided for forming a first region and a second region in the n-type drain layer 2.
[0016]
The first region has an n-type drain connection layer 22 connected to the n-type drain buried layer 21. The second region has a p-type base layer 13 and an n-type source layer 24 formed in a part of the p-type base layer 13. The gate region of the gate insulating film 32 and the gate electrode 41 that are in contact with the n-type source layer 24, the p-type base layer 13, and the n-type drain layer 2 are buried in the second region.
[0017]
A base wiring 51b is formed in the p-type base layer 13, a source wiring 51s is formed in the n-type source layer 24, a gate wiring 51g is formed in the gate electrode 41, and a drain wiring 51d is formed in the n-type drain connection layer 22.
[0018]
The semiconductor device of the present embodiment has an n-type MOS transistor having a channel in the p-type base layer 13 located between the n-type source layer 24 and the n-type drain layer 2 using the gate insulating film 32 and the gate electrode 41 as a gate portion. Can be used as Further, since the semiconductor device of the present embodiment has the same structure as the bipolar transistor except that it has the gate insulating film 32 and the gate portion of the gate electrode 41, the p-type base layer 13, the n-type source layer 24, the n-type The drain layer 2 can be used as a base, an emitter, and a collector, respectively, as a bipolar transistor. That is, the semiconductor device of the present embodiment can be used both as an n-type MOS transistor and an npn bipolar transistor.
[0019]
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. In the present embodiment, a method of manufacturing the above-described n-type vertical MOS transistor shown in FIG. 1 will be described with reference to FIGS.
[0020]
First, after a thermal oxide film is formed on the main surface of Si (silicon) p-type semiconductor substrate 1 to a thickness of about 100 to 500 nm (not shown), the thermal oxide film in a predetermined region is removed. Then, as shown in FIG. 2, an n-type drain buried layer 21 is formed in a predetermined region by, for example, a solid phase diffusion method of Sb (antimony). This n-type drain buried layer 21 is not particularly limited to the solid-phase diffusion method, but can be formed by, for example, ion implantation of impurities.
[0021]
Next, as shown in FIG. 3, an n-type drain layer 2 of, for example, Si is epitaxially grown on the entire main surface of the semiconductor substrate 1 to a specific resistance of about 1 to 10 Ω · cm to about 1 to 2 μm.
[0022]
Next, as shown in FIG. 4, a region separation layer 31 of, for example, SiO ₂ is formed in a part of the n-type drain layer 2 to form a first region and a second region. The region separation layer 31 is formed to a thickness of about 200 to 600 nm by, for example, a LOCOS (Local Oxidation of Silicon) method. Alternatively, the region isolation layer 31 may be formed by STI (Shallow Trench Isolation).
[0023]
Next, as shown in FIG. 5, an n-type drain connection layer 22 connected to the n-type drain buried layer 21 is formed in the n-type drain layer 2 in the first region. The n-type drain connection layer 22 is ion-implanted with an n-type impurity of, for example, P (phosphorus) under the conditions of an ion energy of about 50 to 100 keV and a dose of about 10 ¹⁴ to 10 ¹⁵ / cm ² . Heat treatment is performed under the conditions of 10 to 30 minutes to connect to the n-type drain buried layer 21.
[0024]
Next, as shown in FIG. 6, a p-type base layer 13 is formed on the entire surface of the n-type drain layer 2 in the second region. After the p-type base layer 13 is formed using, for example, a photoresist (not shown) as a mask, B (boron) is applied to the mask opening under the conditions of ion energy of about 10 to 50 keV and a dose of about 10 ¹¹ to 10 ¹³ / cm ^2. It is formed by ion implantation. At this time, conditions can be set under which a desired threshold value Vth or the like is obtained as transistor characteristics. For example, when combining the characteristics of the MOS transistor and the characteristics of the bipolar transistor, it is preferable that the impurity concentration of the p-type base layer 13 be about 10 ¹⁷ to 10 ¹⁸ / cm ³ .
[0025]
Next, as shown in FIG. 7, an n-type source layer 24 is formed on a part of the p-type base layer 13 in the second region. The n-type source layer 24 is formed, for example, by using a photoresist (not shown) as a mask, and then applying As (arsenic) to the mask opening at an ion energy of about 10 to 30 keV and a dose of about 10 ¹⁴ to 10 ¹⁶ / cm ^2. Is formed by ion implantation. Thereafter, in order to activate the impurities of the p-type base layer 13 and the n-type source layer 24, a heat treatment is performed under the conditions of, for example, 800 to 1000 ° C. for about 10 seconds to 30 minutes, and the p-type having a thickness of 50 nm to 500 nm. A base layer 13 and an n-type source layer 24 having a thickness of 50 nm to 500 nm are formed.
[0026]
Next, as shown in FIG. 8, each of the n-type source layer 24, the p-type base layer 13, and the n-type drain layer 2 in contact with the region isolation layer 31 of the second region is partially replaced by the n-type drain layer 2. The opening 40 is formed by etching to an exposed depth. The opening 40 can be formed by, for example, RIE after forming using a photoresist (not shown) as a mask, for example. Although details will be described later, the opening 40 forms the gate of the semiconductor device of the present embodiment, and the p-type base layer 13 between the n-type source layer 24 and the n-type drain layer 2 forms a channel. Therefore, the thickness of the p-type base layer 13 between the n-type source layer 24 and the n-type drain layer 2 corresponds to the effective gate length.
[0027]
Next, as shown in FIG. 9, a gate insulating film 32 of, for example, SiO _{2 is} formed on the surface of the opening 40 by a thermal oxidation method. In this case, the thickness of the gate insulating film 32 is controlled according to the effective gate length, which is the thickness of the p-type base layer 13 between the n-type source layer 24 and the n-type drain layer 2. For example, when the effective gate length is 0.5 μm, the thickness of the gate insulating film 32 is preferably set to 10 to 20 nm. When the effective gate length is 0.3 μm, it is preferable that the thickness of the gate insulating film 32 be 5 to 10 nm.
[0028]
Next, as shown in FIG. 10, a gate electrode 41 is formed by burying a gate insulating film 32 in an opening 40 formed on the surface. The gate electrode 41 is formed by, for example, forming polycrystalline silicon containing impurities on the entire surface, removing the polycrystalline silicon on the surface by a chemical and mechanical polishing (CMP) method, and flattening the polycrystalline silicon. It can be formed leaving silicon.
[0029]
Then, as shown in FIG. 1, after an interlayer insulating film 33 of SiO ₂ is formed on the entire surface by, eg, CVD, contact holes are formed in portions corresponding to the base wiring, the drain wiring, the gate electrode wiring, and the source wiring ( (Not shown). Next, a base wiring 51b is formed on the p-type base layer 13, a source wiring 51s is formed on the n-type source layer 24, a gate wiring 51g is formed on the gate electrode 41, and a drain wiring 51d is formed on the n-type drain connection layer 22. ).
[0030]
As described above, the method for manufacturing a semiconductor device according to the present embodiment can manufacture a semiconductor device that can be used as both an n-type MOS transistor and an npn bipolar transistor. It is the same as the manufacturing process of the bipolar transistor except that a process for forming a gate insulating film and a gate electrode is provided.
[0031]
In this embodiment, the p-type substrate 1, the n-type drain layer 2, the p-type base layer 13, the n-type drain buried layer 21, the n-type drain connection layer 22, the n-type source layer 24, the region isolation layer 31, the gate insulation The film 32, the interlayer insulating film 32, the contact hole 40, and the gate electrode 41 are sequentially formed of the first conductive type semiconductor substrate, the second conductive type semiconductor layer, the first conductive type third diffusion layer, and the second conductive type One diffusion layer, a second conductivity type second diffusion layer, a second conductivity type fourth diffusion layer, a first insulating layer, a second insulating layer, a third insulating layer, an opening, and a conductive layer.
[0032]
As described above, this embodiment is a semiconductor device having a structure in which a gate portion is embedded in a part of the structure of a bipolar transistor, and which can be used as a vertical MOS transistor, and a method of manufacturing the same. For this reason, when manufacturing a BiCMOS transistor, the vertical MOS transistor of this embodiment can use the same process as the bipolar transistor, and can be manufactured with high manufacturing efficiency.
[0033]
The gate electrode 41 in the present embodiment is buried, unlike the gate electrode of a general lateral MOS transistor. Therefore, the effective gate length of the present embodiment is the thickness of the p-type base layer 13 between the n-type drain layer 2 and the n-type source layer 24. The effective gate length of a general lateral MOS transistor is formed by controlling the lithography process. In the present embodiment, the effective gate length is formed by controlling the conditions of ion implantation and heat treatment of each layer. Since the conditions of the ion implantation and the heat treatment can be easily controlled, a finer effective gate length, for example, an effective gate length of 0.1 μm or less can be easily formed in this embodiment.
[0034]
The above-mentioned pair characteristics are affected by the effective gate length, and the smaller the variation of the effective gate length, the better. The variation of the effective gate length in the present embodiment is caused by the variation due to the ion implantation and the heat treatment, but does not need to take into account the variation due to the lithography process unlike a general lateral MOS transistor. As described above, in the present embodiment, since the variation in the effective gate length can be reduced, a semiconductor device having good pair characteristics can be obtained.
[0035]
The p-type base layer 13 forming a channel is formed by ion-implanting the p-type semiconductor substrate 1 in a direction perpendicular to the p-type semiconductor substrate 1. Therefore, the ion concentration of the p-type base layer 13 can be easily distributed as desired in the vertical direction by controlling the ion implantation conditions. For example, the ion concentration distribution of the p-type base layer 13 can be easily formed with a relatively higher ion concentration on the n-type drain layer 2 side than on the n-type source layer 24 side. When the p-type base layer 13 is formed with a relatively higher ion concentration on the n-type drain layer 2 side than on the n-type source layer 24 side, the hot carrier effect is effectively suppressed because the n-type drain layer 2 side is low. Can be.
[0036]
In addition, when the gate insulating film and the gate portion of the gate electrode have the depth of the drain buried layer, the gate-drain capacitance can be reduced, so that high speed operation can be realized.
[0037]
It should be noted that the present invention is not limited to the above-described embodiment, but may adopt various modifications.
[0038]
For example, in the above embodiment, the diffusion layer is formed from the first region, but each diffusion layer may be formed first from the second region.
[0039]
Further, for example, in the above-described embodiment, after the p-type base layer 13 and the n-type source layer 24 are sequentially formed on the n-type drain layer 2 in the second region, the gate insulating film 32 and the gate electrode 41 are buried. The method has been described. Conversely, after the gate insulating film 32 and the gate electrode 41 are buried and formed in the second region, the p-type base layer 13 and the n-type source layer 24 are sequentially formed on the n-type drain layer 2. Is also good.
[0040]
Further, for example, in the above embodiment, a semiconductor device that can be used as an n-type MOS transistor and an npn bipolar transistor has been described. However, a semiconductor device that can also be used as a p-type MOS transistor and a pnp bipolar transistor by changing ion implantation conditions may be used. .
[0041]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor device which is excellent in reliability, has a high degree of integration, and can be manufactured with high manufacturing efficiency, and a method for manufacturing the same. Further, it is possible to provide a semiconductor device having excellent high-speed performance and capable of controlling each diffusion layer at a different potential, and a method for manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view showing a manufacturing step in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 10 is a schematic sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view showing a manufacturing process in a conventional semiconductor device manufacturing method.
FIG. 12 is a schematic cross-sectional view showing a manufacturing step in a conventional semiconductor device manufacturing method.
FIG. 13 is a schematic cross-sectional view showing a manufacturing step in a conventional semiconductor device manufacturing method.
FIG. 14 is a schematic cross-sectional view showing a manufacturing step in a conventional method of manufacturing a semiconductor device.
[Explanation of symbols]
Reference Signs List 1 ... p-type substrate (first conductivity type semiconductor substrate), 2 ... n-type drain layer (second conductivity type semiconductor layer), 13 ... p-type base layer (first conductivity type third diffusion layer), 21 ... n-type Drain buried layer (second conductivity type first diffusion layer), 22... N-type drain connection layer (second conductivity type second diffusion layer), 24... N-type source layer (second conductivity type fourth diffusion layer), 31 ... Area separation layer (first insulating layer), 32 ... Gate insulating film (second insulating layer), 33 ... Interlayer insulating film (third insulating layer), 40 ... Contact hole (opening), 41 ... Gate electrode (conductive) Layer), 51s: source wiring, 51d: drain wiring, 51g: gate wiring, 51b: base wiring

Claims (6)

A first step of forming a second conductivity type first diffusion layer having a conductivity type opposite to that of the first conductivity type semiconductor substrate in a predetermined region of the first conductivity type semiconductor substrate;
A second step of forming a second conductivity type semiconductor layer on the second conductivity type first diffusion layer;
A third step of forming a first region and a second region by providing a first insulating layer on the second conductivity type semiconductor layer;
A fourth step of forming a second conductivity type second diffusion layer connected to the second conductivity type first diffusion layer in the first region;
A fifth step of forming a first conductivity type third diffusion layer in the second region;
A sixth step of forming a second conductivity type fourth diffusion layer on a part of the first conductivity type third diffusion layer in the second region;
The second conductive type fourth diffusion layer, the first conductive type third diffusion layer, and the second conductive type semiconductor layer, which are in contact with the first insulating layer in the second region, are partially stacked with the second conductive type. A seventh step of forming an opening by etching to a depth at which the mold semiconductor layer is exposed;
An eighth step of forming a second insulating layer on the surface of the second conductive type fourth diffusion layer, the first conductive type third diffusion layer, and the second conductive type semiconductor layer in the opening;
A ninth step of embedding a conductive layer in the opening in which the second insulating layer is formed on the surface;
A method for manufacturing a semiconductor device comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the fifth step, the first conductivity type third diffusion layer is formed with a lower ion concentration on the second conductivity type semiconductor layer side than on the second conductivity type fourth diffusion layer side. 3. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the seventh step, the opening is formed by etching a depth from before reaching the second conductivity type semiconductor layer to the second conductivity type first diffusion layer. 3. A first conductivity type semiconductor substrate;
A second conductivity type first diffusion layer formed in a predetermined region of the first conductivity type semiconductor substrate and having a conductivity type opposite to that of the first conductivity type semiconductor substrate;
A second conductivity type semiconductor layer formed on the second conductivity type first diffusion layer;
A first insulating layer provided for forming a first region and a second region in the second conductivity type semiconductor layer;
A second conductivity type second diffusion layer formed in the first region and connected to the second conductivity type first diffusion layer;
A first conductivity type third diffusion layer formed in the second region;
A second conductivity type fourth diffusion layer formed on a part of the first conductivity type third diffusion layer in the second region;
The second conductive type fourth diffusion layer, the first conductive type third diffusion layer, and the second conductive type semiconductor layer, which are in contact with the first insulating layer in the second region, are partially overlapped with the second conductive type second diffusion layer. An opening formed by etching to a depth where the conductive semiconductor layer is exposed,
A second insulating layer formed on a surface of the second conductive type fourth diffusion layer, the first conductive type third diffusion layer, and the second conductive type semiconductor layer in the opening;
A conductive layer embedded in the second insulating layer in the opening;
A semiconductor device comprising: The semiconductor device according to claim 4, wherein the first conductive type third diffusion layer has a lower ion concentration on the second conductive type semiconductor layer side than on the second conductive type fourth diffusion layer side. The semiconductor device according to claim 5, wherein the opening has a depth from the second conductivity type semiconductor layer to the second conductivity type first diffusion layer.

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