JP2004179391A - Method for forming semiconductor multilayer wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a reduction in man-hours and to improve the degree of freedoms of process control without deteriorating a low dielectric layer constituting an interlayer insulating layer, in a method for forming a wiring using a dual damascene process for forming a multilayer wiring structure by embedding a first etching space formed in the interlayer insulating layer and a second etching space communicating with the first etching space with a conductor material. <P>SOLUTION: An embedding material 34b containing a spin on glass material which can be easily removed with a release liquid without imparting a damage to the interlayer insulating layer is used as a material to be filled in the first etching space for protecting a lower layer wiring layer 26 against an exposure light to form a photoresist pattern for forming the second etching space. An absorbance material for absorbing the exposure light is not added to this embedding material, and instead of it, an antireflection film 35 which can be worked by dry etching is formed on an embedding material layer. <P>COPYRIGHT: (C)2004,JPO

Description

（式中、ｎは１以上の整数を表し、Ｘは炭素原子数１〜１０の直鎖もしくは分岐状のアルキル鎖、芳香性もしくは脂環性の環状アルキル鎖、アルキルエステル鎖であり、Ｙは所定のエネルギーの印加を受けてスルホン酸残基を生じる置換基である。）
で表される繰り返し単位を有することを特徴とする。
【００４５】
前記スルホン酸残基を生じさせるために印加される所定のエネルギーとしては、例えば、８０℃以上の加熱処理等でスルホン酸残基を生じさせることができる。このような所定のエネルギーの印加は剥離処理における加熱とアルカリの協奏作用によりさらに促進される。
【００４６】
前記一般式（１）の置換基Ｙとしては、−ＳＯ_３Ｒ_１もしくは−ＳＯ_３ ⁻Ｒ_２ ^＋（式中、Ｒ_１およびＲ_２は１価の有機基）が好ましい。
【００４７】
前記有機基Ｒ_１としては、炭素原子数１〜１０のアルキル基、あるいはヒドロキシアルキル基のなかから選ばれる１種が好ましい。
【００４８】
また、前記有機基Ｒ_２としては、アルカノールアミン、およびアルキルアミンの中から選ばれる少なくとも１種が好ましい。
【００４９】
さらに、前記所定のエネルギーが印加されることにより末端基が脱離してスルホン酸残基を生じる置換基を少なくとも有する樹脂成分として、前述のいずれかの樹脂成分と、アクリル酸またはメタアクリル酸あるいはそれらの誘導体との共重合体あるいは混合樹脂を用いてもよい。
【００５０】
樹脂成分として、前記共重合体あるいは混合樹脂を用いる場合、その重合比あるいは混合比は、レジスト現像液に対する耐性があり、レジスト剥離液にて除去できるという効果を維持できる範囲にあれば、特に限定されない。
【００５１】
さらにまた、前記所定のエネルギーが印加されることにより末端基が脱離してスルホン酸残基を生じる置換基を少なくとも有する樹脂成分として、
前述のいずれかの樹脂成分とアクリル酸またはメタアクリル酸あるいはそれらの誘導体との共重合体あるいは混合樹脂に対して、下記一般式（２）
【化３】

（式中、ｎは１以上の整数を表し、Ｒ_３は水素原子、フッ素原子、水酸基、カルボキシル基、炭素原子数１〜５のヒドロキシアルキル基、炭素原子数１〜５のアルコキシアルキル基の中から選ばれる少なくとも１種であり、Ｚは炭素原子数１〜１０の直鎖もしくは分岐状のアルキル鎖、芳香性もしくは脂環性の環状アルキル鎖、アルキルエステル鎖である。）
で表される繰り返し単位を共重合させた共重合体もしくは前記一般式（２）で表される繰り返し単位を有する樹脂化合物を混合させた混合樹脂からなる樹脂成分を用いてもよい。
【００５２】
前記一般式（２）の誘導体を用いて共重合体を調製し、その共重合体を樹脂成分として反射防止膜材料を構成すれば、樹脂成分のユニットにアントラセンが含まれることになり、このアントラセンは、特にＫｒＦエキシマレーザーを用いたリソグラフィーにおいて吸収特性が高く、好ましい。
【００５３】
この反射防止膜形成材料に用いる溶媒としては、従来の下層膜形成材料に用いられるものであれば、特に制限することなく用いることができる。
【００５４】
前述の「所定のエネルギーが印加されることにより末端基が脱離してスルホン酸残基を生じる置換基を少なくとも有する樹脂成分と、溶媒とを含有してなる樹脂組成物」から反射防止膜を形成すれば、第２のエッチング空間を形成し、埋込材を除去した後、ホトレジスト膜および反射防止膜の除去を行う工程で、通常のリソグラフィー処理で用いられるホトレジスト用剥離剤により簡易に除去することが可能となる。その結果、Ｏ_２プラズマアッシングを用いた反射防止膜除去処理に伴う低誘電体層へのダメージのリスクを回避することができる。また、ホトレジストパターンの形成に失敗した際に行われる半導体基板回収のリワークについても容易となる。
【００５５】
さらに、前記反射防止膜を形成するための他の組成物として、ポリチタノキサンおよびポリシロキサンの混合物もしくはそれらの共重合体を含有してなる樹脂組成物を用いることもできる。この樹脂組成物は、チタノキサン：Ｒ_ｍＴｉ（ＯＲ）_{（４−ｍ）}を縮合させた反応物と、シロキサン：Ｒ_ｎＳｉ（ＯＲ）_{（４−ｎ）}を縮合させた反応物の混合物、もしくはこれらの成分を合わせて縮合させた反応物を主成分とするもので、必要に応じて、活性剤、架橋促進剤等を含有させる。前記式中、Ｒは主にアルキル基であり、同一でも異種でもよく、ｍ、ｎは０〜３の整数である。また、この主成分中のＴｉ含有量は、０．１〜９９．９％であり、好ましくは、５〜７０％である。この樹脂組成物の溶剤としては、主成分樹脂を溶解でき、基板上に塗布し、乾燥した後で、加熱処理することで、レジストとインターミキシングしない程度に、膜を形成できるものであれば、特に限定することなく、何でも使用できる。
【００５６】
前述の「ポリチタノキサンおよびポリシロキサンの混合物もしくはそれらの共重合体を含有してなる樹脂組成物」を用いて反射防止膜を形成すれば、第２のエッチング空間を形成し、埋込材を除去した後、ホトレジスト膜および反射防止膜の除去を行う工程で、通常のリソグラフィー処理で用いられるホトレジスト用剥離剤により簡易に除去することが可能となる。その結果、Ｏ_２プラズマアッシングを用いた反射防止膜除去処理に伴う低誘電体層へのダメージのリスクを回避することができる。また、ホトレジストパターンの形成に失敗した際に行われる半導体基板回収のリワークについても容易となる。
【００５７】
前述のような本発明方法による効果としては、以下のものを得ることができる。
（ｉ） デュアルダマシンプロセスにおけるトレンチ／ビアの形成時に、ビア／トレンチ内の埋込材を、低誘電体層と同時に、あるいは低誘電体層よりも速く、エッチング除去することが可能となる。
（ｉｉ） エッチング除去後にビアホール内に残った埋込材料は、フッ化水素酸を含有する剥離液により容易に除去することが可能となる。
（ｉｉｉ） 有機膜を埋込材料とした従来例では、Ｏ_２プラズマアッシングによる除去が必要であったが、この工程を省くことができるため、低誘電体層へのダメージ（Ｓｉ−Ｒ結合→Ｓｉ−ＯＨ結合）、および誘電率（ｋ）の変動をなくすことが可能となる。
（ｉｖ） 実質的に有機系添加物（先行技術に言うところの高吸光性成分、染料、等）を配合しない埋込材料を用いるので、スピンオングラス材料の経時劣化が防止でき、これにより埋込材溶液の保存安定性、および膜の安定性を高めることができ、工程管理の自由度を高めることができる。また、上層膜との層間にインターミキシングが発生することを抑止することができる。
（ｖ） スピンオングラス材料層の真上層にホトレジスト層を設けるプロセスでは、レジスト膜とのマッチング評価において、ロット間でのバラツキが多く発生したのに対し、反射防止膜を介する構成であるので、ホトレジスト層とのマッチングが容易となる。
【００５８】
【実施例】
以下、本発明を実施例によりさらに詳しく説明する。以下に示す実施例は、本発明を好適に説明する例示に過ぎず、なんら本発明を限定するものではない。
【００５９】
（実施例１）
銅配線が形成された基板上に、ＳｉＮ層、ヒドロキシシルセスキオキサン系低誘電体材料（東京応化工業株式会社製（商品名：ＯＣＤ Ｔ−１２））からなる第１の低誘電体層、ＳｉＮ層、およびヒドロキシシルセスキオキサン系低誘電体材料（東京応化工業株式会社製（商品名：ＯＣＤ Ｔ−１２））からなる第２の低誘電体層の４つの層を、順次積層して、６０００Åの層間絶縁層を形成した。
【００６０】
前記層間絶縁層の上に、ＡＲＣ−２９（Ｂｒｅｗｅｒ ｓｃｉｅｎｃｅ社製）からなる膜厚７７０Åの第１の反射防止膜を形成し、その上に膜厚４０００Åの第１のホトレジスト層を形成し、露光、現像処理を施した。前記第１のホトレジスト層は、アクリル系ポリマーを主成分とするレジスト組成物（東京応化工業株式会社製（商品名：ＴＡｒＦ−７ａ２１））を用いて形成した。
【００６１】
得られたホトレジストパターンをマスクとして、前記層間絶縁層にエッチング処理を施し、直径２００ｎｍのビアホールを形成した。
【００６２】
このビアホールに対して、前記積層およびエッチング工程とは別工程にて調製しておいた埋込材を前記層間絶縁層上に膜厚４０００Åとなるようにスピンコーティングにより均一に塗布し、ビアホールを埋込材にて埋め込んだ。
【００６３】
前記埋込材は、次のようにして調製したものである。すなわち、トリエトキシシラン２３６．５８ｇ（１．４４モル）、テトラメトキシシラン１０８．７２ｇ（０．７２モル）、プロピレングリコールジメチルエーテル２１１７．７１ｇ（２０．４モル）、水１２９．６ｇ（７．２モル）および濃硝酸４３２μＬを配合して溶液を得た。この溶液を１５０ｍｍＨｇ、４０℃で４時間減圧蒸留し、固形分濃度９．０重量％、アルコール濃度３．８重量％の埋込材を調製した。
【００６４】
前述のようにビアホールに埋込材を埋め込むために基板表面に均一に塗布された埋込材層の上に、ＡＲＣ−２９（Ｂｒｅｗｅｒ ｓｃｉｅｎｃｅ社製）からなる膜厚７７０Åの第２の反射防止膜を形成し、その上に膜厚４０００Åの第２のホトレジスト層を形成し、露光、現像処理を施した。第２のホトレジスト層は、前記第１のホトレジスト層と同一組成物から形成した。
【００６５】
得られたホトレジストパターンをマスクとして、Ｎ_２＋０_２の混合ガスからなるエッチングガスを用いて反射防止膜の露出部分を除去した。
【００６６】
続けて、前記ホトレジストパターンをマスクとして、ＣＦ_４＋ＣＨＦ_３の混合ガスからなるエッチングガスを用いて層間絶縁層の要部を除去し、トレンチを形成した。このエッチング処理後もビアホール内に残った埋込材は、０．１質量％バッファードフッ酸を用いて除去した。
【００６７】
その結果、低誘電体層にダメージおよび誘電率の変動を及ぼすことなく、工程を簡略化し、ビアホールとトレンチとからなるデュアルダマシン構造を形成することができた。
【００６８】
（実施例２〜５）
前記実施例１における第１の反射防止膜と第２の反射防止膜とを、以下の４種の樹脂組成物から構成した以外は、実施例１と同様にして、それぞれデュアルダマシン構造を形成した。
【００６９】
反射防止膜形成材料として、次の（Ａ）、（Ｂ）、（Ｃ）、および（Ｄ）の樹脂組成物を調製した。
【００７０】
（Ａ） ｐ−スチレンスルホン酸エチルからなる樹脂成分を、γ−ブチロラクトン／乳酸エチル（２：８）からなる溶媒に溶解し、固形分濃度を６ｗｔ％に調整した樹脂組成物。
【００７１】
（Ｂ） ｐ−スチレンスルホン酸エチル：ヒドロキシエチルアクリレート（＝５：５）からなる樹脂成分と、該樹脂成分量の２０ｗｔ％相当量のサイメル１１７２（三井サイアナミッド社製テトラメチロールグリコールウリル）とを、乳酸エチルからなる溶媒に溶解し、固形分濃度を６ｗｔ％に調整した樹脂組成物。
【００７２】
（Ｃ） ｐ−スチレンスルホン酸エチル：９−ヒドロキシアントラセニルアクリレート（＝５：５）からなる樹脂成分を、γ−ブチロラクトン／乳酸エチル（２：８）からなる溶媒に溶解し、固形分濃度を６ｗｔ％に調整した樹脂組成物。
【００７３】
（Ｄ） ｐ−スチレンスルホン酸エチル：ヒドロキシエチルアクリレート：９−ヒドロキシアントラセニルアクリレート（＝４：３：３）からなる樹脂成分と、該樹脂の２０ｗｔ％相当量のサイメル１１７２（三井サイアナミッド株式会社製テトラメチロールグリコールウリル）と、前記２種の固形分量の１０００ｐｐｍ相当量のメガファックＲ０８（大日本インキ株式会社製フッ素系界面活性剤）とを、乳酸エチルからなる溶媒に溶解し、固形分濃度を６ｗｔ％に調整した樹脂組成物。
【００７４】
これら（Ａ）（Ｂ）（Ｃ）（Ｄ）の樹脂組成物を前記実施例１における第１の反射防止膜と第２の反射防止膜を形成するための材料とした。これら樹脂組成物を反射防止膜形成材料として用い、各反射防止膜の膜厚を２０００Åにした以外は、実施例１と同様にして、トレンチとビアホールからなる配線構造を形成した。なお、各樹脂組成物を塗布して反射防止膜を得るための加熱条件は、２００℃にて９０秒間であった。
【００７５】
その結果、（Ａ）（Ｂ）（Ｃ）（Ｄ）のいずれの樹脂組成物を用いた場合も、低誘電体層にダメージおよび誘電率の変動を及ぼすことなく、工程を簡略化し、ビアホールとトレンチとからなるデュアルダマシン構造を形成することができた。
【００７６】
（実施例６）
前記実施例１における第１の反射防止膜と第２の反射防止膜とを、以下の樹脂組成物から構成した以外は、実施例１と同様にして、それぞれデュアルダマシン構造を形成した。
【００７７】
テトライソプロポキシチタン１００ｇをエタノール３３８ｇに溶解し、次いで酢酸を１２１ｇ、さらにアセチルアセトン３５７ｇを投入して混合物を得た。この混合物を４時間撹拌し、その後、１６時間静置させることによって、ポリチタノキサン１０％液を得た。
【００７８】
次に、テトラエトキシシラン３２４ｇにメタノール１１３ｇ、アセチルアセトン３１２ｇ、酢酸３２４ｇを投入して混合物を得た。この混合物を６時間撹拌し、その後、１６時間静置させることによって、ポリシロキサン９％液を得た。
【００７９】
前記ポリチタノキサン液と、ポリシロキサン液とを、１：１で混合し、ブチルセロソルブで希釈した樹脂混合溶液を、前記実施例１における第１の反射防止膜と第２の反射防止膜を形成するための材料とした。この樹脂混合溶液を反射防止膜形成材料として用い、各反射防止膜の膜厚を１２４０Åにした以外は、実施例１と同様にして、トレンチとビアホールからなる配線構造を形成した。なお、各樹脂組成物を塗布して反射防止膜を得るための加熱処理は、まず９０℃９０秒間加熱し、その後、２２０℃６００秒間加熱するというものであった。
【００８０】
その結果、この樹脂混合物を用いて反射防止膜を形成した場合も、低誘電体層にダメージおよび誘電率の変動を及ぼすことなく、工程を簡略化し、ビアホールとトレンチとからなるデュアルダマシン構造を形成することができた。
【００８１】
（比較例１）
実施例１で用いた埋込材を形成する組成物を、メトキシメチル化ベンゾグアナミンの３０重量％プロピレングリコールモノメチルエーテルアセテート溶液から構成した以外は、全く同様の組成および操作により、デュアルダマシン構造を形成した。
【００８２】
その結果、埋込材は、トレンチを形成するための「ＣＦ_４＋ＣＨＦ_３の混合ガスからなるエッチングガスによるドライエッチング処理」に伴う埋込材のエッチングによっては、殆ど除去できなかった。また、その後の剥離洗浄液を用いた処理によっても除去することができなかった。
【００８３】
そこで、除去できずに残留した埋込材を除去するために、Ｎ_２＋Ｏ_２の混合ガスからなるエッチングガスを用いてドライエッチング処理を行ったところ、埋込材の除去はできたものの、低誘電体層の表面にダメージが現れていることが、走査電子顕微鏡（ＳＥＭ）による観察により判明した。
【００８４】
【発明の効果】
以上説明したように、本発明にかかる半導体多層配線形成方法は、半導体基板上に形成された下層配線層と、その上に層間絶縁層を介して形成された上層配線層とが、前記層間絶縁層を上下に貫通するビア配線によって接続されている半導体多層配線の形成方法において、前記下層配線層上に少なくとも低誘電体層からなる前記層間絶縁層を積層する層間絶縁層形成工程と、前記層間絶縁層上にホトレジスト層を形成し、パターン露光の後、現像処理してホトレジストパターンを形成し、このホトレジストパターンをマスクとしてエッチングを行って前記層間絶縁層に第１エッチング空間を形成する第１エッチング空間形成工程と、前記層間絶縁層上に、少なくともスピンオングラス材料を主成分とする埋込材を塗布することによって、前記第１エッチング空間に前記埋込材を埋め込む埋め込み工程と、前記層間絶縁層上に形成された埋込材層の上にドライエッチングにより加工可能な反射防止膜を形成する反射防止膜形成工程と、前記反射防止膜上にホトレジスト層を形成し、このホトレジスト層にパターン光を照射し、アルカリ現像液により現像して、ホトレジストパターンを形成するホトレジストパターン形成工程と、前記ホトレジストパターンをマスクとして前記反射防止膜の露出部分をドライエッチングにより加工する反射防止膜加工工程と、前記ホトレジストパターンをマスクとしてエッチングを行って、前記第１エッチング空間の上部の前記層間絶縁層を所定のパターンに除去して前記第１エッチング空間と連通する第２エッチング空間を形成すると同時に、前記第１エッチング空間内の埋込材を除去する第２エッチング空間形成および埋込材除去工程と、前記第１エッチング空間と第２エッチング空間とを同時に導体材料で埋め込み、前記ビア配線と上層配線層とを同時に形成する配線一括形成工程と、を有することを特徴とする。
【００８５】
すなわち、本発明方法は、デュアルダマシンプロセスによる半導体多層配線形成方法において、第２エッチング空間形成用のホトレジストパターンを形成するための露光光から下層配線層を保護するために第１エッチング空間内に充填される材料として、層間絶縁層にダメージを与えることのない剥離液により容易に除去することのできるスピンオングラス材料を主成分とする埋込材を用いるとともに、埋込材層の上にドライエッチングにより除去可能な反射防止膜を形成することを特徴する。
【００８６】
したがって、本発明方法によれば、以下のような利点が得られる。
（ｉ） デュアルダマシンプロセスにおける第２エッチング空間の形成時に、第１エッチング空間内の埋込材を、低誘電体層と同時に、あるいは低誘電体層よりも速く、エッチング除去することが可能となる。
（ｉｉ） エッチング除去後に第１エッチング空間内に残った埋込材料は、通常のリソグラフィーで用いられるホトレジスト用剥離液により容易に除去することが可能となる。
（ｉｉｉ） 有機膜を埋込材料とした従来例では、Ｏ_２プラズマアッシングによる除去が必要であったが、この工程を省くことができるため、低誘電体層へのダメージ（Ｓｉ−Ｒ結合→Ｓｉ−ＯＨ結合）、および誘電率（ｋ）の変動をなくすことが可能となる。
（ｉｖ） 実質的に有機系添加物（先行技術に言うところの高吸光性成分、染料、等）を配合しない埋込材料を用いるので、スピンオングラス材料の経時劣化が防止でき、これにより埋込材溶液の保存安定性、および膜の安定性を高めることができ、工程管理の自由度を高めることができる。また、インターミキシングの発生を防止することができる。
（ｖ） スピンオングラス材料層の真上層にホトレジスト層を設けるプロセスでは、レジスト膜とのマッチング評価において、ロット間でのバラツキが多く発生したのに対し、反射防止膜を介する構成であるので、ホトレジスト層とのマッチングが容易となる。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は、デュアルダマシンプロセスを用いた従来の半導体多層配線形成方法の前半の工程を説明した図である。
【図２】（ｅ）〜（ｈ）は、デュアルダマシンプロセスを用いた従来の半導体多層配線形成方法の後半の工程を説明した図である。
【図３】（ａ）〜（ｄ）は、デュアルダマシンプロセスを用いた本発明にかかる半導体多層配線形成方法の前半の工程を説明した図である。
【図４】（ｅ）〜（ｈ）は、デュアルダマシンプロセスを用いた本発明にかかる半導体多層配線形成方法の後半の工程を説明した図である。
【符号の説明】
２１ 基板
２２ 低誘電体層
２３ レジスト膜
２４ 配線溝（トレンチ）
２５ バリヤメタル
２６ 下層配線層
２７ 第１の低誘電体層
２８ 第１のエッチングストッパ膜
２９ 第２の低誘電体層
３０ 第２のエッチングストッパ膜
３１ 反射防止膜
３２ レジストマスク
３３ ビアホール
３４ａ 埋込材層
３４ｂ ビアホール内の埋込材
３５ ドライエッチングにより除去可能な反射防止膜
３６ レジストマスク
３７ トレンチ
３８ ビア配線
３９ 上層配線層[0001]
TECHNICAL FIELD OF THE INVENTION
According to the present invention, a lower wiring layer formed on a semiconductor substrate and an upper wiring layer formed thereon via an interlayer insulating layer are connected by via wiring vertically penetrating the interlayer insulating layer. The present invention relates to a method for forming a semiconductor multilayer wiring, and more particularly, to a method for forming a semiconductor multilayer wiring in which the via wiring and an upper wiring layer are formed by a simpler dual damascene process.
[0002]
[Prior art]
As is well known, a basic wiring structure in a semiconductor integrated circuit includes a lower wiring layer formed directly or indirectly on a semiconductor substrate and an upper wiring layer formed on the lower wiring layer via an interlayer insulating layer. Are connected by via wiring formed so as to penetrate the interlayer insulating layer. By multiplying and multiplying this wiring structure, a multilayer wiring structure of a semiconductor integrated circuit is formed.
[0003]
Heretofore, this wiring structure has been realized by repeating formation of layers such as a conductor layer and an interlayer insulating layer laminated on a semiconductor substrate and patterning by etching. Since the sequential formation method of forming a multilayer wiring by repeating such lamination and etching has many steps and it is difficult to reduce the manufacturing cost, an inlaid method which is generally called a damascene method at present is now used. Has been adopted. The damascene method is a wiring forming method in which a wiring groove called a via hole or a trench for forming a via wiring or an upper wiring layer is formed in an interlayer insulating layer, and a conductive material is buried in the space. In the damascene method, when the via wiring and the upper wiring layer are formed at the same time, it is particularly called a dual damascene process. By adopting this damascene method, it has become possible to use copper which could not be used as a conductor material in the past. That is, as a conductor material for fine wiring, copper is a preferable material because of its excellent electromigration resistance as compared with aluminum, but it is difficult to etch, and therefore, it is difficult to use copper in the conventional multilayer wiring sequential forming method. could not. However, by using the above-described damascene method, the long-awaited copper can be used as a conductor material.
[0004]
The basic steps of such a dual damascene process will be described with reference to FIGS.
[0005]
First, as shown in FIG. 1A, an interlayer insulating layer 2 is formed on a substrate 1 by a CVD method, a spin coating method, or the like. The material forming the interlayer insulating layer 2 is SiO₂And SOG (spin on glass) are used. A resist film 3 is formed on the interlayer insulating layer 2 and patterned. Using the patterned resist film 3 as a mask, the interlayer insulating layer 2 is selectively etched, and then the resist film 3 is removed to form a wiring groove (trench) 4 as shown in FIG. I do. Next, a barrier metal 5 is deposited on the surface of the interlayer insulating layer 2 in which the wiring groove 4 has been formed as described above, so that copper to be buried in the wiring groove 4 is formed on the inner surface of the wiring groove 4. A barrier metal film is formed to improve adhesion to the layer 2 and at the same time prevent copper from diffusing into the interlayer insulating layer 2. Thereafter, as shown in FIG. 1C, copper is buried in the wiring groove 4 by electrolytic plating or the like to form a lower wiring layer 6.
[0006]
Next, at this point, the copper and the remaining barrier metal 5 adhering to the surface of the interlayer insulating layer 2 are removed by chemical polishing (CMP), and the surface of the interlayer insulating layer 2 is planarized. A first low dielectric layer 7, a first etching stopper film 8, a second low dielectric layer 9, and a second etching stopper film 10 are sequentially stacked. Next, a resist mask 11 having a pattern for forming a via hole is formed on the second etching stopper film 10. Next, as shown in FIG. 1D, etching is performed using the resist mask 11 to form a second etching stopper film 10, a second low dielectric layer 9, a first etching stopper layer 8, Then, a via hole 12 penetrating through the first low dielectric layer 7 and reaching the surface of the lower wiring layer 6 is formed. Subsequently, as shown in FIG. 2E, the via hole 12 is filled with an embedding material 13 such as a photoresist material. The embedding material 13 is etched back to leave a predetermined thickness at the bottom of the via hole 12 as shown in FIG. 2F, and further, a pattern for forming a trench is formed on the second etching stopper film 10. Is formed. Using this resist mask 14, as shown in FIG. 2G, the second etching stopper film 10 and the second low dielectric layer 9 are etched to form a trench 15 and the bottom of the via hole 12. Is removed. Thereafter, copper is buried in the via hole 12 and the trench 15 to form a via wiring 16 and an upper wiring layer 17 as shown in FIG. Thus, a multilayer wiring structure in which the lower wiring layer 6 and the upper wiring layer 17 are electrically connected by the via wiring 16 is realized.
[0007]
By the way, an embedding material is used in the above-described method for forming a multilayer wiring, and the role of the embedding material is as follows. That is, when the trench is formed by etching after the formation of the via hole, if the substrate is exposed at the bottom of the via hole, the lower wiring layer existing on the substrate surface is damaged by the etching gas for forming the trench. , Wiring defects and the like. Therefore, the via hole is filled with a filling material to protect the lower wiring layer during the trench forming step.
[0008]
Conventionally, a photoresist composition has been used as the embedding material. However, when the photoresist composition is filled in the via hole, bubbles may be generated and the embedding may not be sufficiently performed. It has been proposed to use a solution in which a thermally crosslinkable compound is dissolved in an organic solvent as a material (Patent Document 1).
[0009]
However, in the configuration using this organic film as the embedding material, it is not easy to remove the embedding material remaining in the via hole after completing the role of the embedding material, and it is necessary to perform a removal process by oxygen plasma ashing. There is a problem. In this case, the etching gas (mainly an oxygen-based gas) may damage the low dielectric layer. As the damage, the Si-R bond of the low dielectric layer changes to a Si-OH bond, and the dielectric constant (k) changes.
[0010]
Further, as another embedding material, a spin-on-glass material or a composition in which a high light-absorbing dye is added thereto has been disclosed (Patent Documents 1 and 2). The purpose of adding a high light-absorbing dye to this composition is that, since the spin-on-glass material is a transparent material, exposure light when patterning a resist for forming a trench reaches the substrate surface, and the reflected light is emitted. This is to prevent the light from being incident on the resist and deteriorating the pattern resolution of the resist. In this embedding material composition, since the spin-on-glass material as a main component has high compatibility with hydrofluoric acid, even if the embedding material remains in the via hole, it is easily prepared by a stripping solution containing hydrofluoric acid. It has the advantage that it can be removed. However, on the other hand, the high-absorbing dye, which is an additive component, is liable to deteriorate, so the storage stability of the embedding material solution is low, and the stability of the embedding film is also low. However, there is a problem that the degree of freedom of process control is greatly restricted. When a high light-absorbing dye is blended, intermixing may occur between the upper layer and the upper layer.
[0011]
Patent Document 3 discloses a configuration in which an anti-reflection film for blocking the reflected light is provided on the burying material layer, and a resist layer for forming a trench is formed on the anti-reflection film. I have. It is stated that conventional organic and inorganic materials are used as the material of the antireflection film.
[0012]
As for the material of the antireflection film, there have been proposed some materials obtained by improving the composition in which a dye is added to a spin-on glass material (for example, Patent Documents 4 and 5). Patent Literature 4 discloses an antireflection coating material having an improved etching rate as compared with a photoresist by improving a silane compound as a main component. Patent Literature 5 discloses an antireflection coating material in which a specific high light-absorbing component is blended with an alkoxysilane-based material to improve light absorption.
[0013]
As described above, in the conventional multilayer wiring forming method by the dual damascene process, when an organic film such as a photosensitive resin or a thermoplastic resin is used for the filling material, the inside of the via hole after the role of the filling material is completed. However, there is a problem that the removal of the embedded material remaining in the substrate is not easy, and a removal treatment by oxygen plasma ashing is required, so that the number of steps is increased, and it is difficult to reduce the manufacturing cost. Further, there is a problem that the low dielectric layer is damaged by the oxygen plasma gas.
[0014]
In addition, when a spin-on glass material having high compatibility with hydrofluoric acid, which is a main component of the release agent, is used in order to facilitate removal of the remaining embedding material, since this material is transparent, exposure light is reduced. A dye having a high light absorption must be added so as not to reach the substrate surface, and the high absorption dye, which is an added component, is liable to deteriorate, so that the storage stability of the embedding material solution is low, and As a result, the stability of the buried film tends to be low, and the degree of freedom in process control is greatly limited. When a high light-absorbing dye is blended, intermixing may occur between the upper layer and the upper layer.
[0015]
[Patent Document 1]
JP 2000-195555 A
[Patent Document 2]
US Patent No. 6,329,118
[Patent Document 3]
U.S. Pat. No. 6,365,529
[Patent Document 4]
JP 2001-92122 A
[Patent Document 5]
US Patent No. 6,268,457
[0016]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and in a method of forming a semiconductor multilayer wiring using a dual damascene process, it is possible to reduce man-hours without deteriorating a low dielectric layer constituting an interlayer insulating layer. It is an object to improve the degree of freedom in process control.
[0017]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the inventors of the present application have considered the role of the embedding material essential for the damascene method and the exposure reflection generated when forming a trench from the flow of the entire process of forming a semiconductor multilayer wiring by a dual damascene process. After reexamining the relationship with the means for preventing light and repeatedly examining materials suitable as the embedding material and the antireflection film material, the following findings were obtained.
[0018]
(I) In order to completely and easily remove the residual embedding material without deteriorating the low dielectric layer, a spin-on-glass material should be used as a main component of the embedding material.
(Ii) Rather than adding a highly light-absorbing dye to the spin-on-glass material to lower its transparency and compensating for the storage stability, the embedding material plays a role only as the embedding material. By adopting a configuration in which the role of preventing exposure light from being reflected from the substrate is provided by providing an anti-reflection film having high storage stability and easy removal, stable supply of materials and process management are facilitated. Accordingly, formation of a multilayer wiring is facilitated.
(Iii) By using an embedding material mainly composed of a spin-on-glass material, the etching rate can be made equal to or higher than the etching rate of the low dielectric layer, and the second etching space can be easily formed. .
(Iv) In the process of providing a photoresist layer immediately above the spin-on-glass material layer, in the evaluation of matching with the resist film, a lot of variations between lots occurred. Is easily matched.
[0019]
The present invention has been made based on such knowledge, and a method of forming a semiconductor multilayer wiring according to the present invention is directed to a method of forming a lower wiring layer formed on a semiconductor substrate and an upper layer formed thereon via an interlayer insulating layer. In a method for forming a semiconductor multilayer wiring in which a wiring layer is connected by a via wiring vertically penetrating the interlayer insulating layer, an interlayer for laminating the interlayer insulating layer made of at least a low dielectric layer on the lower wiring layer An insulating layer forming step, a photoresist layer is formed on the interlayer insulating layer, and after pattern exposure, development processing is performed to form a photoresist pattern, and etching is performed using the photoresist pattern as a mask to form a first layer on the interlayer insulating layer. A first etching space forming step of forming an etching space, and an embedding material containing at least a spin-on-glass material as a main component is formed on the interlayer insulating layer. A burying step of burying the burying material in the first etching space by fabricing; and forming a reflection preventing film which can be processed by dry etching on the burying material layer formed on the interlayer insulating layer. Forming a photoresist layer on the anti-reflection film, irradiating the photoresist layer with pattern light, developing with an alkaline developer, forming a photoresist pattern, the photoresist pattern, An anti-reflection film processing step of processing the exposed portion of the anti-reflection film by dry etching using a mask as a mask, and performing etching using the photoresist pattern as a mask, so that the interlayer insulating layer above the first etching space has a predetermined pattern. And a second etching space communicating with the first etching space Forming a second etching space and removing a filling material in the first etching space at the same time as forming the first etching space; and filling the first etching space and the second etching space with a conductive material at the same time; A wiring collective forming step of simultaneously forming the wiring and the upper wiring layer.
[0020]
In the above configuration, the first etching space means a trench or a via hole, and the second etching space means a via hole or a trench.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
An example of the method for forming a semiconductor multilayer wiring according to the present invention will be described in more detail with reference to FIGS.
[0022]
First, as shown in FIG. 3A, a low dielectric layer (interlayer insulating layer) 22 is formed on a substrate 21 by a CVD method, a spin coating method, or the like. A resist film 23 is formed on the low dielectric layer 22 and patterned. Using the patterned resist film 23 as a mask, the low dielectric layer 22 is selectively etched, and then the resist layer 23 is removed, thereby forming a wiring groove (trench) 24 as shown in FIG. Form. Next, a barrier metal 25 is deposited on the surface of the low dielectric layer 22 in which the wiring groove 24 is formed as described above, so that copper which is to be embedded in the wiring groove 24 is formed on the inner surface of the wiring groove 24. A barrier metal film is formed to improve adhesion to the dielectric layer 22 and prevent copper from diffusing into the low dielectric layer 22. Thereafter, as shown in FIG. 3C, copper is buried in the wiring groove 24 by electrolytic plating or the like to form a lower wiring layer 26.
[0023]
Next, at this point, the copper and the remaining barrier metal 25 adhering to the surface of the low dielectric layer 22 are removed by chemical polishing (CMP), and the surface of the low dielectric layer 22 is planarized. Then, a first low dielectric layer 27, a first etching stopper film 28, a second low dielectric layer 29, and a second etching stopper film 30 are sequentially stacked. Next, an antireflection film 31 is formed on the second etching stopper film 30. A resist is applied on the antireflection film 31 and patterned for forming a via hole, thereby forming a resist mask 32. Next, as shown in FIG. 3D, etching is performed using the resist mask 32 to form an antireflection film 31, a second etching stopper film 30, a second dielectric layer 29, and a first etching. A via hole 33 penetrating through the stopper layer 28 and the first low dielectric layer 27 and reaching the surface of the lower wiring layer 26 is formed. Subsequently, after the resist mask 32 and the anti-reflection film 31 are removed, as shown in FIG. 4E, an embedding material mainly composed of a spin-on-glass material is placed on the second etching stopper 30. The via hole 33 is filled with an embedding material by uniformly applying. As shown in FIG. 4F, an anti-reflection film 35 that can be processed by dry etching is laminated on the burying material layer 34 a formed on the second etching stopper 30, and is formed on the anti-reflection film 35. Then, a resist mask 36 having a pattern for forming a trench is formed. Next, using the resist mask 36 as a mask, the exposed portion of the antireflection film 35 not covered with the resist mask 36 is processed by dry etching. Subsequently, using the resist mask 36, as shown in FIG. 4G, the second etching stopper film 30 and the second low dielectric layer 29 are etched to form a trench 37 and a via hole. The embedding material 34b in 33 is removed. After that, the anti-reflection film 35 is removed, and the burying material layer 34a on the second etching stopper layer 30 and the burying material 34b in the via hole 33 removed by the etching contain hydrofluoric acid. It is completely removed by the stripper. Thereafter, copper is buried in the via hole 33 and the trench 37 to form a via wiring 38 and an upper wiring layer 39 at the same time, as shown in FIG. Thus, a multilayer wiring structure in which the lower wiring layer 26 and the upper wiring layer 39 are electrically connected by the via wiring 38 is realized.
[0024]
Although the above description has been directed to the case where the via hole is formed first, the trench may be formed first, and it is apparent that the method of the present invention can be applied to such a case. It is.
[0025]
In the method for forming a semiconductor multilayer wiring of the present invention having the above structure, a spin-on-glass material preferably used is
(A) Si (OR¹)_a(OR²)_b(OR³)_c(OR⁴)_d
(Where R¹, R², R³, And R⁴Are each independently an alkyl or phenyl group having 1 to 4 carbon atoms, a, b, c, and d are 0 ≦ a ≦ 4, 0 ≦ b ≦ 4, 0 ≦ c ≦ 4, 0 ≦ d ≦ 4 And an integer satisfying the condition of a + b + c + d = 4. ), A compound represented by
(B) R⁵Si (OR⁶)_e(OR⁷)_f(OR⁸)_g
(Wherein, R5 is a hydrogen atom or an alkyl group having 1 to 4 carbon atoms;⁶, R⁷, And R⁸Is an alkyl group or a phenyl group having 1 to 3 carbon atoms, e, f, and g are 0 ≦ e ≦ 3, 0 ≦ f ≦ 3, 0 ≦ g ≦ 3, and e + f + g = 3. Is an integer that satisfies A), and
(C) R⁹R¹⁰Si (OR¹¹)_h(OR¹²)_i
(Where R⁹And R¹⁰Is a hydrogen atom or an alkyl group having 1 to 4 carbon atoms, R¹¹And R¹²Is an alkyl or phenyl group having 1 to 3 carbon atoms, and h and i are integers satisfying 0 ≦ h ≦ 2, 0 ≦ i ≦ 2, and satisfying the condition of h + i = 2. ) Is obtained by hydrolyzing at least one compound selected from the compounds represented by the formula (1) in the presence of water by the action of an acid.
[0026]
Examples of the compound (A) include tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, tetrabutoxysilane, tetraphenyloxysilane, trimethoxymonoethoxysilane, dimethoxydiethoxysilane, triethoxymonomethoxysilane, and triethoxymonomethoxysilane. Methoxymonopropoxysilane, monomethoxytributoxysilane, monomethoxytriphenyloxysilane, dimethoxydipropoxysilane, tripropoxymonomethoxysilane, trimethoxymonobutoxysilane, dimethoxydibutoxysilane, triethoxymonopropoxysilane, diethoxydipropoxy Silane, tributoxy monopropoxy silane, dimethoxy monoethoxy monobutoxy silane, diethoxy monomethoxy monobutoxy silane, diethoxy Nopropoxy monobutoxy silane, dipropoxy monomethoxy monoethoxy silane, dipropoxy monomethoxy monobutoxy silane, dipropoxy monoethoxy monobutoxy silane, dibutoxy monomethoxy monoethoxy silane, dibutoxy monoethoxy monopropoxy silane, monomethoxy monoethoxy Examples thereof include tetraalkoxysilanes such as propoxymonobutoxysilane and oligomers thereof, and among them, tetramethoxysilane, tetraethoxysilane and oligomers thereof are preferable.
[0027]
Examples of the compound (B) include trimethoxysilane, triethoxysilane, tripropoxysilane, triphenyloxysilane, dimethoxymonoethoxysilane, diethoxymonomethoxysilane, dipropoxymonomethoxysilane, and dipropoxy. Monoethoxysilane, diphenyloxylmonomethoxysilane, diphenyloxymonoethoxysilane, diphenyloxymonopropoxysilane, methoxyethoxypropoxysilane, monopropoxydimethoxysilane, monopropoxydiethoxysilane, monobutoxydimethoxysilane, monophenyloxydiethoxysilane, Methyltrimethoxysilane, methyltriethoxysilane, methyltripropoxysilane, ethyltrimethoxysilane, ethyltripropoxysilane, L-triphenyloxysilane, propyltrimethoxysilane, propyltriethoxysilane, propyltriphenyloxysilane, butyltrimethoxysilane, butyltriethoxysilane, butyltripropoxysilane, butyltriphenyloxysilane, methylmonomethoxydiethoxysilane, ethyl Monomethoxydiethoxysilane, propylmonomethoxydiethoxysilane, butylmonomethoxydiethoxysilane, methylmonomethoxydipropoxysilane, methylmonomethoxydiphenyloxysilane, ethylmonomethoxydipropoxysilane, ethylmonomethoxydiphenyloxysilane, propylmono Methoxydipropoxysilane, propylmonomethoxydiphenyloxysilane, butylmonomethoxydipropoxysilane, butyl Nomethoxydiphenyloxysilane, methylmethoxyethoxypropoxysilane, propylmethoxyethoxypropoxysilane, butylmethoxyethoxypropoxysilane, methylmonomethoxymonoethoxymonobutoxysilane, ethylmonomethoxymonoethoxymonobutoxysilane, propylmonomethoxymonoethoxymonobutoxysilane And butylmonomethoxymonoethoxymonobutoxysilane, among which trimethoxysilane and triethoxysilane are preferred.
[0028]
Further, as the compound (C), for example, dimethoxysilane, diethoxysilane, dipropoxysilane, diphenyloxysilane, methoxyethoxysilane, methoxypropoxysilane, methoxyphenyloxysilane, ethoxypropoxysilane, ethoxyphenyloxysilane, Methyldimethoxysilane, methylmethoxyethoxysilane, methyldiethoxysilane, methylmethoxypropoxysilane, methylmethoxyphenyloxysilane, ethyldipropoxysilane, ethylmethoxypropoxysilane, ethyldiphenyloxysilane, propyldimethoxysilane, propylmethoxyethoxysilane, propyl Ethoxypropoxysilane, propyldiethoxysilane, propyldiphenyloxysilane, butyldimethoxysilane Butylmethoxyethoxysilane, butyldiethoxysilane, butylethoxypropoxysilane, butyldipropoxysilane, butylmethylphenyloxysilane, dimethyldimethoxysilane, dimethylmethoxyethoxysilane, dimethyldiethoxysilane, dimethyldiphenyloxysilane, dimethylethoxypropoxysilane, Dimethyldipropoxysilane, diethyldimethoxysilane, diethylmethoxypropoxysilane, diethyldiethoxypropoxysilane, dipropyldimethoxysilane, dipropyldiethoxysilane, dipropyldiphenyloxysilane, dibutyldimethoxysilane, dibutyldiethoxysilane, dibutyldipropoxysilane , Dibutylmethoxyphenyloxysilane, methylethyldimethoxysilane, methyl Tyldiethoxysilane, methylethyldipropoxysilane, methylethyldiphenyloxysilane, methylpropyldimethoxysilane, methylpropyldiethoxysilane, methylbutyldimethoxysilane, methylbutyldiethoxysilane, methylbutyldipropoxysilane, methylethylethoxypropoxysilane , Ethylpropyldimethoxysilane, ethylpropylmethoxyethoxysilane, dipropyldimethoxysilane, dipropylmethoxyethoxysilane, propylbutyldimethoxysilane, propylbutyldiethoxysilane, dibutylmethoxypropoxysilane, butylethoxypropoxysilane, and the like. Dimethoxysilane, diethoxysilane and methyldimethoxysilane are preferred.
[0029]
As described above, in the method of the present invention, by using an alkoxysilane-based embedding material, when forming a via or a trench by dry etching (using a fluorocarbon-based gas), it is the same as or similar to the low dielectric layer. The buried material layer can be removed by etching faster than that, and the process can be simplified. Further, even when the alkoxysilane-based material remains inside the trench or via after completion of the dry etching, it can be easily removed using a stripping solution containing hydrofluoric acid. On the other hand, when a conventional embedding material in which an organic material or an organic material is mixed with an alkoxysilane-based material is used, it may be difficult to remove the organic material remaining in the via hole. Specifically, the organic material is O₂Although it is removed by plasma ashing, there is a possibility that this removal processing may damage the low dielectric layer.
[0030]
Further, in the method of the present invention, the materials used for the low dielectric layer include the following materials. Among them, when a Si-based material having at least a methyl group is used, the spin-on glass material has the general formula (B) When the total composition ratio of the component represented by the formula (C) and the component represented by the formula (C) is 50% or more on a weight basis, the buried material layer can be removed by etching at a speed equal to or faster than that of the low dielectric layer. This is preferred.
[0031]
When the low dielectric layer is a hydroxysilsesquioxane-based material, R⁵Is a hydrogen atom, the compositional ratio of the component represented by the general formula (B) is set to 50% or more on a weight basis, or a polyalkylene glycol-based polymer is blended therein, as described above. Is preferred for the following reasons.
[0032]
In the method of the present invention, the components (A), (B) and (C) are dissolved in an organic solvent to prepare a coating solution for forming an embedding material layer. Monohydric alcohols such as alcohol, ethyl alcohol, propyl alcohol, and butyl alcohol; polyhydric alcohols such as ethylene glycol, diethylene glycol, propylene glycol, glycerin, trimethylolpropane, and hexanetriol; ethylene glycol monomethyl ether; ethylene glycol monoethyl ether , Ethylene glycol monobutyl ether, diethylene glycol monomethyl ether, diethylene glycol monoethyl ether, diethylene glycol monopropyl ether, propylene glycol monomethyl ether, propylene glycol Monoethers of polyhydric alcohols such as monoethyl ether, propylene glycol monopropyl ether and propylene glycol monobutyl ether; esters such as methyl acetate, ethyl acetate and butyl acetate; acetone, methyl ethyl ketone and methyl isoamyl ketone Ketones, polyhydric alcohol ethers such as ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol dipropyl ether, ethylene glycol dibutyl ether, propylene glycol dimethyl ether, propylene glycol diethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether Alkyl etherified Such as Le call ether. Among them, polyhydric alcohol ethers obtained by alkylating polyhydric alcohol ethers, particularly alkylene glycol dialkyl ethers, are preferred.
[0033]
The above-mentioned organic solvents may be used alone or in combination of two or more, but the amount of use is preferably in the range of 10 to 30 mol per 1 mol of the total of the silane compound. The coating solution thus prepared can be used as it is, but may be used after being diluted with a diluting solvent in order to adjust the solid content concentration in the coating solution. The organic solvent can be used as the diluting solvent. In the preparation of the coating solution, when the amount of the alcohol solvent used or the alcohol produced by the hydrolysis reaction of the silane compound exceeds 15% by weight based on the total amount of the coating solution, the H-Si group reacts with the alcohol. As a result, an RO-Si group is easily generated, the coating solution is gelled, storage stability is deteriorated, and cracks are generated. If the alcohol content is excessive, it is removed by distillation under reduced pressure. The distillation under reduced pressure is preferably performed at a degree of vacuum of 30 to 300 mmHg, preferably 50 to 200 mmHg, and a temperature of 20 to 50 ° C. for 2 to 6 hours.
[0034]
The spin-on-glass material used in the present invention does not substantially contain a high light-absorbing dye. This is because the addition of such a dye causes intermixing and lowers storage stability, which is not preferable.
[0035]
As the conductor material for the wiring layer, Cu is preferable, but other than Cu, Cu alloy, Al, Al alloy or the like may be used. The buried wiring layer is formed by an electrolytic plating method or the like, but is not particularly limited.
[0036]
Examples of the material that can be used for the low dielectric layer include carbon-doped oxide (SiOC) -based, methylsilsesquioxane (MSQ) -based, and hydroxysilsesquioxane (HSQ) -based low dielectric materials. Specific examples of the carbon-doped oxide-based low dielectric material include Black Diamond (trade name) manufactured by Applied Materials, Coral (trade name) manufactured by Novellus Systems, and Aurora (trade name) manufactured by ASM Japan. And the like. As the methylsilsesquioxane-based low dielectric material, specifically, "OCD T-9", "OCD T-11", "OCL T-31", manufactured by Tokyo Ohka Kogyo Co., Ltd. Examples include materials marketed under the trade names “OCL T-37” and “OCL T-39”. Further, the hydroxysilsesquioxane-based low dielectric material is specifically marketed under the trade names of “OCD T-12” and “OCL T-32” manufactured by Tokyo Ohka Kogyo Co., Ltd. Materials and the like.
[0037]
In the method of the present invention, the low dielectric layer may be formed on the wiring layer or on a barrier film (SiN, SiC, SiCN, Ta, TaN, etc.) formed on the wiring layer. The firing temperature of the low dielectric layer is usually performed by hard baking at 350 ° C. or higher.
[0038]
The photoresist layer is made of a mercury lamp i-line, g-line, KrF excimer laser, ArF excimer laser, F₂A photoresist material commonly used for an excimer laser and an electron beam (EB) can be used by a lithography method.
[0039]
In the method of the present invention, the antireflection film that can be removed by the dry etching is a conventional CF.₄System etching gas, N₂+ O₂It is possible to use a commercially available material that can be removed by a system etching gas. This antireflection film can prevent the photoresist pattern from deteriorating due to the reflection of the exposure light from the substrate. Commercially available anti-reflective coating materials include trade names such as “SWK-EX1D55”, “SWK-EX3”, “SWK-EX4”, “SWK-T5D60”, and “SWK-T7” manufactured by Tokyo Ohka Kogyo Co., Ltd. Commercially available materials, materials available under the trade names such as “DUV-42”, “DUV-44”, “ARC-28”, and “ARC-29” manufactured by Brewer science, and products manufactured by Shipley And materials commercially available under trade names such as “AR-3” and “AR-19”.
[0040]
When the above-mentioned anti-reflection film is used, the photoresist film and the anti-reflection film are removed after the second etching space is formed and the embedding material is removed.
[0041]
These antireflection films are usually removed by oxygen plasma ashing, but in this case, there is a possibility that the low dielectric layer may be damaged, and it is not preferable to employ the ashing. Therefore, in the present invention, the removal processing of the anti-reflection film is realized by removing the remaining embedded material under the anti-reflection film and performing lift-off.
[0042]
In particular, when a hydroxysilsesquioxane-based material is used as the low dielectric layer, the surface of the low dielectric layer is irradiated with plasma generated from an inert gas such as He or Ar. Reform. By this surface modification treatment, the remaining antireflection film and the photoresist pattern can be removed by oxygen plasma treatment without causing damage to the low dielectric layer.
[0043]
Further, as a material constituting the antireflection film, the following resin composition can be used in addition to the conventional composition. That is, a resin composition containing at least a resin component having at least a substituent from which a terminal group is eliminated by application of a predetermined energy to generate a sulfonic acid residue, and a solvent can be used.
[0044]
The resin component has at least the following general formula (1)
Embedded image

(In the formula, n represents an integer of 1 or more, X is a linear or branched alkyl chain having 1 to 10 carbon atoms, an aromatic or alicyclic alkyl chain, an alkyl ester chain, and Y is A substituent that generates a sulfonic acid residue upon application of predetermined energy.)
It has a repeating unit represented by these.
[0045]
As the predetermined energy applied to generate the sulfonic acid residue, for example, a sulfonic acid residue can be generated by heat treatment at 80 ° C. or more. Such application of the predetermined energy is further promoted by the concerted action of heating and alkali in the peeling treatment.
[0046]
As the substituent Y in the general formula (1), -SO₃R₁Or -SO₃ ⁻R₂ ⁺(Where R₁And R₂Is preferably a monovalent organic group).
[0047]
The organic group R₁Is preferably one selected from an alkyl group having 1 to 10 carbon atoms or a hydroxyalkyl group.
[0048]
Further, the organic group R₂Is preferably at least one selected from alkanolamines and alkylamines.
[0049]
Further, as a resin component having at least a substituent that generates a sulfonic acid residue by elimination of a terminal group by application of the predetermined energy, any of the resin components described above, acrylic acid or methacrylic acid or A copolymer with a derivative of the above or a mixed resin may be used.
[0050]
When the copolymer or the mixed resin is used as the resin component, the polymerization ratio or the mixing ratio is not particularly limited as long as the polymerization ratio or the mixing ratio is within a range that is resistant to the resist developing solution and can maintain the effect of being removable by the resist stripping solution. Not done.
[0051]
Furthermore, as a resin component having at least a substituent that generates a sulfonic acid residue by removing a terminal group by applying the predetermined energy,
For a copolymer or mixed resin of any one of the above resin components and acrylic acid or methacrylic acid or a derivative thereof, the following general formula (2)
Embedded image

(Wherein, n represents an integer of 1 or more;₃Is at least one selected from a hydrogen atom, a fluorine atom, a hydroxyl group, a carboxyl group, a hydroxyalkyl group having 1 to 5 carbon atoms and an alkoxyalkyl group having 1 to 5 carbon atoms, and Z represents 1 carbon atom. And 10 to 10 linear or branched alkyl chains, aromatic or alicyclic alkyl chains, and alkyl ester chains. )
A resin component composed of a copolymer obtained by copolymerizing a repeating unit represented by formula (1) or a mixed resin obtained by mixing a resin compound having a repeating unit represented by formula (2) may be used.
[0052]
If a copolymer is prepared using the derivative of the general formula (2), and the copolymer is used as a resin component to constitute an antireflection film material, the unit of the resin component contains anthracene. Is preferred because of its high absorption characteristics especially in lithography using a KrF excimer laser.
[0053]
The solvent used for the anti-reflection film forming material can be used without any particular limitation as long as it is used for a conventional lower layer film forming material.
[0054]
Forming an antireflection film from the above-mentioned “resin composition containing at least a resin component having at least a substituent from which a terminal group is eliminated by application of predetermined energy to generate a sulfonic acid residue, and a solvent” Then, after forming the second etching space and removing the embedding material, in the step of removing the photoresist film and the antireflection film, the photoresist film and the antireflection film can be easily removed with a photoresist release agent used in a normal lithography process. Becomes possible. As a result, O₂The risk of damage to the low dielectric layer due to the anti-reflection film removal processing using plasma ashing can be avoided. Further, the rework of collecting the semiconductor substrate performed when the formation of the photoresist pattern fails is facilitated.
[0055]
Further, as another composition for forming the antireflection film, a resin composition containing a mixture of polytitanoxane and polysiloxane or a copolymer thereof can be used. This resin composition comprises titanoxane: R_mTi (OR)_(4-m)And a siloxane: R_nSi (OR)_(4-n)The main component is a mixture of reactants obtained by condensing the above or a reactant obtained by condensing these components together. If necessary, an activator, a crosslinking accelerator and the like may be contained. In the above formula, R is mainly an alkyl group, which may be the same or different, and m and n are integers of 0 to 3. The Ti content in the main component is 0.1 to 99.9%, preferably 5 to 70%. As a solvent for the resin composition, a resin capable of dissolving the main component resin, applying it on a substrate, drying, and then performing a heat treatment, as long as it can form a film to the extent that it does not intermix with the resist, Anything can be used without particular limitation.
[0056]
If an antireflection film was formed using the aforementioned “resin composition containing a mixture of polytitanoxane and polysiloxane or a copolymer thereof”, a second etching space was formed, and the embedded material was removed. Thereafter, in a step of removing the photoresist film and the anti-reflection film, the photoresist film and the antireflection film can be easily removed by a photoresist stripping agent used in a usual lithography process. As a result, O₂The risk of damage to the low dielectric layer due to the anti-reflection film removal processing using plasma ashing can be avoided. Further, the rework of collecting the semiconductor substrate performed when the formation of the photoresist pattern fails is facilitated.
[0057]
The following effects can be obtained as the effects of the method of the present invention as described above.
(I) At the time of forming a trench / via in a dual damascene process, it becomes possible to etch away the filling material in the via / trench simultaneously with or faster than the low dielectric layer.
(Ii) The embedding material remaining in the via hole after the etching removal can be easily removed by a stripping solution containing hydrofluoric acid.
(Iii) In the conventional example in which an organic film is embedded,₂Although removal by plasma ashing was necessary, this step can be omitted, so that damage to the low dielectric layer (Si—R bond → Si—OH bond) and fluctuation of the dielectric constant (k) are eliminated. Becomes possible.
(Iv) Since an embedding material which does not substantially contain an organic additive (high-absorbing component, dye, etc. in the prior art) is used, deterioration of the spin-on-glass material over time can be prevented, thereby embedding. The storage stability of the material solution and the stability of the membrane can be improved, and the degree of freedom in process control can be increased. In addition, it is possible to suppress the occurrence of intermixing between layers with the upper layer film.
(V) In the process of providing a photoresist layer directly above the spin-on-glass material layer, a lot of variation among lots occurred in matching evaluation with a resist film. Matching with the layer becomes easy.
[0058]
【Example】
Hereinafter, the present invention will be described in more detail with reference to examples. The following examples are merely examples for suitably describing the present invention, and do not limit the present invention in any way.
[0059]
(Example 1)
A SiN layer, a first low-dielectric layer made of hydroxysilsesquioxane-based low-dielectric material (trade name: OCD T-12, manufactured by Tokyo Ohka Kogyo Co., Ltd.) on a substrate on which copper wiring is formed; Four layers of a SiN layer and a second low dielectric layer made of a hydroxysilsesquioxane-based low dielectric material (trade name: OCD T-12 manufactured by Tokyo Ohka Kogyo Co., Ltd.) are sequentially laminated. , 6000 ° interlayer insulating layer was formed.
[0060]
On the interlayer insulating layer, a first anti-reflection film made of ARC-29 (manufactured by Brewer Science) having a film thickness of 770 ° is formed, and a first photoresist layer having a film thickness of 4000 ° is formed thereon, and exposed. And development processing. The first photoresist layer was formed using a resist composition (trade name: TArF-7a21, manufactured by Tokyo Ohka Kogyo Co., Ltd.) containing an acrylic polymer as a main component.
[0061]
Using the obtained photoresist pattern as a mask, the interlayer insulating layer was etched to form a via hole having a diameter of 200 nm.
[0062]
An embedding material prepared in a step different from the laminating and etching steps is uniformly applied to the via hole by spin coating to a thickness of 4000 ° on the interlayer insulating layer to fill the via hole. Embedded with embedded material.
[0063]
The embedding material was prepared as follows. That is, 236.58 g (1.44 mol) of triethoxysilane, 108.72 g (0.72 mol) of tetramethoxysilane, 2117.71 g (20.4 mol) of propylene glycol dimethyl ether, 129.6 g (7.2 mol) of water ) And 432 μL of concentrated nitric acid to obtain a solution. This solution was distilled under reduced pressure at 150 mmHg and 40 ° C. for 4 hours to prepare an embedding material having a solid content of 9.0% by weight and an alcohol concentration of 3.8% by weight.
[0064]
As described above, the second antireflection film having a thickness of 770 ° made of ARC-29 (manufactured by Brewer Science) is formed on the embedding material layer uniformly applied to the substrate surface to embed the embedding material in the via hole. Was formed thereon, and a second photoresist layer having a thickness of 4000 ° was formed thereon, followed by exposure and development. The second photoresist layer was formed from the same composition as the first photoresist layer.
[0065]
Using the obtained photoresist pattern as a mask, N₂+0₂The exposed portion of the antireflection film was removed using an etching gas comprising a mixed gas of
[0066]
Subsequently, using the photoresist pattern as a mask, CF₄+ CHF₃The main portion of the interlayer insulating layer was removed using an etching gas composed of a mixed gas of the above to form a trench. The embedding material remaining in the via hole even after this etching treatment was removed using 0.1% by mass of buffered hydrofluoric acid.
[0067]
As a result, the process was simplified and a dual damascene structure including via holes and trenches was formed without damaging the low dielectric layer and changing the dielectric constant.
[0068]
(Examples 2 to 5)
A dual damascene structure was formed in the same manner as in Example 1 except that the first antireflection film and the second antireflection film in Example 1 were formed from the following four types of resin compositions. .
[0069]
The following resin compositions (A), (B), (C) and (D) were prepared as antireflection film forming materials.
[0070]
(A) A resin composition in which a resin component composed of ethyl p-styrenesulfonate is dissolved in a solvent composed of γ-butyrolactone / ethyl lactate (2: 8) to adjust the solid content to 6 wt%.
[0071]
(B) A resin component composed of ethyl p-styrenesulfonate: hydroxyethyl acrylate (= 5: 5) and Cymel 1172 (tetramethylol glycoluril manufactured by Mitsui Cyanamid Co., Ltd.) in an amount equivalent to 20% by weight of the resin component, A resin composition dissolved in a solvent composed of ethyl lactate and having a solid content adjusted to 6 wt%.
[0072]
(C) A resin component composed of ethyl p-styrenesulfonate: 9-hydroxyanthracenyl acrylate (= 5: 5) is dissolved in a solvent composed of γ-butyrolactone / ethyl lactate (2: 8), and the solid content concentration is dissolved. Was adjusted to 6 wt%.
[0073]
(D) Ethyl p-styrenesulfonate: hydroxyethyl acrylate: 9-hydroxyanthracenyl acrylate (= 4: 3: 3) and Cymel 1172 (Mitsui Cyanamid Co., Ltd.) in an amount equivalent to 20% by weight of the resin. Tetramethylol glycoluril) and Megafac R08 (a fluorosurfactant manufactured by Dai Nippon Ink Co., Ltd.) in an amount equivalent to 1000 ppm of the above two solid contents were dissolved in a solvent composed of ethyl lactate, and the solid content concentration was changed. Was adjusted to 6 wt%.
[0074]
These resin compositions (A), (B), (C), and (D) were used as materials for forming the first and second antireflection films in Example 1. A wiring structure consisting of trenches and via holes was formed in the same manner as in Example 1 except that these resin compositions were used as materials for forming an anti-reflection film, and the thickness of each anti-reflection film was set to 2000 mm. The heating conditions for applying each resin composition to obtain an antireflection film were 200 ° C. for 90 seconds.
[0075]
As a result, when any of the resin compositions (A), (B), (C) and (D) is used, the process is simplified without damaging the low dielectric layer and changing the dielectric constant, and the via hole and A dual damascene structure including the trench was formed.
[0076]
(Example 6)
A dual damascene structure was formed in the same manner as in Example 1 except that the first antireflection film and the second antireflection film in Example 1 were formed from the following resin compositions.
[0077]
100 g of tetraisopropoxytitanium was dissolved in 338 g of ethanol, and then 121 g of acetic acid and 357 g of acetylacetone were added to obtain a mixture. This mixture was stirred for 4 hours, and then allowed to stand for 16 hours to obtain a 10% solution of polytitanoxane.
[0078]
Next, 113 g of methanol, 312 g of acetylacetone, and 324 g of acetic acid were added to 324 g of tetraethoxysilane to obtain a mixture. The mixture was stirred for 6 hours and then allowed to stand for 16 hours to obtain a 9% solution of polysiloxane.
[0079]
The polytitanoxane solution and the polysiloxane solution were mixed at a ratio of 1: 1 and a resin mixture solution diluted with butyl cellosolve was used to form the first antireflection film and the second antireflection film in Example 1. Material. A wiring structure consisting of trenches and via holes was formed in the same manner as in Example 1 except that this resin mixed solution was used as a material for forming an antireflection film, and that the thickness of each antireflection film was 1240 °. Note that the heat treatment for applying each resin composition to obtain an antireflection film was performed by first heating at 90 ° C. for 90 seconds, and then heating at 220 ° C. for 600 seconds.
[0080]
As a result, even when an anti-reflection film is formed using this resin mixture, a dual damascene structure including via holes and trenches is formed without simplification of the process without damaging the low dielectric layer and changing the dielectric constant. We were able to.
[0081]
(Comparative Example 1)
A dual damascene structure was formed by exactly the same composition and operation except that the composition for forming the embedding material used in Example 1 was composed of a 30% by weight solution of methoxymethylated benzoguanamine in propylene glycol monomethyl ether acetate. .
[0082]
As a result, the embedding material becomes “CF” for forming the trench.₄+ CHF₃By dry etching with an etching gas consisting of a mixed gas of the above, the etching material could hardly be removed. Further, it could not be removed even by a subsequent treatment using a stripping cleaning solution.
[0083]
Therefore, in order to remove the embedded material that cannot be removed,₂+ O₂By performing a dry etching process using an etching gas composed of a mixed gas of the above, the embedding material could be removed, but the surface of the low dielectric layer was found to be damaged by a scanning electron microscope (SEM). Observation revealed.
[0084]
【The invention's effect】
As described above, the method for forming a semiconductor multilayer wiring according to the present invention is characterized in that the lower wiring layer formed on the semiconductor substrate and the upper wiring layer formed thereon with the interlayer A method of forming a semiconductor multilayer wiring connected by via wiring vertically penetrating layers, wherein an interlayer insulating layer forming step of laminating the interlayer insulating layer made of at least a low dielectric layer on the lower wiring layer; Forming a photoresist layer on the insulating layer, performing patterning exposure, and developing to form a photoresist pattern; performing etching using the photoresist pattern as a mask to form a first etching space in the interlayer insulating layer; By forming a space forming step and applying an embedding material containing at least a spin-on-glass material as a main component on the interlayer insulating layer, An embedding step of embedding the embedding material in one etching space, an antireflection film forming step of forming an antireflection film that can be processed by dry etching on the embedding material layer formed on the interlayer insulating layer, Forming a photoresist layer on the anti-reflection film, irradiating the photoresist layer with pattern light, developing with an alkali developing solution, a photoresist pattern forming step of forming a photoresist pattern, and the anti-reflection film using the photoresist pattern as a mask An anti-reflection film processing step of processing the exposed portion of the substrate by dry etching, and etching using the photoresist pattern as a mask to remove the interlayer insulating layer above the first etching space into a predetermined pattern, At the same time as forming a second etching space communicating with the etching space, Forming a second etching space and removing a filling material in the etching space, filling the first etching space and the second etching space with a conductive material simultaneously, and connecting the via wiring and the upper wiring layer to each other; And simultaneously forming a wiring.
[0085]
That is, according to the method of the present invention, in the method of forming a semiconductor multilayer wiring by the dual damascene process, the first etching space is filled to protect the lower wiring layer from exposure light for forming a photoresist pattern for forming the second etching space. As the material to be used, an embedding material mainly composed of a spin-on glass material that can be easily removed by a stripping solution that does not damage the interlayer insulating layer is used, and the embedding material layer is dry-etched on the embedding material layer. It is characterized in that a removable antireflection film is formed.
[0086]
Therefore, according to the method of the present invention, the following advantages can be obtained.
(I) When the second etching space is formed in the dual damascene process, the filling material in the first etching space can be removed by etching simultaneously with the low dielectric layer or faster than the low dielectric layer. .
(Ii) The embedding material remaining in the first etching space after the etching removal can be easily removed by a photoresist stripping solution used in ordinary lithography.
(Iii) In the conventional example in which an organic film is embedded,₂Although removal by plasma ashing was necessary, this step can be omitted, so that damage to the low dielectric layer (Si—R bond → Si—OH bond) and fluctuation of the dielectric constant (k) are eliminated. Becomes possible.
(Iv) Since an embedding material which does not substantially contain an organic additive (high-absorbing component, dye, etc. in the prior art) is used, deterioration of the spin-on-glass material over time can be prevented, thereby embedding. The storage stability of the material solution and the stability of the membrane can be improved, and the degree of freedom in process control can be increased. Further, occurrence of intermixing can be prevented.
(V) In the process of providing a photoresist layer directly above the spin-on-glass material layer, a lot of variation among lots occurred in matching evaluation with a resist film. Matching with the layer becomes easy.
[Brief description of the drawings]
FIGS. 1A to 1D are diagrams illustrating the first half of a conventional semiconductor multilayer wiring forming method using a dual damascene process.
2 (e) to 2 (h) are diagrams illustrating the latter half of a conventional method of forming a semiconductor multilayer wiring using a dual damascene process.
FIGS. 3A to 3D are diagrams illustrating the first half of a method of forming a semiconductor multilayer wiring according to the present invention using a dual damascene process.
4 (e) to 4 (h) are diagrams illustrating the latter half of the method of forming a semiconductor multilayer wiring according to the present invention using a dual damascene process.
[Explanation of symbols]
21 Substrate
22 Low dielectric layer
23 Resist film
24 Wiring groove (trench)
25 Barrier metal
26 Lower wiring layer
27 First Low Dielectric Layer
28 First Etching Stopper Film
29 Second low dielectric layer
30 Second etching stopper film
31 Anti-reflective coating
32 resist mask
33 Beer Hall
34a embedded material layer
34b Embedded material in via hole
35 Anti-reflective coating removable by dry etching
36 Resist mask
37 trench
38 Via wiring
39 Upper wiring layer

Claims (9)

A semiconductor multilayer wiring in which a lower wiring layer formed on a semiconductor substrate and an upper wiring layer formed thereon via an interlayer insulating layer are connected by via wiring vertically penetrating the interlayer insulating layer. In the forming method,
An interlayer insulating layer forming step of laminating the interlayer insulating layer comprising at least a low dielectric layer on the lower wiring layer,
A photoresist layer is formed on the interlayer insulating layer, and after pattern exposure, a developing process is performed to form a photoresist pattern, and etching is performed using the photoresist pattern as a mask to form a first etching space in the interlayer insulating layer. 1 etching space forming step;
An embedding step of embedding the embedding material in the first etching space by applying an embedding material containing at least a spin-on-glass material as a main component on the interlayer insulating layer;
An anti-reflection film forming step of forming an anti-reflection film that can be processed by dry etching on the burying material layer formed on the interlayer insulating layer,
Forming a photoresist layer on the antireflection film, irradiating the photoresist layer with pattern light, developing with an alkali developing solution, a photoresist pattern forming step of forming a photoresist pattern,
An anti-reflection film processing step of processing the exposed portion of the anti-reflection film by dry etching using the photoresist pattern as a mask,
Etching is performed using the photoresist pattern as a mask to remove the interlayer insulating layer above the first etching space into a predetermined pattern to form a second etching space communicating with the first etching space, and simultaneously forming the second etching space. A second etching space forming and burying material removing step of removing the burying material in the one etching space;
A wiring batch forming step of simultaneously filling the first etching space and the second etching space with a conductive material and simultaneously forming the via wiring and the upper wiring layer;
A method of forming a semiconductor multilayer wiring, comprising: The spin-on-glass material is
(A) Si (OR ¹ ) _a (OR ² ) _b (OR ³ ) _c (OR ⁴ ) _d
(Wherein, R ¹ , R ² , R ³ , and R ⁴ are each independently an alkyl group having 1 to 4 carbon atoms or a phenyl group, a, b, c, and d are 0 ≦ a ≦ 4,0 ≦ b ≦ 4, 0 ≦ c ≦ 4, 0 ≦ d ≦ 4, and an integer satisfying the condition of a + b + c + d = 4.)
(B) R ⁵ Si (OR ⁶ ) _e (OR ⁷ ) _f (OR ⁸ ) _g
(Wherein, R ⁵ is a hydrogen atom or an alkyl group having 1 to 4 carbon atoms, R ⁶ , R ⁷ , and R ⁸ are an alkyl group or a phenyl group each having 1 to 3 carbon atoms, and e, f, and g are And an integer satisfying 0 ≦ e ≦ 3, 0 ≦ f ≦ 3, 0 ≦ g ≦ 3 and satisfying the condition of e + f + g = 3), and (C) R ⁹ R ¹⁰ Si (OR ¹¹ ) _h (OR ¹² ) _i
(Wherein, R ⁹ and R ¹⁰ are a hydrogen atom or an alkyl group having 1 to 4 carbon atoms, R ¹¹ and R ¹² are an alkyl group or a phenyl group each having 1 to 3 carbon atoms, and h and i are 0 ≦ h .Ltoreq.2, 0.ltoreq.i.ltoreq.2, and an integer satisfying the condition of h + i = 2.) Wherein at least one compound selected from the compounds represented by the following formulas is hydrolyzed. The method for forming a semiconductor multilayer wiring according to claim 1. The low dielectric layer is formed from a Si-based material having at least a methyl group, and the spin-on-glass material is prepared so that the total content ratio of the compound (B) and the compound (C) is 50% or more. 3. The method for forming a semiconductor multilayer wiring according to claim 2, wherein: A hydroxysilsesquioxane-based material is used as the Si-based material, and the spin-on-glass material is prepared such that the content ratio of the compound (B) in which R ⁵ is a hydrogen atom is 50% or more. The method for forming a semiconductor multilayer wiring according to claim 3. The spin-on-glass material is dissolved by an organic solvent, and the organic solvent is a polyhydric alcohol ether obtained by alkyl etherifying a hydroxyl group of a polyhydric alcohol. The method for forming a semiconductor multilayer wiring according to the above. The antireflection film is composed of a resin composition containing at least a resin component having a substituent at which a terminal group is eliminated by application of predetermined energy to generate a sulfonic acid residue, and a solvent. The method for forming a semiconductor multilayer wiring according to claim 1, wherein: The resin component has at least the following general formula (1)

(In the formula, n represents an integer of 1 or more, X is a linear or branched alkyl chain having 1 to 10 carbon atoms, an aromatic or alicyclic alkyl chain, an alkyl ester chain, and Y is A substituent that generates a sulfonic acid residue upon application of predetermined energy.)
7. The method according to claim 6, comprising a repeating unit represented by the following formula: The semiconductor multilayer according to any one of claims 1 to 5, wherein the anti-reflection film is formed from a resin composition containing a mixture of polytitanoxane and polysiloxane or a copolymer thereof. Wiring formation method. 9. The method according to claim 1, further comprising, after the second etching space forming step, an embedding material removing step of removing an embedding material remaining in the first etching space with a stripping solution. 13. The method for forming a semiconductor multilayer wiring according to any one of the above.

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