JP2004164753A - Memory device and control method of operation of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set many items by a mode register. <P>SOLUTION: A clock signal from the outside is supplied to a clock buffer 15 and a system clock is formed. A command signal from the outside is decoded by a command decoder 16, supplied to a control signal generator 17, and a formed control signal is supplied to a row decoder 12, a column decoder 13, and a sense amplifier 14. An address signal from the outside is supplied to the row decoder 12 and the column decoder 13 through an address buffer 18. Simultaneously, a plurality of mode registers 21 to 24 are provided, setting information is supplied to them through the address buffer 18. In this case, 10 pins A0 to A9 are provided at an input of an address signal, values of the pins A9, A8 out of them are used as a discrimination code, the mode registers 21 to 24 are allotted to each of values (0,0), (0,1), (1,0), (1,1). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory device suitable for use in a synchronous or asynchronous DRAM (Dynamic Random Access Memory) and an operation control method of the memory device. More specifically, the setting range of the operation mode is expanded by simple means so that the setting in the test mode, the adjustment mode, and the like can be easily performed.
[0002]
[Prior art]
In recent years, the demand for faster data transfer, such as writing / reading of data between external devices and storage devices, has increased due to the speeding up of the system and the speeding up of the CPU. 2. Description of the Related Art A type DRAM (Synchronous DRAM, hereinafter, SDRAM) has been proposed. That is, the SDRAM is a DRAM that can transfer data in synchronization with a clock supplied from the outside.
[0003]
On the other hand, in a DRAM among semiconductor memory devices, a predetermined time is required from a read CAS (Column Address Strobe) signal to an output of the DRAM. This time is a time called CAS latency. That is, in the DRAM, an output cannot be obtained unless CAS latency elapses after the CAS signal is applied.
[0004]
The CAS latency time usually requires 2 to 3 clock cycles in the case of SDRAM. Therefore, in the SDRAM, it is necessary to read out the output at an appropriate timing after giving the CAS signal in consideration of the CAS latency in the controller for controlling the internal cell array.
[0005]
For this reason, in the conventional method, not only is the controller or user controlling the cell array having to consider the CAS latency specification of the SDRAM one by one, but also the bus between the controller and the command input pin of the SDRAM is not only troublesome. There is a problem that the use efficiency is reduced.
[0006]
In order to solve these problems, standardization of the CAS latency function has been studied in JEDEC (Joint Electronic Device Engineering Council), which is the International Electronic Standards Organization. That is, the JEDEC standard requires that the number of clocks for the CAS latency can be set in advance through an extended mode register set (hereinafter referred to as EMRS) of an SDRAM.
[0007]
Therefore, in a conventional SDRAM, for example, a configuration as shown in FIG. 7 is used. 7, an external clock signal is supplied to a clock buffer 75, and an internal clock formed by the clock buffer 75 is supplied to each unit. A substrate bias voltage generation circuit 82 is provided inside.
[0008]
Further, an external command signal is supplied to a command decoder 76, and the command decoded by the command decoder 76 is supplied to a control signal generator 77. The control signal formed here is supplied to a row decoder 72, a column decoder 73, a sense It is supplied to the amplifier 74. An external address signal is supplied to the row decoder 72 and the column decoder 73 through the address buffer 78.
[0009]
Then, data is exchanged between the sense amplifier 74 and the outside via the data buffer 79. That is, data is written / read via the data buffer 79 to / from the address of the cell array 71 designated by the externally supplied address signal in accordance with the externally supplied command signal. Further, a refresh counter 80 is provided to perform a refresh operation.
[0010]
At the same time, in this memory device, a mode register 81 is provided, and setting information is supplied to the mode register 81 through an address buffer 78. That is, the writing of the setting information to the mode register 81 is performed, for example, as shown in FIG.
[0011]
8, a mode register set command (MRS) is supplied as an external command signal at an arbitrary timing. At this time, a value (KEY) supplied to the input of an external address signal is stored in mode register 81. Written. In this case, the contents of the setting information to be written are as shown in FIG. 9, for example.
[0012]
In FIG. 9, 10 pins A0 to A9 are provided for input of an address signal from the outside. Then, a burst length is set to the pins A0 to A2, and 1, 2, 4, 8, and a full range are set as the number of input / output data when writing / reading is performed continuously, for example. A burst type is set to the pin A3. For example, as a method of changing a burst address when the burst length is 4 or more, one of sequential and interleave is set.
[0013]
Further, CAS latency is set for the pins A4 to A6. As described above, the CAS latency sets, for example, the number of clock cycles from the read command to the actual output of data, and can be set to 1, 2, and 3. As a result, the operating frequency can be improved. All the pins A7 to A9 have a value of 0.
[0014]
That is, in the above-mentioned conventional SDRAM, for example, before the use of the memory device is started, the value (KEY) for performing the above setting is supplied to the input pins A0 to A9, so that the value (KEY) is written in the mode register 81. Is set. The information on the burst length, burst type, and CAS latency set in this way is supplied to the control signal generator 77 to perform control such as writing / reading.
[0015]
Also, in an asynchronous DRAM, a mode register is provided to perform various settings. FIG. 10 shows the configuration of such a DRAM. In FIG. 10, the same parts as those in the configuration of the SDRAM in FIG.
[0016]
That is, in FIG. 10, the clock buffer 75 and the command decoder 76 are removed from the configuration of the SDRAM, and the respective components are directly controlled by the control signal generator 77 to which external RAS, CAS, WE, and OE signals are supplied. Things.
[0017]
In the DRAM having such a configuration, for example, as shown in FIG. 11, the WE, CAS, and RAS signals are supplied while the value (KEY) to be set is supplied to the input pins A0 to A9 of the address signal. By sequentially activating, a value (KEY) is written in the mode register 81, and the written setting information is supplied to the control signal generator 77, and control according to the setting is performed.
[0018]
However, in the conventional technology described above, for example, in the case of an SDRAM, only information on the burst length, burst type, and CAS latency can be set. On the other hand, in recent years, it has been desired to provide various settings also in the SDRAM and the DRAM, and in particular, it is required to make settings in the test mode and the adjustment mode.
[0019]
Therefore, in the related art, for example, a test mode or an adjustment mode is provided as a command, and when these modes are commanded, the contents of the mode register 81 are adjusted to those modes. However, in this method, a new command is provided, and there is a possibility that other commands may have to be reduced.
[0020]
Note that Patent Document 1 discloses a technique in which control is performed by a command in a semiconductor memory device.
Patent Literature 2 discloses a technique of executing a test mode by providing a command for the test mode.
Patent Literature 3 discloses a technique for performing processing by setting a CAS latency in a mode register.
[0021]
[Patent Document 1]
JP-A-2002-269981 [Patent Document 2]
JP 2002-056695 A [Patent Document 3]
JP 2002-133866 A
[Problems to be solved by the invention]
That is, in the conventional technology, the items that can be set in the SDRAM or the mode register of the DRAM are limited. On the other hand, in recent years, it has been desired to provide various settings. Therefore, it is conceivable to provide a special command and adjust the contents of the mode register to those modes. However, such a method may cause a problem such as reduction of other commands.
[0023]
The present application has been made in view of such a point, and the problem to be solved is that in the conventional device, it was not possible to set many items in the mode register.
[0024]
[Means for Solving the Problems]
For this reason, in the present invention, the upper bits of the address input are determined, and a plurality of registers are selected. According to this, more items can be stored in the mode register by simple means. Can be set.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
That is, the present invention relates to a memory device having a function of performing mode setting using an address input, comprising a plurality of registers used for mode setting, and a determining device for determining a higher-order bit of the address input. The selection of a plurality of registers is performed in accordance with the discrimination value.
[0026]
The present invention is also an operation control method for a memory device having a function of performing mode setting using an address input, wherein a plurality of registers used for mode setting are provided, and a higher-order bit of the address input is determined. The selection of a plurality of registers is performed in accordance with the discriminated value.
[0027]
FIG. 1 is a block diagram showing the configuration of an embodiment of an SDRAM to which a memory device and an operation control method of the memory device according to the present invention are applied.
[0028]
In FIG. 1, a clock signal from the outside is supplied to a clock buffer 15, and an internal clock formed by the clock buffer 15 is supplied to each unit. A substrate bias voltage generation circuit 25 is provided inside.
[0029]
Further, a command signal from the outside is supplied to a command decoder 16, a command decoded by the command decoder 16 is supplied to a control signal generator 17, and a control signal formed here is supplied to a row decoder 12, a column decoder 13, a sense It is supplied to the amplifier 14. An external address signal is supplied to the row decoder 12 and the column decoder 13 through the address buffer 18.
[0030]
Then, data is exchanged between the sense amplifier 14 and the outside via the data buffer 19. That is, data is written / read via the data buffer 19 to the address of the cell array 11 specified by the address signal supplied from the outside in accordance with the command signal supplied from the outside. Further, a refresh counter 20 is provided to perform a refresh operation.
[0031]
In addition, in this memory device, a plurality (four in the figure) of mode registers 21 to 24 are provided, and setting information is supplied to these mode registers 21 to 24 through the address buffer 18. In this case, 10 pins A0 to A9 are provided for inputting an address signal from the outside, and the values of pins A9 and A8 among these pins are used as identification codes, and the values (0, 0), (0, Mode registers 21 to 24 are assigned to each of 1), (1, 0), and (1, 1).
[0032]
That is, in the configuration of the mode registers 21 to 24, for example, as shown in FIG. 2, the row of the values (0, 0) of the pins A9 and A8 is the mode register 21 of the operation mode setting 0. The row of the values (0, 1) of the pins A9 and A8 is set as the mode register 22 of the operation mode setting 1, and the row of the values (1, 0) of the pins A9 and A8 is set as the mode register of the operation mode setting 2. 23, and the row of the values (1, 1) of the pins A9 and A8 is set as the mode register 24 of the operation mode setting 3.
[0033]
Further, the writing of the setting information to the mode registers 21 to 24 is performed, for example, as shown in FIG. In FIG. 3, a command (MRS) of the mode register set is supplied as an external command signal at an arbitrary timing, and the value (KEY) supplied to the input of the external address signal at this time is the mode register 21 to mode register 21. 24 is set.
[0034]
When the values of the pins A9 and A8 are (0, 0), the operation mode setting 0 (KEY0) is written in the mode register 21. When the values of the pins A9 and A8 are (0, 1), the operation mode setting 1 (KEY1) is written in the mode register 22, and when the values of the pins A9 and A8 are (1, 0), the mode register 23 is set. The operation mode setting 2 (KEY3) is written in the mode register 24 when the values of the pins A9 and A8 are (1, 1).
[0035]
Further, the setting information written in the mode registers 21 to 24 is supplied to the control signal generator 17 and arbitrary control settings are performed in accordance with the specified operation modes.
[0036]
FIG. 4 shows specific setting contents. That is, when the values of the pins A9 and A8 are (0, 0), the normal setting is the same as that of the related art, and the burst length is set to the pins A0 to A2. 1, 2, 4, 8, and full range are set as the number of output data. A burst type is set to the pin A3. For example, as a method of changing a burst address when the burst length is 4 or more, one of sequential and interleave is set.
[0037]
Further, CAS latency is set for the pins A4 to A6. As described above, the CAS latency sets, for example, the number of clock cycles from the read command to the actual output of data, and can be set to 1, 2, and 3. As a result, the operating frequency can be improved. The value of the pin A7 is 0.
[0038]
In this way, for example, before the use of the memory device is started, the value (KEY0) for performing the above-described setting is supplied to the input pins A0 to A9 and the pins A9 and A8 are supplied as the value (0, 0). The value (KEY0) is written to 21, and the setting is performed. The set burst length, burst type, and CAS latency information are supplied to the control signal generator 17 to control writing / reading.
[0039]
On the other hand, when the values of the pins A9 and A8 are (0, 1), the value (KEY1) is written to the mode register 22, and the test setting 1 is set. Then, the set values of the acceleration test are written into the pins A0 to A1, and the set values for performing the acceleration test for initial failure selection are provided. As a result, the efficiency of initial defect selection can be improved.
[0040]
Further, a set value of the redundancy test is written to the pins A2 to A4, and a set value for performing a test of the redundant memory cell in the DRAM is provided. As a result, defective redundancy efficiency can be improved. The set values of the input / output pin compression test are written to the pins A5 to A7, and when there are a large number of I / O pins, set values are provided to reduce the number of I / O pins and increase the same measurement number at the time of the test. Thereby, the test efficiency can be improved.
[0041]
When the values of the pins A9 and A8 are (1, 0), the value (KEY2) is written to the mode register 23, and the test setting 2 is set. The set values of the LSI internal substrate bias level fine adjustment are written into the pins A0 to A7. In the case of a DRAM, for example, a boost power supply, a substrate bias power supply, 1 / Set values for fine adjustment of the 2Vcc power supply and the like are provided. Thereby, the operation margin can be expanded.
[0042]
Further, when the values of the pins A9 and A8 are (1, 1), the value (KEY3) is written into the mode register 24, and the test setting 3 is set. Then, a set value for fine timing adjustment in the LSI is written into the pins A0 to A7. For example, in the case of a DRAM, a set value for finely adjusting the timing for DRAM operation generated inside the LSI is provided. Thereby, the operation margin can be expanded.
[0043]
In this way, when the pins A9 and A8 are at the values (0, 1) (1, 0) (1, 1), the desired set values are written into the mode registers 22 to 24, and the desired test modes are respectively set. And settings in the adjustment mode. In the above description, the contents shown in the test settings 1 to 3 are merely examples, and do not limit the present invention. Further, it is also possible to use the value of the pin A7 for identification to expand the set contents. Further, the number of pins may be 10 or more.
[0044]
Therefore, in this embodiment, by determining the upper bits of the address input and selecting a plurality of registers, more items can be set in the mode register by simple means.
[0045]
Thus, according to the present invention, these problems can be easily solved, although the conventional apparatus cannot set many items in the mode register.
[0046]
Further, the invention of the present application can be implemented in an asynchronous DRAM. FIG. 5 shows a configuration of such a DRAM. In FIG. 5, portions common to those in the configuration of the SDRAM in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
[0047]
That is, in FIG. 5, the clock buffer 15 and the command decoder 16 are removed from the configuration of the SDRAM, and the respective components are directly controlled by a control signal generator 17 to which RAS, CAS, WE, and OE signals are externally supplied. Things.
[0048]
In the DRAM having such a configuration, for example, as shown in FIG. 6, the WE, CAS, and RAS signals are supplied while the value (KEY) to be set is supplied to the input pins A0 to A9 of the address signal. By making them active sequentially, the values (KEY0 to 3) are written into the mode registers 21 to 24, and the setting is performed. The set information is supplied to the control signal generator 17, and the control according to the setting is performed. Is what is done.
[0049]
Thus, according to the above-described memory device, the memory device has a function of performing mode setting using an address input, and includes a plurality of registers used for mode setting and a determination unit that determines a higher-order bit of the address input. By selecting a plurality of registers according to the discriminating value of the discriminating means, more items can be set in the mode register by simple means.
[0050]
Further, according to the operation control method for a memory device described above, there is provided an operation control method for a memory device having a function of performing mode setting using an address input. By discriminating the upper bits and selecting a plurality of registers according to the discriminated value, more items can be set in the mode register by simple means.
[0051]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
[0052]
【The invention's effect】
Therefore, according to the first aspect of the present invention, by discriminating the upper bits of the address input and selecting a plurality of registers, more items can be set in the mode register by simple means. It is.
[0053]
According to the second aspect of the invention, in the normal operation mode, the value of the high-order bit of the address input is set to 0, so that compatibility with the conventional device can be maintained.
[0054]
According to the third aspect of the present invention, the setting of the test mode can be performed in the register selected in accordance with the determination value of the determination means by setting the test mode.
[0055]
According to the fourth aspect of the present invention, the setting of the adjustment mode is performed in the register selected according to the determination value of the determination means, so that the setting in the adjustment mode can be performed.
[0056]
According to the fifth aspect of the present invention, the setting selected in the normal operation mode is expanded in the register selected in accordance with the judgment value of the judgment means, so that the setting in the normal operation mode is expanded. Is what you can do.
[0057]
Furthermore, according to the invention of claim 6, by discriminating the upper bits of the address input and selecting a plurality of registers, more items can be set in the mode register by simple means. It is.
[0058]
According to the seventh aspect of the present invention, in the normal operation mode, the value of the upper bit of the address input is set to 0, so that compatibility with the conventional device can be maintained.
[0059]
According to the invention of claim 8, in the register selected according to the discrimination value of the discriminating means, the setting in the test mode can be performed by setting the test mode.
[0060]
According to the ninth aspect of the present invention, the setting of the adjustment mode is performed in the register selected in accordance with the determination value of the determination means, so that the setting in the adjustment mode can be performed.
[0061]
According to the tenth aspect of the present invention, in the register selected in accordance with the discrimination value of the discrimination means, the setting in the normal operation mode is expanded so that the setting in the normal operation mode is expanded. Is what you can do.
[0062]
Thus, according to the present invention, these problems can be easily solved, although the conventional apparatus cannot set many items in the mode register.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of an SDRAM to which a memory device and an operation control method of the memory device according to the present invention are applied.
FIG. 2 is a table for the explanation.
FIG. 3 is a timing chart for explaining the operation.
FIG. 4 is a table for the explanation.
FIG. 5 is a block diagram showing a configuration of an embodiment of a DRAM to which a memory device and an operation control method of the memory device according to the present invention are applied;
FIG. 6 is a timing chart for explaining the operation.
FIG. 7 is a block diagram showing a configuration of a conventional SDRAM.
FIG. 8 is a timing chart for explaining the operation.
FIG. 9 is a table for the explanation.
FIG. 10 is a block diagram showing a configuration of a conventional DRAM.
FIG. 11 is a timing chart for explaining the operation.
[Explanation of symbols]
11 cell array, 12 row decoder, 13 column decoder, 14 sense amplifier, 15 clock buffer, 16 command decoder, 17 control signal generator, 18 address buffer, 19 data buffer, 20 refresh counter, 21 to 24: mode register, 25: substrate bias voltage generation circuit

Claims (10)

A memory device having a function of setting a mode using an address input,
A plurality of registers used for the mode setting are provided,
A determination unit configured to determine a high-order bit of the address input;
The memory device according to claim 1, wherein the plurality of registers are selected according to a determination value of the determination unit. The memory device according to claim 1,
In a normal operation mode, a value of a high-order bit of the address input is set to 0. The memory device according to claim 1,
A memory device, wherein a test mode is set in a register selected according to a judgment value of the judgment means. The memory device according to claim 1,
A memory device, wherein an adjustment mode is set in a register selected according to a judgment value of the judgment means. 3. The memory device according to claim 2, wherein
A memory device characterized in that a setting selected in a register selected according to the discrimination value of the discrimination means is expanded in a setting range in the normal operation mode. An operation control method of a memory device having a function of performing mode setting using an address input, wherein a plurality of registers used for the mode setting are provided,
Determining the upper bits of the address input,
An operation control method for a memory device, wherein the plurality of registers are selected according to the determined value. 7. The operation control method for a memory device according to claim 6, wherein
In a normal operation mode, a value of a high-order bit of the address input is set to 0. 7. The operation control method for a memory device according to claim 6, wherein
A test mode is set in a register selected in accordance with a discrimination value of the discriminating means, and the operation control method for a memory device is performed. 7. The operation control method for a memory device according to claim 6, wherein
An operation control method for a memory device, wherein an adjustment mode is set in a register selected in accordance with a judgment value of the judgment means. The operation control method for a memory device according to claim 7,
An operation control method for a memory device, wherein a setting selected in the normal operation mode is expanded in a register selected according to a judgment value of the judgment means.

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