JP2004164171A - Path redundancy device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance performance concerning responsiveness to a host computer, relating to a path redundancy device and method for use with a disk array device or the like to switch the pass of data input/output. <P>SOLUTION: A path redundancy driver 4 is used for a disk array device 9 which controls the recording and reproduction of data to and from logic discs 70-72 by means of controllers 10, 20 having cache memories 15, 25, and which writes data into the cache memories 15, 25 when the data are written on the logic discs 70-72. The path redundancy driver has the function of allocating the path of read data transfer and the path of write data transfer to each of the controllers 10, 20. The write data transfer is executed only by the specific controller 10 (or 20). As a result, competition is avoided as to the double writing of the write data into the cache memories 15, 25. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a path redundancy device and a method for switching a data input / output path used in a disk array device or the like.
[0002]
[Prior art]
For example, in a disk array device disclosed in Patent Document 1 described below, recording and reproduction of data on a large number of logical disks are controlled by two controllers having cache memories, and caches of the two controllers are used when writing data to the logical disks. The same data is written to the respective memories. Thus, even if a failure (or failure, the same applies hereinafter) occurs in one of the controllers, the data can be written to the logical disk because the data is held in the cache memory of the other controller.
[0003]
A host computer connected to such a disk array device is provided with a path redundancy driver as means for avoiding a connection path failure leading to the disk array device. The path redundancy driver does not affect the operation of the application program running on the host computer even when a failure occurs in a component (controller or the like) of the I / O (input / output) access path. Retry processing is performed using the alternative path. Some path redundancy drivers also have a function of issuing I / O to a plurality of paths so that I / O is not concentrated on a specific path.
[Patent Document 1]
JP 2001-318766 A
[Problems to be solved by the invention]
However, the disk array device employing such a conventional technique, that is, an architecture having an independent cache memory for each controller, has the following problems.
[0005]
▲ 1 ▼. When I / Os are distributed and issued to a plurality of paths by a path redundancy driver, write data from a host computer connected to each controller is written to a cache memory on the other controller in duplicate. It is. This is to prevent unwritten data on the disk existing in the cache memory from being lost when one controller fails. However, when the conflict between the double writes occurs, a response delay of the normal termination to the host computer occurs, and consequently, the load distribution function of the path redundancy driver causes a decrease in performance.
[0006]
▲ 2 ▼. Issuing the read data transfer I / O and the write data transfer I / O to the same controller complicates the control of the cache memory, so that it is difficult to maximize the performance of the cache memory. Become. As a result, the response to the host computer is reduced.
[0007]
[Object of the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a path redundancy device and method which can improve the response performance to a host computer.
[0008]
[Means for Solving the Problems]
[0009]
The path redundancy device according to the present invention controls the recording and reproduction of data on a large number of recording media by a plurality of controllers having a cache memory, and when writing data to a recording medium, stores the data in cache memories of at least two controllers. It is used in a recording device that writes the same data, and has a function of allocating a path between read data transfer and write data transfer for each controller.
[0010]
By allocating the read data transfer path and the write data transfer path for each controller, the write data transfer is executed only by a specific controller. As a result, there is no conflict in double writing of write data to the cache memory. In addition, since the control of each cache memory can be specialized to read data transfer or write data transfer, the performance of the cache memory is maximized.
[0011]
Further, the recording medium may be a logical disk and the recording device may be a disk array device. Furthermore, the plurality of controllers may include a first controller that is a path dedicated to read data transfer, and a second controller that is a path dedicated to write data transfer.
[0012]
The path redundancy method according to the present invention (claims 4 to 6) is used for the path redundancy device according to the present invention, and corresponds to claims 1 to 3, respectively.
[0013]
In other words, the present invention provides an I / O path redundancy system that improves an I / O response by controlling an I / O issue path for each data transfer direction of an I / O request.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a path redundancy device according to the present invention. Hereinafter, description will be made based on this drawing.
[0015]
The path redundancy driver 4 as a path redundancy device according to the present invention controls recording and reproduction of data on the logical disks 70 to 72 by the controllers 10 and 20 having the cache memories 15 and 25, and also controls the logical disks 70 to 72. Is used in the disk array device 9 for writing the same data to the cache memories 15 and 25 when writing the data to the cache memories 15 and 25, respectively, and has a function of allocating the path between the read data transfer and the write data transfer for each controller 10 and 20. .
[0016]
By allocating the read data transfer path and the write data transfer path for each of the controllers 10 and 20, the write data transfer is executed only by the specific controller 10 (or 20). As a result, contention in the double writing of the write data to the cache memories 15 and 25 is eliminated. In addition, since the control of each cache memory 15, 25 can be specialized for read data transfer or write data transfer, the performance of the cache memories 15, 25 is maximized. This will be described in more detail.
[0017]
HBAs (Host Bus Adapters) 6 and 7 of the host computer 1 are connected to controllers 10 and 20 of the disk array device 9 via host interface cables 50 and 51, respectively. The host computer 1 executes I / O for the logical disks 70 to 72 controlled by the disk array device 9. The lower driver 5 performs I / O processing by controlling the HBAs 6 and 7.
[0018]
The path redundancy driver 4 operates as follows. The I / O received from the upper driver 3 is delivered to the lower driver 5. Further, the I / O execution result for the logical disks 70 to 72 controlled by the disk array device 9 is received from the lower driver 5 via the HBAs 6 and 7, and a normal end or an abnormal end is determined. If it is determined that the cause of the abnormal termination is a failure in the path components (HBAs 6, 7, host interface cables 50, 51, controllers 10, 20 and the like), the I / O of the abnormally terminated I / O is determined using the alternative path. Perform retry processing.
[0019]
The host interface control circuits 11 and 21 are connected to the HBAs 6 and 7 via host interface cables 50 and 51, respectively, and control input / output I / O requested from the host computer 1.
[0020]
The data transfer control circuits 12 and 22 include host interface control circuits 11 and 21, MPUs 14 and 24, cache memories 15 and 25, HDD interface control circuits 13 and 23, and a write data mirroring control circuit via internal buses 30 and 40, respectively. 16 and 26, and controls data transfer in each of the controllers 10 and 20.
[0021]
The HDD interface control circuits 13 and 23 are connected to the logical disks 70 to 72 via the disk interface 60. Therefore, input / output control for each of the logical disks 70 to 72 can be performed from either of the controllers 10 and 20.
[0022]
The MPUs 14 and 24 control the control circuits in the controllers 10 and 20 and the cache memories 15 and 25 via the internal buses 30 and 40, respectively.
[0023]
The cache memories 15 and 25 are memories used for improving response performance to input / output requests from the host computer 1.
[0024]
The write data mirroring control circuits 16 and 26 transfer unwritten data to the logical disks 70 to 72 existing only on one cache memory 15 (or 25) to the other cache memory 25 (or 25) via the mirroring data transfer interface 31. Or 15) perform mirroring (that is, copy control) upward.
[0025]
Each of the logical disks 70 to 72 is composed of a plurality of single disks.
[0026]
Next, operations of the host computer 1 and the disk array device 9 will be described.
[0027]
Data (write data transfer I / O) written from the application program 8 operating on the host computer 1 to the disk array device 9 includes the application program 8, the file system 2, the upper driver 3, the path redundancy driver 4, and the lower The data reaches the controller 10 via the driver 5, the HBA 6, and the host interface cable 50, and is written to the designated logical disks 70 to 72.
[0028]
Data (read data transfer I / O) read from the disk array device 9 by the application program 8 operating on the host computer 1 is transmitted from the designated logical disks 70 to 72 via the controller 10 and the host interface cable 50. It reaches the HBA 6 and reaches the application program 8 via the lower driver 5, the path redundancy driver 4, the upper driver 3, and the file system 2.
[0029]
The result of the execution of each I / O by the host computer 1 is determined by each layer of the HBA 6, the lower driver 5, the path redundancy driver 4, the upper driver 3, the file system 2, and the application program 8, and is necessary. Some action is taken in accordance with.
[0030]
Here, the path redundancy driver 4 determines whether the I / O execution result received from the lower driver 5 is a normal end or an abnormal end, and the cause of the abnormal end is a component of the path (HBA 6, 7, the host interface cable). 50, 51, the controllers 10 and 20), a retry process of the abnormally terminated I / O is performed using the alternative path.
[0031]
Further, the path redundancy driver 4 effectively utilizes a plurality of I / O paths so that the I / Os do not concentrate on only one I / O path (for example, via the host interface cable 50). It has a function of distributing / O load (via host interface cables 50 and 51).
[0032]
Next, the cache memories 15 and 25 will be described.
[0033]
If no failure has occurred in the controllers 10 and 20 in the disk array device 9, the write data from the host computer 1 is transferred to the cache memory 15 in the controller 10 in the disk array device 9 via, for example, the host interface cable 50. Stored temporarily. However, since a volatile memory is generally used for the cache memory 15, if a failure occurs in the controller 10 before data is written to an appropriate logical disk among the logical disks 70 to 72, the cache memory 15 is stored in the cache memory 15. The temporarily stored data is lost.
[0034]
To avoid this, the disk array device 9 employs an architecture having independent cache memories 15 and 25 for each controller 10 and 20. In other words, the write data from the host computer 1 is mutually rejected in order to prevent the loss of unwritten data on the disk existing in the cache memory 15 (or 25) when one controller 10 (or 20) fails. The data is duplicately written to the cache memory 25 (or 15) on one controller 20 (or 10). These operations are performed by the write data mirroring control circuits 16 and 26 connected to each other via the mirroring data transfer interface 31.
[0035]
Here, in the prior art, write data (write data transfer I / O) is issued to the controllers 10 and 20 via the host interface cables 50 and 51 by the I / O load distribution function of the path redundancy driver 4. In such a case, the following problem occurs. After the write data is accumulated in the cache memory 15 (or 25) on each controller 10 (or 20), the write data is stored in the cache memory on the other controller 20 (or 10) via the write data mirroring control circuits 16 and 26. 25 (or 15). However, since the reflection processing cannot be performed at the same time, the reflection processing by the other controller 20 (or 10) is waited until the reflection processing from one of the controllers 10 (or 20) is completed. Therefore, a normal end response to the host computer 1 for write data (write data transfer I / O) issued via one of the host interface cables 51 (or 50) is delayed.
[0036]
Further, the fact that the read (read data transfer I / O) and the write (write data transfer I / O) are issued to the same controller 10 (or 20) complicates the control of the cache memories 15 and 25. Therefore, it is difficult to maximize the performance of the cache memory, and as a result, the response to the host computer 1 is delayed.
[0037]
FIG. 2 is a flowchart showing an example of the operation of the path redundancy driver in FIG. Hereinafter, description will be given based on FIG. 1 and FIG.
[0038]
FIG. 2 determines the data transfer direction of the I / O request received from the upper driver 3 and designates that the request involving the data transfer in the read direction and the request involving the data transfer in the write direction are distributed to different paths. 2 shows a part of the processing steps for the above. These processes are performed by the path redundancy driver 4. That is, FIG. 2 is a flow that is executed by the path redundancy driver 4 and shows a part of the processing steps related to the read data transfer I / O and the write data transfer I / O by the path redundancy driver 4. Hereinafter, a method for solving the above-described response delay to the host computer 1 will be described with reference to FIGS.
[0039]
First, setting information for distributing paths to be issued for each of an I / O request involving data transfer in the read direction and an I / O request involving data transfer in the write direction is read (step S201). Here, the setting information is information for allocating the path for issuing the I / O request based on the data transfer direction, and includes the following two types. 1. A path to the controller 10 via the HBA 6 and the host interface cable 50 when the I / O request received from the upper driver 3 involves data transfer in the read direction. 2. A path to the controller 20 via the HBA 7 and the host interface cable 51 when the I / O request involves data transfer in the write direction. These setting information is externally provided as a definition file.
[0040]
Subsequently, an I / O request is received from the upper driver 3 (step S202), and it is determined whether the I / O request involves data transfer in the read direction or data transfer in the write direction (step S202). Step S203). When data transfer in the read direction is involved, the path setting of the I / O request is performed according to the setting information in step S201 so that I / O is issued to the controller 10 via the HBA 6 and the host interface cable 50 (step S201). S204). Similarly, when data transfer in the write direction is involved, the path setting of the I / O request is performed so that I / O is issued to the controller 20 via the HBA 7 and the host interface cable 51 according to the setting information in step S201. Perform (Step S205).
[0041]
Subsequently, the I / O request whose path has been set in step S204 or step S205 is issued to the lower driver 5 (step S206). The lower driver 5 issues an I / O request to the path (HBA 6 or HBA 7) specified in step S204 or S205.
[0042]
As described above, control of the data transfer direction (read direction / write direction) of I / O issued to the disk array device 9 is realized.
[0043]
It is needless to say that the present invention is not limited to the above embodiment. For example, the following may be performed.
[0044]
a. The setting information in step S201 in FIG. 2 is fixed, but there is no such limitation, and the setting information can be changed at any time and by any means. b. The setting information in step S201 in FIG. 2 is provided from a definition file from the outside, but there is no limitation. The setting information may be provided from a medium such as a floppy disk or a ROM, or may be provided by the path redundancy driver 4 itself. The information may be actively fed back based on the analysis result of the I / O pattern. c. FIG. 1 shows an example of the configuration of the host computer 1 on which two HBAs 6 and 7 are installed. , Any number is acceptable. d. Although FIG. 1 shows an example of the configuration of the disk array device 9 having two controllers 10 and 20, the number of controllers and the number of ports for connecting each controller to a host computer or the like via an interface cable are limited. There is no. e. FIG. 1 shows an example in which the HBAs 6 and 7 and the controllers 10 and 20 are directly connected by interface cables, respectively, but a hub or a switch or the like may be interposed in the middle. f. In FIG. 1, the logical disks 70 to 72 are configured in the disk array device 9 as an example. However, the logical disks 70 to 72 are configured by external disks such as JBOD (Just Bunch of Disks) connected to the disk array device 9. You may. g. The number of disk array devices 9 connected to the host computer 1 of FIG. 1 is not limited. h. The number of host computers 1 connected to the disk array device 9 of FIG. 1 is not limited. i. There is no limitation on the number of logical disks 70 to 72 configured in the disk array device 9 of FIG. 1 j. In the present invention, the disk array device 9 has been described as an example, but the present invention is not limited to only the disk array device.
[0045]
【The invention's effect】
According to the path redundancy apparatus and method according to the present invention, the write data transfer is executed by a specific controller by allocating the read data transfer path and the write data transfer path for each controller, so that the write data Contention in the double write to the cache memory of the memory can be eliminated. In addition, since the control of each cache memory can be specialized for read data transfer or write data transfer, the performance of the cache memory can be maximized. Thereby, the response performance to the host computer can be improved.
[0046]
In other words, according to the present invention, the following two effects are achieved by allocating the read data transfer I / O and the write data transfer I / O for each arbitrary controller of the disk array device. The first effect is that the contention in the double writing of write data to the cache memory is eliminated, so that it is possible to avoid a delay in response to a normal termination to the host computer. The second effect is that the control of the cache memory can be tuned specifically for the read data transfer I / O or the write data transfer I / O, so that the cache memory performance can be maximized. Thereby, the response performance to the host computer can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a path redundancy device according to the present invention.
FIG. 2 is a flowchart illustrating an example of an operation of a path redundancy driver in FIG. 1;
[Explanation of symbols]
1 host computer 4 path redundancy driver (path redundancy device)
9 Disk array device 10, 20 Controller 15, 25 Cache memory 70-72 Logical disk

Claims (6)

A recording device that controls recording and reproduction of data on a large number of recording media by a plurality of controllers having a cache memory and writes the same data to the cache memories of at least two controllers when writing data to the recording media. Used for
A function of allocating a path between read data transfer and write data transfer for each controller,
Path redundancy device. The recording medium is a logical disk, the recording device is a disk array device,
The path redundancy device according to claim 1. The plurality of controllers includes a first controller serving as a path dedicated to read data transfer, and a second controller serving as a path dedicated to write data transfer,
The path redundancy device according to claim 1. A recording device that controls recording and reproduction of data on a large number of recording media by a plurality of controllers having a cache memory and writes the same data to the cache memories of at least two controllers when writing data to the recording media. Used for
Allocating paths for read data transfer and write data transfer for each controller,
Path redundancy method. The recording medium is a logical disk, the recording device is a disk array device,
The path redundancy method according to claim 4. The plurality of controllers includes a first controller serving as a path dedicated to read data transfer, and a second controller serving as a path dedicated to write data transfer,
The path redundancy method according to claim 4.

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