JP2004153906A - Device for preventing reverse connection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To assure the prevention of a circuit element from being broken when there is wrong reverse connection by significantly improving the driving performance of a driver, and attain miniaturization and cost reduction. <P>SOLUTION: This preventing device comprises a detection function of reverse connection; a function of disconnecting the state of the reverse connection if the reverse connection is detected; and a function of setting an on-resistance value and a voltage drop below prescribed values at the time of energization so that the driving performance of a driving element is derived to higher than the prescribed value. <P>COPYRIGHT: (C)2004,JPO

Description

駆動能力は、（５）式から
１．６９＝（２．３−１）×（２．３−１） …（６）
なお、図９中のドライバの駆動能力は、従来技術と発明の効果をわかりやすくするためのものであって、実際に流す電流値とは異なる。ただし、従来技術で１．６９Ａの能力があるのに対して、本発明では３．９２Ａの能力があると考えるための補助に用いることは可能である。
【００８４】
また、ドライバの駆動能力が向上する利点を生かす方策としては、
（ａ）３Ｖの仕様であれば、ドライバのサイズを小さくできる（放熱の面でパッケージは変えない）点、
（ｂ）ドライバの大きさを変えないでもっと大きなモータを駆動できる点、
（ｃ）ドライバの大きさを変えないで、かつ、モータの容量変えないで、小さなパッケージに収納可能な点、
などが挙げられる。
【００８５】
【発明の効果】
以上説明したように、本発明によれば、逆接続の検出機能と、逆接続であると判断した場合は該逆接続の状態を切り離す機能と、正常接続時には、駆動素子の駆動能力を一定値以上引き出せるように、通電時の所定の電気的特性（オン抵抗および電圧降下）を所定条件に設定する機能とを設けたので、誤って逆接続した場合の回路素子の破壊防止を保証すると同時に、ドライバ駆動能力を格段に向上させ、小型化、低コスト化を図ることが可能な逆接続防止装置を作製することができる。
【００８６】
また、本発明によれば、トランジスタ素子のバルク間を補償用配線により接続して同電位にして電位差を無くすようにしたので、縦型寄生トランジスタによる貫通電流を阻止することができ、Ｐ基板上にＣＭＯＳプロセスにより逆接続防止装置と信号処理回路とを一体にして集積回路を作製することが可能となり、これにより、個別部品による外付け逆接続防止装置を不要とし、一段と小型で低価格な装置を作製することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態である、逆接続防止装置をＰＭＯＳトランジスタにより構成し、ブラシレス２相ファンモータの駆動制御回路内に備えた例を示す回路図である。
【図２】図１の基板回路の断面構成を示す断面図である。
【図３】本発明の第２の実施の形態である、逆接続防止装置をＣＭＯＳ回路により構成した例を示す回路図である。
【図４】図３の逆接続防止装置とホールＩＣとを、同一Ｐ基板上にＣＭＯＳプロセスにより集化して一体に構成した例を示す回路図である。
【図５】図４のＣＭＯＳ回路の断面構成を示す断面図である。
【図６】本発明の第３の実施の形態である、逆接続防止装置をＰＮＰトランジスタにより構成した例を示す回路図である。
【図７】本発明の第３の実施の形態である、逆接続防止装置をＰＮＰトランジスタと抵抗により構成した例を示す回路図である。
【図８】本発明の第３の実施の形態である、逆接続防止装置をリレーとダイオードにより構成した例を示す回路図である。
【図９】本発明の電気的特性を従来例と比較して示す説明図である。
【図１０】第１の従来例を示す回路図である。
【図１１】第２の従来例を示す回路図である。
【図１２】第３の従来例を示す回路図である。
【図１３】ホールＩＣの内部構成を示す回路図である。
【図１４】ブラシレス２相ファンモータの内部構成を示す構成図である。
【符号の説明】
１ ホールＩＣ
２ 電磁石
２ａ，２ｂ コイル
３ ドライバ回路
４ 逆接続防止回路
５ 静電保護回路
６，７ ドライバ（ＮＰＮトランジスタ）
６ａ，７ａ ドライバ（ＮＭＯＳトランジスタ）
８ 抵抗
９ コンデンサ
１１ 電圧レギュレータ回路
１２ ホールプレート
１３ 信号処理部
１４，１５ 出力バッファ回路
２０ プラス電源端子（＋１２Ｖ）
２１ マイナス電源端子（０Ｖ）
３０ 駆動制御回路
４０ ブラシレス２相ファンモータ
４１ 回転子
４２ 固定子
５０ 電源
１００ 逆接続防止装置（ＰＭＯＳトランジスタ）
１０５ バルク
１１０ 配線
１２０ 配線（内部プラス電源ノード）
１３０〜１３２ 配線
２００ 逆接続防止装置（ＣＭＯＳ回路）
２０５，２０６ バルク
２１０ 第１のＰＭＯＳトランジスタ（ＰＭＯＳ１）
２２０ 第２のＰＭＯＳトランジスタ（ＰＭＯＳ２）
２５０ 集積回路
３００ 縦型ＰＮＰ寄生バイポーラトランジスタ
４００ 逆接続防止装置
４０１ ＰＮＰトランジスタ
４０２ 抵抗
４０３ リレー
４０４ ダイオード
５００ ＯＮ抵抗
５０１ 電圧降下
５０２ ドライバ駆動能力（規格値）
５０３ ドライバ面積
５０４ 集積化の有無
ａ ホールＩＣのプラス電源端子
ｂ ホールＩＣのマイナス電源端子
ｃ ホールＩＣの出力端子
ｄ ホールＩＣの出力端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention can be applied, for example, to a reverse connection prevention circuit using a power supply of a motor driver of a brushless two-phase fan motor, and an overcurrent flows when a positive power supply and a negative power supply of an electronic device are erroneously reversely connected. The present invention relates to a reverse connection prevention device capable of preventing the destruction of elements by preventing the device from being broken.
[0002]
[Prior art]
Fan motors are widely used as air cooling devices for electronic devices. Among them, the brushless two-phase fan motor has a very large market size of 500 million units per year. Basically, a brushless two-phase fan motor has only two terminals, a positive power supply and a negative power supply. When the power is turned on, the brushless two-phase fan motor rotates easily at the rotation speed determined by the power supply voltage and the fan motor coil. Designed.
[0003]
10, 11, and 12 show examples of the configuration of the drive control circuit 30 for the brushless two-phase fan motor. FIG. 12 shows a configuration in which the driver circuit 3 of FIGS. 10 and 11 is integrated with the Hall IC 1 on the same chip.
[0004]
Each of the drive control circuits 30 includes a Hall IC 1, an electromagnet 2 wound with coils 2a and 2b for generating rotational torque, a driver circuit 3, a reverse connection prevention circuit 4 including diodes and resistors, an electrostatic protection circuit ( An ESD protection circuit 5 and the like are provided as necessary.
[0005]
The Hall IC 1 detects the position of the rotor by detecting the polarity of the magnetic field of the permanent magnet attached to the rotor of the two-phase fan motor 40, and generates a timing for energizing the coils 2a and 2b.
[0006]
The driver circuit 3 includes drivers 6 and 7 that alternately supply a large current to the two coils 2a and 2b in synchronization with the timing of the generation of the Hall IC 1, a resistor 8, a capacitor 9, and the like.
[0007]
FIG. 13 shows a typical configuration example of the Hall IC 1 as a signal processing circuit used in the two-phase fan motor 40.
[0008]
The Hall IC 1 includes a voltage regulator circuit 11, a Hall plate 12, a signal processing unit 13, an output buffer circuit 14, and an output buffer circuit 15 with the polarity of the output buffer circuit 14 inverted.
[0009]
The drive control circuit including the Hall IC 1 and the driver circuit 3 has its plus power supply terminal 20 connected to the plus power supply of the two-phase fan motor 40 and its minus power supply terminal 21 connected to the minus power supply of the two-phase fan motor 40. By doing so, normal normal rotation is performed.
[0010]
FIG. 14 shows an example of the internal configuration of the two-phase fan motor 40.
The outside is constituted by a rotor 41 composed of a pair of permanent magnets NS, and the inside is constituted by a stator 42 composed of a field winding having a phase difference of 90 degrees. The rotor 41 is rotated by the rotating magnetic field generated by the field winding of the stator 42.
[0011]
[Patent Document 1]
US Patent No. 6,300,736
[0012]
[Problems to be solved by the invention]
As shown in FIGS. 10 to 12 described above, the two-phase fan motor 40 has only the positive power supply line and the negative power supply line, and the user reverses the wires and connects the positive power supply terminal 20 and the negative power supply terminal 21 in reverse. In some cases.
[0013]
In the case where the reverse connection protection circuit 4 is not provided in the drive control circuit, when the plus power supply and the minus power supply are reversely connected, an excessive through current flows through the Hall IC 1, and the Hall IC 1 is burned out due to heat generation and the motor is destroyed.
[0014]
At this time, the penetrating current also flows through the coils 2a and 2b and the drivers 6 and 7, but the magnitude of the penetrating current is approximately the same as the value of the current flowing during normal driving, and does not lead to burning.
[0015]
Therefore, in consideration of IC protection in the event of reverse connection by mistake, it is standardized that a reverse connection prevention circuit 4 is always provided in the drive control circuit, and any reverse connection prevention circuit is used for any of the conventional circuits. I have.
[0016]
The reverse connection prevention circuit 4 used in the conventional circuit of FIG. 10 is configured by connecting a diode between the positive power supply terminal 20 and the positive power supply of the two-phase fan motor 40. At the time of reverse connection, the diode is reverse-biased and no through current is generated, so that the motor is not destroyed.
[0017]
The reverse connection prevention circuit 4 used in the conventional circuit of FIG. 11 is configured by connecting a diode between the positive power supply terminal 20 and the positive power supply of the Hall IC 1. At the time of reverse connection, the diode becomes reverse-biased and blocks a through current on the side of the Hall IC 1, so that the motor is not destroyed.
[0018]
On the other hand, the reverse connection prevention circuit 4 used in the conventional circuit of FIG. 12 is configured by connecting a resistor between the positive power supply terminal 20 and the positive power supply of the Hall IC 1. At the time of reverse connection, a through current on the IC side is generated, but by limiting the current to such an extent that the IC does not break down due to its resistance, the breakage of the motor can be prevented.
[0019]
By providing such various protection means, the reverse connection prevention circuit 4 can be easily configured.
[0020]
However, the reverse connection prevention circuit 4 using a diode generates a voltage drop of about 0.7 V as a forward voltage of the diode during a normal operation, which brings a great disadvantage to a low-voltage operation of the motor.
[0021]
In particular, in a field such as a notebook computer, a game machine, and a portable terminal, which requires an operation voltage of 3 V, if a voltage drop of 0.7 V occurs due to a diode forward voltage, the voltage applied to the Hall IC becomes 2.3 V, and the Hall IC becomes 2.3 V. Cannot operate stably.
[0022]
Also, the control voltage of the driver connected to the Hall IC becomes 2.3 V, and the ON voltage of the driver increases due to the decrease of the control voltage. A large driver is prepared to satisfy a predetermined initial current for driving the motor. Will do.
[0023]
In particular, in the case of a driver using MOS transistors, the driving capability of the driver is proportional to the square of (driver control voltage-MOS threshold voltage). Assume that the MOS threshold voltage is 1 V. If the diode forward voltage drop is 0.7 V and the control voltage is 2.3 V, the square of (driver control voltage-MOS threshold) is
(2.3-1) × (2.3-1) = 1.69 (V) (1)
It becomes.
[0024]
On the other hand, when there is no diode forward voltage drop and the control voltage is 3 V, the square of (driver control voltage-MOS threshold) is
(3-1) × (3-1) = 4 (V) (2)
It becomes.
[0025]
The driving capability of the driver is more than doubled between when there is a diode forward voltage drop and when there is no diode forward voltage drop, and it can be seen that there is great significance in eliminating the diode in applications requiring low voltage operation.
[0026]
In the case of the diode connection shown in FIG. 10, a large current of several amperes must be supplied to the diode during normal operation, which necessitates a diode having a large current capacity, which is an obstacle to downsizing the motor.
[0027]
As shown in FIG. 12, even in the method of connecting the resistors, a voltage drop corresponding to the current consumption of the Hall IC 1 × the resistance value occurs, and the magnitude of the voltage drop depends on the current limitation at the time of reverse connection. Since the resistance value is about several hundred ohms and the current consumption of the Hall IC 1 is several mA, the voltage drop is about the same as the diode forward voltage, and the same discussion as in the case of the diode results. There is a problem of conversion.
[0028]
Further, the conventional reverse connection prevention circuit has disadvantages such as an increase in cost due to the price of the electronic component and an increase in the cost at the time of assembly because the individual electronic component is attached. In particular, the fan motor as described above has a very large market size of 500 million units per year, which is a great disadvantage in the entire market.
[0029]
Therefore, an object of the present invention is to provide a reverse connection prevention device capable of preventing the destruction of circuit elements in the case of erroneous reverse connection, and at the same time, capable of significantly improving driver driving capability and achieving downsizing and cost reduction. Is to provide.
[0030]
[Means for Solving the Problems]
The present invention is a reverse connection prevention device used for electrical connection between a power supply and a signal processing device, which determines a connection mode between a positive power supply terminal and a negative power supply terminal to prevent reverse connection, wherein the positive power supply terminal The connection detection means for detecting whether a positive voltage that is a normal connection is applied, or a negative voltage that is a reverse connection is applied, and when it is determined that the detection result is a normal connection When the normal connection state is maintained as it is, and the detection result is determined to be a reverse connection, a reverse connection preventing device is configured by including connection control means for disconnecting the reverse connection state.
[0031]
Here, the signal processing device includes a Hall IC for driving and controlling a motor, the driving capability of the motor is at least 1.5 times or more a reference value, and a driver integrated area including the Hall IC has an integrated area. The on-resistance and the voltage drop during energization may be set to a predetermined value or less so as to be about half or less of the reference value.
[0032]
The connection control means includes a single switch. In a normal connection in which a positive voltage is applied to the plus power terminal with respect to the minus power terminal, the switch is in a state of the potential of the normal connection. In the case of reverse connection where a positive power terminal of the signal processing circuit is connected to the positive power terminal and a negative voltage is applied to the positive power terminal with respect to the negative power terminal, The connection between the positive power supply terminal and the positive power supply terminal of the signal processing circuit may be cut off by detecting the reverse connection potential state.
[0033]
The switch includes a PMOS transistor formed in an independent N-well. When the switch is normally connected, a drain of the PMOS transistor is connected to the positive power supply terminal, and a source of the PMOS transistor is connected to a positive power supply of the signal processing circuit. Terminal, and the gate of the PMOS transistor is connected to the minus power supply terminal, so that the plus power supply terminal of the signal processing circuit is connected to the plus power supply terminal. The connection between the positive power supply terminal and the positive power supply terminal of the signal processing circuit may be cut off by connecting to a negative power supply terminal and connecting a gate of the PMOS transistor to the positive power supply terminal.
[0034]
The connection control means includes a first switch and a second switch, and the first switch is provided in a case where a normal connection is performed in which a positive voltage is applied to the plus power terminal with respect to the minus power terminal. Detecting the potential state of the normal connection, connecting a positive power supply terminal of the signal processing circuit to the positive power supply terminal, and setting the second switch based on the negative power supply terminal to the positive power supply terminal. In the case of a reverse connection in which a negative voltage is applied to the signal processing circuit, a positive power supply terminal of the signal processing circuit may be connected to the negative power supply terminal by detecting the potential state of the reverse connection.
[0035]
The first switch includes a first PMOS transistor formed in an independent N-well, and the second switch includes a second PMOS transistor formed in an independent N-well. At the time of connection, the drain of the first PMOS transistor is connected to the positive power supply terminal, the source of the first PMOS transistor is connected to the positive power supply terminal of the signal processing circuit, and the gate of the first PMOS transistor is connected. By connecting to the minus power supply terminal, the plus power supply terminal of the signal processing circuit is connected to the plus power supply terminal, and at the time of the reverse connection, the drain of the second PMOS transistor is connected to the minus power supply terminal, Connecting the source of the second PMOS transistor to the positive power supply terminal of the signal processing circuit; By connecting the gates of the serial second PMOS transistor to said positive power supply terminal, a positive power supply terminal of the signal processing circuit may be connected to the negative power supply terminal.
[0036]
In a case where the first PMOS transistor and the second PMOS transistor are configured as a CMOS circuit on a common P substrate, and the CMOS circuit and the signal processing circuit are integrally integrated, The bulk of the first PMOS transistor and the bulk of the second PMOS transistor, which are connected to the positive power supply terminal of the signal processing circuit, are connected to maintain the same potential as each other, so that the second PMOS transistor and the second PMOS transistor are connected at the same time. A through current may not flow from the bulk of one PMOS transistor to the plus power supply terminal of the signal processing circuit.
[0037]
The first PMOS transistor and the second PMOS transistor may be simultaneously formed in one N-well on the P-substrate constituting the CMOS circuit.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First example]
A first embodiment of the present invention will be described with reference to FIGS. In addition, about the same part as the conventional example of FIGS. 10-13, the description is abbreviate | omitted and the same code | symbol is attached.
[0039]
(Overview)
First, an outline of the present invention will be described.
The reverse connection prevention device according to the present invention includes a connection detection function, a connection control function, and a drive condition setting function during energization, so that a drive element (for example, a fan motor) and a signal processing device (for example, a Hall IC are connected). And a reverse power supply terminal (for example, +12 V) for electrically connecting the power supply terminal to a negative power supply terminal (for example, 0 V).
[0040]
The connection detection function refers to a function of detecting whether a positive voltage, which is a normal connection, or a negative voltage, which is a reverse connection, is applied to a positive power supply terminal.
[0041]
The connection control function maintains the normal connection state when the detection result is determined to be a normal connection, and disconnects the reverse connection state when determined that the detection result is a reverse connection. Say.
[0042]
The energizing drive condition setting function sets a predetermined electrical characteristic (for example, an on-resistance and a voltage drop) during energization so that the drive capability of the drive element can be extracted to a certain value or more when a drive current flows during normal connection. Function to satisfy the above condition.
Therefore, the reverse connection prevention device is configured by one having the above function, and a specific example thereof will be described below.
[0043]
<Structure>
FIG. 1 shows an example in which a reverse connection prevention device according to the present invention is provided in a drive control circuit 30 of a brushless two-phase fan motor.
[0044]
The drive control circuit 30 includes a reverse connection prevention device 100, a Hall IC 1, an electromagnet 2 wound with coils 2a and 2b for generating rotational torque, a driver circuit 3,
, An electrostatic protection circuit (ESD protection circuit) 5.
[0045]
In FIG. 1, the reverse connection prevention device 100 is configured by a PMOS transistor 100 (here, an enhancement type is taken as an example) formed in an independent N well.
[0046]
In the PMOS transistor 100, the drain D is connected to a positive power supply terminal 20 of +12 V via a wiring 110, the source S is connected to the positive power supply terminal a of the Hall IC 1 through a wiring (internal positive power supply node) 120, G is connected to a negative power terminal b of 0 V via a wiring 130. The bulk 105 of the PMOS transistor 100 is connected via a wiring (internal plus power supply node) 120 to the plus power supply terminal a of the Hall IC 1 as a signal processing circuit.
[0047]
FIG. 2 shows a cross-sectional configuration of the substrate circuit of FIG. The PMOS transistor 100 and the Hall IC 1 are provided on independent substrates.
[0048]
Note that the concentration was 2.6 × 10 ¹⁶ , P well region is 6.1 × 10 ¹⁶ Is set to a low concentration. The N + and P + regions are both 1.0 × 10 ¹⁹ ~ 2.0 × 10 ²⁰ Is set to a high concentration.
[0049]
<Operation>
The operation of the reverse connection prevention device 100 will be described according to the connection state.
(When connected normally)
First, the normal connection will be described.
Normally, it is assumed that 12 V is applied to the positive power supply terminal 20 and 0 V is applied to the negative power supply terminal 21 during operation of the brushless two-phase fan motor.
[0050]
In this voltage state, the PMOS transistor 100 used as the reverse connection prevention device is turned on (ON) because the gate voltage is reduced with respect to the source voltage, and supplies the operating voltage to the Hall IC 1. It is easy to make the ON (ON) resistance value of the PMOS transistor 100 about 10 ohms. At that time, the voltage drop in the PMOS transistor 100 is roughly calculated by calculating the current consumption of the Hall IC 1 × the ON resistance value of the PMOS transistor 100. Is the voltage drop
10Ω × 2mA = 20mV (3)
It becomes.
[0051]
The voltage drop value of the equation (3) can be a very small voltage drop value as compared with the diode forward voltage 0.7 V used in the reverse connection prevention device described in the related art.
[0052]
(At reverse connection)
Next, the case of reverse connection will be described.
When 0 V is applied to the positive power supply terminal 20 and +12 V is applied to the negative power supply terminal 21 by mistake, the PMOS transistor 100 used as the reverse connection prevention device is turned off (OFF) because the gate voltage becomes higher with respect to the source voltage. In this state, the through current is prevented from flowing through the Hall IC 1, so that the motor 40 can be protected from destruction.
[0053]
[Second example]
Next, a second embodiment of the present invention will be described with reference to FIGS. The description of the same parts as those in the first example is omitted, and the same reference numerals are given.
<Structure>
FIG. 3 shows an example in which the reverse connection prevention device is configured by the CMOS circuit 200. The CMOS circuit 200 includes a first PMOS transistor 210 (PMOS1) and a second PMOS transistor 220 (PMOS2).
[0054]
FIG. 4 is an example of an integrated circuit 250 in which the reverse connection prevention device 200 and the Hall IC 1 of FIG. 3 are integrated on the same P substrate by a CMOS process to be integrated.
[0055]
FIG. 5 shows a cross-sectional configuration of the CMOS circuit of FIG. 1 shows a cross-sectional structure of PMOS transistors 210 and 220 and a Hall IC 1 integrally formed on a substrate.
[0056]
In the first PMOS transistor 210 (PMOS1) formed in the independent N well shown in FIGS. 4 and 5, the drain D is connected to the + 12V positive power supply terminal 20 via the wiring 110, and the source S is connected to the wiring (Internal plus power supply node) 120, gate G is connected to minus power supply terminal b via wiring 131, and bulk 205 is connected to plus power supply terminal a of Hall IC 1 via wiring (internal plus power supply node) 120. And constitutes a first switch.
[0057]
In the second PMOS transistor 220 (PMOS2) formed in the independent N well, the drain D is connected to the minus power supply terminal 210 via the wiring 130, and the source S is provided via the wiring 120 (internal plus power supply node). The gate G is connected to the positive power supply terminal 20 via a wiring 132, the bulk 206 is connected to the positive power supply terminal a via a wiring 120 (internal positive power supply node), and the second switch Is composed.
[0058]
By connecting the positive power supply terminal a of the Hall IC 1 to the internal positive power supply node 120 and connecting the negative power supply terminal b of the Hall IC 1 to the negative power supply terminal 21 in this way, the reverse connection prevention device 200 and the Hall IC 1 are made of the same silicon. This constitutes a new IC integrated on the substrate.
[0059]
<Operation>
Next, the operation of the present apparatus will be described.
(When connected normally)
First, the normal connection will be described.
[0060]
It is assumed that +12 V is applied to the plus power supply terminal 20 and 0 V is applied to the minus power supply terminal 21 when the brushless two-phase fan motor operates.
[0061]
In this voltage state, the first PMOS transistor 210 used in the reverse connection prevention device 200 is turned on because the gate voltage is low with respect to the source voltage, while the second PMOS transistor 220 is Since the gate voltage increases with reference to the source voltage, the transistor is turned off, and the operating voltage of the Hall IC 1 is supplied through the first PMOS transistor 210.
[0062]
It is easy to set the ON resistance value of the first PMOS transistor 210 to about 10 ohms, and when the voltage drop at the first PMOS transistor 210 at that time is roughly estimated, the current consumption of the Hall IC 1 × the first PMOS transistor The voltage drop for the ON resistance value of 210 is
10 × 2 mA = 20 mV (4)
It becomes.
[0063]
A very small voltage drop can be achieved as compared with the diode forward voltage of 0.7 V used in the conventional reverse connection prevention device.
[0064]
(At reverse connection)
Next, the case of reverse connection will be described.
When 0 V is applied to the positive power supply terminal 20 and +12 V is applied to the negative power supply terminal 21 by mistake, the gate voltage of the first PMOS transistor 210 used in the reverse connection prevention device 200 becomes higher based on the source voltage. Although it is in the OFF state, when the reverse connection prevention device 200 and the Hall IC 1 are simultaneously integrated as a CMOS circuit on the P substrate, a through current actually occurs only with the first PMOS transistor 210 due to the structure of the CMOS circuit. Resulting in.
[0065]
Here, considering the cross section of the first PMOS transistor 210 of the reverse connection prevention device 200 with reference to FIG. 5, the bulk 205 of the first PMOS transistor 210 is formed on an independent N well on the P substrate, and the N A PMOS transistor is formed in the well.
[0066]
Therefore, although not shown on the circuit, there is a vertical PNP parasitic bipolar transistor 300 having a P substrate as a collector C, an N well as a base B, and a drain D of the first PMOS transistor 210 as an emitter E.
[0067]
At the time of reverse connection, the P substrate has +12 V, the drain D of the first PMOS transistor 210 has 0 V, the N well has an undefined potential, and the N well is connected to the internal plus power supply node 120. , A current flows to the N well.
[0068]
The current flowing through the N well becomes the base current of the above-described vertical PNP parasitic bipolar transistor 300, and the through current I flows through the vertical PNP parasitic bipolar transistor 300.
[0069]
Therefore, some means is required to eliminate the through current I of the vertical PNP parasitic bipolar transistor 300.
[0070]
Therefore, in the present invention, in the second PMOS transistor 220 formed in the independent N well, the drain D is connected to the minus power supply terminal 21 and the source S is connected to the plus power supply terminal a of the Hall IC 1 as a signal processing circuit. Connection, the gate G is connected to the positive power supply terminal 110, and the bulk 206 is connected to the positive power supply terminal a of the Hall IC 1; in other words, the bulk 205 of the first PMOS transistor 210 and the bulk 205 of the second PMOS transistor 220 are connected. By connecting the bulk 206 to each other and to the positive power supply terminal a of the Hall IC 1, the potential difference between the bulk 205 and the bulk 206 is eliminated so as to maintain the same potential.
[0071]
Thereby, the N-well potential of the first PMOS transistor 210 can be fixed to be the same as the potential of the P substrate, and the vertical PNP parasitic bipolar transistor 300 can be prevented from being turned on.
[0072]
At the time of reverse connection, the second PMOS transistor 220 is turned ON because the gate voltage is lowered with reference to the source voltage, and the N-well of the first PMOS transistor 210, that is, the base potential of the vertical PNP parasitic bipolar transistor 300 Is fixed to be the same potential as the P substrate potential, so that the vertical PNP parasitic bipolar transistor is not turned on.
[0073]
With such wiring, the through current I is prevented from flowing through the Hall IC 1 and the motor can be protected from destruction.
[0074]
Further, what has been described above can also be configured by using NMOS transistors instead of PMOS transistors. That is, the positive power terminal 20 is connected to the negative power terminal 21, the positive power terminal 20 of the Hall IC 1 as a signal processing circuit is connected to the negative power terminal 21 of the Hall IC 1 as a signal processing circuit, and the negative power terminal 21 is connected to the positive power terminal 20. A similar configuration can be obtained simply by replacing the CMOS circuit on the P substrate with the CMOS circuit on the N substrate.
[0075]
[Third example]
A third embodiment of the present invention will be described with reference to FIGS. The description of the same parts as those in the above-described examples is omitted, and the same reference numerals are given.
[0076]
6 to 8 show modified examples of the reverse connection prevention device 400. 6 is configured as a reverse connection prevention device 400 by a PNP transistor 401, in the example of FIG. 7, by a PNP transistor and a resistor 402, and in the example of FIG. 8 by a relay 403 and a diode 404.
[0077]
FIG. 9 compares various characteristics including the electrical characteristics of the reverse connection prevention device according to the present invention with those of the conventional circuit.
[0078]
Here, the reverse connection prevention device 100 of FIG. 1, the reverse connection prevention device 200 of FIG. 4, and the reverse connection prevention device 400 of FIGS. 6 and 7 are taken as an example, and the ON resistance 500, the voltage drop 501, and the driver driving capability (standard) Values) 502, a driver area 503, and the presence or absence of integration 504 with the Hall IC 1 were compared and examined.
[0079]
As can be seen from FIG. 9, the values of the ON resistance 500 and the voltage drop 501 are set much lower than those of the conventional circuit.
[0080]
As a result, the driver driving capability 502 can be expanded to a range of about 1.7 to 2.3 times the conventional circuit. Further, the driver area 503 can be reduced to about 1/2 or less as compared with the conventional circuit.
[0081]
As can be seen from the above comparison, the driver driving capability 502 can be significantly improved, the driver area 503 can be reduced, and an integrated configuration can be obtained. can do.
[0082]
(Example of calculation)
Here, comparison will be made with reference to calculation examples.
It is assumed that the motor power supply voltage = 3 V and the current consumption of the Hall IC = 2 mA. At this time, the driving capability of the driver (drive control circuit)
IDS = K * W / L * (VGS-VTH) * (VGS-VTH) (5)
Where IDS: current flowing through MOS, K: constant determined by process,
W: gate width, L: gate length, VGS: gate-source voltage,
VTH: threshold
And is proportional to the square of the voltage.
Here, for simplicity of calculation, K = 1, W = 1, L = 1, and VTH = 1.
[0083]
As a calculation example, when a diode is used, there is a voltage drop (loss) of 0.7 V, and the maximum voltage applied to the gate of the driver MOS transistor is:

The driving capacity is calculated from the equation (5).
1.69 = (2.3-1) × (2.3-1) (6)
Note that the driving capability of the driver in FIG. 9 is for the purpose of making the effects of the prior art and the invention easy to understand, and is different from the current value that is actually passed. However, while the conventional technology has a capability of 1.69 A, the present invention can be used to assist in considering that it has a capability of 3.92 A.
[0084]
Also, as a measure to take advantage of the improvement of the driving capability of the driver,
(A) If the specification is 3V, the size of the driver can be reduced (the package is not changed in terms of heat radiation).
(B) a larger motor can be driven without changing the size of the driver;
(C) a small package without changing the size of the driver and the capacity of the motor;
And the like.
[0085]
【The invention's effect】
As described above, according to the present invention, the function of detecting reverse connection, the function of disconnecting the state of reverse connection when it is determined that the connection is reverse, and the function of driving the drive element at a constant value during normal connection. A function for setting predetermined electrical characteristics (on resistance and voltage drop) at the time of energization to predetermined conditions is provided so that the circuit element can be prevented from being broken in case of reverse connection by mistake, It is possible to manufacture a reverse connection prevention device capable of remarkably improving the driver driving capability and reducing the size and cost.
[0086]
Further, according to the present invention, since the bulks of the transistor elements are connected to each other by the compensating wiring so as to have the same potential and eliminate the potential difference, it is possible to prevent a through current caused by the vertical parasitic transistor and to reduce In addition, a reverse connection prevention device and a signal processing circuit can be integrated with each other by a CMOS process to produce an integrated circuit, thereby eliminating the need for an external reverse connection prevention device using individual components, and making the device more compact and inexpensive. Can be produced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example in which a reverse connection prevention device according to a first embodiment of the present invention is configured by a PMOS transistor and provided in a drive control circuit of a brushless two-phase fan motor.
FIG. 2 is a sectional view showing a sectional configuration of the substrate circuit of FIG. 1;
FIG. 3 is a circuit diagram showing an example in which a reverse connection prevention device according to a second embodiment of the present invention is configured by a CMOS circuit.
4 is a circuit diagram showing an example in which the reverse connection prevention device and the Hall IC of FIG. 3 are integrated on the same P substrate by a CMOS process.
FIG. 5 is a cross-sectional view illustrating a cross-sectional configuration of the CMOS circuit of FIG. 4;
FIG. 6 is a circuit diagram showing an example in which a reverse connection preventing device according to a third embodiment of the present invention is configured by a PNP transistor.
FIG. 7 is a circuit diagram showing an example in which a reverse connection prevention device according to a third embodiment of the present invention is configured by a PNP transistor and a resistor.
FIG. 8 is a circuit diagram showing an example in which a reverse connection prevention device according to a third embodiment of the present invention is configured by a relay and a diode.
FIG. 9 is an explanatory diagram showing electrical characteristics of the present invention in comparison with a conventional example.
FIG. 10 is a circuit diagram showing a first conventional example.
FIG. 11 is a circuit diagram showing a second conventional example.
FIG. 12 is a circuit diagram showing a third conventional example.
FIG. 13 is a circuit diagram showing an internal configuration of a Hall IC.
FIG. 14 is a configuration diagram showing an internal configuration of a brushless two-phase fan motor.
[Explanation of symbols]
1 Hall IC
2 electromagnet
2a, 2b coil
3 Driver circuit
4 Reverse connection prevention circuit
5 Electrostatic protection circuit
6,7 Driver (NPN transistor)
6a, 7a Driver (NMOS transistor)
8 Resistance
9 Capacitor
11 Voltage regulator circuit
12 hole plate
13 signal processing unit
14, 15 output buffer circuit
20 Positive power supply terminal (+ 12V)
21 Negative power supply terminal (0V)
30 Drive control circuit
40 brushless two-phase fan motor
41 Rotor
42 Stator
50 power supply
100 Reverse connection prevention device (PMOS transistor)
105 Bulk
110 Wiring
120 Wiring (internal plus power supply node)
130-132 wiring
200 Reverse connection prevention device (CMOS circuit)
205, 206 Bulk
210 First PMOS transistor (PMOS1)
220 Second PMOS transistor (PMOS2)
250 integrated circuit
300 Vertical PNP parasitic bipolar transistor
400 Reverse connection prevention device
401 PNP transistor
402 resistance
403 relay
404 diode
500 ON resistance
501 Voltage drop
502 Driver driving capability (standard value)
503 Driver area
504 Integration status
a Positive power supply terminal of Hall IC
b Hall IC negative power terminal
c Hall IC output terminal
d Hall IC output terminal

Claims (8)

A reverse connection prevention device that is used for electrical connection between a power supply and a signal processing device and that determines a connection mode between a positive power supply terminal and a negative power supply terminal to prevent reverse connection,
Connection detection means for detecting whether a positive voltage that is a normal connection is applied to the positive power supply terminal, or a negative voltage that is a reverse connection is applied,
When it is determined that the detection result is a normal connection, the state of the normal connection is maintained as it is, and when it is determined that the detection result is a reverse connection, connection control means for disconnecting the state of the reverse connection is provided. A reverse connection prevention device, comprising: The signal processing device includes a Hall IC that drives and controls a motor,
The on-resistance during energization is set such that the driving capability of the motor is at least 1.5 times the reference value and the driver integration area including the Hall IC is about half or less of the reference value. 2. The reverse connection prevention device according to claim 1, wherein the voltage drop is set to a predetermined value or less. The connection control means includes one switch;
The switch is
In the case of a normal connection in which a positive voltage is applied to the plus power terminal with reference to the minus power terminal, the normal connection potential state is detected, and the plus power terminal of the signal processing circuit is connected. Connect to the plus power terminal,
In the case of a reverse connection in which a negative voltage is applied to the plus power terminal with respect to the minus power terminal, the potential of the reverse connection is detected, and the positive power terminal and the signal processing circuit are connected. The reverse connection prevention device according to claim 1 or 2, wherein the connection to the positive power supply terminal is disconnected. The switch comprises a PMOS transistor formed in an independent N-well,
At the time of the normal connection,
The drain of the PMOS transistor is connected to the positive power supply terminal, the source of the PMOS transistor is connected to the positive power supply terminal of the signal processing circuit, and the gate of the PMOS transistor is connected to the negative power supply terminal. Connect the positive power terminal of the processing circuit to the positive power terminal,
At the time of the reverse connection,
By connecting the drain of the PMOS transistor to the minus power supply terminal and connecting the gate of the PMOS transistor to the plus power supply terminal, it is possible to disconnect the connection between the plus power supply terminal and the plus power supply terminal of the signal processing circuit. 4. The reverse connection prevention device according to claim 3, wherein: The connection control means includes a first switch and a second switch,
The first switch includes:
In the case of a normal connection in which a positive voltage is applied to the plus power terminal with reference to the minus power terminal, the normal connection potential state is detected, and the plus power terminal of the signal processing circuit is connected. Connect to the plus power terminal,
The second switch includes:
In the case of a reverse connection in which a negative voltage is applied to the plus power terminal with respect to the minus power terminal, it is detected that the potential is in the reverse connection, and the plus power terminal of the signal processing circuit is connected to the minus power terminal. 3. The reverse connection prevention device according to claim 1, wherein the reverse connection prevention device is connected to a negative power supply terminal. The first switch comprises a first PMOS transistor formed in an independent N-well,
The second switch comprises a second PMOS transistor formed in an independent N-well,
At the time of the normal connection,
The drain of the first PMOS transistor is connected to the positive power supply terminal, the source of the first PMOS transistor is connected to the positive power supply terminal of the signal processing circuit, and the gate of the first PMOS transistor is connected to the negative power supply. Connecting the positive power supply terminal of the signal processing circuit to the positive power supply terminal,
At the time of the reverse connection,
The drain of the second PMOS transistor is connected to the minus power supply terminal, the source of the second PMOS transistor is connected to the plus power supply terminal of the signal processing circuit, and the gate of the second PMOS transistor is connected to the plus power supply. The reverse connection prevention device according to claim 5, wherein a positive power supply terminal of the signal processing circuit is connected to the negative power supply terminal by connecting to the terminal. In the case where the first PMOS transistor and the second PMOS transistor are configured as a CMOS circuit on a common P substrate and the CMOS circuit and the signal processing circuit are integrally integrated,
The bulk of the first PMOS transistor and the bulk of the second PMOS transistor, which are connected to a positive power supply terminal of the signal processing circuit, are connected to maintain the same potential with each other. 7. The reverse connection prevention device according to claim 6, wherein a through current does not flow from a bulk of the first PMOS transistor to a positive power supply terminal of the signal processing circuit. 8. The reverse connection prevention according to claim 7, wherein the first PMOS transistor and the second PMOS transistor are simultaneously formed in one N-well on the P substrate constituting the CMOS circuit. apparatus.

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