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JP2004153130A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004153130A
JP2004153130A JP2002318206A JP2002318206A JP2004153130A JP 2004153130 A JP2004153130 A JP 2004153130A JP 2002318206 A JP2002318206 A JP 2002318206A JP 2002318206 A JP2002318206 A JP 2002318206A JP 2004153130 A JP2004153130 A JP 2004153130A
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chip
semiconductor
semiconductor element
semiconductor device
chips
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JP2002318206A
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Japanese (ja)
Inventor
Shigeru Hosogai
茂 細貝
Kenji Miyata
憲治 宮田
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Olympus Corp
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Olympus Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device allowed to be highly integrated and miniaturized and having a function equivalent to a system on-chip. <P>SOLUTION: A plurality of semiconductor element chips 1a-1d are aligned at a narrow pitch so that the surfaces of respective chips 1a-1d are on the same plane and arranged like an array and gaps between respective semiconductor element chips 1a-1d are sealed by insulating seal resin 4, a reinforcing material 5 is stuck to the rear faces of these chips 1a-1d, and a stress buffering layer 6 is formed on the surfaces of the chips 1a-1d. Via-holes 7 are formed on the stress buffering layer 6 and metallic wires 2 are formed so as to electrically connect respective semiconductor element chips 1a-1d to constitute a semiconductor device. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は、複数の半導体素子チップをアレイ状に配置構成した半導体装置、特にはシステムオンチップと同等の機能を有する半導体システムチップアレイを形成した半導体装置に関する。
【０００２】
【従来の技術】
【特許文献１】特開２００１−１５６２４５号公報
【０００３】
近年、例えば携帯機器を中心として小型化が進み、それに伴ってその筐体及び内部回路基板においても、更なる小型化が求められている。これにより、回路基板への実装部品の一つである半導体素子についても、実装実効面積の縮小を強いられることになっている。これを解決する一つの手法として、ロジック回路やアナログ回路、更にはメモリ等を同一のシリコンチップに集積するシステムオンチップが挙げられる。
【０００４】
システムオンチップは、システムとして機能する構成要素を１チップ内で収めることが出来るというメリットを持つ反面、高い耐圧性能が要求されると共に、微細化が困難なアナログ回路と年々シュリンクを続けるロジック回路の混載を両立可能とする製造プロセスの開発が難しいため、開発期間が長くなる傾向にあり、ひいてはコスト上昇につながるという弊害がある。
【０００５】
これらの不具合を解決するものとして、近年マルチチップモジュールの流れを汲んだ、システムインパッケージの手法が脚光をあびている。このような実装形態の１例として、特開２００１−１５６２４５号公報（特許文献１）に示されるような実装形態が提案されている。この公報提案の半導体装置を、図１８の（Ａ），（Ｂ）に示す。図１８の（Ａ）は平面図で、図１８の（Ｂ）は図１８の（Ａ）のＸ−Ｘ′線に沿った断面図であり、主表面に接続電極をそれぞれ有する複数のＩＣベアチップ１０１ ，１０２ ，１０３ ，１０４ が、一方面側に外部端子１０８ が配され、他方面側にこの外部端子とつながる導電パターンが設けられた実装用基材１０５ に、異方性導電膜１０６ によるフリップチップ実装がなされている。更に、複数のＩＣベアチップ １０１〜１０４ の裏面は、共通に硬質板１０７ に接着層１０９ を介して固着されて、ＩＣベアチップのマルチチップモジュールは、パッケージとしての一体構造となっているものである。ここで、各ＩＣベアチップ間の相互配線は、実装用基材１０５ 上に設けられた導電パターンにより行われている。
【０００６】
このような構造とすることにより、高密度実装でコンパクトなパッケージとして、一体構造がとりやすく、速い納期にも応じられるマルチチップモジュールを実現する半導体装置が可能になった。
【０００７】
【発明が解決しようとする課題】
しかしながら、上記提案の従来例にも、次のような課題がある。まず、ＩＣベアチップを実装用基材に実装する必要があるため、マルチチップモジュールとしての高さが増加してしまう。更に、ＩＣベアチップの裏面側には硬質板を接着するため、最終形態の高さは更に増加することになる。また、このように、ＩＣベアチップの表面側を実装用基材にフリップチップ実装し、裏面側を硬質板に接着する構造は、固体撮像素子チップなど受光部を備えたＩＣベアチップには不向きであると共に、上記公報開示の提案では、これらに関しては何も考慮がなされていない。
【０００８】
また、バンプ加工を施したチップを実装用基材に実装する際には、アライメントを行う以外に圧着、加熱のプロセスを個々にチップに施さねばならず、生産性が悪くコストアップを招くと共に、作業性にも不安がある。更に、チップを実装するための実装用基材を別途用意する必要があるが、微細パターンを施すと共に多層化した積層基板は、現在のところ非常に高価である。
【０００９】
本発明は、従来提案の半導体装置における上記問題点を解消するためになされたもので、更なる高集積化及び小型化が可能であると共に、チップ間の相互配線も容易に行われ、信頼性があり、種々の実装形態への応用が可能なシステムオンチップと同等の機能を有する半導体装置を提供することを目的とする。
【００１０】
請求項毎の目的を述べると、次の通りである。すなわち、請求項１に係る発明は、薄型化が可能で、複数の半導体素子チップを並べたウエハーと同等の半導体システムチップアレイを構成することが可能な半導体装置を提供することを目的とする。請求項２に係る発明は、複数種類の半導体チップで構成した半導体装置を提供することを目的とする。請求項３に係る発明は、一部を固体撮像素子チップで構成した半導体装置を提供することを目的とする。請求項４に係る発明は、薄型化された平板状の半導体装置を提供することを目的とする。請求項５に係る発明は、半導体素子チップを積層した積層半導体チップユニットをアレイ化した半導体装置を提供することを目的とする。
【００１１】
また請求項６に係る発明は、半導体素子チップ間及び外部端子との最適な電気的接続構造を備えた半導体装置を提供することを目的とする。請求項７に係る発明は、半導体素子チップ間の最適な配線構造及び外部端子との最適な電気的接続構造を備えた半導体装置を提供することを目的とする。請求項８に係る発明は、薄型化が可能で、複数の半導体素子チップを並べたウエハーと同等の半導体システムチップアレイを形成することが可能な半導体装置の製造方法を提供することを目的とする。請求項９に係る発明は、半導体素子チップを正確に且つ容易に位置合わせを行うことが可能な半導体装置の製造方法を提供することを目的とする。
【００１２】
【課題を解決するための手段】
上記問題点を解決するため、請求項１に係る発明は、複数の半導体素子チップを、各チップ表面が同一平面をなすようにアライメントを行ってアレイ状に配置し、各チップ間及び周辺を絶縁性樹脂で樹脂封止して半導体システムチップアレイを形成し半導体装置を構成するものである。
【００１３】
このように構成した半導体装置においては、薄型化が可能で、複数の半導体素子チップをアレイ状に並べたウエハーと同等の半導体システムチップアレイ構成をもつ半導体装置を実現することができる。
【００１４】
請求項２に係る発明は、請求項１に係る半導体装置において、前記複数の半導体素子チップは、複数種類の半導体素子チップであることを特徴とするものである。このように構成することにより、複数種類の半導体素子チップで構成した半導体装置が得られる。
【００１５】
請求項３に係る発明は、請求項１又は２に係る半導体装置において、前記複数の半導体素子チップの少なくとも１つは、固体撮像素子チップであることを特徴とするものである。このように構成することにより、固体撮像素子チップを備え、小型化され高信頼性の受光センサへの応用が容易な半導体装置が得られる。
【００１６】
請求項４に係る発明は、請求項１〜３のいずれか１項に係る半導体装置において、前記半導体素子チップは、単体の半導体素子チップで構成されていることを特徴とするものである。このように構成することにより、薄型化された平板状の半導体装置が得られる。
【００１７】
請求項５に係る発明は、請求項１〜３のいずれか１項に係る半導体装置において、前記半導体素子チップは、複数の半導体素子チップを積層してなる半導体素子チップユニットで構成されていることを特徴とするものである。このように構成することにより、半導体素子チップを積層した半導体素子チップユニットをアレイ化した半導体装置が得られる。
【００１８】
請求項６に係る発明は、請求項５に係る半導体装置において、前記半導体チップユニットを構成する前記複数の半導体素子チップは、チップ側面、あるいはチップ側面を通って裏面に亘って、チップ間の電気的接続あるいは外部端子との電気的接続を行う配線領域を形成していることを特徴とするものである。このように構成することにより、半導体素子チップ間及び外部端子との最適な電気的接続構造を備えた半導体装置が得られる。
【００１９】
請求項７に係る発明は、請求項１〜６のいずれか１項に係る半導体装置において、前記半導体システムチップアレイは、表面に応力緩和層を備え、該応力緩和層上に前記複数の半導体素子チップ間を電気的に接続するための配線領域と、外部端子との電気的接続を行う突起電極とを形成していることを特徴とするものである。このように構成することにより、半導体素子チップ間の最適な配線構造、及び外部端子との最適な電気的接続構造を備えた半導体装置が得られる。
【００２０】
請求項８に係る発明は、請求項１〜７のいずれか１項に係る半導体装置の製造方法において、複数の半導体素子チップを接着剤を介して基材部に、各チップ表面が同一平面をなすようにアライメントを行って貼り付ける工程と、前記複数の半導体素子チップを絶縁性樹脂で樹脂封止を行う工程と、前記基材部を剥離する工程とを少なくとも備え、前記樹脂封止された複数の半導体素子チップからなる半導体システムチップアレイを形成することを特徴とするものである。
【００２１】
このように構成された半導体装置の製造方法によれば、薄型化が可能で複数の半導体素子チップを並べたウエハーと同等の半導体システムチップアレイ構成をもつ半導体装置を容易に製造することができる。
【００２２】
請求項９に係る発明は、請求項８に係る半導体装置の製造方法において、前記基材部は、アライメント用の位置合わせマークが形成されていることを特徴とするものである。このように構成することにより、半導体素子チップを正確に且つ容易に位置合わせを行って半導体装置を製造することが可能となる。
【００２３】
【発明の実施の形態】
次に、実施の形態について説明する。まず、本発明の第１の実施の形態について説明する。図１及び図２は、それぞれ本発明に係る半導体装置の第１の実施の形態を一部省略して示す斜視図及び平面図で、図３は図２のＡ−Ａ′線に沿った省略部分を含む断面図を示す。図１〜３において、１ａ，１ｂ，１ｃ，１ｄは、それぞれ機能が異なる非積層の平面状に配置した単体の半導体素子チップで、通常のＩＣなどと同様にパッシベーション膜までウエーハ状態で製造され、検査後に個片化された良品の半導体素子チップである。これらの半導体素子チップ１ａ〜１ｄは極力狭ピッチで配置され、各半導体素子チップ間は絶縁性の樹脂４で封止されており、これらの平面状に配置された複数の半導体素子チップ裏面には、補強材５が接着されている。また半導体素子チップ表面には応力緩和層６が形成され、必要に応じてビアホール７を設けると共に、応力緩和層６上には金属配線２が形成されて、各半導体素子チップ１ａ〜１ｄ間の電気的接続がなされている。更に、応力緩和層６上には保護膜８が形成されて、該保護膜８の必要個所にはビアホール９と共に外部電極との電気的接続を行うための突起電極３が形成されている。なお、図１及び図２においては、先に述べたように、応力緩和層６及び保護膜８の図示が省略されているが、応力緩和層６上に形成される金属配置線２及び保護膜８上に形成される突起電極３は、模式的に図示している。
【００２４】
このようにして、種々の機能を有する複数の半導体素子チップ１ａ〜１ｄから、新たに多機能化された半導体システムチップアレイが形成される。したがって、システムオンチップと同等あるいはそれ以上の機能を有しながら、更なる高集積化及び小型化が可能であると共に、半導体素子チップ間の相互配線も容易に行われて電気的特性の劣化もなく、信頼性があり、種々の実装形態への応用が可能な半導体装置が実現可能となる。
【００２５】
次に、第１の実施の形態に係る半導体装置の製造方法を、図４乃至図１２を参照しながら説明する。本半導体装置の製造にあたっては、単一の半導体装置すなわち単一の半導体システムチップアレイのみを製造するのではなく、ウエーハに複数のＩＣチップを製造するのと同様に、複数の半導体システムチップアレイを同時に製造するものである。まず図４に示すように、位置合わせ用のアライメントマークを施した基材１０に接着剤１１を介して、アライメントを行って異なる機能を有する複数の半導体素子チップ１の表面側を接着する。接着剤としてはエポキシ系の接着剤が望ましいが、半導体素子チップ表面が正確に同一平面上に揃えられるように貼り合わせることができ、且つ半導体素子チップに特性上の悪影響を与えるものでなければ、接着剤の種類及び材質は問わない。貼り合わされる基材１０の材質は、プラスチックやセラミックなど考えられるが、ガラスなど透明な材質のものを使用することにより、貼り合わせの様子が観察でき、更なる正確なアライメントが可能となる。
【００２６】
次に、図５に示すように、半導体素子チップ１の裏面側及び該チップ間の隙間を、樹脂４により樹脂封止を行う。この封止樹脂４としては、絶縁性であると共に、半導体チップ１の特性に悪影響を与えない材質が必要となり、エポキシ系あるいはシリコン系樹脂や紫外線硬化型の接着剤などが好ましい。しかしながら、これらに限定されることはなく、前述した特性を有するものであれば、その種類及び材質は問わない。
【００２７】
続いて図６に示すように、半導体素子チップ１の裏面が剥き出し状態になるまで、封止樹脂４を研磨する。更に、チップアレイの薄型化を図りたい場合には、半導体素子チップ自体をも研磨して、全体を薄くしてもよい。
【００２８】
次に、図７に示すように、研磨面すなわち半導体素子チップ裏面側に補強材５を貼り付け、半導体素子チップ表面側の基材１０を接着剤１１ごと剥離する。補強材５の材質としては、セラミックやガラスなど挙げられるが、熱による線膨張係数が低く、絶縁性があり、形成されたチップアレイを保持出来る強度を備えたものであれば、有機、無機材料に関わらず、その材質は問わない。この状態で、機能の異なる半導体素子チップが複数個規則正しく配列され、且つチップ表面が同一平面上に揃えられることにより、後述する半導体製造の前工程に準ずるスパッタや蒸着などの薄膜形成や、ビア形成などの手法が使え、且つこの工程をバッチ処理で行えるようになる、半導体システムチップアレイのベースとなる半導体基板が完成する。
【００２９】
次に、図８に示すように、図７に示した半導体基板の表裏を反転して、半導体素子チップ表面に応力緩和層６を形成する。この応力緩和層６は、本半導体装置を更に別のボードに、突起電極を介して接合する際に、接合部分の応力や負荷を分散させて、接合信頼性を確保するためのものであり、材料としては、シアノアクリレート類、ポリウレタンやシリコンベース類の接着剤及び接着フィルム、並びにエポキシ類樹脂及び樹脂フィルム、並びにポリイミド類のフィルムなど挙げられるが、応力開放に関して所望の特性（弾性、厚み、絶縁性）が得られれば、何を用いてもよい。
【００３０】
次に、図９に示すように、各半導体素子チップ間の相互配線及び外部電極接続用に、応力緩和層６に対して必要に応じてビアホール７を設けると共に、金属配線２を形成する。ビアホール７の形成は、フォトエッチングが一般的であり望ましい。金属配線２としては、Ａｌ が一般的であるが、この他にもＣｕ やＴｉ など、通常の半導体プロセスでの配線工程に使用される配線材料でもよいことは言うまでもない。金属配線２の形成においては、全面に金属膜を形成後フォトエッチにより配線パターンを形成してもよいし、印刷によって形成してもよい。
【００３１】
次に，図１０に示すように、半導体素子チップアレイ上に絶縁層となる保護膜８を塗布する。保護膜８としては、電気的に絶縁性があり、且つ耐湿性があり、後述するような加工（ビアホール加工、メタライゼーション）が容易であれば、その材質は問わない。また、形成方法としては、スピンコートによって塗布してもよいし、印刷によって形成してもよいが、後述するようにビアホールを設ける必要があるため、２０〜３０μｍ程度の厚さが望ましい。しかしながら、ビアホールの形成が可能であれば、保護膜の厚さは、この限りではない。
【００３２】
続いて、図１１に示すように、保護膜８にビアホール９の形成を行い、ビアホール９内に金属材料を充填すると共に、ビアホール９上に外部端子との電気的接続手段となる突起電極３を形成する。ビアホール９の形成には、通常レーザー加工が一般的であるが、絶縁層である保護膜８の深さに対応したディープエッチが可能であれば、フォトエッチングでもよい。ビアホール９内に充填する金属としては、Ａｌ やＣｕ などが挙げられるが、通常の半導体プロセスのビアホールやコンタクト形成に用いられる金属材料を流用しても勿論かまわない。また、必要に応じて、金属配線２を形成する配線層と保護膜８を形成する絶縁層を、それぞれ複数層形成しても構わない。その後、ビアホール９上に外部端子との電気的接続を行うために、ニッケルあるいは金メッキを施した上、突起電極３を形成する。もしくは、ビアホール９上に改めて金属配線層を形成した上で、同様にして突起電極３を形成する。突起電極３としては、通常半田やＣｕ のバンプあるいは半田ボールなどが用いられるが、他の基板に対して電気的接続が不具合なく取れるようであれば、その形状、製造方法は問わない。
【００３３】
以上のような製造方法により、例えば、図１２に示すような複数の半導体素子チップからなる半導体システムチップアレイが複数個形成された半導体システムチップアレイ群ができる。なお、図１２においても、応力緩和層６及び保護膜８の図示が省略されている。ここで、スクライブライン１２に沿ってダイシングすることにより、図１に示すような単体の半導体システムチップアレイが完成する。ここで、ビアホール上での金属配線を自由に引き回すことにより、この金属配線上に形成する突起電極の任意の配列が可能となる。勿論、各半導体素子チップ内の回路素子から直上に最短距離で突起電極まで金属配線を引き出せることは言うまでもない。また、本実施の形態では、突起電極位置がランダムに記載されているが、半導体素子チップにかかる応力を分散させるため、ダミーバンプの配設を含めて、チップ中心に対して対称に形成してもよい。
【００３４】
また、本実施の形態では金属配線層は単層としたものを示したが、多層化することにより電源層あるいは接地層を設けることが可能となり、電気的特性の向上が図れる。更に半導体素子チップ間は、絶縁性樹脂で絶縁されているため、事実上の確実な素子分離が図られていることとなり、電気的にも非常に有利となる。また、各半導体素子チップ間の相互配線等を最短距離でレイアウトして信号の劣化を防ぐことにより、更に電気的特性を向上させることが可能となる。
【００３５】
更に、本実施の形態では、半導体システムチップアレイの表面側に、外部端子との電気的接続手段である突起電極（バンプ）を設けたものを示したが、表面側に突起電極を設けるのではなく、次のように突起電極を設けてもよい。すなわち、ダイシングして単体の半導体システムチップアレイを形成した後、該チップアレイの表面側のビアホールから側面に、あるいは側面から裏面にわたって配線領域を形成する。そして、その配線領域上に外部端子との電気的接続手段である突起電極などを形成してもよい。このような構造とすることにより、種々の実装形態への応用が可能となる。
【００３６】
更に、本実施の形態では、半導体装置となる半導体システムチップアレイを構成する複数の半導体素子チップの種類には何等制限はなく、本実施の形態はあらゆる種類の半導体素子チップに応用可能である。すなわち、デジタル・アナログの分け隔てなく、これらの半導体素子チップを混載することが可能となる。例えば、固体撮像素子などの受光センサチップと、駆動回路及び信号処理回路などのＩＣチップを集積化して、１システムチップアレイ化することも可能である。このような構成によれば、複雑且つ大規模な駆動回路あるいは信号処理回路により１チップ化できなかった固体撮像装置も、小型化できると共に、撮像特性への悪影響の心配もない信頼性のある固体撮像装置が実現できる。また、チップアレイの裏面に貼り付ける補強材５や、この補強材５を半導体システムチップアレイに貼り付ける接着剤として、光学的な透過率の高い材料を使用することにより、裏面照射型撮像素子のシステムチップアレイ化にも対応可能となる。
【００３７】
次に、第２の実施の形態について説明する。本実施の形態は、第１の実施の形態のように、良品チップ単体を平面状に配置して、半導体システムチップアレイを構成するのではなく、図１３に示すような、複数の半導体素子チップを積層してなる積層半導体チップユニット２１をアレイ状に配置して半導体システムチップアレイを形成し、半導体装置を構成するものである。図１３において、２２ａ，２２ｂ，２２ｃは機能が異なる半導体素子チップで、通常のＩＣチップなどと同様にパッシベーション膜までウエーハ状態で製造され、検査後に個片化された良品の半導体素子チップである。２３は各半導体素子チップ２２ａ，２２ｂ，２２ｃの電極パッドからチップ側面及び裏面にまで形成された配線領域、２４は各半導体素子チップ間の電気的接続を行うための配線領域２３上に形成された突起電極である。そして、このように構成されている複数の積層半導体チップユニット２１を、第１の実施の形態と同様に、僅かな間隔をおいてアレイ状に配置し、封止樹脂で封止して半導体装置を構成している。また、本積層半導体チップユニット２１の表面あるいは裏面に、外部との電気的接続を行うための突起電極を設けてもよいことは言うまでもない。
【００３８】
次に、本実施の形態に係わる半導体装置の製造方法について説明する。本実施の形態に係る半導体装置の製造方法は、基本的には第１の実施の形態の半導体装置の製造方法と同様であるため、図１４〜図１７を参照しながら簡単に説明する。なお、本積層半導体チップユニット自体の製造方法については、その説明を省略する。まず、図１４に示すように、複数の積層半導体チップユニット２１の表面側を接着剤２５を介して基材２６に接着する。次に、図１５に示すように、樹脂２７にて封止を行う。ここで、封止樹脂２７としては、積層半導体チップユニット２１の隙間にも十分入り込めるだけの低い粘性を有していれば、その種類は問わない。次に、図１６に示すように、封止樹脂２７を研磨などして、積層半導体チップユニット２１の最下層チップのチップ裏面を露出させる。ここでは、研磨後に配線領域２３が露出される様に高精度に研磨することで、裏面に接続手段を確保することも可能になる。
【００３９】
続いて、図１７に示すように、補強材２８を裏面側に接着した後に、基材２６及び接着剤２５を除去する。最後に第１の実施の形態と同様に、必要に応じて各積層半導体チップユニット２１間の配線を表面上に形成すると共に、外部電極との電気的接続を行うための突起電極を形成する（図示せず）。これにより、積層半導体チップユニットを用いた場合もシステムチップアレイを形成することが可能となる。なお、本実施の形態で用いる接着剤、基材及び補強材、更には突起電極は、第１の実施の形態で用いたものが使用可能である。
【００４０】
このような第２の実施の形態に係る半導体装置の構成及び製造方法により、擬似的にウエハーを積層したものと等価な半導体システムチップアレイからなる半導体装置を実現することができ、生産性がよく、コストの点でも有意である。また、同一の半導体チップでなく、複数種類の半導体チップを積層した積層半導体チップユニットについても、同様の手法を用いることにより、擬似的にウエハーを積層したものと等価な半導体システムチップアレイからなる半導体装置を実現することができ、生産性がよく、コストの点でも有意である。
【００４１】
【発明の効果】
以上実施の形態に基づいて説明したように、請求項１に係る発明によれば、薄型化が可能で複数の半導体素子チップをアレイ状に並べたウエハーと同等の半導体システムチップアレイ構成をもつ半導体装置を実現することができ、また各チップ表面が同一平面をなすように配列された各チップ間段差のない構成をもたせることにより、半導体製造の前工程に準ずるスパッタや蒸着などの薄膜形成や、ビア等の形成手法が使え、且つこの工程をバッチ処理で行う手法などを用いることが可能となる。また請求項２に係る発明によれば、複数種類の半導体チップで構成した半導体装置を得ることができる。また請求項３に係る発明によれば、固体撮像素子チップを備え、小型化され高信頼性の受光センサへの応用が容易な半導体装置が得られる。また請求項４に係る発明によれば、薄型化された平板状の半導体装置が得られる。また請求項５に係る発明によれば、半導体素子チップを積層した積層半導体チップユニットをアレイ化した半導体装置を得ることができる。また請求項６に係る発明によれば、半導体素子チップ間及び外部端子との最適な電気的接続構造を備えた半導体装置が得られる。また請求項７に係る発明によれば、半導体素子チップ間の最適な配線構造、及び外部端子との最適な電気的接続構造を備えた半導体装置が得られる。また請求項８に係る発明によれば、薄型化が可能で複数の半導体素子チップを並べたウエハーと同等の半導体システムチップアレイをもつ半導体装置を容易に製造することができる。また請求項９に係る発明によれば、半導体素子チップを正確に且つ容易に位置合わせを行って半導体装置を製造することができる。
【図面の簡単な説明】
【図１】本発明に係わる半導体装置の第１の実施の形態を一部省略して示す斜視図である。
【図２】図１に示した第１の実施の形態を一部省略して示す平面図である。
【図３】図２のＡ−Ａ′線に沿った断面を省略部分を含めて示す第１の実施の形態の断面図である。
【図４】本発明に係わる第１の実施の形態の半導体装置の製造方法を説明するための製造工程を示す断面図である。
【図５】図４に示した製造工程に続く製造工程を示す断面図である。
【図６】図５に示した製造工程に続く製造工程を示す断面図である。
【図７】図６に示した製造工程に続く製造工程を示す断面図である。
【図８】図７に示した製造工程に続く製造工程を示す断面図である。
【図９】図８に示した製造工程に続く製造工程を示す断面図である。
【図１０】図９に示した製造工程に続く製造工程を示す断面図である。
【図１１】図１０に示した製造工程に続く製造工程を示す断面図である。
【図１２】図４〜図１１に示した製造工程で製造された半導体システムチップアレイ群を一部省略した状態で示す斜視図である。
【図１３】本発明の第２の実施の形態の積層半導体チップユニットを示す断面図である。
【図１４】本発明の第２の実施の形態に係る半導体装置の製造方法を説明するための製造工程を示す断面図である。
【図１５】図１４に示した製造工程に続く製造工程を示す断面図である。
【図１６】図１５に示した製造工程に続く製造工程を示す断面図である。
【図１７】図１６に示した製造工程に続く製造工程を示す断面図である。
【図１８】従来提案の混載集積回路装置の一例を示す平面図及び断面図である。
【符号の説明】
１，１ａ，１ｂ，１ｃ，１ｄ，２２ａ，２２ｂ，２２ｃ 半導体素子チップ
２ 金属配線
３，２４ 突起電極
４，２７ 封止樹脂
５， ２８ 補強材
６ 応力緩和層
７，９ ビアホール
８ 保護膜
１０，２６ 基材
１１， ２５ 接着剤
１２ スクライブライン
２１ 積層半導体チップユニット
２３ 配線領域[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a plurality of semiconductor element chips arranged in an array, and more particularly to a semiconductor device having a semiconductor system chip array having the same function as a system-on-chip.
[0002]
[Prior art]
[Patent Document 1] JP-A-2001-156245
[0003]
In recent years, miniaturization has progressed mainly in portable devices, for example, and accordingly, further miniaturization has been demanded for the housing and the internal circuit board. As a result, the effective mounting area of the semiconductor element, which is one of the components mounted on the circuit board, must be reduced. One method for solving this problem is a system-on-chip in which logic circuits, analog circuits, and memories are integrated on the same silicon chip.
[0004]
System-on-a-chip has the merit that components that function as a system can be contained in one chip, but it also requires high withstand voltage performance, and also requires analog circuits that are difficult to miniaturize and logic circuits that continue to shrink year by year. Since it is difficult to develop a manufacturing process capable of coexistence of mixed loading, there is a tendency that the development period tends to be long, which leads to an increase in cost.
[0005]
In order to solve these problems, a system-in-package method that draws on the trend of multi-chip modules in recent years has been spotlighted. As one example of such a mounting form, a mounting form as disclosed in JP-A-2001-156245 (Patent Document 1) has been proposed. FIGS. 18A and 18B show a semiconductor device proposed in this publication. FIG. 18A is a plan view, and FIG. 18B is a cross-sectional view taken along line XX ′ of FIG. 18A, and includes a plurality of IC bare chips each having a connection electrode on a main surface. 101, 102, 103, 104, an external terminal 108 is disposed on one side, and a conductive substrate 105 provided with a conductive pattern connected to the external terminal on the other side is flipped by an anisotropic conductive film 106. Chip mounting is performed. Further, the back surfaces of the plurality of IC bare chips 101 to 104 are commonly fixed to a hard plate 107 via an adhesive layer 109, so that the multi-chip module of the IC bare chips has an integrated structure as a package. Here, the interconnection between the IC bare chips is performed by a conductive pattern provided on the mounting substrate 105.
[0006]
By adopting such a structure, a semiconductor device capable of realizing a multi-chip module which can easily take an integrated structure as a compact package with high-density mounting and can meet a quick delivery date has become possible.
[0007]
[Problems to be solved by the invention]
However, the conventional example of the above proposal also has the following problem. First, since the IC bare chip needs to be mounted on the mounting base material, the height as a multi-chip module increases. Further, since a hard plate is bonded to the back surface side of the IC bare chip, the height of the final form is further increased. Further, the structure in which the front surface side of the IC bare chip is flip-chip mounted on the mounting base material and the back surface side is bonded to the hard plate is not suitable for the IC bare chip having a light receiving portion such as a solid-state image sensor chip. In addition, in the proposal of the above-mentioned publication, no consideration is given to these.
[0008]
Also, when mounting a chip that has been subjected to bump processing on a mounting substrate, it is necessary to individually apply a pressure bonding and heating process to the chip in addition to performing alignment, resulting in poor productivity and cost increase, I am worried about workability. Further, it is necessary to separately prepare a mounting base material for mounting the chip. However, a multilayer substrate having a fine pattern and a multilayer structure is very expensive at present.
[0009]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventionally proposed semiconductor device. The present invention enables further high integration and miniaturization, and facilitates interconnection between chips, thereby improving reliability. It is an object of the present invention to provide a semiconductor device having a function equivalent to that of a system-on-chip that can be applied to various mounting forms.
[0010]
The purpose of each claim is as follows. That is, an object of the invention according to claim 1 is to provide a semiconductor device which can be reduced in thickness and can form a semiconductor system chip array equivalent to a wafer on which a plurality of semiconductor element chips are arranged. A second object of the present invention is to provide a semiconductor device including a plurality of types of semiconductor chips. A third object of the present invention is to provide a semiconductor device partially constituted by a solid-state image sensor chip. A fourth object of the present invention is to provide a thin plate-shaped semiconductor device. An object of the invention according to claim 5 is to provide a semiconductor device in which a stacked semiconductor chip unit in which semiconductor element chips are stacked is arrayed.
[0011]
Another object of the present invention is to provide a semiconductor device having an optimum electrical connection structure between semiconductor element chips and with external terminals. It is another object of the present invention to provide a semiconductor device having an optimum wiring structure between semiconductor element chips and an optimum electrical connection structure with external terminals. An object of the invention according to claim 8 is to provide a method of manufacturing a semiconductor device which can be thinned and can form a semiconductor system chip array equivalent to a wafer in which a plurality of semiconductor element chips are arranged. . An object of a ninth aspect of the present invention is to provide a method of manufacturing a semiconductor device capable of accurately and easily aligning a semiconductor element chip.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 arranges a plurality of semiconductor element chips in an array by performing alignment so that each chip surface forms the same plane, and insulates each chip and the periphery. The semiconductor device is formed by forming a semiconductor system chip array by resin sealing with a conductive resin.
[0013]
In the semiconductor device configured as described above, it is possible to realize a semiconductor device which can be thinned and has a semiconductor system chip array configuration equivalent to a wafer in which a plurality of semiconductor element chips are arranged in an array.
[0014]
The invention according to claim 2 is the semiconductor device according to claim 1, wherein the plurality of semiconductor element chips are a plurality of types of semiconductor element chips. With this configuration, a semiconductor device including a plurality of types of semiconductor element chips can be obtained.
[0015]
The invention according to claim 3 is the semiconductor device according to claim 1 or 2, wherein at least one of the plurality of semiconductor element chips is a solid-state imaging element chip. With this configuration, it is possible to obtain a semiconductor device having a solid-state imaging device chip, which is small in size and easily applied to a highly reliable light receiving sensor.
[0016]
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the semiconductor element chip is constituted by a single semiconductor element chip. With this configuration, a thin, flat, semiconductor device can be obtained.
[0017]
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the semiconductor element chip includes a semiconductor element chip unit formed by stacking a plurality of semiconductor element chips. It is characterized by the following. With this configuration, it is possible to obtain a semiconductor device in which semiconductor element chip units in which semiconductor element chips are stacked are arrayed.
[0018]
According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the plurality of semiconductor element chips constituting the semiconductor chip unit are provided between a chip side surface or a back surface through the chip side surface. And a wiring region for making an electrical connection or an electrical connection with an external terminal is formed. With this configuration, a semiconductor device having an optimal electrical connection structure between semiconductor element chips and with external terminals can be obtained.
[0019]
According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects, the semiconductor system chip array includes a stress relaxation layer on a surface, and the plurality of semiconductor elements are provided on the stress relaxation layer. It is characterized in that a wiring region for electrically connecting the chips and a projecting electrode for making an electrical connection with an external terminal are formed. With this configuration, a semiconductor device having an optimal wiring structure between semiconductor element chips and an optimal electrical connection structure with external terminals can be obtained.
[0020]
According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to seventh aspects, a plurality of semiconductor element chips are provided on a base portion via an adhesive, and each chip surface has the same plane. At least comprising the steps of: performing alignment and bonding, performing a resin sealing of the plurality of semiconductor element chips with an insulating resin, and removing the base portion, wherein the resin sealing is performed. A semiconductor system chip array comprising a plurality of semiconductor element chips is formed.
[0021]
According to the method of manufacturing a semiconductor device configured as described above, a semiconductor device having a semiconductor system chip array configuration equivalent to a wafer on which a plurality of semiconductor element chips can be arranged can be easily manufactured.
[0022]
According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the base portion is provided with an alignment mark for alignment. With this configuration, it is possible to manufacture a semiconductor device by accurately and easily aligning a semiconductor element chip.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment will be described. First, a first embodiment of the present invention will be described. 1 and 2 are a perspective view and a plan view, respectively, showing a first embodiment of a semiconductor device according to the present invention, with a part thereof being omitted. FIG. 3 is an illustration along an AA 'line in FIG. FIG. 4 shows a cross-sectional view including a portion. In FIGS. 1 to 3, reference numerals 1a, 1b, 1c, and 1d denote single semiconductor element chips arranged in a non-stacked planar shape having different functions, and are manufactured in a wafer state up to a passivation film in the same manner as an ordinary IC. This is a non-defective semiconductor element chip that has been singulated after inspection. These semiconductor element chips 1a to 1d are arranged with a narrow pitch as much as possible, the space between the semiconductor element chips is sealed with an insulating resin 4, and the back surface of the plurality of semiconductor element chips arranged in a plane is , The reinforcing material 5 is bonded. Further, a stress relaxation layer 6 is formed on the surface of the semiconductor element chip, and a via hole 7 is provided if necessary, and a metal wiring 2 is formed on the stress relaxation layer 6 so that the electric power between the semiconductor element chips 1a to 1d is reduced. Connection is made. Further, a protective film 8 is formed on the stress relieving layer 6, and the projecting electrode 3 for making an electrical connection with an external electrode is formed at a necessary portion of the protective film 8 together with the via hole 9. Although the illustration of the stress relaxation layer 6 and the protective film 8 is omitted in FIGS. 1 and 2 as described above, the metal arrangement line 2 and the protective film formed on the stress relaxation layer 6 are omitted. The projecting electrodes 3 formed on 8 are schematically shown.
[0024]
In this manner, a semiconductor system chip array having a new multifunction is formed from the plurality of semiconductor element chips 1a to 1d having various functions. Therefore, while having a function equal to or higher than that of the system-on-chip, further high integration and miniaturization are possible, and the interconnection between the semiconductor element chips is easily performed, so that the electrical characteristics are not deteriorated. Therefore, a semiconductor device which is reliable and can be applied to various mounting forms can be realized.
[0025]
Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. In manufacturing the semiconductor device, not only a single semiconductor device, that is, a single semiconductor system chip array, but also a plurality of semiconductor system chip arrays are manufactured in the same manner as manufacturing a plurality of IC chips on a wafer. It is manufactured at the same time. First, as shown in FIG. 4, alignment is performed via a bonding agent 11 on a base material 10 on which alignment marks for positioning have been provided, and the surface sides of a plurality of semiconductor element chips 1 having different functions are bonded. As the adhesive, an epoxy-based adhesive is desirable, but it can be bonded so that the surface of the semiconductor element chip can be accurately aligned on the same plane, and if it does not adversely affect the characteristics of the semiconductor element chip, The type and material of the adhesive are not limited. The material of the substrate 10 to be bonded can be considered to be plastic or ceramic, but by using a transparent material such as glass, the state of bonding can be observed, and more accurate alignment can be performed.
[0026]
Next, as shown in FIG. 5, the resin 4 seals the back surface of the semiconductor element chip 1 and the gap between the chips. As the sealing resin 4, a material that is insulative and does not adversely affect the characteristics of the semiconductor chip 1 is required, and an epoxy-based or silicon-based resin, an ultraviolet-curable adhesive, or the like is preferable. However, the present invention is not limited to these, and any type and material may be used as long as it has the above-described characteristics.
[0027]
Subsequently, as shown in FIG. 6, the sealing resin 4 is polished until the back surface of the semiconductor element chip 1 is exposed. Further, when it is desired to reduce the thickness of the chip array, the semiconductor element chip itself may be polished to reduce the overall thickness.
[0028]
Next, as shown in FIG. 7, the reinforcing material 5 is attached to the polished surface, that is, the back surface of the semiconductor element chip, and the base material 10 on the front surface side of the semiconductor element chip is peeled off together with the adhesive 11. Examples of the material of the reinforcing material 5 include ceramic and glass. Organic and inorganic materials may be used as long as they have a low coefficient of linear expansion due to heat, have insulation properties, and have strength enough to hold the formed chip array. Regardless of the material, it does not matter. In this state, a plurality of semiconductor element chips having different functions are regularly arranged and the chip surfaces are aligned on the same plane, thereby forming a thin film such as sputtering or vapor deposition according to a pre-process of semiconductor manufacturing described later, or forming a via. A semiconductor substrate serving as a base of a semiconductor system chip array is completed, and a method such as this can be used and this process can be performed by batch processing.
[0029]
Next, as shown in FIG. 8, the stress relaxation layer 6 is formed on the surface of the semiconductor element chip by turning over the semiconductor substrate shown in FIG. The stress relaxation layer 6 is for distributing the stress and load at the joint portion when joining the semiconductor device to another board via the protruding electrode, thereby ensuring joint reliability. Materials include cyanoacrylates, polyurethane and silicone based adhesives and adhesive films, epoxy resins and resin films, and polyimide films, but with the desired properties (elasticity, thickness, insulation) for stress relief. Any property can be used as long as the property is obtained.
[0030]
Next, as shown in FIG. 9, via holes 7 are provided in the stress relieving layer 6 as necessary and metal wirings 2 are formed for interconnection between the semiconductor element chips and connection of external electrodes. The formation of the via hole 7 is generally and preferably performed by photoetching. Al 2 is generally used as the metal wiring 2, but it goes without saying that other wiring materials such as Cu and Ti used in a wiring process in a normal semiconductor process may be used. In forming the metal wiring 2, a wiring pattern may be formed by photoetching after forming a metal film on the entire surface, or may be formed by printing.
[0031]
Next, as shown in FIG. 10, a protective film 8 serving as an insulating layer is applied on the semiconductor element chip array. The material of the protective film 8 is not limited as long as it is electrically insulative, has moisture resistance, and is easily processed (via hole processing, metallization) as described later. In addition, as a forming method, it may be applied by spin coating or may be formed by printing. However, since a via hole needs to be provided as described later, a thickness of about 20 to 30 μm is desirable. However, if a via hole can be formed, the thickness of the protective film is not limited to this.
[0032]
Subsequently, as shown in FIG. 11, a via hole 9 is formed in the protective film 8, a metal material is filled in the via hole 9, and the projection electrode 3 serving as an electrical connection means with an external terminal is formed on the via hole 9. Form. Laser processing is generally used to form the via hole 9, but photo etching may be used as long as deep etching corresponding to the depth of the protective film 8 as an insulating layer is possible. Examples of the metal to be filled in the via hole 9 include Al and Cu. However, a metal material used for forming a via hole and a contact in a normal semiconductor process may be used. If necessary, a plurality of wiring layers for forming the metal wiring 2 and a plurality of insulating layers for forming the protective film 8 may be formed. Thereafter, nickel or gold plating is applied to the via hole 9 for electrical connection with an external terminal, and then the bump electrode 3 is formed. Alternatively, after a metal wiring layer is formed again on the via hole 9, the bump electrode 3 is formed in the same manner. Usually, solder, Cu bumps, solder balls, or the like are used as the protruding electrodes 3, but any shape and manufacturing method can be used as long as electrical connection to other substrates can be made without any problem.
[0033]
According to the above-described manufacturing method, for example, a semiconductor system chip array group in which a plurality of semiconductor system chip arrays including a plurality of semiconductor element chips are formed as shown in FIG. In FIG. 12, the illustration of the stress relaxation layer 6 and the protective film 8 is omitted. Here, by dicing along the scribe line 12, a single semiconductor system chip array as shown in FIG. 1 is completed. Here, by freely arranging the metal wiring on the via hole, an arbitrary arrangement of the protruding electrodes formed on the metal wiring becomes possible. Of course, it is needless to say that the metal wiring can be drawn from the circuit element in each semiconductor element chip to the projecting electrode at the shortest distance directly above. Further, in the present embodiment, the positions of the protruding electrodes are described at random. However, in order to disperse the stress applied to the semiconductor element chip, even if the dummy electrode is formed symmetrically with respect to the chip center, including the arrangement of the dummy bumps Good.
[0034]
Further, in this embodiment, the metal wiring layer is shown as a single layer. However, by making the metal wiring layer multi-layered, a power supply layer or a ground layer can be provided, so that electrical characteristics can be improved. Further, since the semiconductor element chips are insulated by the insulating resin, the element separation is effectively performed effectively, which is very advantageous electrically. Further, by laying out the interconnections between the semiconductor element chips at the shortest distance to prevent signal deterioration, it is possible to further improve the electrical characteristics.
[0035]
Further, in the present embodiment, the projection electrode (bump) which is a means for electrically connecting to the external terminal is provided on the front side of the semiconductor system chip array. However, the projection electrode is not provided on the front side. Instead, a protruding electrode may be provided as follows. That is, after dicing to form a single semiconductor system chip array, a wiring region is formed from the via hole on the front surface side of the chip array to the side surface or from the side surface to the back surface. Then, a protruding electrode or the like, which is an electrical connection means with an external terminal, may be formed on the wiring region. With such a structure, application to various mounting forms becomes possible.
[0036]
Furthermore, in the present embodiment, there is no limitation on the types of the plurality of semiconductor element chips constituting the semiconductor system chip array serving as the semiconductor device, and the present embodiment can be applied to all types of semiconductor element chips. That is, these semiconductor element chips can be mixedly mounted without being separated into digital and analog. For example, a light receiving sensor chip such as a solid-state imaging device and an IC chip such as a driving circuit and a signal processing circuit can be integrated to form a single system chip array. According to such a configuration, a solid-state imaging device that could not be integrated into one chip due to a complicated and large-scale driving circuit or signal processing circuit can be downsized, and a solid-state imaging device that has no fear of adversely affecting imaging characteristics. An imaging device can be realized. Also, by using a material having high optical transmittance as a reinforcing material 5 to be attached to the back surface of the chip array and an adhesive to attach the reinforcing material 5 to the semiconductor system chip array, It becomes possible to correspond to the system chip array.
[0037]
Next, a second embodiment will be described. This embodiment is different from the first embodiment in that a single non-defective chip is arranged in a plane to form a semiconductor system chip array, but a plurality of semiconductor element chips as shown in FIG. Are arranged in an array to form a semiconductor system chip array, thereby constituting a semiconductor device. In FIG. 13, reference numerals 22a, 22b, and 22c denote semiconductor element chips having different functions, which are non-defective semiconductor element chips that are manufactured in a wafer state up to a passivation film, like an ordinary IC chip, and singulated after inspection. Reference numeral 23 denotes a wiring region formed from the electrode pads of each of the semiconductor element chips 22a, 22b, and 22c to the side and back surfaces of the chip, and reference numeral 24 denotes a wiring region formed for electrical connection between the semiconductor element chips. It is a protruding electrode. Then, similarly to the first embodiment, a plurality of the laminated semiconductor chip units 21 configured as described above are arranged in an array at a small interval, and are sealed with a sealing resin to form a semiconductor device. Is composed. Needless to say, a protruding electrode for making an electrical connection to the outside may be provided on the front surface or the back surface of the present laminated semiconductor chip unit 21.
[0038]
Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. Since the method for manufacturing the semiconductor device according to the present embodiment is basically the same as the method for manufacturing the semiconductor device according to the first embodiment, the method will be briefly described with reference to FIGS. The description of the method of manufacturing the present laminated semiconductor chip unit itself is omitted. First, as shown in FIG. 14, the surface sides of the plurality of stacked semiconductor chip units 21 are bonded to a base material 26 via an adhesive 25. Next, as shown in FIG. Here, the type of the sealing resin 27 is not limited as long as it has a low viscosity enough to enter the gap between the stacked semiconductor chip units 21. Next, as shown in FIG. 16, the sealing resin 27 is polished or the like to expose the chip back surface of the lowermost layer chip of the laminated semiconductor chip unit 21. Here, by performing polishing with high precision so that the wiring region 23 is exposed after polishing, it is also possible to secure connection means on the back surface.
[0039]
Subsequently, as shown in FIG. 17, the base material 26 and the adhesive 25 are removed after bonding the reinforcing material 28 to the back surface side. Finally, similarly to the first embodiment, if necessary, wiring between the stacked semiconductor chip units 21 is formed on the surface, and projecting electrodes for making electrical connection to external electrodes are formed ( Not shown). This makes it possible to form a system chip array even when a stacked semiconductor chip unit is used. Note that the adhesive, the base material, the reinforcing material, and the protruding electrodes used in the present embodiment can be the same as those used in the first embodiment.
[0040]
According to the configuration and the manufacturing method of the semiconductor device according to the second embodiment, it is possible to realize a semiconductor device including a semiconductor system chip array equivalent to a quasi-stacked wafer, and to improve productivity. It is also significant in terms of cost. Also, for a stacked semiconductor chip unit in which a plurality of types of semiconductor chips are stacked instead of the same semiconductor chip, a semiconductor system chip array composed of a semiconductor system chip array equivalent to a quasi-stacked wafer is obtained by using the same method. The device can be realized, the productivity is good, and the cost is significant.
[0041]
【The invention's effect】
As described above with reference to the embodiment, according to the first aspect of the present invention, a semiconductor which can be reduced in thickness and has a semiconductor system chip array configuration equivalent to a wafer in which a plurality of semiconductor element chips are arranged in an array. The device can be realized, and by providing a structure without steps between chips arranged so that the chip surfaces are arranged on the same plane, thin film formation such as sputtering or vapor deposition according to the previous process of semiconductor manufacturing, A method of forming a via or the like can be used, and a method of performing this step by batch processing can be used. According to the second aspect of the invention, a semiconductor device including a plurality of types of semiconductor chips can be obtained. According to the third aspect of the present invention, there is provided a semiconductor device having a solid-state image sensor chip, which is small in size and easily applied to a highly reliable light receiving sensor. According to the fourth aspect of the present invention, a thin plate-shaped semiconductor device can be obtained. Further, according to the invention of claim 5, it is possible to obtain a semiconductor device in which stacked semiconductor chip units in which semiconductor element chips are stacked are arrayed. According to the invention of claim 6, a semiconductor device having an optimum electrical connection structure between semiconductor element chips and with external terminals can be obtained. According to the invention according to claim 7, a semiconductor device having an optimum wiring structure between semiconductor element chips and an optimum electric connection structure with external terminals can be obtained. According to the eighth aspect of the present invention, it is possible to easily manufacture a semiconductor device having a semiconductor system chip array equivalent to a wafer on which a plurality of semiconductor element chips can be arranged, which can be thinned. According to the ninth aspect, a semiconductor device can be manufactured by accurately and easily aligning a semiconductor element chip.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a first embodiment of a semiconductor device according to the present invention with a part thereof omitted;
FIG. 2 is a plan view showing the first embodiment shown in FIG. 1 with a part thereof omitted;
FIG. 3 is a cross-sectional view of the first embodiment showing a cross-section along the line AA ′ of FIG. 2 including an omitted part.
FIG. 4 is a cross-sectional view showing a manufacturing process for describing a method of manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 4;
FIG. 6 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 5;
FIG. 7 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 6;
FIG. 8 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 7;
FIG. 9 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 8;
FIG. 10 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 9;
FIG. 11 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 10;
FIG. 12 is a perspective view showing a state in which a semiconductor system chip array group manufactured in the manufacturing process shown in FIGS. 4 to 11 is partially omitted.
FIG. 13 is a sectional view showing a laminated semiconductor chip unit according to a second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing step for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 14;
16 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG.
FIG. 17 is a cross-sectional view showing a manufacturing step that follows the manufacturing step shown in FIG. 16;
18A and 18B are a plan view and a cross-sectional view illustrating an example of a conventionally proposed hybrid integrated circuit device.
[Explanation of symbols]
1,1a, 1b, 1c, 1d, 22a, 22b, 22c Semiconductor element chip
2 Metal wiring
3,24 protruding electrode
4,27 sealing resin
5, 28 reinforcement
6 Stress relaxation layer
7,9 Via hole
8 Protective film
10,26 base material
11, 25 adhesive
12 Scribe Line
21 Stacked semiconductor chip unit
23 Wiring area

Claims (9)

複数の半導体素子チップを、各チップ表面が同一平面をなすようにアライメントを行ってアレイ状に配置し、各チップ間及び周辺を絶縁性樹脂で樹脂封止して半導体システムチップアレイを形成することを特徴とする半導体装置。A semiconductor system chip array is formed by arranging a plurality of semiconductor element chips in an array so that each chip surface forms the same plane, and sealing between and around each chip with an insulating resin. A semiconductor device characterized by the above-mentioned. 前記複数の半導体素子チップは、複数種類の半導体素子チップであることを特徴とする請求項１に係る半導体装置。2. The semiconductor device according to claim 1, wherein the plurality of semiconductor element chips are a plurality of types of semiconductor element chips. 前記複数の半導体素子チップの少なくとも１つは、固体撮像素子チップであることを特徴とする請求項１又は２に係る半導体装置。3. The semiconductor device according to claim 1, wherein at least one of the plurality of semiconductor element chips is a solid-state imaging element chip. 前記半導体素子チップは、単体の半導体素子チップで構成されていることを特徴とする請求項１〜３のいずれか１項に係る半導体装置。The semiconductor device according to claim 1, wherein the semiconductor element chip is configured by a single semiconductor element chip. 前記半導体素子チップは、複数の半導体素子チップを積層してなる半導体素子チップユニットで構成されていることを特徴とする請求項１〜３のいずれか１項に係る半導体装置。The semiconductor device according to claim 1, wherein the semiconductor element chip is configured by a semiconductor element chip unit formed by stacking a plurality of semiconductor element chips. 前記半導体チップユニットを構成する前記複数の半導体素子チップは、チップ側面、あるいはチップ側面を通って裏面に亘って、チップ間の電気的接続あるいは外部端子との電気的接続を行う配線領域を形成していることを特徴とする請求項５に係る半導体装置。The plurality of semiconductor element chips constituting the semiconductor chip unit form a wiring area for performing an electrical connection between the chips or an electrical connection with an external terminal, on the chip side surface or on the rear surface through the chip side surface. The semiconductor device according to claim 5, wherein 前記半導体システムチップアレイは、表面に応力緩和層を備え、該応力緩和層上に前記複数の半導体素子チップ間を電気的に接続するための配線領域と、外部端子との電気的接続を行う突起電極とを形成していることを特徴とする請求項１〜６のいずれか１項に係る半導体装置。The semiconductor system chip array includes a stress relieving layer on a surface, and a wiring region for electrically connecting the plurality of semiconductor element chips on the stress relieving layer, and a protrusion for electrically connecting an external terminal. The semiconductor device according to claim 1, further comprising an electrode. 請求項１〜７のいずれか１項に係る半導体装置の製造方法において、複数の半導体素子チップを接着剤を介して基材部に、各チップ表面が同一平面をなすようにアライメントを行って貼り付ける工程と、前記複数の半導体素子チップを絶縁性樹脂で樹脂封止を行う工程と、前記基材部を剥離する工程とを少なくとも備え、前記樹脂封止された複数の半導体素子チップからなる半導体システムチップアレイを形成することを特徴とする半導体装置の製造方法。The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein a plurality of semiconductor element chips are aligned and adhered to a base member via an adhesive so that each chip surface is on the same plane. A semiconductor comprising the plurality of resin-sealed semiconductor element chips, comprising at least a attaching step, a step of resin-sealing the plurality of semiconductor element chips with an insulating resin, and a step of peeling the base portion. A method for manufacturing a semiconductor device, comprising forming a system chip array. 前記基材部は、アライメント用の位置合わせマークが形成されていることを特徴とする請求項８に係る半導体装置の製造方法。9. The method according to claim 8, wherein an alignment mark for alignment is formed in the base portion.
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