JP2004144599A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of testing at desired timing a delay time or an operation speed of an internal circuit without being affected by a floating capacity or the like in a measuring system. <P>SOLUTION: This semiconductor integrated circuit is equipped with the internal circuit 1 for applying a prescribed processing to an input signal and outputting it, a PLL circuit 2 for generating a clock signal synchronized with the input signal, a dividing circuit 3 for dividing the clock signal generated by the PLL circuit, and holding circuits FF1, FF2 for generating an output signal corresponding to the difference between the delay time in the internal circuit and a prescribed value by holding the signal outputted from the internal circuit synchronously with the clock signal divided by the dividing circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a built-in test circuit for testing an internal circuit.
[0002]
[Prior art]
Conventionally, in order to test a delay time or an operation speed in an internal circuit of a semiconductor integrated circuit, a tester is connected to the internal circuit by setting a probe on a terminal (pin or pad) of the semiconductor integrated circuit, and an input signal is input to the internal circuit. And the output signal of the internal circuit was measured. However, such a measurement is affected by stray capacitance in a measurement system from a measurement tool such as a probe to a tester, and by skew and jitter between a plurality of terminals of the tester. It has become difficult to accurately measure the delay time or operation speed of a high-speed device manufactured by a fine process. Therefore, in order to accurately measure them, a high-precision and expensive tester is required.
[0003]
Meanwhile, Japanese Patent Application Laid-Open No. H11-163,897 discloses a semiconductor test circuit that can simulate a function test when a test circuit is operated at an actual operating frequency in a semiconductor device including a clock generation unit. . The semiconductor test circuit includes a test data generation unit that generates test data according to a clock, and a first path that receives an output of a flip-flop that performs a latch operation on the test data according to the clock as an input and derives a predetermined output. A second path for deriving an output delayed from the output of the first path by a delay circuit, and two flip-flops each performing a latch operation on an input from the first and second paths in accordance with a clock. The operation is confirmed by comparing the outputs of the two flip-flops.
[0004]
However, this semiconductor test circuit is for testing an internal circuit including a clock generation unit at an actual operating frequency using a clock signal generated by the clock generation unit. Cannot be tested. Further, the output signal of the internal circuit cannot be sampled except for the period of the clock signal generated by the clock generation unit.
[0005]
[Patent Document 1]
JP-A-11-174125 (page 1, FIG. 1)
[0006]
[Problems to be solved by the invention]
In view of the above, an object of the present invention is to provide a semiconductor integrated circuit that can test a delay time or an operation speed of an internal circuit at a desired timing without being affected by stray capacitance or the like in a measurement system. With the goal.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention includes an internal circuit that performs predetermined processing on an input signal and outputs the processed signal, and a PLL circuit that generates a clock signal synchronized with the input signal. , A frequency divider that divides the clock signal generated by the PLL circuit, and a signal that is output from the internal circuit is held in synchronization with the clock signal that is divided by the frequency divider. And a holding circuit for generating an output signal according to whether the time is larger or smaller than a predetermined value.
[0008]
A semiconductor integrated circuit according to a second aspect of the present invention includes an internal circuit that performs predetermined processing on an applied signal and outputs the processed signal, a PLL circuit that generates a clock signal synchronized with an input signal, and a PLL circuit. A divider circuit for dividing the generated clock signal, a selection circuit for selecting the clock signal divided by the divider circuit in the test mode and applying the clock signal to the internal circuit, and a signal output from the internal circuit. A holding circuit that generates an output signal according to whether the delay time in the internal circuit is larger or smaller than a predetermined value by holding the clock signal in synchronization with the clock signal divided by the frequency dividing circuit.
[0009]
In the above, the holding circuit converts the signal output from the internal circuit into a first flip-flop that generates a trigger signal whose level changes only once in synchronization with the clock signal divided by the frequency dividing circuit. A second flip-flop that generates an output signal according to whether the delay time in the internal circuit is larger or smaller than a predetermined value by holding the trigger signal generated by the first flip-flop in synchronization with a level change of the trigger signal May be used.
[0010]
In that case, the PLL circuit outputs a lock signal that changes from the first level to the second level when the lock state is established, and the first flip-flop operates when the lock signal is at the second level. Alternatively, a trigger signal whose level changes in synchronization with the clock signal divided by the divider circuit may be generated.
[0011]
According to the present invention, in the semiconductor integrated circuit, the output signal is generated according to whether the delay time in the internal circuit is larger or smaller than a predetermined value by holding the signal output from the internal circuit. The delay time or the operation speed of the internal circuit can be tested at a desired timing without being affected by the stray capacitance or the like in the measurement system. Further, when a variable frequency dividing circuit capable of changing the frequency dividing ratio according to the control signal is used as the frequency dividing circuit, the delay time or the operation speed of the internal circuit can be tested at a plurality of different timings. .
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a block diagram showing the structure of the semiconductor integrated circuit according to the first embodiment of the present invention. This semiconductor integrated circuit includes an internal circuit 1 to be tested, a PLL circuit 2, a frequency dividing circuit 3, and flip-flops FF1 and FF2 for testing a delay time or an operation speed in the internal circuit 1.
[0013]
The internal circuit 1 is a circuit that performs predetermined processing on a digital input signal applied to an input terminal and outputs the processed signal. In this processing, a signal is delayed. In the present embodiment, a test is performed to determine whether the delay time is larger or smaller than a predetermined value.
[0014]
The PLL circuit 2 generates a clock signal synchronized with the input signal, and outputs a lock signal that changes from a low level to a high level when the PLL circuit 2 is locked. The frequency divider 3 divides the frequency of the clock signal generated by the PLL circuit 2 to generate a frequency-divided clock signal. Here, the frequency dividing circuit 3 sets the frequency-divided clock signal immediately after the PLL circuit 2 is locked to a low level based on the lock signal supplied from the PLL circuit 2.
[0015]
The PLL circuit 2 and the frequency divider 3 are controlled by a control signal supplied from a control terminal, and operate only in a test mode, and do not operate in a normal mode. Further, it is also possible to change the frequency division ratio in the frequency dividing circuit 3 by the control signal, whereby the delay time in the internal circuit 1 can be tested at a plurality of different timings.
[0016]
The flip-flops FF1 and FF2 are used as a holding circuit that holds a signal output from the internal circuit 1 in synchronization with the divided clock signal. A lock signal output from the PLL circuit 2 is supplied to a negative logic reset terminal of the flip-flop FF1. When the PLL circuit 2 enters the locked state and the lock signal goes high, the flip-flop FF1 is released from the reset state and outputs its output in synchronization with the rising edge of the divided clock signal output from the frequency dividing circuit 3. Change from low level to high level.
[0017]
The signal output from the flip-flop FF1 is used as a trigger signal in the flip-flop FF2. The flip-flop FF2 holds the signal output from the internal circuit 1 in synchronization with the rising edge of the trigger signal, thereby outputting an output signal corresponding to whether the delay time in the internal circuit 1 is larger or smaller than a predetermined value. Generate. For example, when the input signal changes from low level to high level, if the delay time in the internal circuit 1 is smaller than a predetermined value, the output signal of the flip-flop FF2 becomes high level and the delay time in the internal circuit 1 becomes predetermined. , The output signal of the flip-flop FF2 becomes low level.
[0018]
Next, the operation of the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit according to the first embodiment of the present invention.
[0019]
When an input signal is supplied to the input terminal, the PLL circuit 2 enters a locked state, and the PLL circuit 2 generates a clock signal synchronized with the input signal. The frequency divider 3 divides the frequency of the clock signal generated by the PLL circuit 2 by 4, and outputs a frequency-divided clock signal. Further, the PLL circuit 2 changes the lock signal from a low level to a high level. As a result, the reset state of the flip-flop FF1 is released, and the output (trigger signal) changes from the low level to the high level in synchronization with the rising edge of the divided clock signal.
[0020]
If the delay time in the internal circuit 1 is smaller than twice the clock cycle output from the PLL circuit 2, the input signal is delayed in the internal circuit 1 and the signal A is output. The flip-flop FF2 continuously outputs a high-level signal by holding the signal A in synchronization with the rising edge of the trigger signal. On the other hand, if the delay time in internal circuit 1 is greater than twice the clock cycle output from PLL circuit 2, the input signal is delayed in internal circuit 1 and signal B is output. The flip-flop FF2 continuously outputs a low-level signal by holding the signal B in synchronization with the rising edge of the trigger signal. Thereby, the delay time in the internal circuit 1 can be tested at a desired timing without being affected by the stray capacitance or the like in the measurement system.
[0021]
Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram showing a structure of a semiconductor integrated circuit according to the second embodiment of the present invention. This semiconductor integrated circuit includes an internal circuit 1 to be tested, a PLL circuit 2, a frequency dividing circuit 3, a selection circuit 4, and flip-flops FF1 and FF2 for testing a delay time or an operation speed in the internal circuit 1. Contains.
[0022]
In the present embodiment, the frequency dividing circuit 3 divides the frequency of the clock signal generated by the PLL circuit 2 to generate two types of frequency-divided clock signals of positive phase (+) and negative phase (-). The phases of these frequency-divided clock signals are determined based on the lock signal supplied from the PLL circuit 2. In the normal mode, the selection circuit 4 selects a signal applied from another circuit in the semiconductor integrated circuit and supplies the selected signal to the internal circuit 1 in accordance with the control signal supplied to the control terminal. The positive-phase clock signal divided by the frequency divider 3 is selected and supplied to the internal circuit 1.
[0023]
Thus, in the normal mode, the internal circuit 1 performs predetermined processing on a signal applied from another circuit in the semiconductor integrated circuit and outputs the signal, and in the test mode, the frequency is divided by the frequency dividing circuit 3. The positive phase clock signal is subjected to predetermined processing and output. In the present embodiment, a test is performed to determine whether the delay time in the internal circuit 1 is larger or smaller than a predetermined value.
[0024]
Next, the operation of the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a timing chart showing the operation of the semiconductor integrated circuit according to the second embodiment of the present invention.
[0025]
When an input signal is supplied to the input terminal, the PLL circuit 2 enters a locked state, and the PLL circuit 2 generates a clock signal synchronized with the input signal. The frequency dividing circuit 3 divides the frequency of the clock signal generated by the PLL circuit 2 by 4, and outputs a frequency-divided clock signal having a positive phase (+) and a negative phase (-). Further, the PLL circuit 2 changes the lock signal from a low level to a high level. As a result, the reset state of the flip-flop FF1 is released, and the trigger signal changes from the low level to the high level in synchronization with the rising edge of the divided clock signal having the opposite phase.
[0026]
If the delay time in the internal circuit 1 is smaller than twice the clock cycle, the internal circuit 1 delays the positive-phase divided clock signal and outputs the signal A. The flip-flop FF2 continuously outputs a high-level signal by holding the signal A in synchronization with the rising edge of the trigger signal. On the other hand, when the delay time in the internal circuit 1 is larger than twice the clock cycle, the internal circuit 1 delays the positive-phase divided clock signal and outputs the signal B. The flip-flop FF2 continuously outputs a low-level signal by holding the signal B in synchronization with the rising edge of the trigger signal. Thus, the delay time in the internal circuit 1 can be tested at a desired timing without being affected by the stray capacitance or the like in the measurement system.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a structure of a semiconductor integrated circuit according to a first embodiment.
FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit.
FIG. 3 is a block diagram showing a structure of a semiconductor integrated circuit according to a second embodiment.
FIG. 4 is a timing chart showing the operation of the semiconductor integrated circuit.
[Explanation of symbols]
1 internal circuit, 2 PLL circuit, 3 divider circuit, 4 selection circuit, FF1, FF2 flip-flop

Claims (5)

An internal circuit that performs predetermined processing on the input signal and outputs the processed signal;
A PLL circuit for generating a clock signal synchronized with the input signal;
A frequency dividing circuit for dividing the frequency of the clock signal generated by the PLL circuit;
By holding the signal output from the internal circuit in synchronization with the clock signal divided by the frequency dividing circuit, an output corresponding to whether the delay time in the internal circuit is larger or smaller than a predetermined value is maintained. A holding circuit for generating a signal,
A semiconductor integrated circuit comprising: An internal circuit that performs predetermined processing on the applied signal and outputs the processed signal;
A PLL circuit for generating a clock signal synchronized with the input signal;
A frequency dividing circuit for dividing the frequency of the clock signal generated by the PLL circuit;
In a test mode, a selection circuit that selects a clock signal divided by the divider circuit and applies the selected clock signal to the internal circuit;
By holding the signal output from the internal circuit in synchronization with the clock signal divided by the frequency dividing circuit, an output corresponding to whether the delay time in the internal circuit is larger or smaller than a predetermined value is maintained. A holding circuit for generating a signal,
A semiconductor integrated circuit comprising: 3. The semiconductor integrated circuit according to claim 1, wherein said frequency dividing circuit is a variable frequency dividing circuit capable of changing a frequency dividing ratio according to a control signal. The holding circuit,
A first flip-flop for generating a trigger signal whose level changes only once in synchronization with the clock signal divided by the frequency dividing circuit;
By holding the signal output from the internal circuit in synchronization with the level change of the trigger signal generated by the first flip-flop, it is possible to determine whether the delay time in the internal circuit is larger or smaller than a predetermined value. A second flip-flop for generating an output signal corresponding to
The semiconductor integrated circuit according to claim 1, comprising: The PLL circuit outputs a lock signal that changes from a first level to a second level when the PLL circuit enters a locked state;
5. The semiconductor according to claim 4, wherein the first flip-flop generates a trigger signal whose level changes in synchronization with the clock signal divided by the frequency dividing circuit when the lock signal is at the second level. Integrated circuit.

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