JP2004039690A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an inexpensive semiconductor device which has high performance and a high degree of integration, operates at a high speed on a low drive voltage, and is low in power consumption. <P>SOLUTION: A bulk semiconductor device 12 is formed on a semiconductor substrate 11, a thin film transistor 14 is formed as interposing an inter-element insulating film 13 between itself and the semiconductor device 12, and the semiconductor device 12 is electrically connected to the thin film transistor 14 through a contact hole 15 formed in the inter-element insulating film 13. Or, the first thin film transistor is formed on the insulating substrate, the second thin film transistor is formed so as to interpose the inter-layer insulating film between itself and the first thin film transistor, and the first thin film transistor is electrically connected to the second thin film transistor through the contact hole formed in the inter-element insulating film. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor element, and more particularly to a semiconductor element that achieves high performance, high integration, high-speed operation, low driving voltage, low power consumption, low cost, and the like.
[0002]
[Background Art]
A three-dimensional semiconductor device is one promising technology for realizing a high degree of integration and high-speed operation (Mitsumasa Koyanagi, Hideki Motai, Semiconductor FPD World 2002, pp. 36). Conventionally, three-dimensional semiconductor technology has often been achieved by forming a bulk semiconductor element on a semiconductor substrate and laminating the substrate.
[0003]
On the other hand, recently, the characteristics of thin film transistors have been remarkably improved. In particular, in the case of laser crystallized thin film transistors, those having characteristics comparable to those of bulk semiconductor devices have begun to appear (H. Wakabebe and T. Sameshima, “Defect reduce technology used to fabricate high-performance TFT-based TFT-LCD-based TFT-LCD-based TFT-LCD-based TFT-LCD). , Tokyo, Japan, TFT2-3, to be presented, July 2002).
[0004]
[Problems to be solved by the invention]
In the three-dimensional technology of the conventional semiconductor technology, that is, a technology of forming a bulk semiconductor element on a semiconductor substrate and laminating the substrates, a parasitic capacitance and a wiring delay occur because each substrate has a considerable thickness, It has been difficult to realize high-speed operation, low drive voltage, low power consumption, and the like. Also, since each substrate is quite expensive, it has been difficult to realize low cost. Therefore, an object of the present invention is to realize a semiconductor device with high performance, high integration, high speed operation, low driving voltage, low power consumption, and low cost.
[0005]
[Means for Solving the Problems]
According to the first aspect of the present invention, a bulk semiconductor element is formed on a semiconductor substrate, a thin film transistor is formed with an inter-element insulating film interposed therebetween, and the bulk semiconductor element is formed through a contact hole formed in the inter-element insulating film. A semiconductor element characterized by being electrically connected to a thin film transistor.
[0006]
According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein a single layer or a plurality of layers of thin film transistors are formed further above the thin film transistors.
[0007]
According to a third aspect of the present invention, a first layer of thin film transistor is formed on an insulator substrate, a second layer of thin film transistor is formed with an inter-element insulating film interposed therebetween, and the first layer of thin film transistor is formed of an element. A semiconductor element which is electrically connected to a second-layer thin film transistor through a contact hole formed in an inter-insulation film.
[0008]
According to a fourth aspect of the present invention, there is provided the semiconductor device according to the third aspect, wherein a single-layer or a plurality of thin-film transistors are formed further above the second-layer thin-film transistor. is there.
[0009]
According to the semiconductor device according to the first to fourth aspects, it is possible to realize a semiconductor device with high performance, high integration, high speed operation, low driving voltage, low power consumption, and low cost. As described in the background art, the characteristics of a thin film transistor have recently been remarkably improved, and a high-performance semiconductor device can be realized. Further, similarly to the three-dimensional technology of the conventional semiconductor technology, it is possible to realize a highly integrated semiconductor device. Further, since the inter-element insulating film is a thin film, it is possible to realize a semiconductor element with high speed operation, low driving voltage and low power consumption. Further, since only one substrate is used, a low-cost semiconductor element can be realized. Note that since the temperature of the manufacturing process of the thin film transistor can be reduced, the lower layer is not damaged.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described.
[0011]
FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.
[0012]
In the semiconductor device of the present embodiment, as described in claim 1, a bulk semiconductor device 12 is formed on a semiconductor substrate 11, a thin film transistor 14 is formed across an inter-device insulating film 13, and the bulk semiconductor device 12 It is electrically connected to the thin film transistor 14 through a contact hole 15 opened in the insulating film 13. Further, as described in claim 2, an upper layer thin film transistor 16 is formed further above the thin film transistor 14. In this embodiment, the thin film transistor 14 and the upper thin film transistor 16 form a two-layer thin film transistor on the lowermost bulk semiconductor element 12, but a single layer or three or more layers is formed. Is also good.
[0013]
FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
[0014]
In the semiconductor device of this embodiment, a first-layer thin film transistor 22 is formed on an insulator substrate 21, and a second-layer thin film transistor 24 is formed with an inter-element insulating film 23 interposed therebetween. The first-layer thin film transistor 22 is electrically connected to the second-layer thin film transistor 24 through a contact hole 25 formed in the inter-element insulating film 23. Further, as described in claim 4, an upper layer thin film transistor 26 is formed further above the second layer thin film transistor 24. In this embodiment, the two-layered thin film transistor 24 and the upper-layered thin film transistor 26 are formed on the lowermost first-layer thin film transistor 22; May also be three or more layers.
[0015]
FIG. 3 is a diagram illustrating an example of a method for manufacturing a thin film transistor according to the present invention. Here, a laser crystallized polycrystalline thin film transistor will be described as an example. The thin film transistors of the first and second embodiments are formed by this manufacturing method. First, an amorphous silicon film is formed on the substrate 31 by PECVD using SiH ₄ or LPCVD using Si ₂ H ₆ . By irradiating the laser 33, the amorphous silicon film is crystallized and becomes a polycrystalline silicon film 32 (FIG. 3A). After patterning the polycrystalline silicon film 32, a gate insulating film 34 is formed, and a gate electrode 35 is formed and patterned (FIG. 3B). Impurities such as phosphorus and boron are implanted into the polycrystalline silicon film 32 in a self-aligned manner using the gate electrode 35 and activated, thereby forming a source region and a drain region 36 having a CMOS structure. An interlayer insulating film 37 is formed, a contact hole is opened, and a source electrode and a drain electrode 38 are formed and patterned (FIG. 3C). As shown in this figure, when the bulk semiconductor element 12 and the thin film transistor 14 are present in the lower layer as in the first embodiment, and as in the second embodiment, the first thin film transistor 22 and the second thin film transistor When the thin film transistor 24 is formed, the contact hole is opened, and when the source electrode and the drain electrode 36 are formed, conduction with the lower layer is performed, so that a desired structure can be obtained without increasing an extra step. be able to.
[0016]
In this manufacturing process, the maximum temperature is about 400 ° C., and even if the bulk semiconductor element 12 and the thin film transistor 14 are provided in the lower layer as in the first embodiment, or the second semiconductor device is formed as in the second embodiment. Even if the first-layer thin film transistor 22 and the second-layer thin film transistor 24 are present, no damage is caused.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a diagram showing an example of a method for manufacturing a thin film transistor of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Bulk semiconductor element 13 Inter-element insulating film 14 Thin-film transistor 15 Contact hole 16 Upper thin-film transistor 21 Insulator substrate 22 First-layer thin-film transistor 23 Inter-element insulating film 24 Second-layer thin-film transistor 25 Contact hole 26 Thin film transistor 31 Substrate 32 Polycrystalline silicon film 33 Laser 34 Gate insulating film 35 Gate electrode 36 Source and drain regions 37 Interlayer insulating film 38 Source and drain electrodes

Claims (4)

A bulk semiconductor element is formed on a semiconductor substrate, a thin film transistor is formed with an inter-element insulating film interposed therebetween, and the bulk semiconductor element is electrically connected to the thin film transistor through a contact hole opened in the inter-element insulating film. A semiconductor device, characterized in that: The semiconductor device according to claim 1,
A semiconductor device, wherein a single layer or a plurality of layers of thin film transistors are formed further above the thin film transistors. A first-layer thin film transistor is formed on an insulator substrate, a second-layer thin film transistor is formed with an inter-element insulating film interposed therebetween, and the first-layer thin film transistor is opened in the inter-element insulating film. A semiconductor element that is electrically connected to the second-layer thin film transistor via the contact hole. The semiconductor device according to claim 3,
A semiconductor element, wherein a single layer or a plurality of layers of thin film transistors are formed further above the second layer of thin film transistors.

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