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JP2004031790A5 - - Google Patents

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Publication number
JP2004031790A5
JP2004031790A5 JP2002188053A JP2002188053A JP2004031790A5 JP 2004031790 A5 JP2004031790 A5 JP 2004031790A5 JP 2002188053 A JP2002188053 A JP 2002188053A JP 2002188053 A JP2002188053 A JP 2002188053A JP 2004031790 A5 JP2004031790 A5 JP 2004031790A5
Authority
JP
Japan
Prior art keywords
input
output terminals
layer
semiconductor chip
rewiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002188053A
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Japanese (ja)
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JP2004031790A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2002188053A priority Critical patent/JP2004031790A/en
Priority claimed from JP2002188053A external-priority patent/JP2004031790A/en
Publication of JP2004031790A publication Critical patent/JP2004031790A/en
Publication of JP2004031790A5 publication Critical patent/JP2004031790A5/ja
Pending legal-status Critical Current

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Description

【０００９】
【課題を解決するための手段】
本発明は、前記の目的を達成するため、複数の入出力端子中に複数の同種の入出力端子が配置されたＩＣを備え、当該ＩＣ上に絶縁層を介して再配線層が形成され、当該再配線層を介して前記入出力端子とバンプとが電気的に接続された半導体チップにおいて、前記再配線層を用いて前記同種の入出力端子を電気的に接続するという構成にした。
また、回路形成面の外周領域に複数の入出力端子が配列され、かつこれら複数の入出力端子中に複数の同種の入出力端子が配置されたＩＣを備え、当該ＩＣの前記回路成形面上に絶縁層を介して再配線層が形成され、当該再配線層を介して前記回路成形面の外周部に配置された入出力端子と前記回路成形面の内周部に配置されたバンプとが電気的に接続された半導体チップにおいて、前記再配線層を用いて前記同種の入出力端子を電気的に接続するという構成にした。 0009
[Means for solving problems]
In the present invention, in order to achieve the above object, an IC in which a plurality of input / output terminals of the same type are arranged in a plurality of input / output terminals is provided, and a rewiring layer is formed on the IC via an insulating layer. In a semiconductor chip in which the input / output terminals and bumps are electrically connected via the rewiring layer, the same type of input / output terminals are electrically connected using the rewiring layer .
Further, an IC in which a plurality of input / output terminals are arranged in the outer peripheral region of the circuit forming surface and a plurality of input / output terminals of the same type are arranged in the plurality of input / output terminals is provided on the circuit forming surface of the IC. A rewiring layer is formed via the insulating layer, and the input / output terminals arranged on the outer peripheral portion of the circuit forming surface and the bumps arranged on the inner peripheral portion of the circuit forming surface are formed via the rewiring layer. In the electrically connected semiconductor chip, the same type of input / output terminals are electrically connected by using the rewiring layer.

再配線層は、絶縁層上に自由に形成することができるので、回路成形面に形成された回路ブロックによって配線の自由度が制限されるＩＣの内部配線に比べて導体抵抗や配線間容量を低減することができる。したがって、再配線層を用いて同種の入出力端子間を電気的に接続すると、同種の入出力端子間における電圧降下や信号波形のなまりを防止することができるので、半導体チップの動作特性を向上させることができる。 Since the rewiring layer can be freely formed on the insulating layer, the conductor resistance and the capacity between wirings can be increased as compared with the internal wiring of an IC in which the degree of freedom of wiring is limited by the circuit block formed on the circuit forming surface. Can be reduced. Therefore, by electrically connecting the same type of input / output terminals using the rewiring layer, it is possible to prevent voltage drop and signal waveform blunting between the same type of input / output terminals, thus improving the operating characteristics of the semiconductor chip. Can be made to.

【００３７】
【発明の効果】
以上説明したように、本発明によると、ＩＣの内部配線に比べて導体抵抗や配線間容量が小さい再配線層を用いて、ＩＣ上に配列された同種の入出力端子間を電気的に接続したので、同種の入出力端子間における電圧降下や信号波形のなまりを防止することができ、半導体チップの動作特性を向上させることができる。 0037
【The invention's effect】
As described above, according to the present invention, the same type of input / output terminals arranged on the IC are electrically connected by using a rewiring layer having a smaller conductor resistance and inter-wiring capacitance than the internal wiring of the IC. Therefore, it is possible to prevent a voltage drop and signal waveform blunting between input / output terminals of the same type, and it is possible to improve the operating characteristics of the semiconductor chip.

Claims (5)

複数の入出力端子中に複数の同種の入出力端子が配置されたＩＣを備え、当該ＩＣ上に絶縁層を介して再配線層が形成され、当該再配線層を介して前記入出力端子とバンプとが電気的に接続された半導体チップにおいて、前記再配線層を用いて前記同種の入出力端子を電気的に接続したことを特徴とする半導体チップ。 The IC includes an IC in which a plurality of identical input / output terminals are disposed in a plurality of input / output terminals, a rewiring layer is formed on the IC via an insulating layer, and the input / output terminals 1. A semiconductor chip electrically connected to a bump, wherein the same type of input / output terminals are electrically connected using the rewiring layer . 回路形成面の外周領域に複数の入出力端子が配列され、かつこれら複数の入出力端子中に複数の同種の入出力端子が配置されたＩＣを備え、当該ＩＣの前記回路成形面上に絶縁層を介して再配線層が形成され、当該再配線層を介して前記回路成形面の外周部に配置された入出力端子と前記回路成形面の内周部に配置されたバンプとが電気的に接続された半導体チップにおいて、前記再配線層を用いて前記同種の入出力端子を電気的に接続したことを特徴とする半導体チップ。 The IC includes an IC having a plurality of input / output terminals arranged in an outer peripheral area of the circuit formation surface and a plurality of same input / output terminals arranged in the plurality of input / output terminals, and insulating on the circuit formation surface of the IC. The rewiring layer is formed through the layers, and the input / output terminals disposed on the outer periphery of the circuit molding surface via the rewiring layer and the bumps disposed on the inner periphery of the circuit molding surface are electrically semiconductors chips in connected semiconductor chips, you characterized by using said re-wiring layer connecting the input and output terminals of the same type electrically to. 前記絶縁層が厚膜プロセスで形成されていることを特徴とする請求項１又は請求項２に記載の半導体チップ。The semiconductor chip according to claim 1, wherein the insulating layer is formed by a thick film process. 前記再配線層が厚膜プロセスで形成されていることを特徴とする請求項１又は請求項２に記載の半導体チップ。The semiconductor chip of claim 1 or claim 2, wherein the redistribution layer is formed by thick film processes. 前記再配線層が銅で形成されていることを特徴とする請求項１又は請求項２に記載の半導体チップ。The semiconductor chip of claim 1 or claim 2, wherein the redistribution layer is formed of copper.
JP2002188053A 2002-06-27 2002-06-27 Semiconductor chip Pending JP2004031790A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002188053A JP2004031790A (en) 2002-06-27 2002-06-27 Semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002188053A JP2004031790A (en) 2002-06-27 2002-06-27 Semiconductor chip

Publications (2)

Publication Number Publication Date
JP2004031790A JP2004031790A (en) 2004-01-29
JP2004031790A5 true JP2004031790A5 (en) 2005-05-12

Family

ID=31182914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002188053A Pending JP2004031790A (en) 2002-06-27 2002-06-27 Semiconductor chip

Country Status (1)

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JP (1) JP2004031790A (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101814458B (en) * 2004-12-03 2012-05-30 罗姆股份有限公司 Semiconductor device with a plurality of semiconductor chips
JP4774248B2 (en) 2005-07-22 2011-09-14 Ｏｋｉセミコンダクタ株式会社 Semiconductor device
JP2009212481A (en) * 2007-04-27 2009-09-17 Sharp Corp Semiconductor device and manufacturing method thereof
JP4683082B2 (en) * 2007-09-04 2011-05-11 エプソンイメージングデバイス株式会社 Semiconductor device, semiconductor mounting structure, electro-optical device
JP4645635B2 (en) * 2007-11-02 2011-03-09 セイコーエプソン株式会社 Electronic components
JP5655197B2 (en) * 2010-10-27 2015-01-21 リコー電子デバイス株式会社 Semiconductor package
JP6194516B2 (en) * 2014-08-29 2017-09-13 豊田合成株式会社 MIS type semiconductor device
US9589946B2 (en) * 2015-04-28 2017-03-07 Kabushiki Kaisha Toshiba Chip with a bump connected to a plurality of wirings
JP2017174994A (en) 2016-03-24 2017-09-28 ソニー株式会社 Imaging apparatus and electronic apparatus
JP7303343B2 (en) * 2017-11-29 2023-07-04 ラピスセミコンダクタ株式会社 Semiconductor device and method for manufacturing semiconductor device

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