JP2004029247A

JP2004029247A - Driving circuit for light emitting element, and picture display device

Info

Publication number: JP2004029247A
Application number: JP2002183540A
Authority: JP
Inventors: Yasuichiro Kurita; 栗田　泰市郎; Seiji Tokito; 時任　静士; Yoji Inoue; 井上　陽司
Original assignee: Nippon Hoso Kyokai NHK; Japan Broadcasting Corp
Current assignee: Japan Broadcasting Corp
Priority date: 2002-06-24
Filing date: 2002-06-24
Publication date: 2004-01-29

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting element driving circuit in which a deterioration in quality of a moving picture is prevented, a variation in emission brightness of a light emitting element is reduced and the light emitting element is driven by an n-type transistor, and also to provide a picture display device having the driving circuit. <P>SOLUTION: The light emitting element driving circuit having the light emitting element 1, an n-type 1st field effect transistor (FET) 2 connected between the element 1 and a power supply and a 2nd FET 4 connected between the gate electrode and data electrode of the 1st FET 2 has also a capacitor 3 connected between the gate electrode of the 1st FET 2 and the element 1 and a 3rd FET 6 connected between the 1st FET 2 and a common electrode and turns on/off the 3rd FET 6 during a prescribed period in the 1st field period of a picture signal synchronously with the vertical period of the picture signal. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、供給される直流電流に応じて発光する発光素子をｎ型トランジスタで駆動する駆動回路、及び該駆動回路を有する画像表示装置に関する。
【０００２】
【従来の技術】
近年、有機電界発光（エレクトロルミネッセンス、ＥＬ）素子又は発光ダイオード（ＬＥＤ）などの発光素子を電界効果トランジスタ（ＦＦＴ）で駆動する駆動回路、及びこのような駆動回路を用いた画像表示装置が各種提案されてきている。
【０００３】
有機ＥＬ素子又はＬＥＤなどの発光素子をＦＥＴで駆動する駆動回路としては、例えば、図７（ａ）の回路図に示すような、発光素子をｎ型ＦＥＴで駆動する駆動回路が考えられる。
【０００４】
図７（ａ）に示す発光素子をｎ型ＦＥＴで駆動する駆動回路は、画像表示装置の１画素における駆動回路であり、発光素子１、２個のＦＥＴ２及び４、コンデンサ３又は１０を有する。ただし、ＦＥＴ２は、ｎ型ＦＥＴである。発光素子１は、有機ＥＬ素子又はＬＥＤであり、一定方向に直流電流を流すと、その電流値に応じた輝度で発光する。発光素子１のカソードは、共通電極（図７においてはアース）に接続されており、発光素子１のアノードは、ｎ型ＦＥＴ２のソース電極Ｓに接続されている。ｎ型ＦＥＴ２のドレイン電極Ｄは、共通電極に対して正の電位にある＋電源に接続されている。なお、一般にＦＥＴでは、構造上はＤとＳを特に区別する必要がなく、ＤとＳを互いに逆に接続しても同様に動作するため、以下では特に必要ない限りＤとＳを区別しない。図７の点線で示すように、ｎ型ＦＥＴ２のゲート電極Ｇと共通電極の間には、コンデンサ３又は１０が接続される。ただし、コンデンサ３の代わりに、ｎ型ＦＥＴ２のゲート電極Ｇと＋電源との間にコンデンサ１０を接続してもよい。即ち、＋電源と共通電極との間の電圧は、一定な直流電圧であるため、どちらの場合も駆動回路は、同様に動作する。ｎ型ＦＥＴ２のＧは、またＦＥＴ４のドレイン電極Ｄ（又はソース電極Ｓ）が接続されており、ＦＥＴ４のソース電極Ｓ（又はドレイン電極Ｄ）は、データ電極（以後、簡単のために単にデータと呼ぶ）に接続されている。なお、ＦＥＴ４に関しては、ｎ型でもｐ型でもよい。また、ＦＥＴ４のゲート電極は、走査電極Ｓ１に接続される。
【０００５】
図７（ｂ）は、図７（ａ）に示す駆動回路における走査電極Ｓ１及びデータ電極の電圧の波形、並びに発光素子１の発光輝度Ｌの波形を示す。各波形の横軸は時間ｔであり、縦軸は、各電極の電圧又は発光素子の輝度を表す。図７（ａ）に示す駆動回路において、データ電極からは、複数の画素の発光に関する電圧が１フィールド周期で連続的に駆動回路に供給される。ＦＥＴ４がｎ型ＦＥＴであるとして、画像信号の１フィールド期間に１回、Ｓ１を短時間だけ＋電位にする。
ＦＥＴ４は、その時間だけオン状態になり、ＦＥＴ４を通してその時点におけるデータ電極の電圧（その時点におけるその画素の発光に必要な電圧）でコンデンサ３又は１０が充電される。ｎ型ＦＥＴ２のソース電圧は、ゲート電圧すなわちコンデンサ３又は１０の両端間の電圧に応じた一定値となる性質があり、発光素子１のアノード電圧もその一定値となる。発光素子１には、その電圧−電流特性に応じて＋電源から共通電極へ一定の電流が流れ、その電流値に応じた輝度で発光する。ＦＥＴ４をオフ状態にすると、コンデンサ３又は１０に蓄積された電荷が維持されているため、発光素子１は、１フィールドの間（テレビ画像であれば１／６０秒間（約１６．７ｍｓｅｃ））一定の輝度で発光し続ける。
【０００６】
このような駆動回路によって、発光素子１を１フィールドの間連続して発光させ、人間の目で感知できる輝度及びコントラストの発光を得ることができる。また、発光素子１の輝度は、データ電源からの電圧の大きさに依存して変化する。なお、ＦＥＴ４が、ｐ型ＦＥＴである場合には、Ｓ１の波形を上下（正負）反転すれば、上記のｎ型ＦＥＴである場合と全く同様な動作を実現できる。
【０００７】
【発明が解決しようとする課題】
このように、発光素子をＦＥＴで駆動する駆動回路、従ってその駆動回路を有する画像表示装置は、画素から発光する光の輝度が、画像信号の１フィールドの間ほぼ一定に保たれるホールド効果を有する。この発光のホールド効果のため、上記の画像表示装置に動画を表示した際には、表示画像に動きボケが発生して、動画の表示画質が劣化することは、例えば、栗田泰市郎，“液晶表示装置で生じる原理的な動画質劣化とその改善法”，映像情報メディア学会技術報告，Ｖｏｌ．２４，Ｎｏ．５４，ＰＰ．１３−１６，ＩＤＹ２０００−１４７，（Ｓｅｐ．２０００）に記載されるように知られている。このような動画の表示画質の劣化を改善するひとつの方法は、画素の表示輝度のホールド時間を短縮することである。また、液晶表示装置については、上記文献や本願の出願人による発明（特開平９−３２５７１５「画像表示装置」）にホールド時間を短縮する具体的方法が開示されている。
【０００８】
しかしながら、有機ＥＬ素子又はＬＥＤなどの発光素子を、ｎ型ＴＦＴで駆動する駆動回路、及びこのような駆動回路を用いた画像表示装置については、ホールド効果による動画の表示画質の劣化を有効に改善する具体的な手段は示されていない。
【０００９】
また、発光素子の電圧−電流特性にばらつきが無ければ、発光素子は、コンデンサに充電された電圧に応じた一定の輝度で発光するが、一般には発光素子の電圧−電流特性にはばらつきがある。これにより、これらの発光素子に一定の電圧を印加しても、発光素子を流れる電流値にばらつきを生じるため、これらの発光素子の発光輝度にもばらつきが生じる。よって、これらの電圧−電流特性にばらつきのある発光素子で画像表示装置を構成した場合、このばらつきが画素ごとの輝度のばらつきに関する一つの原因となり、表示画質の著しい劣化を招く。
【００１０】
本発明は、上記問題に鑑みなされたものであり、動画の画質劣化を改善した、及び／又は発光素子の発光輝度のばらつきを低減した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路、及び該駆動回路を有する画像表示装置を提供することを目的とする。
【００１１】
【課題を解決するための手段】
請求項１記載の発明は、供給される直流電流に応じて発光する二端子の発光素子と、前記発光素子の一方の端子と電源との間に、ソース電極とドレイン電極とが接続されるｎ型の第一の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極とデータ電極との間に、ソース電極とドレイン電極とが接続される第二の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極と前記電源との間、又は前記第一の電界効果トランジスタのゲート電極と共通電極との間に、接続されるコンデンサと、を有する発光素子の駆動回路において、前記コンデンサに並列に接続されてオン／オフする第三の電界効果トランジスタをさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第三の電界効果トランジスタをオン／オフすることを特徴とする。
【００１２】
請求項１記載の発明によれば、前記コンデンサに並列に接続されてオン／オフする第三の電界効果トランジスタをさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第三の電界効果トランジスタをオン／オフするので、動画の画質劣化を改善した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路を提供することができる。
【００１３】
請求項２記載の発明は、供給される直流電流に応じて発光する二端子の発光素子と、前記発光素子の一方の端子と電源との間に、ソース電極とドレイン電極とが接続されるｎ型の第一の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極とデータ電極との間に、ソース電極とドレイン電極とが接続される第二の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極と前記電源との間、又は前記第一の電界効果トランジスタのゲート電極と共通電極との間に、接続されるコンデンサと、を有する発光素子の駆動回路において、前記電源と前記第一の電界効果トランジスタとの間に、前記第一の電界効果トランジスタに直列に接続され、オン／オフする第三の電界効果トランジスタをさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第三の電界効果トランジスタをオン／オフすることを特徴とする。
【００１４】
請求項２記載の発明によれば、前記電源と前記第一の電界効果トランジスタとの間に、前記第一の電界効果トランジスタに直列に接続され、オン／オフする第三の電界効果トランジスタをさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第三の電界効果トランジスタをオン／オフするので、動画の画質劣化を改善した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路を提供することができる。
【００１５】
請求項３記載の発明は、供給される直流電流に応じて発光する二端子の発光素子と、前記発光素子の一方の端子と電源との間に、ソース電極とドレイン電極とが接続されるｎ型の第一の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極とデータ電極との間に、ソース電極とドレイン電極とが接続される第二の電界効果トランジスタと、を有する発光素子の駆動回路において、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続される第三の電界効果トランジスタをさらに有することを特徴とする。
【００１６】
請求項３記載の発明によれば、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続される第三の電界効果トランジスタをさらに有するので、発光素子の発光輝度のばらつきを低減した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路を提供することができる。
【００１７】
請求項４記載の発明は、供給される直流電流に応じて発光する二端子の発光素子と、前記発光素子の一方の端子と電源との間に、ソース電極とドレイン電極とが接続されるｎ型の第一の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極とデータ電極との間に、ソース電極とドレイン電極とが接続される第二の電界効果トランジスタと、を有する発光素子の駆動回路において、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続され、オン／オフする第三の電界効果トランジスタをさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第三の電界効果トランジスタをオン／オフすることを特徴とする。
【００１８】
請求項４記載の発明によれば、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続され、オン／オフする第三の電界効果トランジスタをさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第三の電界効果トランジスタをオン／オフするので、動画の画質劣化を改善した、及び発光素子の発光輝度のばらつきを低減した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路を提供することができる。
【００１９】
請求項５記載の発明は、供給される直流電流に応じて発光する二端子の発光素子と、前記発光素子の一方の端子と電源との間に、ソース電極とドレイン電極とが接続されるｎ型の第一の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極とデータ電極との間に、ソース電極とドレイン電極とが接続される第二の電界効果トランジスタと、を有する発光素子の駆動回路において、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続され、オン／オフする第三の電界効果トランジスタと、前記コンデンサの両端に並列に接続され、オン／オフする第四の電界効果トランジスタと、をさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第四の電界効果トランジスタをオン／オフすることを特徴とする。
【００２０】
請求項５記載の発明によれば、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続され、オン／オフする第三の電界効果トランジスタと、前記コンデンサの両端に並列に接続され、オン／オフする第四の電界効果トランジスタと、をさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第四の電界効果トランジスタをオン／オフするので、動画の画質劣化を改善した、及び発光素子の発光輝度のばらつきを低減した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路を提供することができる。
【００２１】
請求項６記載の発明は、供給される直流電流に応じて発光する二端子の発光素子と、前記発光素子の一方の端子と電源との間に、ソース電極とドレイン電極とが接続されるｎ型の第一の電界効果トランジスタと、前記第一の電界効果トランジスタのゲート電極とデータ電極との間に、ソース電極とドレイン電極とが接続される第二の電界効果トランジスタと、を有する発光素子の駆動回路において、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続され、オン／オフする第三の電界効果トランジスタと、前記電源と前記第一の電界効果トランジスタとの間に、前記第一の電界効果トランジスタに直列に接続され、オン／オフする第四の電界効果トランジスタと、をさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第四の電界効果トランジスタをオン／オフすることを特徴とする。
【００２２】
請求項６記載の発明によれば、前記第一の電界効果トランジスタのゲート電極と前記発光素子の前記一方の端子との間に接続されるコンデンサと、前記発光素子の前記一方の端子と共通電極との間に接続され、オン／オフする第三の電界効果トランジスタと、前記電源と前記第一の電界効果トランジスタとの間に、前記第一の電界効果トランジスタに直列に接続され、オン／オフする第四の電界効果トランジスタと、をさらに有し、画像信号の垂直同期に同期して前記画像信号の１フィールド期間内の所定期間、前記第四の電界効果トランジスタをオン／オフするので、動画の画質劣化を改善した、及び発光素子の発光輝度のばらつきを低減した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路を提供することができる。
【００２３】
請求項７記載の発明は、画像表示装置において、請求項１乃至６いずれか１項記載の発光素子の駆動回路を有する。
【００２４】
請求項７記載の発明によれば、請求項１乃至６いずれか１項記載の発光素子の駆動回路を有するので、動画の画質劣化を改善した、及び／又は発光素子の発光輝度のばらつきを低減した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路を有する画像表示装置を提供することができる。
【００２５】
【発明の実施の形態】
次に、本発明の実施の形態について図面と共に説明する。
【００２６】
まず、本発明における発光素子を駆動する駆動回路の第一の実施形態を図１とともに説明する。図１（ａ）に示す本発明の、発光素子をｎ型電界効果トランジスタ（ＦＥＴ）で駆動する駆動回路は、画像表示装置の１画素における駆動回路であり、発光素子１、３個のＦＥＴ２、４及び５、コンデンサ３を有する。ただし、ＦＥＴ２は、ｎ型ＦＥＴである。発光素子１は、例えば、有機電界発光（エレクトロルミネッセンス、ＥＬ）素子又は発光ダイオード（ＬＥＤ）などであり、二つの端子を有し、一定方向に直流電流を流すと、その電流値に応じた輝度で発光する。発光素子１のカソードは、共通電極（図１においてはアース）に接続されており、発光素子１のアノードは、ｎ型ＦＥＴ２のドレイン（又はソース）電極に接続されている。ｎ型ＦＥＴ２のソース（又はドレイン）電極は、共通電極に対して正の電位にある＋電源に接続されている。なお、一般にＦＥＴでは、構造上はドレイン電極とソース電極を特に区別する必要がなく、ドレイン電極とソース電極を互いに逆に接続しても同様に動作するため、以下では特に必要ない限りドレイン電極とソース電極を区別しない。ｎ型ＦＥＴ２のゲート電極と共通電極の間には、コンデンサ３接続される。ただし、コンデンサ３の代わりに、ｎ型ＦＥＴ２のゲート電極と＋電源との間にコンデンサを接続してもよい。即ち、＋電源と共通電極との間の電圧は、一定な直流電圧であるため、どちらの場合も駆動回路は、同様に動作する。ｎ型ＦＥＴ２のゲート電極は、またＦＥＴ４のドレイン電極（又はソース電極）が接続されており、ＦＥＴ４のソース電極（又はドレイン電極）は、データ電極（以後、簡単のために単にデータと呼ぶ）に接続されている。また、ＦＥＴ４のゲート電極は、第一の走査電極Ｓ１に接続される。さらに、ＦＥＴ５が、コンデンサ３に対して並列に設けられ、ＦＥＴ５のドレイン電極（又はソース電極）は、ｎ型ＦＥＴ２のゲート電極に接続しており、ＦＥＴ５のソース電極（又はドレイン電極）は共通電極（図１では、アース）に接続している。また、ＦＥＴ５のゲート電極は、第２の走査電極Ｓ２に接続される。なお、ＦＥＴ４、５に関しては、ｎ型でもｐ型でもよい。
【００２７】
図１（ｂ）は、図１（ａ）に示す駆動回路における走査電極Ｓ１、データ電極、走査電極Ｓ２の電圧の波形、並びに発光素子１の発光輝度Ｌの波形を示す。各波形の横軸は、時間ｔであり、縦軸は、各電極の電圧又は発光素子の輝度を表す。図１（ａ）に示す駆動回路において、データ電極からは、複数の画素の発光に関する電圧が１フィールド周期で連続的に駆動回路に供給される。ＦＥＴ４がｎ型ＦＥＴであるとして、画像信号の１フィールド期間に１回、Ｓ１を短時間だけ＋電位にする。ＦＥＴ４は、その時間だけオン状態になり、ＦＥＴ４を通してその時点におけるデータ電極の電圧（その時点におけるその画素の発光に必要な電圧）でコンデンサ３が充電される。ｎ型ＦＥＴ２のドレイン（ソース）電圧は、ゲート電圧すなわちコンデンサ３の両端間の電圧に応じた一定値となる性質があり、発光素子１のアノード電圧もその一定値となる。発光素子１には、その電圧−電流特性に応じて＋電源から共通電極へ一定の電流が流れ、その電流値に応じた輝度で発光する。ＦＥＴ４をオフ状態にすると、コンデンサ３に蓄積された電荷が維持されているため、発光素子１は、発光し続ける。また、発光素子１の輝度は、データ電源からの電圧の大きさに依存して変化する。
【００２８】
ここで、図１（ｂ）に示すように、Ｓ１を短時間＋電位にし、発光素子を、人間の目の感度に対して十分な輝度が得られるまで発光させた後、ＦＥＴ５もｎ型であるとして、１フィールド期間内で一定の時間だけ遅延させて、Ｓ２を短時間だけ＋電位にする。Ｓ２が＋電位になった時点でＦＥＴ５がオン状態となり、ＦＥＴ５のソース電極及びドレイン電極が導通する。これによりコンデンサ３は、短絡し、コンデンサ３に蓄積されていた電荷は、ＦＥＴ５を通して放電され、これ以後はコンデンサ３の両端間の電圧はゼロになる。これにより、ｎ型ＦＥＴ２のゲート電圧もゼロとなって、ｎ型ＦＥＴ２がオフ状態となる。よって、発光素子１を流れる電流が遮断され、発光素子１の発光輝度Ｌもゼロ（黒表示）となる。
【００２９】
なお、ＦＥＴ４及び／又は５が、ｐ型ＦＥＴである場合には、Ｓ１及び／又はＳ２の波形を上下（正負）反転すれば、上記のｎ型ＦＥＴである場合と全く同様な動作を実現できる。
【００３０】
このように本実施形態によれば、発光素子をｎ型ＦＥＴで駆動する駆動回路及びその駆動回路を有する画像表示装置において、画像信号の１フィールド期間内の一定時間だけ発光素子を発光させると共に、一定時間だけ発光素子に流れる電流を遮断することができる。すなわち、発光素子の発光のホールド時間を、Ｓ１とＳ２をオン状態にする時間間隔を制御することで、調整することができる。よって、発光素子の発光のホールド時間が短縮され、発光素子を流れる電流を遮断した一定時間だけ、画像の表示光の輝度をゼロにする、又は画像を黒表示とすることができる。このようにして、人間の目の感度に対して十分な輝度の発光を得ると共に、ＦＥＴのホールド効果に起因する表示画像の動きボケを減少させ、本実施形態の駆動回路を用いた画像表示装置における動画の表示画質を改善することができる。
【００３１】
次に、本発明における発光素子を駆動する駆動回路の第二の実施形態を図２とともに説明する。本実施形態は、図２（ａ）に示すように、図１に示す本発明の駆動回路における第一の実施形態において、コンデンサ３と並列に設けられたＦＥＴ５の代わりに、ｎ型ＦＥＴ２と直列にＦＥＴ６が設けられている。発光素子１、ＦＥＴ２及び４、コンデンサ３の配置及び動作は、第一実施形態における配置及び動作と同様である。ＦＥＴ６のソース電極（又はドレイン電極）は、ｎ型ＦＥＴのドレイン電極（ソース電極）に接続され、ＦＥＴ６のドレイン電極（又はソース電極）は、＋電源に接続される。また、ＦＥＴ６のゲート電極は、第２の走査電極Ｓ２に接続される。
【００３２】
図２（ｂ）に示すように、ＦＥＴ６がｎ型であるとして、画像信号の垂直同期に同期して、１フィールド内の一定時間だけ＋電位であり他の時間はゼロ電位であるような電圧をＳ２からＦＥＴ６のゲート電極へ印加する。Ｓ２からの電圧がゼロ電位である間は、ＦＥＴ６がオフ状態にあり、ｎ型ＦＥＴ２のソース電極とドレイン電極間に電流が流れない。よって、このとき発光素子１を流れる電流が遮断され、発光素子１の発光輝度Ｌもゼロ（黒表示）となる。またＳ２からの電圧が＋電位にあるときには、ＦＥＴ６がオン状態にあり、ＦＥＴ６のソース電極とドレイン電極間を電流が流れて、発光素子１が発光する。
【００３３】
なお、ＦＥＴ６も、ｎ型でもｐ型でもよく、ｐ型の場合には、Ｓ２の波形を上下（正負）反転すれば、上記のｎ型ＦＥＴである場合と全く同様な動作を実現できる。
【００３４】
このように本実施形態によれば、第一の実施形態と同様に、発光素子の発光のホールド時間が短縮され、ＦＥＴのホールド効果に起因する表示画像の動きボケを減少させ、動画の表示画質を改善することができる。
【００３５】
次に、本発明における発光素子を駆動する駆動回路の第三の実施形態を図３とともに説明する。図３（ａ）に示す本発明の、発光素子をｎ型電界効果トランジスタ（ＦＥＴ）で駆動する駆動回路は、画像表示装置の１画素における駆動回路であり、発光素子１、３個のＦＥＴ２、４及び５、コンデンサ３を有する。ただし、ＦＥＴ２は、ｎ型ＦＥＴである。発光素子１のカソードは、共通電極（図３においてはアース）に接続されており、発光素子１のアノードは、ｎ型ＦＥＴ２のソース電極Ｓに接続されている。ｎ型ＦＥＴ２のドレイン電極Ｄは、共通電極に対して正の電位にある＋電源に接続されている。なお、一般にＦＥＴでは、構造上はドレイン電極とソース電極を特に区別する必要がなく、ドレイン電極とソース電極を互いに逆に接続しても同様に動作するため、以下では特に必要ない限りドレイン電極とソース電極を区別しない。ｎ型ＦＥＴ２のゲート電極Ｇは、またＦＥＴ４のドレイン電極（又はソース電極）が接続されており、ＦＥＴ４のソース電極（又はドレイン電極）は、データ電極に接続されている。また、ＦＥＴ４のゲート電極は、走査電極Ｓ１に接続される。
【００３６】
ここで、ｎ型ＦＥＴ２のゲート電極Ｇとソース電極Ｓの間には、コンデンサ３が接続される。図３においては、コンデンサ３は、ゲート電極Ｇとソース電極Ｓの間に接続されているが、ＦＥＴの構造においてソース電極とドレイン電極を区別する必要がないので、コンデンサ３は、ｎ型ＦＥＴ２のゲート電極と、ソース電極及びドレイン電極のうち発光素子と接続している電極との間に接続される。
さらに、ＦＥＴ５が、発光素子１に対して並列に設けられ、ＦＥＴ５のドレイン電極（又はソース電極）は、発光素子１のアノードに接続され、ＦＥＴ５のソース電極（又はドレイン電極）は発光素子１のカソード即ち共通電極（図３では、アース）に接続される。また、ＦＥＴ５のゲート電極は、走査電極Ｓ１に接続される。なお、ＦＥＴ４、５は、共にｎ型又は共にｐ型のどちらかである。
【００３７】
図３（ｂ）は、図３（ａ）に示す駆動回路における走査電極Ｓ１、データ電極の電圧の波形、並びに発光素子１の発光輝度Ｌの波形を示す。各波形の横軸は、時間ｔであり、縦軸は、各電極の電圧又は発光素子の輝度を表す。図３（ａ）に示す駆動回路において、データ電極からは、複数の画素の発光に関する電圧が１フィールド周期で連続的に駆動回路に供給される。ＦＥＴ４、５が共にｎ型ＦＥＴであるとして、画像信号の１フィールド期間に１回、Ｓ１を短時間だけ＋電位にする。ＦＥＴ４、５は、その時間だけオン状態になり、ＦＥＴ４、５を通してその時点におけるデータ電極の電圧（その時点におけるその画素の発光に必要な電圧）でコンデンサ３が充電される。ここで、仮にＦＥＴ５が駆動回路中に無いとすれば、コンデンサ３と共通電極（アース）と間に発光素子１が存在するため、コンデンサ３の両端に印加される電圧が低下し、データ電極の電圧に対応する電荷をコンデンサ３に蓄積することができない。本実施形態では、ＦＥＴ５をオン状態にしてコンデンサ３を共通電極に導通させることで、データ電極の電圧に対応する電荷をコンデンサ３に蓄積することができる。また、発光素子１は、ＦＥＴ５がオン状態にあるときは、短絡されて発光しない。
【００３８】
ＦＥＴ４、５がオフ状態になった後は、コンデンサ３に蓄積された電荷が維持される。ｎ型ＦＥＴ２は、ゲート−ソース（又はドレイン）間電圧すなわちコンデンサ３の両端間の電圧に応じた一定値の電流をドレイン電極−ソース電極間に流す性質がある。即ち、このｎ型ＦＥＴ２のソース電極−ドレイン電極間を流れる電流が、発光素子１に流れる。その結果、発光素子１は、コンデンサ３に充電された電圧に応じた輝度で１フィールド期間発光し続ける。走査電極Ｓ１を、再びオン状態にすると、発光素子１は短絡されて発光せず、Ｓ１を、再びオフ状態にすると、発光素子１がデータ電極からの電圧に応じた輝度で再び発光する。
【００３９】
本実施形態においては、発光素子１の電圧−電流特性にばらつきがあっても、ｎ型ＦＥＴ２のゲート−ソース（又はドレイン）間電圧がコンデンサ３によって維持されるため、ｎ型ＦＥＴ２及び発光素子１に一定の電流を流すことができる。即ち、発光素子１に流れる電流には、ばらつきを生じないため、発光素子１を、コンデンサ３に充電された電圧に応じて一定の輝度で発光させることができる。
【００４０】
なお、ＦＥＴ４、５が、共にｐ型ＦＥＴである場合には、Ｓ１の波形を上下（正負）反転すれば、上記のｎ型ＦＥＴである場合と全く同様な動作を実現できる。
【００４１】
このようにして本実施形態によれば、発光素子の電圧−電流特性のばらつきに関わらず、一定の電流を発光素子に流すことにより、発光素子の発光輝度のばらつきを低減させることができる。
【００４２】
次に、本発明における発光素子を駆動する駆動回路の第四の実施形態を図４とともに説明する。本実施形態は、図４（ａ）に示すように、図３に示す本発明の駆動回路における第三の実施形態において、ＦＥＴ５のゲート電極を走査電極Ｓ１に接続する代わりに、ＦＥＴ６のゲート電極を第二の走査電極Ｓ２に接続する。発光素子１、ＦＥＴ２及び４、コンデンサ３の配置及び動作は、第三の実施形態における配置及び動作と同様である。また、ＦＥＴ６が発光素子１と並列に設けられ、ＦＥＴ６のドレイン電極及びソース電極が、発光素子１のカソード、アノードに接続される点でも第三の実施形態と同様である。ただし、ＦＥＴ６は、ＦＥＴ４と独立して、ｎ型でもｐ型でもよい。
【００４３】
図４（ｂ）に示すように、ＦＥＴ６がｎ型であるとして、画像信号の垂直同期に同期して、第一の走査電極Ｓ１からの電圧が＋電位である時間を含む１フィールド内の一定時間だけ＋電位であり、他の時間はゼロ電位であるような電圧を第二の走査電極Ｓ２からＦＥＴ６のゲート電極へ印加する。Ｓ２からの電圧が＋電位である間は、ＦＥＴ６がオン状態にあり、ｎ型ＦＥＴ２のソース電極とドレイン電極間を流れる電流は、全てＦＥＴ６を通じて共通電極へ流れる。よって、発光素子１を流れる電流は遮断され、発光素子１の発光輝度Ｌもゼロ（黒表示）となる。また、コンデンサ３には、Ｓ１とＳ２とが共に＋電位であるときに、データ電極からの電圧に応じて電荷が蓄積される。Ｓ１をゼロ電位にした後は、コンデンサ３に電荷が蓄積されている。
【００４４】
Ｓ２からの電圧がゼロ電位にあるときには、ＦＥＴ６がオフ状態にあり、コンデンサ３の両端間の電圧に応じてｎ型ＦＥＴ２のソース電極とドレイン電極間流れる電流が、発光素子１に流れ、発光素子１が発光する。図３に示す第三の実施例と同様に、コンデンサ３が、ｎ型ＦＥＴ２のゲート電極−ソース電極（又はドレイン電極）間に設けられているため、ｎ型ＦＥＴ２のソース電極−ドレイン電極間に、従って発光素子１に、一定の電流を流すことができる。
【００４５】
なお、ＦＥＴ６は、ｎ型でもｐ型でもよく、ｐ型の場合には、Ｓ２の波形を上下（正負）反転すれば、上記のｎ型ＦＥＴである場合と全く同様な動作を実現できる。
【００４６】
このように本実施形態によれば、発光素子の発光のホールド時間を調整することで、人間の目の感度に対して十分な輝度の発光を得ると共に、ＦＥＴのホールド効果に起因する表示画像の動きボケを減少させ、本実施形態の駆動回路を用いた画像表示装置における動画の表示画質を改善することができる。また、発光素子の電圧−電流特性のばらつきに関わらず、一定の電流を発光素子に流すことにより、発光素子の発光輝度のばらつきを低減させることができる。
【００４７】
なお、Ｓ２が＋電位である時間は、Ｓ１が＋電位である時間を含んでいれば１フィールド内で連続でなくてもよく、１フィールド内で複数回（例えば２回）でもよい。
【００４８】
次に、本発明における発光素子を駆動する駆動回路の第五の実施形態を図５とともに説明する。本実施形態は、図５（ａ）に示すように、図３に示す本発明の駆動回路における第三の実施形態において、さらなるＦＥＴ７をｎ型ＦＥＴ２のゲート電極と発光素子１のアノードの間に設けてある。発光素子１、ＦＥＴ２、４及び５、コンデンサ３の配置及び動作は、第三の実施形態における配置及び動作と同様である。ＦＥＴ７のドレイン電極（又はソース電極）は、ｎ型ＦＥＴ２のゲート電極に接続され、ＦＥＴ７のソース電極（又はドレイン電極）は、発光素子１のアノードに接続される。また、ＦＥＴ７のゲート電極は、第二の走査電極Ｓ２に接続される。ここで、ＦＥＴ４及び５は、共にｎ型又は共にｐ型であり、ＦＥＴ７は、ＦＥＴ４、５と独立して、ｎ型でもｐ型でもよい。
【００４９】
図５（ｂ）に示すように、例えば、第一の走査電極Ｓ１からの電圧と同じ大きさの電圧を一定時間遅延させて第二の走査電極からＦＥＴ７のゲート電極に印可する。ＦＥＴ７がｎ型であるとして、第二の走査電極Ｓ２が＋電位にあるとき、ＦＥＴ７が、オン状態になり、コンデンサ３が短絡される。このとき、コンデンサ３に蓄積されていた電荷が、ＦＥＴ７を通して放電され、それ以後、コンデンサ３の両端間の電圧は、ゼロになる。これにより、ｎ型ＦＥＴ２のゲート−ソース（又はドレイン）電圧もゼロになり、ｎ型ＦＥＴ２は、オフ状態となる。よって、発光素子１を流れる電流が遮断され、発光輝度Ｌもゼロ（黒表示）となる。
なお、ＦＥＴ７は、ｎ型でもｐ型でもよく、ｐ型の場合には、Ｓ２の波形を上下（正負）反転すれば、上記のｎ型ＦＥＴである場合と全く同様な動作を実現できる。
【００５０】
このように本実施形態によれば、発光素子の発光のホールド時間を調整することで、人間の目の感度に対して十分な輝度の発光を得ると共に、ＦＥＴのホールド効果に起因する表示画像の動きボケを減少させ、本実施形態の駆動回路を用いた画像表示装置における動画の表示画質を改善することができる。また、発光素子の電圧−電流特性のばらつきに関わらず、一定の電流を発光素子に流すことにより、発光素子の発光輝度のばらつきを低減させることができる。
【００５１】
次に、本発明における発光素子を駆動する駆動回路の第六の実施形態を図６とともに説明する。本実施形態は、図６（ａ）に示すように、図３に示す本発明の駆動回路における第三の実施形態において、さらなるＦＥＴ８をｎ型ＦＥＴ２＋電源の間に、ｎ型ＦＥＴ２と直列に設けてある。発光素子１、ＦＥＴ２、４及び５、コンデンサ３の配置及び動作は、第三の実施形態における配置及び動作と同様である。ＦＥＴ８のソース電極（又はドレイン電極）は、ｎ型ＦＥＴ２のドレイン電極（又はソース電極）に接続され、ＦＥＴ８のドレイン電極（又はソース電極）は、＋電源に接続される。また、ＦＥＴ８のゲート電極は、第二の走査電極Ｓ２に接続される。
【００５２】
図６（ｂ）に示すように、ＦＥＴ８がｎ型であるとして、画像信号の垂直同期に同期して、１フィールド内の一定時間だけ＋電位であり他の時間はゼロ電位であるような電圧をＳ２からＦＥＴ８のゲート電極へ印加する。Ｓ２からの電圧がゼロ電位である間は、ＦＥＴ８がオフ状態にあり、ｎ型ＦＥＴ２のソース電極とドレイン電極間に電流が流れない。よって、このとき発光素子１を流れる電流が遮断され、発光素子１の発光輝度Ｌもゼロ（黒表示）となる。またＳ２からの電圧が＋電位にあるときには、ＦＥＴ８がオン状態にあり、ＦＥＴ８のソース電極とドレイン電極間を電流が流れて、発光素子１が発光する。なお、ＦＥＴ８は、ｎ型でもｐ型でもよく、ｐ型の場合には、Ｓ２の波形を上下（正負）反転すれば、上記のｎ型ＦＥＴである場合と全く同様な動作を実現できる。
【００５３】
このように本実施形態によれば、発光素子の発光のホールド時間を調整することで、人間の目の感度に対して十分な輝度の発光を得ると共に、ＦＥＴのホールド効果に起因する表示画像の動きボケを減少させ、本実施形態の駆動回路を用いた画像表示装置における動画の表示画質を改善することができる。また、発光素子の電圧−電流特性のばらつきに関わらず、一定の電流を発光素子に流すことにより、発光素子の発光輝度のばらつきを低減させることができる。
【００５４】
【発明の効果】
本発明によれば、動画の画質劣化を改善した、及び／又は発光素子の発光輝度のばらつきを低減した、発光素子をｎ型トランジスタで駆動する発光素子の駆動回路、及び該駆動回路を有する画像表示装置を提供することができる。
【００５５】
【図面の簡単な説明】
【図１】本発明による発光素子の駆動回路における第一の実施形態を説明する図であり、（ａ）は、回路図、（ｂ）は、その駆動回路における動作の波形を示す図である。
【図２】本発明による発光素子の駆動回路における第二の実施形態を説明する図であり、（ａ）は、回路図、（ｂ）は、その駆動回路における動作の波形を示す図である。
【図３】本発明による発光素子の駆動回路における第三の実施形態を説明する図であり、（ａ）は、回路図、（ｂ）は、その駆動回路における動作の波形を示す図である。
【図４】本発明による発光素子の駆動回路における第四の実施形態を説明する図であり、（ａ）は、回路図、（ｂ）は、その駆動回路における動作の波形を示す図である。
【図５】本発明による発光素子の駆動回路における第五の実施形態を説明する図であり、（ａ）は、回路図、（ｂ）は、その駆動回路における動作の波形を示す図である。
【図６】本発明による発光素子の駆動回路における第六の実施形態を説明する図であり、（ａ）は、回路図、（ｂ）は、その駆動回路における動作の波形を示す図である。
【図７】ｎ型ＦＥＴを用いた従来の発光素子の駆動回路を説明する図であり、（ａ）は、回路図、（ｂ）は、その駆動回路における動作の波形を示す図である。
【符号の説明】
１　　発光素子
２　　ｎ型ＦＥＴ
３、１０　　コンデンサ
４、５、６、７、８　　ＦＥＴ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a drive circuit for driving a light-emitting element that emits light in accordance with a supplied direct current with an n-type transistor, and an image display device including the drive circuit.
[0002]
[Prior art]
In recent years, various proposals have been made for a driving circuit for driving a light-emitting element such as an organic electroluminescence (electroluminescence, EL) element or a light-emitting diode (LED) by a field-effect transistor (FFT), and for an image display device using such a driving circuit. Have been.
[0003]
As a driving circuit for driving a light emitting element such as an organic EL element or an LED by an FET, for example, a driving circuit for driving a light emitting element by an n-type FET as shown in the circuit diagram of FIG.
[0004]
The drive circuit for driving the light emitting element shown in FIG. 7A with an n-type FET is a drive circuit for one pixel of an image display device, and has a light emitting element 1, two FETs 2 and 4, and a capacitor 3 or 10. However, FET2 is an n-type FET. The light emitting element 1 is an organic EL element or an LED, and emits light at a luminance corresponding to the current value when a direct current is passed in a certain direction. The cathode of the light emitting element 1 is connected to a common electrode (earth in FIG. 7), and the anode of the light emitting element 1 is connected to the source electrode S of the n-type FET 2. The drain electrode D of the n-type FET 2 is connected to a positive power supply having a positive potential with respect to the common electrode. Generally, in an FET, D and S do not need to be distinguished from each other in terms of structure, and the same operation is performed even if D and S are connected to each other. Therefore, D and S are not distinguished unless particularly necessary. As shown by the dotted line in FIG. 7, a capacitor 3 or 10 is connected between the gate electrode G of the n-type FET 2 and the common electrode. However, instead of the capacitor 3, a capacitor 10 may be connected between the gate electrode G of the n-type FET 2 and the + power supply. That is, since the voltage between the + power supply and the common electrode is a constant DC voltage, the drive circuit operates similarly in both cases. G of the n-type FET 2 is connected to the drain electrode D (or source electrode S) of the FET 4, and the source electrode S (or drain electrode D) of the FET 4 is connected to the data electrode (hereinafter simply referred to as data for simplicity). Call). The FET 4 may be either n-type or p-type. The gate electrode of the FET 4 is connected to the scan electrode S1.
[0005]
FIG. 7B shows the waveform of the voltage of the scan electrode S1 and the data electrode and the waveform of the light emission luminance L of the light emitting element 1 in the drive circuit shown in FIG. The horizontal axis of each waveform is time t, and the vertical axis represents the voltage of each electrode or the luminance of the light emitting element. In the driving circuit shown in FIG. 7A, the voltages related to light emission of a plurality of pixels are continuously supplied from the data electrodes to the driving circuit in one field cycle. Assuming that the FET 4 is an n-type FET, S1 is set to the + potential for a short time only once during one field period of the image signal.
The FET 4 is turned on for that time, and the capacitor 3 or 10 is charged with the voltage of the data electrode at that time (the voltage required for light emission of the pixel at that time) through the FET 4. The source voltage of the n-type FET 2 has a property of being constant according to the gate voltage, that is, the voltage between both ends of the capacitor 3 or 10, and the anode voltage of the light emitting element 1 also has the constant value. A constant current flows from the + power supply to the common electrode according to the voltage-current characteristics of the light emitting element 1, and emits light at a luminance corresponding to the current value. When the FET 4 is turned off, the charge accumulated in the capacitor 3 or 10 is maintained, so that the light emitting element 1 is kept constant for one field (for 1/60 second (about 16.7 msec in the case of a television image)). Continue to emit light at the brightness of.
[0006]
With such a driving circuit, the light-emitting element 1 can emit light continuously for one field, and light emission with luminance and contrast that can be sensed by human eyes can be obtained. Further, the luminance of the light emitting element 1 changes depending on the magnitude of the voltage from the data power supply. When the FET 4 is a p-type FET, the same operation as in the case of the n-type FET can be realized by inverting the waveform of S1 up and down (positive / negative).
[0007]
[Problems to be solved by the invention]
As described above, the driving circuit for driving the light emitting element by the FET, and therefore, the image display device having the driving circuit has a holding effect in which the luminance of the light emitted from the pixel is kept substantially constant during one field of the image signal. Have. Due to the hold effect of the light emission, when a moving image is displayed on the image display device, motion blur occurs in the displayed image, and the display quality of the moving image is degraded. Fundamental Degradation of Video Quality Caused by Display Device and Its Improvement Method ", Technical Report of the Institute of Image Information and Television Engineers, Vol. 24, no. 54, PP. 13-16, IDY2000-147, (Sep. 2000). One method for improving the deterioration of the display quality of a moving image is to shorten the hold time of the display luminance of the pixel. As for the liquid crystal display device, a specific method for shortening the hold time is disclosed in the above-mentioned document and the invention by the applicant of the present application (Japanese Patent Application Laid-Open No. 9-325715 "Image display device").
[0008]
However, for a driving circuit that drives an organic EL element or a light-emitting element such as an LED with an n-type TFT, and an image display device using such a driving circuit, the deterioration of display quality of a moving image due to a hold effect is effectively improved. No specific means for doing so is shown.
[0009]
In addition, if there is no variation in the voltage-current characteristics of the light-emitting element, the light-emitting element emits light at a constant luminance according to the voltage charged in the capacitor, but generally, there is variation in the voltage-current characteristic of the light-emitting element. . As a result, even when a constant voltage is applied to these light emitting elements, the current value flowing through the light emitting elements varies, so that the light emission luminance of these light emitting elements also varies. Therefore, when an image display device is configured with a light emitting element having a variation in the voltage-current characteristics, the variation is one of the causes of the variation in the luminance of each pixel, and the display quality is significantly deteriorated.
[0010]
The present invention has been made in view of the above problems, and has a light-emitting element driving circuit in which a light-emitting element is driven by an n-type transistor, in which image quality deterioration of a moving image is improved and / or variation in light-emitting luminance of the light-emitting element is reduced. And an image display device having the driving circuit.
[0011]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a two-terminal light emitting element that emits light in response to a supplied direct current, and a source electrode and a drain electrode connected between one terminal of the light emitting element and a power supply. A first field-effect transistor, a second field-effect transistor having a source electrode and a drain electrode connected between a gate electrode and a data electrode of the first field-effect transistor; and A capacitor connected between the gate electrode of the field-effect transistor and the power supply, or between the gate electrode of the first field-effect transistor and the common electrode, and a driving circuit of the light-emitting element, A third field effect transistor connected in parallel and turned on / off, wherein the third field effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal; And wherein the turning on / off the serial third field effect transistor.
[0012]
According to the first aspect of the present invention, there is further provided a third field-effect transistor which is connected in parallel to the capacitor and is turned on / off, and in one field period of the image signal in synchronization with vertical synchronization of the image signal. Since the third field-effect transistor is turned on / off for a predetermined period of time, it is possible to provide a light-emitting element driving circuit in which the light-emitting element is driven by an n-type transistor, in which the image quality of a moving image is improved.
[0013]
According to a second aspect of the present invention, there is provided a two-terminal light emitting element which emits light in response to a supplied DC current, and a source electrode and a drain electrode connected between one terminal of the light emitting element and a power supply. A first field-effect transistor, a second field-effect transistor having a source electrode and a drain electrode connected between a gate electrode and a data electrode of the first field-effect transistor; and A capacitor connected between the gate electrode of the field-effect transistor and the power supply or between the gate electrode of the first field-effect transistor and the common electrode; and a driving circuit for a light-emitting element, A third field-effect transistor that is connected in series with the first field-effect transistor and that is turned on / off between the first field-effect transistor and the first field-effect transistor; Predetermined period in one field period of the image signal in synchronization with the vertical synchronization, and wherein the turning on / off the third field effect transistor.
[0014]
According to the invention described in claim 2, a third field-effect transistor that is connected in series with the first field-effect transistor and that is turned on / off is further provided between the power supply and the first field-effect transistor. The third field-effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with the vertical synchronization of the image signal. It is possible to provide a driving circuit of a light emitting element driven by a type transistor.
[0015]
According to a third aspect of the present invention, there is provided a two-terminal light emitting element which emits light in response to a supplied direct current, and a source electrode and a drain electrode connected between one terminal of the light emitting element and a power supply. A light emitting device comprising: a first field-effect transistor of a type; and a second field-effect transistor having a source electrode and a drain electrode connected between a gate electrode and a data electrode of the first field-effect transistor. Wherein the capacitor is connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element, and is connected between the one terminal of the light emitting element and a common electrode. And a third field-effect transistor.
[0016]
According to the invention described in claim 3, a capacitor connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element, and the one terminal of the light emitting element and a common electrode And a third field-effect transistor connected between the light-emitting element and the third light-emitting element. Thus, it is possible to provide a light-emitting element driving circuit in which the light-emitting element is driven by an n-type transistor, in which variation in light emission luminance of the light-emitting element is reduced.
[0017]
According to a fourth aspect of the present invention, there is provided a two-terminal light emitting element which emits light in response to a supplied direct current, and a source electrode and a drain electrode connected between one terminal of the light emitting element and a power supply. A light emitting device comprising: a first field-effect transistor of a type; and a second field-effect transistor having a source electrode and a drain electrode connected between a gate electrode and a data electrode of the first field-effect transistor. Wherein the capacitor is connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element, and is connected between the one terminal of the light emitting element and a common electrode. A third field effect transistor that is turned on / off, and the third field effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal. And wherein the turning on / off the register.
[0018]
According to the invention described in claim 4, a capacitor connected between the gate electrode of the first field-effect transistor and the one terminal of the light emitting element, and the one terminal of the light emitting element and a common electrode And a third field-effect transistor that is turned on / off and is connected between the third field-effect transistor for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal. Is turned on / off, it is possible to provide a driving circuit for a light-emitting element in which a light-emitting element is driven by an n-type transistor, in which deterioration in moving image quality is reduced and variation in light-emitting luminance of the light-emitting element is reduced.
[0019]
According to a fifth aspect of the present invention, a two-terminal light-emitting element that emits light in response to a supplied direct current, and a source electrode and a drain electrode are connected between one terminal of the light-emitting element and a power supply. A light emitting device comprising: a first field-effect transistor of a type; and a second field-effect transistor having a source electrode and a drain electrode connected between a gate electrode and a data electrode of the first field-effect transistor. Wherein the capacitor is connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element, and is connected between the one terminal of the light emitting element and a common electrode. And a third field-effect transistor that is turned on / off and a fourth field-effect transistor that is connected in parallel to both ends of the capacitor and that is turned on / off, further comprising an image signal. Predetermined period within one field period of the image signal in synchronization with the vertical synchronization, and wherein the turning on / off said fourth field-effect transistor.
[0020]
According to the invention described in claim 5, a capacitor connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element, and the one terminal of the light emitting element and a common electrode And a fourth field-effect transistor connected in parallel between both ends of the capacitor and turned on / off, and a third field-effect transistor connected in parallel between both ends of the capacitor. Since the fourth field-effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with the synchronization, image quality deterioration of a moving image is improved, and variation in light emission luminance of the light emitting element is reduced. In addition, it is possible to provide a driving circuit of a light emitting element in which the light emitting element is driven by an n-type transistor.
[0021]
According to a sixth aspect of the present invention, there is provided a two-terminal light emitting element that emits light in response to a supplied direct current, and a source electrode and a drain electrode connected between one terminal of the light emitting element and a power supply. A light emitting device comprising: a first field-effect transistor of a type; and a second field-effect transistor having a source electrode and a drain electrode connected between a gate electrode and a data electrode of the first field-effect transistor. Wherein the capacitor is connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element, and is connected between the one terminal of the light emitting element and a common electrode. A third field-effect transistor that is turned on / off, and connected between the power supply and the first field-effect transistor in series with the first field-effect transistor; And turning on / off the fourth field effect transistor for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal. Features.
[0022]
According to the invention described in claim 6, a capacitor connected between the gate electrode of the first field-effect transistor and the one terminal of the light emitting element, and the one terminal of the light emitting element and a common electrode A third field-effect transistor connected between the power supply and the first field-effect transistor, and connected in series with the first field-effect transistor between the power supply and the first field-effect transistor; And a fourth field-effect transistor for turning on / off the fourth field-effect transistor for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal. It is possible to provide a driving circuit for a light-emitting element in which the light-emitting element is driven by an n-type transistor, in which the deterioration of the image quality of the light-emitting element is improved and the variation in the light emission luminance of the light-emitting element is reduced.
[0023]
According to a seventh aspect of the present invention, in an image display device, there is provided a driving circuit for a light emitting element according to any one of the first to sixth aspects.
[0024]
According to the seventh aspect of the present invention, since the driving circuit of the light emitting element according to any one of the first to sixth aspects is provided, deterioration of moving image quality is improved, and / or variation in light emission luminance of the light emitting element is reduced. Further, it is possible to provide an image display device having a light emitting element driving circuit in which a light emitting element is driven by an n-type transistor.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0026]
First, a first embodiment of a drive circuit for driving a light emitting element according to the present invention will be described with reference to FIG. A drive circuit for driving a light emitting element with an n-type field effect transistor (FET) according to the present invention shown in FIG. 1A is a drive circuit for one pixel of an image display device, and includes a light emitting element 1, three FETs 2, 4 and 5 and a capacitor 3. However, FET2 is an n-type FET. The light-emitting element 1 is, for example, an organic electroluminescence (electroluminescence, EL) element or a light-emitting diode (LED), and has two terminals. When a direct current flows in a certain direction, the luminance according to the current value is obtained. Emits light. The cathode of the light emitting element 1 is connected to a common electrode (earth in FIG. 1), and the anode of the light emitting element 1 is connected to the drain (or source) electrode of the n-type FET 2. The source (or drain) electrode of the n-type FET 2 is connected to a + power supply having a positive potential with respect to the common electrode. In general, in a FET, it is not necessary to distinguish the drain electrode and the source electrode from each other in terms of structure, and the same operation is performed even if the drain electrode and the source electrode are connected to each other in reverse. No distinction is made between source electrodes. A capacitor 3 is connected between the gate electrode of the n-type FET 2 and the common electrode. However, instead of the capacitor 3, a capacitor may be connected between the gate electrode of the n-type FET 2 and the + power supply. That is, since the voltage between the + power supply and the common electrode is a constant DC voltage, the drive circuit operates similarly in both cases. The gate electrode of the n-type FET 2 is connected to the drain electrode (or source electrode) of the FET 4, and the source electrode (or drain electrode) of the FET 4 is connected to the data electrode (hereinafter simply referred to as data for simplicity). It is connected. The gate electrode of the FET 4 is connected to the first scan electrode S1. Further, an FET 5 is provided in parallel with the capacitor 3, a drain electrode (or a source electrode) of the FET 5 is connected to a gate electrode of the n-type FET 2, and a source electrode (or a drain electrode) of the FET 5 is a common electrode. (In FIG. 1, ground). The gate electrode of the FET 5 is connected to the second scan electrode S2. The FETs 4 and 5 may be n-type or p-type.
[0027]
FIG. 1B shows the waveforms of the voltages of the scan electrode S1, the data electrode, and the scan electrode S2 and the waveform of the light emission luminance L of the light emitting element 1 in the drive circuit shown in FIG. The horizontal axis of each waveform is time t, and the vertical axis represents the voltage of each electrode or the luminance of the light emitting element. In the drive circuit shown in FIG. 1A, the voltages related to light emission of a plurality of pixels are continuously supplied from the data electrodes to the drive circuit in one field cycle. Assuming that the FET 4 is an n-type FET, S1 is set to the + potential for a short time only once during one field period of the image signal. The FET 4 is turned on for that time, and the capacitor 3 is charged with the voltage of the data electrode at that time (the voltage required for light emission of the pixel at that time) through the FET 4. The drain (source) voltage of the n-type FET 2 has a property of being a constant value according to the gate voltage, that is, the voltage between both ends of the capacitor 3, and the anode voltage of the light emitting element 1 also has the constant value. A constant current flows from the + power supply to the common electrode according to the voltage-current characteristics of the light emitting element 1, and emits light at a luminance corresponding to the current value. When the FET 4 is turned off, the charge accumulated in the capacitor 3 is maintained, so that the light emitting element 1 continues to emit light. Further, the luminance of the light emitting element 1 changes depending on the magnitude of the voltage from the data power supply.
[0028]
Here, as shown in FIG. 1B, S1 is set to a positive potential for a short time to cause the light emitting element to emit light until a luminance sufficient for human eye sensitivity is obtained. Suppose there is a delay for a certain time within one field period, and S2 is set to the + potential for a short time. When S2 becomes a positive potential, the FET 5 is turned on, and the source electrode and the drain electrode of the FET 5 become conductive. As a result, the capacitor 3 is short-circuited, and the electric charge stored in the capacitor 3 is discharged through the FET 5, and thereafter, the voltage between both ends of the capacitor 3 becomes zero. As a result, the gate voltage of the n-type FET 2 also becomes zero, and the n-type FET 2 is turned off. Therefore, the current flowing through the light emitting element 1 is cut off, and the light emission luminance L of the light emitting element 1 also becomes zero (black display).
[0029]
When the FETs 4 and / or 5 are p-type FETs, the same operation as that of the n-type FET can be realized by inverting the waveform of S1 and / or S2 up and down (positive / negative). .
[0030]
As described above, according to the present embodiment, in a drive circuit that drives a light-emitting element by an n-type FET and an image display device having the drive circuit, the light-emitting element emits light for a fixed time within one field period of an image signal. The current flowing to the light emitting element can be cut off for a certain time. That is, the light emission hold time of the light emitting element can be adjusted by controlling the time interval for turning on S1 and S2. Accordingly, the hold time of light emission of the light emitting element is reduced, and the brightness of display light of an image can be reduced to zero or the image can be displayed in black for a fixed time during which the current flowing through the light emitting element is cut off. In this way, while obtaining light emission of sufficient luminance for the sensitivity of the human eye, reducing the motion blur of the display image caused by the FET hold effect, the image display device using the drive circuit of the present embodiment , It is possible to improve the display quality of moving images.
[0031]
Next, a second embodiment of a drive circuit for driving a light emitting element according to the present invention will be described with reference to FIG. As shown in FIG. 2A, the present embodiment is different from the first embodiment in the drive circuit of the present invention shown in FIG. 1 in that instead of the FET 5 provided in parallel with the capacitor 3, the n-type FET 2 is connected in series. Is provided with an FET 6. The arrangement and operation of the light emitting element 1, the FETs 2 and 4, and the capacitor 3 are the same as the arrangement and operation in the first embodiment. The source electrode (or drain electrode) of the FET 6 is connected to the drain electrode (source electrode) of the n-type FET, and the drain electrode (or source electrode) of the FET 6 is connected to the + power supply. Further, the gate electrode of the FET 6 is connected to the second scan electrode S2.
[0032]
As shown in FIG. 2B, assuming that the FET 6 is of the n-type, the voltage is such that the potential is + potential for a certain time within one field and zero potential at other times in synchronization with the vertical synchronization of the image signal. From S2 to the gate electrode of FET6. While the voltage from S2 is at zero potential, FET 6 is off, and no current flows between the source electrode and the drain electrode of n-type FET 2. Therefore, at this time, the current flowing through the light emitting element 1 is cut off, and the light emission luminance L of the light emitting element 1 also becomes zero (black display). When the voltage from S2 is at the + potential, the FET 6 is in the ON state, a current flows between the source electrode and the drain electrode of the FET 6, and the light emitting element 1 emits light.
[0033]
The FET 6 may be of the n-type or the p-type. In the case of the p-type, the same operation as that of the n-type FET can be realized by inverting the waveform of S2 up and down (positive / negative).
[0034]
As described above, according to the present embodiment, similarly to the first embodiment, the light emission hold time of the light emitting element is shortened, the motion blur of the display image due to the FET hold effect is reduced, and the display quality of the moving image is reduced. Can be improved.
[0035]
Next, a third embodiment of the drive circuit for driving the light emitting element according to the present invention will be described with reference to FIG. A drive circuit for driving a light emitting element by an n-type field effect transistor (FET) according to the present invention shown in FIG. 3A is a drive circuit in one pixel of an image display device, and includes a light emitting element 1, three FETs 2, 4 and 5 and a capacitor 3. However, FET2 is an n-type FET. The cathode of the light emitting element 1 is connected to a common electrode (earth in FIG. 3), and the anode of the light emitting element 1 is connected to the source electrode S of the n-type FET 2. The drain electrode D of the n-type FET 2 is connected to a positive power supply having a positive potential with respect to the common electrode. In general, in a FET, it is not necessary to distinguish the drain electrode and the source electrode from each other in terms of structure, and the same operation is performed even if the drain electrode and the source electrode are connected to each other in reverse. No distinction is made between source electrodes. The gate electrode G of the n-type FET 2 is connected to the drain electrode (or source electrode) of the FET 4, and the source electrode (or drain electrode) of the FET 4 is connected to the data electrode. The gate electrode of the FET 4 is connected to the scan electrode S1.
[0036]
Here, the capacitor 3 is connected between the gate electrode G and the source electrode S of the n-type FET 2. In FIG. 3, the capacitor 3 is connected between the gate electrode G and the source electrode S. However, it is not necessary to distinguish between the source electrode and the drain electrode in the structure of the FET. The light-emitting element is connected between the gate electrode and the source electrode and the drain electrode that are connected to the light-emitting element.
Further, an FET 5 is provided in parallel with the light emitting element 1, a drain electrode (or a source electrode) of the FET 5 is connected to an anode of the light emitting element 1, and a source electrode (or a drain electrode) of the FET 5 is connected to the light emitting element 1. The cathode is connected to a common electrode (in FIG. 3, ground). The gate electrode of the FET 5 is connected to the scan electrode S1. The FETs 4 and 5 are either n-type or p-type.
[0037]
FIG. 3B shows the waveform of the voltage of the scan electrode S1 and the data electrode and the waveform of the light emission luminance L of the light emitting element 1 in the drive circuit shown in FIG. The horizontal axis of each waveform is time t, and the vertical axis represents the voltage of each electrode or the luminance of the light emitting element. In the drive circuit shown in FIG. 3A, the voltages related to the light emission of the plurality of pixels are continuously supplied from the data electrodes to the drive circuit in one field cycle. Assuming that both FETs 4 and 5 are n-type FETs, S1 is set to the + potential only once for one field period of the image signal for a short time. The FETs 4 and 5 are turned on for that time, and the capacitor 3 is charged through the FETs 4 and 5 with the voltage of the data electrode at that time (the voltage required for light emission of the pixel at that time). If the FET 5 is not present in the drive circuit, the light-emitting element 1 exists between the capacitor 3 and the common electrode (earth). The charge corresponding to the voltage cannot be stored in the capacitor 3. In the present embodiment, the FET 5 is turned on to make the capacitor 3 conductive to the common electrode, so that the charge corresponding to the voltage of the data electrode can be stored in the capacitor 3. Further, when the FET 5 is in the ON state, the light emitting element 1 is short-circuited and does not emit light.
[0038]
After the FETs 4 and 5 are turned off, the charge stored in the capacitor 3 is maintained. The n-type FET 2 has a property of flowing a constant current between the drain electrode and the source electrode according to the voltage between the gate and the source (or the drain), that is, the voltage between both ends of the capacitor 3. That is, a current flowing between the source electrode and the drain electrode of the n-type FET 2 flows to the light emitting element 1. As a result, the light emitting element 1 continues to emit light at a luminance corresponding to the voltage charged in the capacitor 3 for one field period. When the scan electrode S1 is turned on again, the light emitting element 1 is short-circuited and does not emit light. When the scan electrode S1 is turned off again, the light emitting element 1 emits light again at a luminance corresponding to the voltage from the data electrode.
[0039]
In the present embodiment, even if the voltage-current characteristics of the light-emitting element 1 vary, the voltage between the gate and the source (or the drain) of the n-type FET 2 is maintained by the capacitor 3. A constant current can flow through the device. That is, since the current flowing through the light emitting element 1 does not vary, the light emitting element 1 can emit light with a constant luminance according to the voltage charged in the capacitor 3.
[0040]
When the FETs 4 and 5 are both p-type FETs, exactly the same operation as the above-described n-type FET can be realized by inverting the waveform of S1 up and down (positive and negative).
[0041]
As described above, according to the present embodiment, it is possible to reduce the variation in the light emission luminance of the light emitting element by flowing a constant current through the light emitting element regardless of the variation in the voltage-current characteristics of the light emitting element.
[0042]
Next, a fourth embodiment of the drive circuit for driving the light emitting element according to the present invention will be described with reference to FIG. In the present embodiment, as shown in FIG. 4A, in the third embodiment of the drive circuit of the present invention shown in FIG. 3, instead of connecting the gate electrode of the FET 5 to the scan electrode S1, the gate electrode of the FET 6 Is connected to the second scan electrode S2. The arrangement and operation of the light emitting element 1, the FETs 2 and 4, and the capacitor 3 are the same as the arrangement and operation in the third embodiment. Further, the third embodiment is the same as the third embodiment in that the FET 6 is provided in parallel with the light emitting element 1, and the drain electrode and the source electrode of the FET 6 are connected to the cathode and the anode of the light emitting element 1. However, the FET 6 may be n-type or p-type independently of the FET 4.
[0043]
As shown in FIG. 4 (b), assuming that the FET 6 is of the n-type, the constant within one field including the time when the voltage from the first scan electrode S1 is + potential is synchronized with the vertical synchronization of the image signal. A voltage which is a + potential only for a time and is a zero potential at other times is applied from the second scan electrode S2 to the gate electrode of the FET6. While the voltage from S2 is at the + potential, the FET 6 is in the ON state, and all the current flowing between the source electrode and the drain electrode of the n-type FET 2 flows to the common electrode through the FET 6. Therefore, the current flowing through the light emitting element 1 is cut off, and the light emission luminance L of the light emitting element 1 also becomes zero (black display). When both S1 and S2 are at a positive potential, charges are accumulated in the capacitor 3 according to the voltage from the data electrode. After S1 is set to zero potential, electric charges are stored in the capacitor 3.
[0044]
When the voltage from S2 is at zero potential, the FET 6 is in the off state, and a current flowing between the source electrode and the drain electrode of the n-type FET 2 flows through the light emitting element 1 according to the voltage across the capacitor 3, and the light emitting element 1 1 emits light. As in the third embodiment shown in FIG. 3, since the capacitor 3 is provided between the gate electrode and the source electrode (or the drain electrode) of the n-type FET 2, the capacitor 3 is provided between the source electrode and the drain electrode of the n-type FET 2. Therefore, a constant current can flow through the light emitting element 1.
[0045]
The FET 6 may be either n-type or p-type. In the case of the p-type, the same operation as that of the n-type FET can be realized by inverting the waveform of S2 up and down (positive / negative).
[0046]
As described above, according to the present embodiment, by adjusting the light emission hold time of the light emitting element, light emission with sufficient luminance for the sensitivity of the human eye is obtained, and the display image of the display image caused by the FET hold effect is obtained. Motion blur can be reduced, and the display quality of a moving image in an image display device using the drive circuit of the present embodiment can be improved. In addition, by supplying a constant current to the light emitting element regardless of the variation in the voltage-current characteristics of the light emitting element, the variation in the light emission luminance of the light emitting element can be reduced.
[0047]
The time during which S2 is at the + potential may not be continuous within one field as long as it includes the time at which S1 is at the + potential, and may be a plurality of times (for example, two times) within one field.
[0048]
Next, a fifth embodiment of the drive circuit for driving the light emitting element according to the present invention will be described with reference to FIG. In this embodiment, as shown in FIG. 5A, in the third embodiment of the drive circuit of the present invention shown in FIG. 3, an additional FET 7 is provided between the gate electrode of the n-type FET 2 and the anode of the light emitting element 1. It is provided. The arrangement and operation of the light emitting element 1, the FETs 2, 4, and 5, and the capacitor 3 are the same as those in the third embodiment. The drain electrode (or source electrode) of the FET 7 is connected to the gate electrode of the n-type FET 2, and the source electrode (or drain electrode) of the FET 7 is connected to the anode of the light emitting device 1. The gate electrode of the FET 7 is connected to the second scan electrode S2. Here, the FETs 4 and 5 are both n-type or both p-type, and the FET 7 may be n-type or p-type independently of the FETs 4 and 5.
[0049]
As shown in FIG. 5B, for example, a voltage having the same magnitude as the voltage from the first scan electrode S1 is applied to the gate electrode of the FET 7 from the second scan electrode with a delay for a predetermined time. Assuming that the FET 7 is n-type, when the second scan electrode S2 is at the + potential, the FET 7 is turned on and the capacitor 3 is short-circuited. At this time, the electric charge stored in the capacitor 3 is discharged through the FET 7, and thereafter, the voltage between both ends of the capacitor 3 becomes zero. As a result, the gate-source (or drain) voltage of the n-type FET 2 also becomes zero, and the n-type FET 2 is turned off. Therefore, the current flowing through the light emitting element 1 is interrupted, and the light emission luminance L also becomes zero (black display).
The FET 7 may be an n-type or a p-type. In the case of the p-type, if the waveform of S2 is inverted up and down (positive / negative), the same operation as that of the n-type FET can be realized.
[0050]
As described above, according to the present embodiment, by adjusting the light emission hold time of the light emitting element, light emission with sufficient luminance for the sensitivity of human eyes can be obtained, and the display image of the display image caused by the FET hold effect can be obtained. Motion blur can be reduced, and the display quality of a moving image in an image display device using the drive circuit of the present embodiment can be improved. In addition, by supplying a constant current to the light emitting element regardless of the variation in the voltage-current characteristics of the light emitting element, the variation in the light emission luminance of the light emitting element can be reduced.
[0051]
Next, a sixth embodiment of the drive circuit for driving the light emitting element according to the present invention will be described with reference to FIG. In the present embodiment, as shown in FIG. 6A, in the third embodiment of the drive circuit of the present invention shown in FIG. 3, an additional FET 8 is provided in series with the n-type FET 2 between the n-type FET 2 and the power supply. It is. The arrangement and operation of the light emitting element 1, the FETs 2, 4, and 5, and the capacitor 3 are the same as those in the third embodiment. The source electrode (or the drain electrode) of the FET 8 is connected to the drain electrode (or the source electrode) of the n-type FET 2, and the drain electrode (or the source electrode) of the FET 8 is connected to the + power supply. The gate electrode of the FET 8 is connected to the second scan electrode S2.
[0052]
As shown in FIG. 6B, assuming that the FET 8 is of the n-type, the voltage is such that the potential is + potential for a certain time within one field and zero potential at other times in synchronization with the vertical synchronization of the image signal. Is applied from S2 to the gate electrode of FET8. While the voltage from S2 is at zero potential, the FET 8 is off and no current flows between the source electrode and the drain electrode of the n-type FET2. Therefore, at this time, the current flowing through the light emitting element 1 is cut off, and the light emission luminance L of the light emitting element 1 also becomes zero (black display). When the voltage from S2 is at the positive potential, the FET 8 is in the ON state, a current flows between the source electrode and the drain electrode of the FET 8, and the light emitting element 1 emits light. Note that the FET 8 may be either an n-type or a p-type. In the case of the p-type, the same operation as that of the n-type FET can be realized by inverting the waveform of S2 up and down (positive / negative).
[0053]
As described above, according to the present embodiment, by adjusting the light emission hold time of the light emitting element, light emission with sufficient luminance for the sensitivity of the human eye is obtained, and the display image of the display image caused by the FET hold effect is obtained. Motion blur can be reduced, and the display quality of a moving image in an image display device using the drive circuit of the present embodiment can be improved. In addition, by supplying a constant current to the light emitting element regardless of the variation in the voltage-current characteristics of the light emitting element, the variation in the light emission luminance of the light emitting element can be reduced.
[0054]
【The invention's effect】
According to the present invention, a driving circuit of a light-emitting element in which a light-emitting element is driven by an n-type transistor, in which deterioration of moving image quality is improved and / or variation in light-emitting luminance of the light-emitting element is reduced, and an image including the driving circuit A display device can be provided.
[0055]
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams illustrating a first embodiment of a light emitting element driving circuit according to the present invention, wherein FIG. 1A is a circuit diagram, and FIG. 1B is a diagram illustrating an operation waveform in the driving circuit. .
FIGS. 2A and 2B are diagrams illustrating a second embodiment of a light emitting element driving circuit according to the present invention, in which FIG. 2A is a circuit diagram, and FIG. 2B is a diagram illustrating an operation waveform in the driving circuit. .
3A and 3B are diagrams illustrating a third embodiment of a light emitting element driving circuit according to the present invention, wherein FIG. 3A is a circuit diagram, and FIG. 3B is a diagram illustrating an operation waveform in the driving circuit. .
4A and 4B are diagrams illustrating a fourth embodiment of a light emitting element drive circuit according to the present invention, wherein FIG. 4A is a circuit diagram, and FIG. 4B is a diagram illustrating operation waveforms in the drive circuit. .
5A and 5B are diagrams illustrating a fifth embodiment of a light emitting element driving circuit according to the present invention, wherein FIG. 5A is a circuit diagram, and FIG. 5B is a diagram illustrating an operation waveform in the driving circuit. .
FIGS. 6A and 6B are diagrams illustrating a sixth embodiment of the light emitting element driving circuit according to the present invention, wherein FIG. 6A is a circuit diagram, and FIG. 6B is a diagram illustrating an operation waveform in the driving circuit. .
FIGS. 7A and 7B are diagrams illustrating a conventional light-emitting element driving circuit using an n-type FET. FIG. 7A is a circuit diagram, and FIG. 7B is a diagram illustrating operation waveforms in the driving circuit.
[Explanation of symbols]
1 Light-emitting element
2 n-type FET
3, 10 capacitors
4, 5, 6, 7, 8 FET

Claims

A two-terminal light-emitting element that emits light in accordance with a supplied direct current, and an n-type first field-effect transistor in which a source electrode and a drain electrode are connected between one terminal of the light-emitting element and a power supply When,
Between the gate electrode and the data electrode of the first field-effect transistor, a second field-effect transistor connected to a source electrode and a drain electrode,
A capacitor connected between the gate electrode of the first field-effect transistor and the power supply, or between the gate electrode of the first field-effect transistor and a common electrode, and a driving circuit for a light-emitting element. ,
A third field-effect transistor that is connected in parallel to the capacitor and that is turned on / off;
A driving circuit for a light emitting element, wherein the third field effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal.

A two-terminal light-emitting element that emits light in accordance with a supplied direct current, and an n-type first field-effect transistor in which a source electrode and a drain electrode are connected between one terminal of the light-emitting element and a power supply When,
Between the gate electrode and the data electrode of the first field-effect transistor, a second field-effect transistor connected to a source electrode and a drain electrode,
A capacitor connected between the gate electrode of the first field-effect transistor and the power supply, or between the gate electrode of the first field-effect transistor and a common electrode, and a driving circuit for a light-emitting element. ,
A third field-effect transistor that is connected between the power supply and the first field-effect transistor in series with the first field-effect transistor and that is turned on / off;
A driving circuit for a light emitting element, wherein the third field effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal.

A two-terminal light-emitting element that emits light in accordance with a supplied direct current, and an n-type first field-effect transistor in which a source electrode and a drain electrode are connected between one terminal of the light-emitting element and a power supply When,
In the drive circuit of the light-emitting element, having a second field-effect transistor, the source electrode and the drain electrode are connected between the gate electrode and the data electrode of the first field-effect transistor,
A capacitor connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element;
The driving circuit for a light-emitting element, further comprising a third field-effect transistor connected between the one terminal of the light-emitting element and a common electrode.

A two-terminal light-emitting element that emits light in accordance with a supplied direct current, and an n-type first field-effect transistor in which a source electrode and a drain electrode are connected between one terminal of the light-emitting element and a power supply When,
In the drive circuit of the light-emitting element, having a second field-effect transistor, the source electrode and the drain electrode are connected between the gate electrode and the data electrode of the first field-effect transistor,
A capacitor connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element;
A third field-effect transistor that is connected between the one terminal of the light-emitting element and a common electrode and that is turned on / off;
A driving circuit for a light emitting element, wherein the third field effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal.

A two-terminal light-emitting element that emits light in accordance with a supplied direct current, and an n-type first field-effect transistor in which a source electrode and a drain electrode are connected between one terminal of the light-emitting element and a power supply When,
In the drive circuit of the light-emitting element, having a second field-effect transistor, the source electrode and the drain electrode are connected between the gate electrode and the data electrode of the first field-effect transistor,
A capacitor connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element;
A third field-effect transistor connected between the one terminal of the light-emitting element and a common electrode and turned on / off;
A fourth field-effect transistor that is connected in parallel to both ends of the capacitor and that is turned on / off;
A drive circuit for a light emitting element, wherein the fourth field effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal.

A two-terminal light-emitting element that emits light in accordance with a supplied direct current, and an n-type first field-effect transistor in which a source electrode and a drain electrode are connected between one terminal of the light-emitting element and a power supply When,
In the drive circuit of the light-emitting element, having a second field-effect transistor, the source electrode and the drain electrode are connected between the gate electrode and the data electrode of the first field-effect transistor,
A capacitor connected between the gate electrode of the first field effect transistor and the one terminal of the light emitting element;
A third field-effect transistor connected between the one terminal of the light-emitting element and a common electrode and turned on / off;
A fourth field-effect transistor that is connected between the power supply and the first field-effect transistor in series with the first field-effect transistor and that is turned on / off;
A drive circuit for a light emitting element, wherein the fourth field effect transistor is turned on / off for a predetermined period within one field period of the image signal in synchronization with vertical synchronization of the image signal.

An image display device comprising the light-emitting element driving circuit according to claim 1.