JP2004093888A - Method for driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prolong the lifetime of a display surface and to reduce electric power consumption by reducing the discharge impact deteriorating cells. <P>SOLUTION: A lighting rate which is the ratio of the number of the cells to be lighted to the total number of the cells is detected in accordance with the display data to determine the contents of addressing. The setting of the sustaining voltage to be impressed during sustaining to display the corresponding display data is changed according to the detected lighting rate in such a manner that the voltage at the low lighting rate is made lower than the voltage at the greater lighting rate. When the cells to be lighted are a few, the amount of the voltage drop of a power source is relatively small and therefore even if the set value of the sustaining voltage is low, the sustaining voltage is prevented from dropping down to the permissible lower limit or below due to the voltage drop. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for driving a plasma display panel (PDP).
[0002]
Large-screen television receivers equipped with a PDP are becoming widespread. The demands for PDPs include longer life and lower power consumption.
[0003]
[Prior art]
An AC PDP having a surface discharge structure for color display is used. The surface discharge structure referred to here is a structure in which display electrodes for generating a display discharge that determines the amount of light emitted from a cell are arranged in parallel on a front substrate or a rear substrate, and are formed by discharge to a phosphor for color display. Suitable for reducing impact.
[0004]
In an AC type PDP, a display electrode is covered with a dielectric, and a driving method of generating a display discharge using a wall voltage generated by charging of the dielectric is applied. At the time of display, addressing for generating an appropriate wall voltage is performed on the cells to be lit indicated by the display data among the cells constituting the display surface, and then the alternating voltage sustain voltage Vs is applied to all the cells simultaneously. To perform display discharge of the number of times corresponding to the brightness to be displayed in the cell to be lit. The sustain voltage Vs satisfies the following equation.
[0005]
Vf−Vw <Vs <Vf
Vf: Discharge starting voltage Vw: Cell voltage (sum of voltage applied to electrode and wall voltage) is changed to discharge starting voltage only in cells where a wall voltage of a predetermined value or more is generated by application of wall voltage maintaining voltage Vs between electrodes. A display discharge occurs beyond Vf. The light emission of the cell due to the display discharge is called “lighting”. Since the application cycle of the sustain voltage Vs is as short as about several microseconds, light emission visually continues.
[0006]
The sustain voltage Vs is naturally set to a value within the drive margin (permissible range). The drive margin is defined by the difference between the discharge start voltage Vf and the minimum drive voltage Vs _min required to maintain lighting. When the sustain voltage Vs is set to Vf or more, discharge occurs even in a cell which is turned off by addressing. If the sustain voltage Vs is less than Vs _min , the cell in the lighting state is turned off.
[0007]
[Problems to be solved by the invention]
One pixel on the display surface is composed of at least three cells having emission colors of R, G, and B, and the total number of cells is three times the resolution. For example, even in the case of the VGA specification having a relatively low resolution, the display surface includes 640 × 480 × 3 cells. Therefore, a situation that frequently exceeds tens of thousands of cells to be set by one addressing frequently occurs. In sustain, display discharge occurs almost simultaneously in a large number of cells, and a discharge current intensively flows from the power supply to the PDP at one time. This causes a so-called voltage drop in which the sustain voltage Vs applied to the cell temporarily drops. The drop amount increases as the number of cells to be lit increases. It is not practical to solve the voltage drop by increasing the size of the power supply, because it significantly increases the price of the display device.
[0008]
There are slight variations in discharge characteristics between cells of the PDP, and there are cells having relatively short discharge delay times and cells having long discharge delay times. In response to the application of the sustain voltage, display discharge occurs first in a cell having a short discharge delay time, and thereafter occurs in a cell having a long discharge delay time. At this time, there is a possibility that a display discharge at a later time does not occur due to a voltage drop accompanying an earlier display discharge.
[0009]
Conventionally, when setting the drive voltage in the design of the drive circuit operation, a sufficiently high voltage within the drive margin is set in consideration of the voltage drop so that display discharge occurs in all cells when all the cells are turned on. It was set as a maintenance voltage and the setting was fixed. When the number of cells to be lit is small, a high sustaining voltage is applied in the same manner as when the number of cells to be lit is large, so that the excessively high voltage causes the phosphor and the dielectric to be subjected to an extra discharge shock and wasteful power consumption. There is a problem that the luminous efficiency decreases due to consumption. It is also desirable to reduce discharge shock in order to suppress image sticking on the display surface.
[0010]
It is an object of the present invention to reduce the discharge impact that deteriorates the cell, extend the life of the display surface, and reduce power consumption.
[0011]
[Means for Solving the Problems]
In the present invention, based on display data that determines the content of addressing, a lighting rate that is a ratio of the number of cells to be lit to the total number of cells is detected, and the corresponding display data is displayed according to the detected lighting rate. The setting of the sustaining voltage applied in the sustaining is changed so that the voltage is lower when the lighting rate is low than when the lighting rate is high.
[0012]
When the number of cells to be lit is small, the voltage drop amount of the power supply is relatively small. Therefore, even if the set value of the sustain voltage is low, the sustain voltage does not fall below the allowable lower limit due to the voltage drop. By setting the sustain voltage low, the discharge impact caused by the display discharge is reduced and the power consumption is reduced.
[0013]
The setting change of the maintenance voltage may be a stepwise change in which the lighting rate is divided into a plurality of ranges and different settings are made for each section, or a continuous change in which different settings are made for each value of the lighting rate.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a configuration diagram of a display device according to the present invention, and FIG. 2 is a schematic configuration diagram of an X driver and a Y driver for driving display electrodes. The display device 100 includes a surface-discharge AC type PDP 1 having a color display surface and a drive unit 70 for controlling light emission of cells, and is used as a wall-mounted television receiver, a monitor of a computer system, or the like. .
[0015]
In the PDP 1, a display electrode X and a display electrode Y forming an electrode pair for generating a display discharge are arranged in parallel with each other, and address electrodes A are arranged so as to intersect the display electrodes X and Y. The display electrodes X and Y extend in the row direction (horizontal direction) of the screen, and the address electrodes extend in the column direction (vertical direction).
[0016]
The drive unit 70 has a controller 71, a data conversion circuit 72, a power supply circuit 73, a state detection circuit 74, an X driver 75, a Y driver 76, and an A driver 77. Frame data Df indicating the luminance levels of the three colors R, G, and B are input to the drive unit 70 from external devices such as a TV tuner and a computer together with various synchronization signals. The frame data Df is temporarily stored in a frame memory in the data conversion circuit 72. The data conversion circuit 72 converts the frame data Df into sub-frame data Dsf for gradation display and sends the sub-frame data Dsf to the A driver 77. The sub-frame data Dsf is a set of 1-bit display data per cell, and the value of each bit indicates whether or not light emission of the cell in the corresponding one sub-frame is necessary, or strictly, whether or not address discharge is required. The A driver 77 applies an address pulse to an address electrode A passing through a cell where an address discharge is to be caused according to the subframe data Dsf. Note that applying a pulse to an electrode means temporarily biasing the electrode to a predetermined potential. The controller 71 controls the application of the pulse and the transfer of the subframe data Dsf. The power supply circuit 73 supplies power required for driving the PDP 1 to each driver.
[0017]
The state detection circuit 74 detects the “display load ratio” for each frame and the “lighting ratio” specific to the present invention for each subframe. The display load factor is an index of power consumption, and is defined as an average value over the entire discharge cells of the ratio Gi / Gmax when the gradation value of a cell in one frame is Gi (0 ≦ Gi ≦ Gmax). This display load factor is used for automatic power control (Auto Power Control: APC) that suppresses power consumption and heat generation by reducing the application of a sustain pulse when displaying a bright image. On the other hand, the lighting rate is a ratio of the number k of cells to be lit in the subframe to the total number of cells K (for example, lighting rate = k / K × 100 in percentage), and is an index of voltage drop in sustain. The state detection circuit 74 detects a lighting rate by counting bits indicating cells to be turned on based on the subframe data Dsf, and notifies the controller 71 of the detected lighting rate. The lighting rate is used for changing the setting of the amplitude of the sustain pulse (that is, the sustain voltage).
[0018]
As shown in FIG. 2, the X driver 75 includes a reset circuit 81 for applying a pulse for initializing wall charges to the display electrode X, a bias circuit 82 for controlling the potential of the display electrode X in addressing, and a display electrode X. The sustain circuit 83 applies a sustain pulse to X. The Y driver 76 applies a reset circuit 85 for applying a pulse for initializing wall charges to the display electrode Y, a scan circuit 86 for applying a scan pulse to the display electrode Y in addressing, and applies a sustain pulse to the display electrode Y. It comprises a sustain circuit 87.
[0019]
FIG. 3 is a diagram showing an example of the cell structure of the PDP. In FIG. 3, a portion corresponding to three cells related to the display of one pixel in the PDP 1 is illustrated by separating the pair of substrate structures 10 and 20 so that the internal structure can be clearly understood. The PDP 1 includes a pair of substrate structures 10 and 20. The substrate structure means a structure in which electrodes and other components are provided on a glass substrate. In the PDP 1, display electrodes X and Y, a dielectric layer 17 and a protective film 18 are provided on the inner surface of a glass substrate 11 on the front side, and address electrodes A, an insulating layer 24, partition walls 29, And phosphor layers 28R, 28G, 28B. Each of the display electrodes X and Y is composed of a transparent conductive film 41 forming a surface discharge gap and a metal film 42 as a bus conductor. The partition walls 29 are provided one for each electrode gap of the address electrode array, and the discharge spaces are partitioned by the partition walls 29 in the row direction for each column. The column space 31 corresponding to each column in the discharge space is continuous over all the rows. The phosphor layers 28R, 28G and 28B are locally excited by ultraviolet rays emitted by the discharge gas to emit light. Italic alphabets R, G, and B in the figure indicate the emission colors of the phosphor.
[0020]
Hereinafter, a method of driving the PDP 1 in the display device 100 will be described.
[0021]
FIG. 4 is a conceptual diagram of frame division. In the display by the PDP 1, a time-series frame F which is an input image is divided into a predetermined number q of sub-frames SF in order to perform color reproduction by binary lighting control. That is, each frame F is replaced with a set of q subframes SF. A weight of, for example, 2 ⁰ , 2 ¹ , 2 ² ,... 2 ^q−1 is assigned to these sub-frames SF in order to set the number of display discharges of each sub-frame SF. In the figure, the subframe arrangement is in the order of the weight, but may be in another order. Redundant weighting may be employed to reduce false contours. In accordance with such a frame configuration, the frame period Tf, which is a frame transfer cycle, is divided into q subframe periods Tsf, and one subframe period Tsf is assigned to each subframe SF. Further, the subframe period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for sustain. While the lengths of the reset period TR and the address period TA are constant regardless of the weight, the length of the display period TS increases as the weight increases. Therefore, the length of the subframe period Tsf is also longer as the weight of the corresponding subframe SF is larger. The driving sequence is repeated for each subframe, and the order of the reset period TR, the address period TA, and the display period TS is common in the q subframes SF.
[0022]
FIG. 5 is a voltage waveform diagram showing an outline of the driving sequence. In the figure, the suffixes (1, n) of the reference signs of the display electrodes X and Y indicate the arrangement order of the corresponding rows, and the suffixes (1, m) of the reference signs of the address electrodes A indicate the arrangement order of the corresponding columns. The illustrated waveform is an example, and the amplitude, polarity, and timing can be variously changed.
[0023]
In the reset period TR of each sub-frame SF, a negative pulse Prx1 and a positive pulse Prx2 are sequentially applied to all display electrodes X, and a positive pulse Pry1 is applied to all display electrodes Y. A negative pulse Pry2 is applied in order. The pulses Prx1, Prx2, Pry1, and Pry2 are ramp waveform pulses whose amplitude gradually increases at a change rate at which a minute discharge occurs. The first applied pulses Prx1 and Pry1 are applied to generate appropriate wall voltages of the same polarity in all cells regardless of lighting / non-lighting in the previous subframe. By applying the pulses Prx2 and Pry2 to the cell having an appropriate wall charge, the wall voltage can be adjusted to a value corresponding to the difference between the discharge start voltage and the pulse amplitude according to the values of the pulses Prx2 and Pry2. . The initialization in this example is to set the wall charges (that is, wall voltages) of all cells to set values. The initialization can be performed by applying a pulse to only one of the display electrodes X and Y, but by applying pulses of opposite polarities to both the display electrodes X and Y as shown in the figure, the driver circuit element can be initialized. Low withstand voltage can be achieved. The drive voltage applied to the cell is a combined voltage obtained by adding the amplitudes of the pulses applied to the display electrodes X and Y.
[0024]
In the address period TA, wall charges necessary for maintaining lighting are formed only in cells to be turned on. In a state where all display electrodes X and all display electrodes Y are biased to a predetermined potential, a scan pulse Py of a negative polarity is applied to one display electrode Y corresponding to the selected row in each row selection period (scan time for one row). Is applied. At the same time as this row selection, an address pulse Pa is applied only to an address electrode A corresponding to a selected cell in which an address discharge is to be generated. That is, the potential of the address electrode A is binary-controlled based on the subframe data Dsf for m columns of the selected row. In the selected cell, a discharge occurs between the display electrode Y and the address electrode A, which triggers a surface discharge between the display electrodes. These series of discharges are address discharges.
[0025]
In the display period TS, first, a positive sustain pulse Ps having an amplitude Vs is applied to all the display electrodes Y. Thereafter, the display electrode X and the display electrode Y are alternately switched as application targets, and the sustain pulse Ps is applied. Thus, a sustain pulse train whose polarity is alternately applied is applied between the XY electrodes. By the application of the sustain pulse, surface discharge occurs in a cell in which a predetermined wall charge remains. The number of times the sustain pulse is applied corresponds to the weight of the subframe as described above.
[0026]
Among the above driving sequences, the application of the sustain pulse Ps in the display period TS is deeply related to the present invention. What is important is that the amplitude (sustain voltage) Vs of the sustain pulse Ps is not fixed, but is changed according to the above-mentioned lighting rate. Hereinafter, the configuration and operation of a sustain circuit 83 (see FIG. 3), which is a means for applying a sustain pulse to the display electrode X, will be described. The configuration and operation of the sustain circuit 87, which is a means for applying a sustain pulse to the display electrode Y, are the same as those of the sustain circuit 83, and a description thereof will be omitted.
[0027]
FIG. 6 is a configuration diagram of a sustain circuit according to the present invention. The sustain circuit 83 includes a pulse generation circuit 831 having a function of outputting a rectangular wave pulse having an amplitude Vs, a power recovery circuit 832 for performing high-speed charging and discharging of electrostatic capacity between electrodes by LC resonance, and an amplitude of the sustain pulse Ps. It comprises a voltage change circuit 833 for changing. The pulse generation circuit 831 is a switching circuit having a push-pull configuration having a pair of switching elements, and connects the display electrode X to an output terminal of the voltage changing circuit 833 or GND. The potential difference between the output terminal of the voltage change circuit 833 and GND is the sustain voltage Vs. The controller 71 instructs the voltage changing circuit 833 to output a voltage corresponding to the lighting rate.
[0028]
FIG. 7 is a conceptual diagram of switching of the driving voltage during the display period. Lighting rate is exemplified, 1% to 30%, is divided into three ranges of 31-70%, and 71-100%, the sustain voltage _Vs L different for each category, _Vs M, Vs _H are determined. Relationship of the sustain voltage _Vs L, _Vs M, the _{Vs H Vs L <Vs M <} Vs H. These sustain voltage _Vs L, _Vs M, _{Vs H} Is the above-mentioned sustain voltage Vs. The maintenance voltages Vs _L , Vs _M , and Vs _H are determined so that the drive voltage at the time of the drop does not become lower than the minimum voltage Vs _min required to maintain the lighting in consideration of the voltage drop. If the driving voltage is higher than the voltage Vs _min , there is no problem in displaying.
[0029]
In the sustain in the sub-frame in which the lighting rate is 71 to 100%, the sustain voltage Vs _H There is set, the sustain in the lighting rate is 31 to 70% of the sub-frame is set sustain voltage Vs _M is maintained lighting rate is the sustain in 1% to 30% of the sub-frame voltage Vs _L Is set. When the lighting rate is 0%, the maintenance voltage Vs is set to zero. The lower the sustaining voltage Vs, the smaller the discharge shock and the smaller the discharge current that the phosphor and the dielectric receive. This is advantageous for preventing cell deterioration and improving the activation efficiency. Further, by substantially stopping the voltage application by setting the sustain voltage Vs to zero, it is possible to eliminate unnecessary power consumption due to charging and discharging of the capacitance between the electrodes.
[0030]
In the above embodiment, a function of detecting a drop of the sustain voltage due to the display discharge and adjusting the sustain voltage so as not to fall below the allowable lower limit can be incorporated.
[0031]
In the above-described embodiment, an example has been described in which sustain pulses Ps having a single polarity are alternately applied to the display electrodes X and Y. However, positive and negative pulses having an amplitude of Vs / 2 are simultaneously applied to the display electrodes X and Y. Drive voltage may be applied between the display electrodes. The arrangement of the display electrodes X and Y is not limited to the arrangement in which one pair is arranged for each row of the matrix display, and the number of display electrodes obtained by adding 1 to the number n of rows is arranged at equal intervals at a ratio of 3 in 2 rows. It may be in a form to perform. The present invention can be applied regardless of the arrangement form.
[0032]
【The invention's effect】
According to the first to fourth aspects of the present invention, it is possible to reduce the discharge impact that deteriorates the cell, extend the life of the display surface, and reduce the power consumption.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a display device according to the present invention.
FIG. 2 is a schematic configuration diagram of an X driver and a Y driver for driving display electrodes.
FIG. 3 is a diagram illustrating an example of a cell structure of a PDP.
FIG. 4 is a conceptual diagram of frame division.
FIG. 5 is a voltage waveform diagram showing an outline of a driving sequence.
FIG. 6 is a configuration diagram of a sustain circuit according to the present invention.
FIG. 7 is a conceptual diagram illustrating switching of a driving voltage during a display period.
[Explanation of symbols]
Dsf subframe data (display data)
_{Vs, Vs L, Vs M,} Vs H sustain voltage 1 PDP (plasma display panel)
70 Drive unit (drive device)
74 State detection circuit (lighting rate detection circuit)
71 Controller

Claims (4)

Addressing is performed to generate a wall voltage in the cells to be lit indicated by the display data among the cells constituting the display surface, and thereafter, a sustain voltage is applied to all the cells at once to perform display in the cells to be lit. A driving method of a plasma display panel for performing a sustain that causes a display discharge a number of times according to the brightness,
Based on the display data that determines the content of the addressing, a lighting rate that is a ratio of the number of cells to be lit to the total number of cells is detected,
According to the detected lighting rate, the setting of the sustain voltage applied in the sustain for displaying the corresponding display data is changed so that the voltage is lower when the lighting rate is low than when the lighting rate is high. Panel driving method. 2. The method of driving a plasma display panel according to claim 1, wherein the sustain voltage is set to a voltage within an allowable range in consideration of a decrease in power supply output due to display discharge. 2. The driving method of a plasma display panel according to claim 1, wherein when the detected lighting rate is zero, the value of the sustain voltage is set to zero. Addressing is performed to generate a wall voltage in the cells to be lit indicated by the display data among the cells constituting the display surface, and thereafter, a sustain voltage is applied to all the cells at once to perform display in the cells to be lit. A driving device for a plasma display panel that performs sustaining to cause display discharge of a number of times according to brightness,
A lighting rate detection circuit that detects a lighting rate, which is a ratio of the number of cells to be lit to the total number of cells, based on display data that determines the content of addressing;
A controller that changes the setting of the sustain voltage applied in the sustain for displaying the corresponding display data according to the detected lighting rate so that the voltage is lower when the lighting rate is low than when the lighting rate is high. Characteristic plasma display panel driving device.

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