JP2004088527A - Audio interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce circuit scale, to reduce costs and to make fully duplex operations possible even in input audio data and output audio data of different sampling frequencies in an audio interface circuit for inputting/outputting audio data. <P>SOLUTION: The audio interface circuit is composed of an interface circuit for inputting/outputting audio data, a buffer memory, a filter circuit and a filter operation control circuit. The buffer memory shares a buffer memory for output audio data, a buffer memory for input audio data and a filter delay memory that the filter circuit has. Besides, the filter circuit shares a filter circuit for the input audio data and a filter circuit for the output audio data. Further, the fully duplex operations of the input audio data and the output audio data are realized by the filter operation control circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an interface circuit required for transmitting / receiving an audio signal or the like between various devices such as a portable terminal and an audio device.
[0002]
[Prior art]
In recent years, there are digital audio signals having various types of attributes. Considering the sampling frequency of a signal, 44.1 kHz, 22.05 kHz, and 11.25 kHz are used in a general audio signal interface section of a personal computer or the like. Also, 48 kHz is adopted for a digital audio tape recorder (DAT) and the like, and 32 kHz is adopted for a satellite broadcast.
Further, there is known an editing apparatus which converts an audio signal into digital data through an audio interface and records or reproduces the data on a recording medium such as a hard disk. In recent years, some portable terminals have an audio signal input / output and a recording / reproducing function.
For this reason, when recording a sound source having a different sampling frequency such as 48 kHz such as DAT from a personal computer or the like on a CD-R or the like, the audio interface needs to convert the sampling frequency.
Many of the signals existing in the world are still analog signals. Therefore, the signal contains more or less noise components, and a filter circuit is required as an audio interface to remove only noise components that are well mixed in the signal without affecting the signal components. ing.
A device equipped with a general audio function includes a CPU for controlling an audio interface and an audio interface circuit for receiving a control signal of the CPU and performing an input / output operation of audio data.
For example, FIG. 5 shows a conventional technique disclosed in Japanese Patent Application Laid-Open No. H9-139671. This shows that the input / output filter circuit and the input / output buffer for audio data exist independently of each other.
In FIG. 5, the input audio data is input from the interface circuit 506 as the sampling frequency Nfs. Audio data of the sampling frequency Nfs is subjected to a predetermined band limitation by a filter circuit 505 (oversampling filter), and is supplied to a decimator 504. The decimator 504 outputs audio data having a sampling frequency fs by performing a 1 / N thinning process on the supplied audio data. The audio data of the sampling frequency fs output from the decimator 504 is written to the input buffer 503 and output to the CPU bus 511 at a predetermined timing.
The operation of each unit described above is controlled by the timing generation unit 502. The CPU 501 specifies the sampling frequency fs of the audio data to be captured, and notifies the timing generation unit 502 of the frequency. The timing generator 502 inputs audio data to the interface circuit 506 at N times the sampling frequency Nfs according to the designated sampling frequency fs. At this time, “N” is a fixed value. The timing generator 502 further controls writing / reading of the audio data processed by the filter circuit 505 and the decimator 504 to / from the input buffer 503. Audio data output from the input buffer 503 to the CPU bus 511 is recorded on a hard disk or the like.
Next, a case where audio data is output will be described. First, based on a command from the CPU 501, the timing generator fetches audio data supplied from the CPU bus 511 into the output buffer 507. Then, the audio data read from the output buffer 507 is supplied to the imperator 508 in synchronization with the transmission timing. When the timing generator 502 captures the sampling frequency fs of audio data transmitted and output from the CPU 501, the timing generator 502 causes the interpolator 508 to execute N-times data interpolation processing. That is, audio data of the sampling frequency Nfs is output. The audio data of the sampling frequency Nfs is band-limited by the filter circuit 509 (oversampling filter). The output of the digital filter 509 is passed to the interface circuit 510, and the timing generator 502 outputs audio data at a timing of N times the frequency Nfs according to the designated frequency fs. These frequency conversion processes and the like are based on FIR filter operation.
Next, an FIR filter performed by the filter circuit will be described with reference to FIG.
In FIG. 2, the latest data to be input is input from the memory 1, and the data is moved to the right one position each time it is processed once. Then, the latest data is input to the position of the memory 1 again. When the output audio data of FIG. 5 is considered, the input data is the data stored in the output audio buffer memory 507. At this time, the data stored in the memories 1 to n is the FIR filter delay memory. Each data stored in the memory is multiplied by the filter coefficients h1 to hn prepared respectively, and the results are accumulated to obtain a filter output (output data).
[0003]
[Problems to be solved by the invention]
As seen in the above-mentioned prior art, the audio interface circuit uses input audio data and output audio data, each using a filter circuit, a buffer memory for transmission and reception with the CPU, a filter delay memory of the filter circuit, and a filter operation. The use of such a circuit configuration increases the circuit scale as hardware and leads to an increase in cost.
Further, in the above-described prior art, full-duplex operation can be performed, but the sampling frequency specified by the timing generator can only operate at the same rate for input audio data and output audio data. There are many standards for the sampling frequency of a device, and the frequency ratio is not simple. In order to realize a more versatile audio interface, it is important that input and output audio data operate at different sampling frequencies.
In view of the above problems, the present invention reduces the circuit scale of an audio interface, reduces costs, and enables full-duplex operation at different sampling frequencies for input and output.
[0004]
[Means for Solving the Problems]
In order to solve the above-described problem, one of the representative embodiments of the present invention is an audio interface circuit for inputting and outputting audio data, wherein the audio interface circuit performs a filter operation on the audio data. A filter circuit is provided, wherein the filter circuit is configured to be shared by input audio data and output audio data.
Another typical example of the present invention is an audio interface circuit that transmits first audio data and receives second audio data, wherein the audio interface circuit includes a filter circuit, a filter operation circuit, A buffer memory, an interface circuit for the first audio data, and an interface circuit for the second audio data, wherein the filter circuit performs a filter operation on both the first audio data and the second audio data; Further, a double operation of a filter operation of the first audio data and the second audio data is enabled by time division.
[0005]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
First, the operation of the buffer memory 103 in FIG. 1 will be described with reference to FIG. As described in the description of the operation of the conventional FIR filter, the latest data input in FIG. 2 is input from the memory 1, and the data is moved to the right one position each time it is processed once. Here, as the input data in FIG. 2, the latest data stored in the output audio data buffer memory is read. Accordingly, the data stored in the output audio data buffer memory is the same as the FIR filter delay memories 1 to N of the FIR filter memories in FIG. Therefore, it is possible to operate by sharing the buffer memory for output audio data and the FIR filter delay memory as one buffer memory.
Further, in this embodiment, the operation is performed by sharing the buffer memory for input audio data and the buffer memory for output audio data necessary for reading and writing audio data with the CPU 101 as one buffer memory. Similarly, this buffer memory can be shared as a filter coefficient memory necessary for reading out a filter coefficient used for a filter operation.
Next, the operation of the filter circuit 102 will be described with reference to FIG.
The horizontal axis in FIG. 3 represents time, and shows the execution period of the arithmetic processing of the input audio data and output audio data of 48 kHz, and the input audio data and output audio data in the present embodiment. One sample period of each of the input data 1 to 4 and the output data 1 to 4 input to the filter circuit has a cycle of 48 kHz.
If input audio data and output audio data are shared by a combination of filter circuits using the conventional concept, the arithmetic unit processing of the filter operation performs one data processing in one sample period. The arithmetic processing cannot be performed simultaneously on the audio data and the output audio data.
Therefore, in the present embodiment, as shown in FIG. 3, the processing operation is performed by dividing the calculation processing time of one sample period into the input processing and the output processing, respectively. By setting the operation scale of the filter operation unit to be within the processing period, an operation in which the filter circuits for the input audio data and the output audio data are shared can be performed.
Next, an operation method will be described using the block configuration of the audio interface shown in FIG.
Input audio data is externally input to the interface circuit 104. The input audio data is passed to the filter circuit 102, where a filter operation process is performed. This audio data is written and stored in the buffer memory 103. The data is output from the buffer memory 103 to the CPU bus 107 at a predetermined timing. The audio data output to the CPU bus 107 is supplied to another CPU peripheral circuit 106 under the control of the CPU 101, and a recording operation on a hard disk or the like is performed.
When the audio data is output to the outside as output audio data, the audio data is transferred to the buffer memory 103 via the CPU bus 107 at a predetermined timing according to a command from the CPU 101. Then, the output audio data is passed to the filter circuit 102, where a filter operation process and a sampling frequency conversion process are performed. The output of the filter circuit 102 is passed to the interface circuit 105 and outputs audio data in accordance with the transmission timing.
The CPU 101 designates a sampling frequency of the input audio data and the output audio data, and transmits them to the filter operation control circuit 108. The filter calculation control circuit 108 performs control according to the designated input audio data and output audio data, and the sampling frequency of each of them, on the calculation processing of the filter circuit 102.
Finally, a method of the arithmetic processing of the filter circuit 102 having different sampling frequencies of the input audio data and the output audio data will be described with reference to the example of FIG.
The horizontal axis in FIG. 4 represents time, and indicates the execution period of the arithmetic processing of the input audio data of 44.1 kHz and the output audio data of 48 kHz, the input audio data and the output audio data. One sample period of each of the input data 1 to 4 input to the filter circuit has a period of 44.1 kHz, and one sample period of each of the output data 1 to 4 has a period of 48 kHz. A, B, C, D, E, and F each represent one sample period of 48 kHz. In this case, since the period of the output audio data is shorter in the arithmetic processing, the input and output arithmetic processing is performed at a cycle of 48 kHz. Basically, the filter operation process performs an input process and an output process.
In the filter calculation process in the period B in FIG. 4, the output process of the output data 1 determined in the period A is performed. This is because the sampling frequency of the input audio data is as slow as 44.1 kHz, so that the data is not determined within the period A, and it is not possible to meet the timing of the arithmetic processing at the start of the period B. Therefore, the input data 1 and the output data 2 determined in the period B are processed in the period C. In period D, the arithmetic processing of input data 2 and output data 3 is performed, and in period E, the arithmetic processing of input data 3 and output data 4 is performed. In the last F period, the arithmetic processing of the input data 4 is performed.
In the case of performing a filter operation of a different sampling frequency between the input audio data and the output audio data, the above-described operation is controlled by the filter operation control circuit 108 to execute and stop the input operation and the output operation.
In the control procedure as shown in FIG. 4, the sampling frequency of 48 kHz of the output audio data having a short period of one sample is set as one sample period for performing the data arithmetic processing. Next, the input operation processing and the output operation processing are controlled to be within one sample period. In the data processing, since there is no input data and only output data 1 is determined in the period A, the output process is performed in the period B and the input process is controlled not to be performed. In the period B, the input data 1 and the output data 2 are determined, so that the input process and the output process are controlled to be performed in the period C. Further, the input data 2 and the output data 3 are determined in the C period, the input data 3 and the output data 4 are determined in the D period, and the input data 4 and the output data 5 are determined in the E period. Is controlled to perform input processing and output processing.
As described above, the audio interface circuit according to the present embodiment controls the arithmetic processing, thereby enabling full-duplex operation with different sampling frequencies.
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and can be variously modified without departing from the gist of the invention.
For example, in the above embodiment, both the filter circuit and the buffer memory are shared. However, the present invention is not limited to this, and only one of the sharing targets may be used.
The buffer memory has been described as sharing the buffer memory for the output audio data, the buffer memory for the input audio data, and the filter delay memory included in the filter circuit. However, the present invention is not limited to this, and two of these three memories are used. One may share one. Further, another memory may be shared.
[0006]
【The invention's effect】
As described above, by using the audio interface circuit of the present invention, it is possible to reduce the circuit scale and cost by sharing the filter operation circuit for input audio data and output audio data.
Further, sharing the transmission / reception buffer memory with the CPU as hardware can further contribute to reduction in circuit size and cost.
Even when input audio data and output audio data having different sampling frequencies are handled, full-duplex operation is possible.
[Brief description of the drawings]
FIG. 1 is a block diagram of an audio interface.
FIG. 2 is a signal processing diagram of an FIR filter.
FIG. 3 is a processing method 1 of a filter operation.
FIG. 4 is a processing method 2 of a filter operation.
FIG. 5 is a block diagram of a conventional audio interface.
[Explanation of symbols]
101: CPU, 102: Filter circuit, 103: Buffer, 104, 105: Interface circuit, 106: Other CPU peripheral circuits, 107: CPU bus, 108: Filter operation control circuit

Claims (13)

An audio interface circuit for inputting and outputting audio data,
The audio interface circuit has a filter circuit that performs a filter operation on the audio data,
An audio interface circuit, wherein the filter circuit is configured to be shared by input audio data and output audio data. The audio interface circuit according to claim 1,
The audio interface circuit further has a buffer memory,
The audio interface circuit, wherein the buffer memory is configured to be shared by the input audio data and the output audio data. The audio interface circuit according to claim 2,
The audio interface circuit, wherein the buffer memory is configured to function as a filter delay memory of the filter circuit. The audio interface circuit according to claim 2 or 3,
The audio interface circuit, wherein the buffer memory is configured to function as a filter coefficient memory of the filter circuit. The audio interface circuit according to any one of claims 1 to 4,
The audio interface circuit has a filter operation control circuit,
The audio interface circuit, wherein the filter operation control circuit controls the filter circuit so as to perform a filter operation process by a double operation of the input audio data and the output audio data. The audio interface circuit according to claim 5,
The audio interface circuit, wherein the filter circuit is configured to perform the filter operation processing by time division. The audio interface circuit according to claim 5,
The audio circuit, wherein the filter circuit is configured to perform the filter operation processing by the double operation even when the sampling frequency of the input audio data is different from the sampling frequency of the output audio data. Interface circuit. The audio interface circuit according to claim 7,
One sample period in the double operation is configured to compare the input audio data with the output audio data and set a cycle of the filter operation processing in accordance with a shorter cycle. Audio interface circuit. The audio interface circuit according to any one of claims 1 to 8,
The audio interface circuit, wherein the audio data is digital data. The audio interface circuit according to any one of claims 1 to 9,
The audio interface circuit, wherein the audio interface circuit is configured to correspond to a portable terminal. An audio interface circuit for transmitting first audio data and receiving second audio data, comprising:
The audio interface circuit includes a filter circuit, a filter operation circuit, a buffer memory, an interface circuit for the first audio data, and an interface circuit for the second audio data,
The filter circuit performs a filter operation on both the first audio data and the second audio data, and a double operation of the filter operation on the first audio data and the second audio data can be performed by time division. An audio interface circuit characterized by being performed. The audio interface circuit according to claim 11,
The buffer memory shares a buffer memory for transmitting the first audio data, a buffer memory for receiving the second audio data, a filter delay memory, and a filter coefficient memory used in a filter operation. Characteristic audio interface circuit. The audio interface circuit according to claim 11 or 12,
An audio interface circuit characterized in that the double operation can be performed in a time-division manner even when the frequency of the first audio data is different from the frequency of the second audio data.

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