JP2004080227A - Solid state imaging apparatus and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of controlling a solid state imaging apparatus to satisfactorily perform a parallel signal processing. <P>SOLUTION: The control method for a solid state imaging apparatus comprises a step (a) of feeding a plurality of signal processors in parallel with a series of image signals corresponding to one row or column of pixels in a solid stage imaging device, a step (b) of selecting and processing a part of the image signals as those to be processed by the individual signal processors wherein there are common image signals between the image signals to be processed by one of the signal processors and those to be processed by another of the signal processors, and a step (c) of collecting output signals from the plurality of signal processors into one block to generate a series of image signals corresponding to one row or column of pixels in the solid stage imaging device. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a control method thereof, and more particularly to a solid-state imaging device having a signal processing unit that performs color interpolation processing and the like and a control method thereof.
[0002]
[Prior art]
In a solid-state imaging device, a color image is obtained by forming red, green, and blue color filters on a pixel of a solid-state imaging device. However, since only one color filter is formed on one pixel of the solid-state image sensor, only one color signal determined by the color filter is output from each pixel at the output stage of the solid-state image sensor. In order to actually obtain a color image, color interpolation processing for generating at least two colors other than one color determined by the color filter for each pixel is performed.
[0003]
In the configuration of the conventional solid-state imaging device, for example, one signal processing IC is used for this color interpolation processing. This signal processing IC is manufactured so as to have a processing capability corresponding to the number of pixels of the solid-state imaging device used in the solid-state imaging device.
[0004]
Therefore, even when a solid-state imaging device is manufactured using a solid-state imaging device with a large number of pixels that cannot be expected to be shipped in large quantities, it is necessary to manufacture a signal processing IC according to the solid-state imaging device. It has become.
[0005]
[Problems to be solved by the invention]
In a solid-state imaging device having a signal processing unit, processing such as color interpolation processing is performed.
[0006]
An object of the present invention is to provide a novel control method for a solid-state imaging device.
[0007]
Another object of the present invention is to provide a novel control method for favorably performing parallel signal processing in a solid-state imaging device.
[0008]
[Means for Solving the Problems]
The solid-state imaging device control method of the present invention includes: (a) supplying a series of image signals corresponding to one pixel row or one pixel column of a solid-state imaging device in parallel to a plurality of signal processing units;
(B) Each of the signal processing units is a step of selecting and processing a portion of the image signal as a processing target image signal, and the processing target image signal processed by a certain signal processing unit, and the other A common image signal exists between the other image signal to be processed and processed by the signal processing unit.
(C) combining the output signals from the plurality of signal processing units into one, and generating a series of image signals corresponding to one pixel row or one pixel column of the solid-state imaging device;
Have
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1A is a block diagram illustrating a configuration of a digital camera (solid-state imaging device) according to an embodiment of the present invention.
[0010]
The solid-state imaging device 1 converts the received light into an electrical signal and outputs it.
[0011]
FIG. 1B is a plan view schematically showing the configuration of the solid-state imaging device 1. In the light receiving surface of the solid-state imaging device 1, red pixels RA and RB, green pixels GA and GB, blue pixels BA and BB are arranged in a matrix. Note that the drawing is simplified, and an actual element has a pixel matrix of several hundred rows and hundreds to thousands of columns, for example.
[0012]
In this embodiment, the pixels RA, RB, GA, GB, BA, and BB are formed in a stripe shape in which three colors of red R columns, green G columns, and blue B columns are repeatedly arranged as shown in FIG. Is arranged.
[0013]
Here, the pixels arranged in a matrix are classified into odd-numbered rows of pixels RA, GA, BA and even-numbered rows of pixels RB, GB, BB counted from the lower side in the drawing. Odd-numbered pixels form an A field, and even-numbered pixels form a B field, and a screen of one frame is configured by these two fields.
[0014]
A photodiode (not shown) is formed in each pixel, and the photodiode accumulates electric charge according to the amount of received light.
[0015]
A plurality of vertical charge transfer paths VCCD composed of charge-coupled devices (CCDs) are arranged adjacent to the pixel columns and coupled to the pixels. In the VCCD, two electrodes are formed for one pixel. The image charge accumulated in the photodiode is read out to the VCCD.
[0016]
The VCCD is driven by four-phase drive signals V1, V2, V3, and V4, and transfers image charges downward in the figure. One horizontal charge transfer path HCCD composed of a CCD is coupled to one end of each VCCD.
[0017]
The HCCD is driven by the two-phase drive signals H1 and H2, and transfers image charges for each row of the pixel matrix in the left direction.
[0018]
The image charge transferred to the HCCD is converted into a voltage signal by the output amplifier AMP, amplified, and output from the chip output terminal Vout.
[0019]
Returning to FIG. 1A, the chip output Vout is supplied to the analog front end 2. The analog front end 2 includes an A / D converter and the like, and performs processing such as converting the chip output Vout, which is an analog signal, into a digital signal.
[0020]
The output of the analog front end 2 is supplied to the first stage signal processing unit 3. In the first stage signal processing unit 3, color interpolation processing and the like are performed.
[0021]
On one pixel of the solid-state imaging device 1, a color filter of only one color of red R, green G, and blue B is formed. From one pixel, only a signal related to any one color of R, G, or B is formed. Not output.
[0022]
Therefore, in order to obtain information on all the R, G, and B colors for a certain pixel position, a process for generating two colors other than the color of the pixel (color interpolation process) is required after the output of the solid-state imaging device. It becomes.
[0023]
As a method of generating a certain color other than the color of the pixel (hereinafter referred to as color C) for the position of a certain pixel, any number of colors C that are positioned so as to surround the pixel can be used. A method of performing weighted averaging of the signal of the pixel and adopting it as the color C signal for the pixel is widely used.
[0024]
At this time, in general, in order to prevent generation of false colors, it is preferable that the plurality of pixels having the color C used for the average operation be selected so as not to be biased to one region around one pixel to be subjected to color interpolation processing.
[0025]
In this embodiment, as a method of color interpolation processing, a method is adopted in which an average value of two pixels on both the left and right sides included in the same row as the pixel to be subjected to color interpolation processing is used.
[0026]
That is, for example, if a pixel to be subjected to color interpolation processing (hereinafter referred to as a pixel P) is blue B, a red R for the pixel P is included in the same row as the pixel P, and the red pixel signal closest to the left side of the pixel P A value obtained by averaging signals of red pixels closest to the right side of the pixel P that are included in the same row as the pixel P is employed. Then, as a green G for the pixel P, a signal of a green pixel closest to the left side of the pixel P and a signal of a green pixel closest to the right side of the pixel P included in the same row as the pixel P are included. The average value is used. The same procedure is used when the pixel to be color-interpolated is red R or green G.
[0027]
Specifically, the red signal RA33 and the green signal GA33 corresponding to the pixel BA33 shown in FIG. 1B are generated as follows.
[0028]
An average value of the output of the red pixel RA31 on the left side of the pixel BA33 and the output of the red pixel RA34 on the right side of the pixel BA33 is set as a red signal RA33 for the pixel BA33. Similarly, an average value of the output of the green pixel GA32 on the left side of the pixel BA33 and the output of the green pixel GA35 on the right side of the pixel BA33 is defined as a green signal GA33 for the pixel BA33.
[0029]
When this color interpolation processing method is applied to the solid-state imaging device of the present embodiment in which the rows of red pixels, green pixels, and blue pixels are arranged in stripes, two colors that do not have a color filter are generated for a certain pixel. In order to do this, it is necessary to have two pixels on the left side of the pixel and two pixels on the right side.
[0030]
In this embodiment, color interpolation processing is performed using only pixels in the same row as the pixel for which color interpolation processing is to be performed, but more generally, by using a method including pixels in the upper and lower rows of the pixel for which color interpolation processing is to be performed. The color interpolation process is also performed.
[0031]
In this embodiment, in order to execute the color interpolation processing, two pixels are required on the left side and two pixels on the right side of the pixel on which color interpolation processing is to be performed. In general, the number and the arrangement shape are appropriately set according to the pixel arrangement type of the solid-state imaging device to be used, the color interpolation processing method, and the like.
[0032]
In the present embodiment, the first stage signal processing unit 3 includes three signal processing ICs 3A, 3B, and 3C.
[0033]
The output from the solid-state imaging device 1 is divided into three for each specific pixel region, and each is supplied to the signal processing ICs 3A, 3B, and 3C and processed. Details of the signal processing in the first stage signal processing unit 3 will be described later with reference to FIGS.
[0034]
Each of the signal processing ICs 3 </ b> A, 3 </ b> B, and 3 </ b> C performs the first-stage image signal processing, outputs a display horizontal synchronization signal, and supplies it to the programmable logic synthesis circuit 6.
[0035]
The programmable logic synthesis circuit 6 includes an FPGA (Field Programmable Gate Array), a PLD (Programmable Logic Device), and the like. The image signal is generated as a single image.
[0036]
The timing generator 7 generates a two-phase pulse for driving the HCCD and supplies it to the solid-state imaging device 1, and also generates a four-phase pulse necessary for driving the VCCD and supplies it to the V driver 8. Further, a horizontal synchronization signal, a vertical synchronization signal, and the like are generated. The V driver 8 supplies the solid-state imaging device 1 with a 4-phase signal for driving the VCCD.
[0037]
2A and 2B are timing charts showing the operation of the solid-state imaging device according to the present embodiment.
[0038]
FIG. 2A shows two vertical periods TV1 and TV2.
[0039]
First, in the TV 1, when the vertical synchronization signal VD rises, a readout pulse is superimposed on the VCCD drive signal V 2, and image charges are read out to the VCCD from the pixels in the A field (odd row).
[0040]
The image charges read out to the VCCD are transferred in the VCCD by the four-phase drive signals V1, V2, V3, and V4 and in the HCCD by the two-phase drive signals H1 and H2. Then, it is converted into a voltage signal by an output amplifier, amplified, and then supplied to the analog front end.
[0041]
In the analog front end, an analog signal from the solid-state imaging device is converted into a digital signal, and an output 2out is generated.
[0042]
When all the image signals of the A field are output, the first vertical period TV1 ends. When the first vertical period TV1 ends, the vertical synchronization signal VD rises again, and the second vertical period TV2 starts.
[0043]
At the beginning of the vertical period TV2, a readout pulse is superimposed on the VCCD drive signal V4, and the image signal of the B field (even-numbered rows) is read out to the VCCD. Thereafter, in the same process as in the vertical period TV1, the B-field image signal is read from the solid-state imaging device, and the output 2out from the analog front end is generated accordingly.
[0044]
The readout of the image charges of the entire pixel matrix is completed by two vertical periods TV1 and TV2.
[0045]
FIG. 2B is a timing chart obtained by enlarging a part of FIG. 2A in time, and shows a process for two horizontal transfers. However, the vertical synchronization signal VD is not shown.
[0046]
A single horizontal scanning period TH starts with the rising edge of the horizontal synchronizing signal HD as a signal. In one horizontal scanning period TH, an image signal for one row is output from the solid-state imaging device.
[0047]
At the beginning of the horizontal scanning period TH, the four-phase signals V1, V2, V3, V4 for driving the VCCD change to a predetermined level, the image charge is transferred in the vertical direction, and the image charge for one row moves to the HCCD. (Line shift)
[0048]
When the line shift is completed, the two-phase drive signals H1 and H2 are applied to the HCCD. The two-phase drive signals H1 and H2 have waveforms that change alternately while maintaining opposite phases. The HCCD sequentially transfers image charges for one row in the horizontal direction in accordance with the two-phase drive signals H1 and H2.
[0049]
The image charge transferred to the HCCD is sequentially converted into a voltage signal by an output amplifier, amplified, supplied to the analog front end, and one line of digital output 2out is generated.
[0050]
When one horizontal period TH ends and the output of the image signal for one row is completed, the horizontal synchronization signal HD rises again, and the horizontal scanning period TH for outputting the next row starts.
[0051]
The horizontal scanning period TH is repeated a predetermined number of times until the image signals of all the rows in the field being read at that time are output.
[0052]
FIG. 3 is a diagram for explaining an outline of signal processing by the signal processing ICs 3A, 3B, and 3C.
[0053]
In FIG. 3, the pixel area of the solid-state imaging device 1 is divided into three strip-shaped areas DA, DB, and DC. The signal processing ICs 3A, 3B, and 3C include image signals from the areas DA, DB, and DC. Are set to be supplied respectively.
[0054]
The regions DA and DB have a region Dab that overlaps with each other at the edge, and the regions DB and DC have a region Dbc that overlaps with each other at the edge.
[0055]
The pixel signal from the area Dab is set to be supplied to both the signal processing ICs 3A and 3B, and the pixel signal from the area Dbc is set to be supplied to both the signal processing ICs 3B and 3C.
[0056]
On the other hand, pixel signals from the areas Da, Db, and Dc are supplied only to the signal processing ICs 3A, 3B, and 3C, respectively.
[0057]
Image signals divided and processed by the signal processing ICs 3A, 3B, and 3C are combined into one using a programmable logic synthesis circuit to obtain an image signal for the entire pixel region.
[0058]
The shapes of the areas Da, Db, and Dc are appropriately set according to the processing capability of the signal processing IC to be used.
[0059]
By appropriately setting the shapes of the areas Da, Db, and Dc, the three signal processing ICs to be used can be of the same type.
[0060]
Regions Dab and Dbc in which pixel signals are supplied redundantly to a plurality of signal processing ICs are provided in order to satisfactorily combine image signals that have been divided and processed.
[0061]
The shapes of the regions Dab and Dbc that are processed in duplicate by the plurality of signal processing ICs are appropriately set according to the pixel arrangement type of the solid-state imaging device to be used, the color interpolation processing method, and the like.
[0062]
In this way, the image signal output from one solid-state image sensor is divided and processed by a plurality of signal processing ICs, so that a signal processing IC for a small number of pixels is provided for a solid-state image sensor having a large number of pixels. Signal processing using a plurality of signals becomes possible. For example, when a new solid-state imaging device having a large number of pixels is newly produced, an existing signal processing IC for a small number of pixels can be used without creating a new signal processing IC that matches the number of pixels of the solid-state imaging device. Can be used.
[0063]
Hereinafter, specific signal processing steps of the signal processing ICs 3A, 3B, and 3C in the present embodiment will be described with reference to a timing chart shown in FIG. FIG. 4A shows a process of processing a signal for one row of the pixel matrix. Note that the position of the horizontal axis is partially offset for easy understanding.
[0064]
When a single row of image signals is output from the solid-state imaging device 1 shown in FIG. 1B, first, the signals of the pixels included in the region Da of FIG. 3 are output, and then sequentially the regions Dab and Db. , Dbc continues to output the pixel signals, and finally outputs the pixel signals included in the region Dc, completing the output of the pixel signals for one row.
[0065]
The output for one row is sequentially converted into a digital signal by the analog front end, and an output 2out as shown in the uppermost part of FIG. 4A is obtained from the analog front end. Signals Sa, Sab, Sb, Sbc, and Sc indicate outputs from the pixels included in the areas Da, Dab, Db, Dbc, and Dc in FIG. 3, respectively.
[0066]
Outputs of the signal processing ICs 3A, 3B, and 3C are indicated by 3Aout, 3Bout, and 3Cout. The signal processing IC 3A performs signal processing on the output 2out (that is, the signals Sa and Sab) in accordance with the horizontal synchronization signal HDA, and outputs a color interpolation processing result SA for a portion where the color interpolation processing can be performed. To do. The processing IC 3B performs signal processing on the output 2out (that is, for the signals Sab, Sb, and Sbc) in accordance with the horizontal synchronization signal HDB, and performs the color interpolation processing result SB for the portion that can perform color interpolation processing. Is output. The signal processing IC 3C performs signal processing on the output 2out (that is, on the signals Sbc and SC) in accordance with the horizontal synchronization signal HDC, and outputs the color interpolation processing result SC for a portion where color interpolation processing is possible. Output.
[0067]
By the way, due to the signal processing performed by dividing the pixel area, color interpolation processing is performed on the edges of the areas DA, DB, and DC in FIG. 3 (except for the edges of the solid-state imaging device). A pixel that cannot be produced. Therefore, in this embodiment, the signal processing ICs 3A, 3B, and 3C are set so as to output the color interpolation processing results SA, SB, and SC only for pixel signals that can perform normal color interpolation processing. Note that the result of the color interpolation process is not output for the pixels at the edge of the solid-state imaging device that cannot perform the color interpolation process regardless of the division of the pixel area.
[0068]
For example, consider a case where the signal processing IC 3A performs color interpolation processing on the pixel rows included in the area DA of FIG. At this time, even if an attempt is made to perform color interpolation processing on the pixel at the right end of the area DA (hereinafter referred to as pixel P1), there is no pixel belonging to the area DA on the right side of the pixel P1, and therefore color interpolation processing for the pixel P1 is performed. Cannot be implemented.
[0069]
Also, for example, when color interpolation processing is performed on the pixel in the second column from the right end of the area DA (hereinafter referred to as pixel P2) by the signal processing IC 3A, there is only one pixel on the right side of the pixel P2 in the area DA. Therefore, color interpolation processing can be performed for one color, but color interpolation processing cannot be performed for the remaining one color (in this case, the area DA is set so that there are two or more pixels on the left side of the pixel P2). ing).
[0070]
On the other hand, since there are two or more pixels on the right side of the pixel P3 in the area DA for the pixels on the left and third columns from the right end of the area DA (hereinafter referred to as the pixel P3), the signal processing IC 3A uses the color. Interpolation processing can be executed (here, the area DA is set so that there are two or more pixels on the left side of the pixel P3).
[0071]
Thus, since there is a pixel that cannot perform color interpolation processing near the right end of the area DA in FIG. 3, for all of the output signals Sa and Sab from the analog front end shown in FIG. The color interpolation process cannot be executed by the signal processing IC 3A. Some pixel signals near the right end of the signal Sab are not subjected to color interpolation processing.
[0072]
Similarly, for the signal processing IC 3B, pixel signals near the left end of the signal Sab and the right end of the signal Sbc are not subjected to color interpolation processing, and for the signal processing IC 3C, the pixel signal near the left end of the signal Sbc Some color interpolation processing has not occurred.
[0073]
Now, by appropriately setting the overlapping width of the areas DA and DB (width of the area Dab) in FIG. 3, the pixel corresponding to the right end of the signal SA and the pixel corresponding to the left end of the signal SB are adjacent to each other. Similarly, by appropriately setting the overlapping width of the regions DB and DC (the width of the region Dbc), the pixel corresponding to the right end of the signal SB and the pixel corresponding to the left end of the signal SC are adjacent to each other. Can be. That is, when the signals SA, SB, and SC are connected without overlapping, it is possible to generate one row of pixel signals for which color interpolation processing has been completed.
[0074]
In this embodiment, the overlapping width of the regions DA and DB (the width of the region Dab) and the overlapping width of the regions DB and DC (the width of the region Dbc) are both set to 4 pixels. Each of the signals Sab and Sbc is a signal for four pixels.
[0075]
In this case, the signal processing IC 3A cannot execute the color interpolation processing on the third and fourth pixels from the left end of the signal Sab, but can execute it on the first and second pixels from the left end as the signal SA. (The area DA is set so that there are two or more pixels on the left side of the pixel to be subjected to color interpolation processing). On the other hand, the signal processing IC 3B cannot perform color interpolation processing on the first and second pixels from the left end of the signal Sab, but can execute it on the third and fourth pixels from the left end and outputs it as a signal SB. (Note that the region DB is set so that there are two or more pixels on the right side of the pixel for which color interpolation processing is desired). The same applies to the signal Sbc.
[0076]
In the color interpolation processing method of this embodiment, two pixels are required on one side (left side or right side) of a pixel to be subjected to color interpolation processing. By setting the overlap width to, for example, four pixels (four columns) twice the two pixels necessary for color interpolation in this way, the signals SA, SB, SC are connected without overlapping, and one pixel signal line is connected. Minutes can be generated.
[0077]
The output of the programmable logic synthesis circuit is indicated by 6out. In the programmable logic synthesis circuit, 3Aout (signal SA) during the period when the display horizontal synchronization signal HBLKA rises, 3Bout (signal SB) during the period when the display horizontal synchronization signal HBLKB rises, and the display horizontal synchronization signal HBLKC rises. 3Cout (signal SC) for a certain period is supplied. In the programmable logic synthesis circuit, the signals SA, SB, and SC are connected to generate an image signal for one row in which the color interpolation processing is completed.
[0078]
The display horizontal synchronization signals HBLKA, HBLKB, and HBLKC are supplied from the signal processing ICs 3A, 3B, and 3C, respectively.
[0079]
In this embodiment, the overlap between the pixel areas is set to four columns so that outputs from a plurality of signal processing ICs can be connected without overlapping to obtain an image signal for one row. When the pixel arrangement type of the solid-state imaging device to be used, the color interpolation processing method, and the like are different, the required overlapping shape between the pixel regions is different. Even in such a case, the overlapping shape between the pixel regions may be appropriately set in consideration of the number of pixels necessary for the periphery of the pixel to be subjected to the color interpolation processing and the arrangement shape.
[0080]
FIG. 4B is a timing chart for explaining another embodiment of the present invention.
[0081]
The process up to the stage of obtaining the output 2out from the analog front end is the same as that of the first embodiment described with reference to FIG.
[0082]
In the first embodiment, the signal processing ICs 3A (3B, 3C) output color signals only to pixels that can perform color interpolation processing. In this embodiment, the signal processing IC 3A (3B, 3C) generates and outputs a temporary color signal for an image signal for which the color interpolation process cannot be normally executed. However, the color interpolation processing result is set so as not to be output for the pixels at the edge of the solid-state imaging device in this embodiment.
[0083]
The temporary color signal is generated using pixels that exist only on one side (right side or left side) of the pixel to be subjected to color interpolation processing.
[0084]
Further, in the present embodiment, the programmable logic synthesis circuit has a function of synthesizing and combining the results processed by the plurality of signal processing ICs in the first stage signal processing unit.
[0085]
The signal processing IC 3A performs signal processing on the output 2out (that is, for the signals Sa and Sab) in accordance with the horizontal synchronization signal HDA. Signals SA and SAB-A are generated for the analog front end outputs Sa and Sab, respectively. The processing IC 3B performs signal processing on the output 2out (that is, on the signals Sab, Sb, and Sbc) in accordance with the horizontal synchronization signal HDB. Signals SAB-B, SB, and SBC-B are generated for the analog front end outputs Sab, Sb, and Sbc, respectively. The signal processing IC 3C performs signal processing on the output 2out (that is, for the signals Sbc and Sc) in accordance with the horizontal synchronization signal HDC. Signals SBC-C and SC are output for analog front end outputs Sbc and Sc, respectively.
[0086]
Here, for example, consider a pixel (hereinafter referred to as pixel P4) in which color interpolation processing cannot be normally performed in signal processing in the signal processing IC 3A. The pixel P4 exists in the vicinity of the right end of the area Dab in FIG. 3. However, since there is no pixel that can be used for the color interpolation process on the right side of the pixel P4, the color interpolation process cannot be performed. Therefore, a temporary signal of a color to be supplemented is generated using the signal of the pixel on the left side of the pixel P4. For example, a signal of one pixel of the color that is closest to the left side of the pixel P4 is a temporary signal of the color for the pixel P4.
[0087]
However, since the temporary color signal generated in this way uses only the signal of the pixel existing only on one side of the pixel to be subjected to the color interpolation process, if it is used as it is as the color signal for the pixel P4, the generation of false colors Etc. are unfavorable.
[0088]
By the way, the pixel P4 is also processed by the signal processing IC 3B. If the number of pixels necessary for the color interpolation process exists on both sides of the pixel P4 during the processing by the signal processing IC 3B, the normal color interpolation process is executed. If there is no pixel that can be used for color interpolation processing on the left side of the pixel P4, a temporary color signal is generated using only the signal of the pixel on the right side of the pixel P4. In any case, when the pixel P4 is processed by the signal processing IC 3B, the output includes the signal of the pixel existing on the right side of the pixel P4.
[0089]
Accordingly, as a color signal supplemented to the pixel P4, the signal SAB-A includes a color signal generated only from the signal of the pixel existing on the left side of the pixel P4, and the signal SAB-B includes the pixel signal. The color signal generated from the signal including the pixel existing on the right side of P4 is included.
[0090]
Then, by combining the signals SAB-A and SAB-B, it is possible to compensate for a color signal including information on the left and right sides of the pixel P4.
[0091]
The programmable logic synthesis circuit synthesizes the signals SAB-A and SAB-B by a process such as taking a weighted average to generate the signal SAB. In the signal SAB, a color signal including information on the left and right sides of the pixel P4 is supplemented for the pixel P4.
[0092]
By appropriately setting the weighted average method, the color signal of the pixel P4 can be supplemented to match the color interpolation processing method in the first stage signal processing unit.
[0093]
Similarly, the color signal that the pixel does not have can be compensated for the pixel in which the color interpolation process cannot be normally executed in the signal processing ICs 3B and 3C.
[0094]
In the programmable logic synthesis circuit, 3Aout (signals SA and SAB-A) during which the display horizontal synchronization signal HBLKA rises and 3Bout (signals SAB-B, SB and SBC) during which the display horizontal synchronization signal HBLKB rises. -B) and 3Cout (signals SBC-C, SC) during the period when the display horizontal synchronizing signal HBLKC rises are supplied.
[0095]
In the programmable logic synthesis circuit, the output SAB-A from the signal processing IC 3A and the output SAB-B from the signal processing IC 3B are synthesized and output as one signal SAB. Further, the output SBC-B from the signal processing IC 3B and the output SBC-C from the signal processing IC 3C are combined and output as one signal SBC. In this synthesis process, the process of supplementing the color signal is completed for the pixels for which the color interpolation process cannot be normally executed by the first-stage signal processing unit. Signals SA, SB and SC are output as they are.
[0096]
In this way, finally, the image signals SA, SAB, SB, SBC, and SC for one row in which the color signal is supplemented for each pixel are generated in the programmable logic synthesis circuit.
[0097]
In the above two embodiments, color interpolation processing is performed using only pixels in the same row as the pixel for which color interpolation processing is to be performed. However, by providing a delay circuit before the signal processing IC, pixels for which color interpolation processing is to be performed. Color interpolation processing can be performed in a form including pixels in the upper and lower rows.
[0098]
For example, as shown in FIG. 5, for the output from the analog front end 2, a signal without delay, a delay signal for one row by the delay circuit 20, and a delay signal for two rows by the delay circuit 21 are generated. The signal processing ICs 3A ′ (3B ′, 3C ′) are supplied in parallel. The signal processing IC 3A ′ (3B ′, 3C ′) can input color signals for three rows and perform color interpolation processing.
[0099]
In the above two embodiments, the solid-state imaging device that reads out image signals in units of rows has been described, but a solid-state imaging device that reads out in units of columns may be used. What is necessary is just to read description about a row into a column.
[0100]
As mentioned above, although this invention was demonstrated along the Example, this invention is not restrict | limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0101]
【The invention's effect】
As described above, according to the present invention, a novel control method for favorably performing parallel signal processing regarding color interpolation processing and the like in a solid-state imaging device is provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a solid-state imaging device and a schematic plan view of a solid-state imaging device.
FIG. 2 is a timing chart schematically showing the operation of the solid-state imaging device.
FIG. 3 is a diagram for explaining an outline of signal processing in a first stage signal processing unit;
FIG. 4 is a timing chart showing a specific signal processing process in the signal processing IC.
FIG. 5 is a block diagram showing a configuration including a delay circuit between an analog front end and a signal processing IC.
[Explanation of symbols]
1 Solid-state image sensor
2 Analog front end
3 First stage signal processor
3A, 3B, 3C Signal processing IC
6 Programmable logic synthesis circuit
7 Timing generator
8 V driver

Claims (4)

(A) supplying a series of image signals corresponding to one pixel row or one pixel column of a solid-state imaging device in parallel to a plurality of signal processing units;
(B) Each of the signal processing units is a step of selecting and processing a portion of the image signal as a processing target image signal, and the processing target image signal processed by a certain signal processing unit, and the other A common image signal exists between the other image signal to be processed and processed by the signal processing unit.
(C) combining the output signals from the plurality of signal processing units into one, and generating a series of image signals corresponding to one pixel row or one pixel column of the solid-state imaging device;
A control method for a solid-state imaging device. The method for controlling a solid-state imaging device according to claim 1, wherein color interpolation processing is performed in the step (b). An output unit that outputs a series of image signals corresponding to one pixel row or one pixel column of the solid-state imaging device;
A plurality of signal processing units for processing the image signals in parallel;
A timing signal for selecting a part of the image signal as a processing target image signal for each of the signal processing units, the processing target image signal processed by a certain signal processing unit, and another Timing signal generator for generating a timing signal for selecting the processing target image signal so that there is a common image signal with the other processing target image signal processed by the signal processing unit When,
A signal generation unit that combines outputs from the plurality of signal processing units into one and generates a series of image signals corresponding to one pixel row or one pixel column of the solid-state imaging device;
A solid-state imaging device. The solid-state imaging device according to claim 3, wherein the signal processing unit performs color interpolation processing.

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