JP2004072434A - Data output circuit and integrated circuit having the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data output circuit having increased reliability of operation and an integrated circuit having the same. <P>SOLUTION: The data output circuit contains an inverter IV1 activated by elevating a power voltage VDL for a logic circuit and a level shifter LS1; and inverters IV3, IV4 activated by elevating power voltages VDH for the data output circuit and buffering data supplied from the level shifter LS1 for external output, and an N channel MOS transistor NT3, and is provided with a reset circuit RS fixing the potential of a wiring node L3 until the power voltage VDL exceeds the specified value after the power supply for the logic circuit is turned on when a power supply for the data output circuit is turned on prior to a power supply for the logic circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data output circuit for outputting data and an integrated circuit including the same.
[0002]
[Prior art]
FIG. 2 is a block diagram illustrating a configuration of a conventional information processing apparatus. In the information processing apparatus shown in FIG. 2, a plurality of integrated circuits (ICs) 1 to 3 are interconnected by a bus 4, and a monitor 5 for monitoring the potential of the bus 4 is connected to the bus 4. A power supply node is connected to the bus 4 via a pull-up resistor 7.
[0003]
In the information processing apparatus having the above-described configuration, the potential of the bus 4 is constantly raised to the high level by the pull-up resistor 7 and the potential of the bus 4 is lowered when any of the ICs 1 to 3 outputs low-level data. Descend. Here, the monitor 5 detects the potential drop of the bus 4 and executes a predetermined operation.
[0004]
FIG. 3 is a diagram showing a configuration of the IC 1 shown in FIG. IC2 and IC3 shown in FIG. 2 have the same configuration as IC1. As shown in FIG. 3, the IC 1 includes a logic circuit 9 and a plurality of data output circuits 10 arranged adjacent to the logic circuit 9 and externally outputting data generated by the logic circuit 9.
[0005]
Here, in recent ICs 1 to 3, a power supply is separated into a plurality of power supplies to reduce power consumption and noise, and a level shifter is often built in the data output circuit 10. At this time, for example, in the so-called N-channel open-drain data output circuit 10 having the level shifter and the output node connected to the ground node via the N-channel MOS transistor, the ICs 1 to 3 transition from the off state to the on state. In some cases, the order in which power is turned on at the time of operation may be a problem.
[0006]
That is, if the power supply for supplying a relatively low voltage to the logic circuit 9 inside the IC 1 is turned on after the power supply for supplying a high voltage to the data output circuit 10 is turned on in the above, the logic circuit 9 There is a problem that the data output circuit 10 may erroneously output low-level data before the voltage rises.
[0007]
Hereinafter, the malfunction will be described in detail. FIG. 4 is a circuit diagram showing a configuration of data output circuit 10 shown in FIG. As shown in FIG. 4, the conventional data output circuit 10 includes a level shifter LS1, inverters IV1, IV3, IV4, N-channel MOS transistors NT3, and wiring nodes L3 to L5. The level shifter LS1 includes an inverter IV2, an N-channel MOS transistor NT1, NT2, P-channel MOS transistors PT1 to PT4 and wiring nodes L1, L2.
[0008]
Inverters IV1 and IV2 operate between power supply voltage VDL for logic circuit 9 and the ground voltage, and inverters IV3 and IV4 operate between power supply voltage VDH for data output circuit 10 and the ground voltage. The level shifter LS1 operates between the power supply voltage VDH and the ground voltage.
[0009]
In the data output circuit 10 having the above-described configuration, the signal Sin generated in the logic circuit 9 is input to the inverter IV1 and level-converted by the level shifter LS1, and then supplied to the gate of the N-channel MOS transistor NT3. Here, a signal _SOUT is output from the drain of the N-channel MOS transistor NT3 to the outside of the IC according to the voltage supplied to the gate.
[0010]
In the data output circuit 10, when the power supply for the logic circuit 9 is turned off, the potentials of the wiring nodes L1 and L2 become low level. Here, if the power supply for the data output circuit 10 is turned on before the power supply for the logic circuit 9 while the power supply voltage VDH for the data output circuit 10 is close to the ground level, the output of the level shifter LS1 will be disabled. As a result, the P-channel MOS transistors PT1 and PT2 are turned on, and the potential of the output node (interconnection node L3) may exceed the threshold value of the inverter IV3.
[0011]
In such a case, the potential of the wiring node L4 goes low and the potential of the wiring node N5 goes high, so that a high-level voltage is supplied to the gate of the N-channel MOS transistor NT3 to turn it on. Therefore, at this time, the low level signal _SOUT is erroneously output from the data output circuit 10.
[0012]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and has as its object to provide a data output circuit with improved operation reliability and an integrated circuit including the same.
[0013]
[Means for Solving the Problems]
An object of the present invention is to activate a first power supply and turn on a first internal circuit for buffering input data and a second power supply different from the first power supply. And a second internal circuit that buffers data buffered by the first internal circuit and outputs the data to the outside, wherein the second power supply is higher than the first power supply. Clamp means for supplying a predetermined signal to the second internal circuit from when the first power supply is turned on until the voltage supplied from the first power supply exceeds a predetermined value when the first power supply is turned on. This is achieved by providing a data output circuit characterized by comprising:
[0014]
According to such a means, when the operation of the first internal circuit is not stable even when the second internal circuit is activated by turning on the second power supply, the first internal circuit is not activated. Until the operation is stabilized, the clamp means supplies a predetermined signal to the second internal circuit, so even when the second power supply is turned on before the first power supply, An incorrect external output is avoided.
[0015]
Here, for example, the first internal circuit includes a level shifter that converts a signal level of input data and supplies the signal to the second internal circuit, and the second internal circuit includes a voltage supplied to the gate. May include a transistor that outputs data from the drain to the outside in accordance with the above.
[0016]
In addition, since the above operation is preferably performed by the data output circuit itself when the first and second power supplies are turned on, the clamp means is driven only by the first power supply and the second power supply. It is said.
[0017]
Further, an object of the present invention is to provide a logic circuit that performs a logical operation and a first circuit that is activated by turning on a first power supply for driving the logic circuit and buffers data input from the logic circuit. An internal circuit, a second internal circuit that is activated by turning on a second power supply different from the first power supply, buffers the data buffered by the first internal circuit, and outputs the data to the outside; When the second power supply is turned on before the first power supply, the voltage supplied from the first power supply after the first power supply is turned on exceeds a predetermined value. In the meantime, the present invention is attained by providing an integrated circuit having a clamp means for supplying a predetermined signal to the second internal circuit.
[0018]
According to such a means, when the operation of the first internal circuit is not stable even when the second internal circuit is activated by turning on the second power supply, the first internal circuit is not activated. Until the operation is stabilized, the clamp means supplies a predetermined signal to the second internal circuit. Therefore, even when the second power supply is turned on before the first power supply, an erroneous external signal is output from the integrated circuit. Output is avoided.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0020]
FIG. 1 is a circuit diagram showing a configuration of a data output circuit 20 according to an embodiment of the present invention. The data output circuit 20 is built in the integrated circuit 1 together with, for example, the logic circuit 9, similarly to the data output circuit 10 shown in FIG. 3, and outputs data between the outside of the integrated circuit 1 and the logic circuit 9. Hand over.
[0021]
As shown in FIG. 1, the data output circuit 20 according to the present embodiment includes a level shifter LS1, a reset circuit RS, inverters IV1, IV3, IV4, an N-channel MOS transistor NT3, and wiring nodes L3 to L5. Includes an inverter IV2, N-channel MOS transistors NT1 and NT2, P-channel MOS transistors PT1 to PT4, and wiring nodes L1 and L2.
[0022]
The reset circuit RS includes an on / off control unit RS1, an on-time control unit RS3, and an N-channel MOS transistor NT4. The on-time control unit RS3 includes an N-channel MOS transistor NT8 and P-channel MOS transistors PT10 to PT12.
[0023]
The on / off control unit RS1 includes a buffer circuit RS2, N-channel MOS transistors NT5 and NT7, and P-channel MOS transistors PT5 to PT7. Further, buffer circuit RS2 includes an N-channel MOS transistor NT6 and P-channel MOS transistors PT8 and PT9. Note that the threshold values of N-channel MOS transistor NT6 and P-channel MOS transistors PT8 and PT9 included in buffer circuit RS2 are lower than the threshold values of the other transistors forming reset circuit RS.
[0024]
Here, an N-channel MOS transistor NT4 is connected between the wiring node L3 and the ground node, and an ON / OFF control unit RS1 is connected to a gate of the N-channel MOS transistor NT4. Further, an on-time control unit RS3 is connected to the gate of the N-channel MOS transistor NT7 included in the on / off control unit RS1.
[0025]
The N-channel MOS transistor NT5 and the P-channel MOS transistors PT5 to PT7 included in the on / off control unit RS1 are cascaded, and the intermediate node connecting the N-channel MOS transistor NT5 and the P-channel MOS transistor PT7 is N. Connected to the gate of channel MOS transistor NT4.
[0026]
Here, the power supply voltage for the logic circuit is supplied to the gates of the N-channel MOS transistor NT5 and the P-channel MOS transistors PT6 and PT7, and the power supply voltage VDH for data output is supplied to the source of the P-channel MOS transistor PT5. . Further, the gate of P-channel MOS transistor PT5 is connected to the drain of N-channel MOS transistor NT7.
[0027]
On the other hand, N-channel MOS transistor NT6 and P-channel MOS transistors PT8 and PT9 included in buffer circuit RS2 are cascaded, and the gates of N-channel MOS transistor NT6 and P-channel MOS transistors PT8 and PT9 are respectively connected to N-channel MOS transistor NT4. Connected to gate. The source of P-channel MOS transistor PT8 is supplied with power supply voltage VDH, and an intermediate node between N-channel MOS transistor NT6 and P-channel MOS transistor PT9 is connected to the drain of N-channel MOS transistor NT7.
[0028]
The N-channel MOS transistor NT8 and the P-channel MOS transistors PT10 to PT12 included in the on-time control unit RS3 are cascaded, and the intermediate node connecting the N-channel MOS transistor NT8 and the P-channel MOS transistor PT12 is an N-channel MOS transistor. Connected to the gate of MOS transistor NT7. Further, P-channel MOS transistors PT10 and PT11 are each diode-connected, a power supply voltage VDH is supplied to the source of P-channel MOS transistor PT10, and a power supply is supplied to the gates of N-channel MOS transistor NT8 and P-channel MOS transistor PT12. The voltage VDL is supplied.
[0029]
In the data output circuit 20 having the above-described configuration, when the power supply for the data output circuit 20 is first turned on and the power supply voltage VDH starts to rise first, the power supply voltage VDL for the logic circuit is sufficiently increased. During the start-up time, the output node (wiring node L3) of the level shifter LS1 is fixed to the low level by the reset circuit RS.
[0030]
Thus, during the start-up time, the operations of the inverters IV3 and IV4 and the N-channel MOS transistor NT3 are stabilized, and the output node of the data output circuit 20 is set to a high impedance state, so that malfunction of the data output circuit 20 is avoided. You.
[0031]
Hereinafter, the operation of the data output circuit 20 according to the present embodiment shown in FIG. 1 will be described in detail.
[0032]
The on / off control unit RS1 controls on / off of the N-channel MOS transistor NT4, and the on-time control unit RS3 controls the time during which the N-channel MOS transistor NT4 is turned on.
[0033]
Here, it is assumed that the power supply for the data output circuit 20 is turned on first, the power supply voltage VDH rises, and the power supply voltage VDL for the logic circuit is close to the ground level. At this time, the potential of the output node (wiring node L9) in the on-time control unit RS3 is a voltage lower than the power supply voltage VDH by 2 Vth or more, where the threshold voltage of the P-channel MOS transistors PT10 and PT11 is Vth.
[0034]
Note that when the level of power supply voltage VDL rises and N-channel MOS transistor NT8 turns on, it is necessary to sufficiently lower the potential of interconnection node L9 to a low level. It is preferable that the impedance between them is high. In addition, it is necessary to suppress a leak current that passes from the P-channel MOS transistor PT10 to the ground node via the N-channel MOS transistor NT8 when the power supply voltage VDL rises. For these reasons, in the on-time control unit RS3, two P-channel MOS transistors PT10 and PT11 are cascaded.
[0035]
In data output circuit 20 according to the present embodiment, when power supply voltage VDH rises, on-time control unit RS3 turns on N-channel MOS transistor NT7 and wiring node L8 attains a low level, so P-channel MOS transistor PT5 turns on. . Further, since P-channel MOS transistors PT6 and PT7 are turned on until power supply voltage VDL sufficiently rises, power supply voltage VDH is supplied to wiring node L7 via P-channel MOS transistors PT5 to PT7. Thus, until power supply voltage VDL rises sufficiently, N-channel MOS transistor NT4 is turned on, and the potential of interconnection node L3 is fixed at the low level.
[0036]
Next, as power supply voltage VDL increases, N-channel MOS transistor NT5 transitions to the on state, and the on-resistance of P-channel MOS transistors PT6 and PT7 increases. Therefore, during the rising period of the power supply voltage VDL, the potential of the wiring node L7 is divided by the power supply voltage VDH divided by the N-channel MOS transistor NT5 and the P-channel MOS transistors PT5 to PT7. It is supplied to the gates of the transistors PT8 and PT9 and the N-channel MOS transistor NT6.
[0037]
When the power supply voltage VDL rises sufficiently, the N-channel MOS transistor NT8 is turned on, so that the potential of the wiring node L9 goes low. As a result, the N-channel MOS transistor NT7 is turned off, and the potential of the wiring node L8 changes from a low level to a high level. Therefore, P-channel MOS transistor PT5 is completely turned off. At this time, power supply voltage VDL sufficiently rises to completely turn on N-channel MOS transistor NT5, so that N-channel MOS transistor NT4 is completely turned off.
[0038]
As described above, when the power supply voltage VDL rises due to the power supply for the data output circuit 20 being turned on first and the power supply voltage VDL rising after the power supply for the logic circuit is turned on, the reset circuit RS The output of the data output circuit 20 is brought into a high impedance state by clamping (fixing) the potential of the wiring node L3 to a low level until the power supply voltage VDL rises sufficiently until the potential rises sufficiently. Is not affected.
[0039]
When the threshold value of N-channel MOS transistor NT4 is the same as the threshold value of the N-channel MOS transistor forming inverter IV3, the timing when power supply voltage VDH rises and inverter IV3 starts operating , The N-channel MOS transistor NT4 is turned on, and the potential of the wiring node L3 is clamped to a low level. Therefore, even when the power supply voltage VDH rises, malfunction of the data output circuit 20 is effectively avoided.
[0040]
If the N-channel MOS transistor NT4 has a sufficiently high breakdown voltage, it is desirable that the N-channel MOS transistor NT4 has a threshold lower than that of the N-channel MOS transistor forming the inverter IV3. By operating the reset circuit RS at an early stage after the power supply voltage VDH starts to rise and clamping the potential of the wiring node L3 to a low level early, the reliability of the operation of the data output circuit 20 can be further improved. That's why.
[0041]
As described above, according to the data output circuit 20 according to the embodiment of the present invention and the integrated circuit including the same, the malfunction of the data output circuit 20 that occurs when the power supply for the data output circuit 20 is first turned on is simplified. With such a configuration, the reliability of the operation of the data output circuit 20 or the integrated circuit including the same can be improved.
[0042]
In order to improve the reliability of the data output operation of the integrated circuit, a clamp circuit corresponding to the reset circuit RS may be provided in a logic circuit built in the integrated circuit, or a malfunction may occur outside the integrated circuit. It is conceivable to provide a control circuit for avoiding the above problem, but in any case, the circuit scale and cost increase as a whole. On the other hand, since the data output circuit 20 according to the embodiment of the present invention incorporates the reset circuit RS for preventing malfunction, the circuit scale and cost of the integrated circuit or the entire system using the integrated circuit increase. Is avoided.
[0043]
【The invention's effect】
According to the data output circuit and the integrated circuit including the same according to the present invention, even when the second power supply is turned on before the first power supply, an erroneous external output is made from the second internal circuit. Therefore, the reliability of the data output operation can be improved.
[0044]
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a data output circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a conventional information processing apparatus.
FIG. 3 is a diagram showing a configuration of an integrated circuit (IC) shown in FIG.
FIG. 4 is a circuit diagram showing a configuration of a data output circuit shown in FIG. 3;
[Explanation of symbols]
1-3 integrated circuit (IC), 4 bus, 5 monitor, 7 pull-up resistor, 9 logic circuit, 10, 20 data output circuit (OC), LS1 level shifter, RS reset circuit, RS1 on / off control unit, RS2 buffer Circuit, RS3 on-time control unit, IV1 to IV4 inverter, NT1 to NT8 N-channel MOS transistor, PT1 to PT12 P-channel MOS transistor, L1 to L9 Wiring node.

Claims (7)

The first power supply is activated by being turned on, the first internal circuit for buffering input data, and activated by turning on a second power supply different from the first power supply, A data output circuit including a second internal circuit that buffers data buffered by the first internal circuit and outputs the data to the outside,
When the second power supply is turned on earlier than the first power supply, from when the first power supply is turned on until the voltage supplied from the first power supply exceeds a predetermined value, A data output circuit comprising a clamp unit for supplying a predetermined signal to the second internal circuit. The data output circuit according to claim 1, wherein the first internal circuit includes a level shifter that converts a signal level of the input data and supplies the signal level to the second internal circuit. 2. The data output circuit according to claim 1, wherein the second internal circuit includes a transistor that outputs the data to the outside from a drain according to a voltage supplied to a gate. 2. The data output circuit according to claim 1, wherein said clamp means is driven only by said first power supply and said second power supply. A logic circuit that executes a logical operation; a first internal circuit that is activated by turning on a first power supply for driving the logic circuit and buffers data input from the logic circuit; A second internal circuit that is activated when a second power supply different from the one power supply is turned on, buffers the data buffered by the first internal circuit, and outputs the buffered data to the outside And
When the second power supply is turned on earlier than the first power supply, from when the first power supply is turned on until the voltage supplied from the first power supply exceeds a predetermined value, An integrated circuit, comprising: a clamp for supplying a predetermined signal to the second internal circuit. 6. The integrated circuit according to claim 5, wherein the first internal circuit includes a level shifter that converts a signal level of data input from the logic circuit and supplies the converted signal level to the second internal circuit. 6. The integrated circuit according to claim 5, wherein said clamping means is driven only by said first power supply and said second power supply.

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