[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP2004071998A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2004071998A
JP2004071998A JP2002232289A JP2002232289A JP2004071998A JP 2004071998 A JP2004071998 A JP 2004071998A JP 2002232289 A JP2002232289 A JP 2002232289A JP 2002232289 A JP2002232289 A JP 2002232289A JP 2004071998 A JP2004071998 A JP 2004071998A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor
semiconductor device
rewiring
upper layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002232289A
Other languages
Japanese (ja)
Other versions
JP3918681B2 (en
Inventor
Hiroyasu Sadabetto
定別当　裕康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2002232289A priority Critical patent/JP3918681B2/en
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to PCT/JP2003/009958 priority patent/WO2004015771A2/en
Priority to AU2003253425A priority patent/AU2003253425C1/en
Priority to KR1020047005322A priority patent/KR100593049B1/en
Priority to CA2464078A priority patent/CA2464078C/en
Priority to CN038012693A priority patent/CN1568546B/en
Priority to EP03784529A priority patent/EP1527480A2/en
Priority to TW092121811A priority patent/TWI231551B/en
Publication of JP2004071998A publication Critical patent/JP2004071998A/en
Priority to US10/826,039 priority patent/US7294922B2/en
Priority to HK05105873.6A priority patent/HK1073389A1/en
Priority to US11/671,318 priority patent/US7547967B2/en
Priority to US11/671,268 priority patent/US7618886B2/en
Application granted granted Critical
Publication of JP3918681B2 publication Critical patent/JP3918681B2/en
Priority to US12/415,782 priority patent/US7737543B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To realize conductive connection between a silicon substrate and a solder ball without through a bonding process, when manufacturing a semiconductor device called BGA for example. <P>SOLUTION: Onto a bonding layer 22 on a base plate 21 of a size dealing with a plurality of semiconductor devices, semiconductor elements 23 formed by providing a rewiring 32, a columnar electrode 33 and a sealing film 34 on a silicon substrate 24 are bonded with spaces from one another. Then a sealing film 35 is formed on a peripheral side surface of the semiconductor element. Then a first upper insulation film 36, a first upper rewiring 39, a second upper insulation film 41, a second upper rewiring 44 and a third upper insulation film 45 are laminated in this order. At the last, a solder ball 47 is formed. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
例えばＢＧＡ（ｂａｌｌ　ｇｒｉｄ　ａｒｒａｙ）と呼ばれる半導体装置には、ＬＳＩなどからなる半導体チップを該半導体チップのサイズよりもやや大きいサイズの中継基板（インターポーザ）の上面中央部に搭載し、中継基板の下面に半田ボールによる接続端子をマトリクス状に配置したものがある。ここで、中継基板は、半導体チップ上に形成された外部接続電極を他の回路基板にボンディングする際、接続強度および信頼性を得るために、再配線によりそのサイズおよびピッチを充分大きなものとするために用いられる。
【０００３】
図３０は従来のこのような半導体装置の一例の断面図を示したものである。半導体チップ１は、シリコン基板２の周辺部に銅などからなる複数のバンプ電極３が設けられた構造となっている。
【０００４】
中継基板４は、サイズが半導体チップ１のシリコン基板２のサイズよりもやや大きいベースフィルム５を備えている。ベースフィルム５の上面には、半導体チップ１のバンプ電極３に接続される再配線６が設けられている。
【０００５】
再配線６は、半導体チップ１のバンプ電極３に対応して設けられた第１の接続パッド７と、マトリクス状に設けられた第２の接続パッド８と、第１と第２の接続パッド７、８を接続する引き回し線９とからなっている。第２の接続パッド８の中央部に対応する部分におけるベースフィルム５には円孔１０が設けられている。
【０００６】
そして、半導体チップ１は中継基板４の上面中央部に異方性導電接着剤１１を介して搭載されている。異方性導電接着剤１１は、熱硬化性樹脂１２中に多数の導電性粒子１３を含有させたものからなっている。
【０００７】
半導体チップ１を中継基板４上に搭載する場合には、まず、中継基板４の上面中央部にシート状の異方性導電接着剤１１を介して半導体チップ１を位置合わせしてただ単に載置する。
【０００８】
次に、熱硬化性樹脂１２が硬化する温度にて所定の圧力を加えてボンディングする。すると、バンプ電極３が熱硬化性樹脂１２を押し退けて第１の接続パッド７の上面に導電性粒子１３を介して導電接続され、且つ、半導体チップ１の下面が中継基板４の上面に熱硬化性樹脂１２を介して接着される。
【０００９】
次に、半導体チップ１を含む中継基板４の上面全体にエポキシ系樹脂からなる樹脂封止膜１４を形成する。次に、円孔１０内およびその下方に半田ボール１５を第２の接続パッド８に接続させて形成する。この場合、第２の接続パッド８はマトリクス状に配置されているため、半田ボール１５もマトリクス状に配置される。
【００１０】
ここで、半田ボール１５のサイズは半導体チップ１のバンプ電極３のサイズより大きく、また、各半田ボール１５相互の接触を避けるため、その配置間隔をバンプ電極３の配置間隔より大きくする必要がある。そこで、半導体チップ１のバンプ電極３の数が増大した場合、各半田ボール１５に必要な配置間隔を得るため、その配置領域を半導体チップ１のサイズより大きくすることが必要となり、そのために、中継基板４のサイズを半導体チップ１のサイズよりもやや大きくしている。したがって、マトリクス状に配置された半田ボール１５のうち、周辺部の半田ボール１５は半導体チップ１の周囲に配置されている。
【００１１】
【発明が解決しようとする課題】
ところで、上記従来の半導体装置では、再配線６が形成された中継基板４を用い、位置合わせした後のボンディングにより、半導体チップ１のバンプ電極３の下面を中継基板４の再配線６の第１の接続パッド７の上面に異方性導電接着剤１１の導電性粒子１３を介して導電接続する構成としているので、半導体チップ１のバンプ電極３の数が増大し、バンプ電極３のサイズおよび配置間隔が小さくなると、位置合わせが極めて大変であるという問題があった。この場合、半導体チップ１のサイズを大きくすれば、バンプ電極３のサイズおよび配置間隔を大きくすることができることは当然であるが、そのようにすると、ウエハ状態からの半導体チップの取り数が激減し、極めて高価なものとなってしまう。また、半導体チップ１を１つずつ中継基板４上にボンディングして搭載しなければならず、製造工程が煩雑であるという問題があった。このようなことは、半導体チップを複数個備えたマルチチップモジュール型の半導体装置の場合も同様である。
【００１２】
そこで、この発明は、ボンディングによることなく外部接続電極の配置間隔を大きくすることができる半導体装置およびその製造方法を提供することを目的とする。
また、この発明は、複数の半導体装置を一括して製造することができる半導体装置の製造方法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
請求項１に記載の発明は、半導体基板の上面に設けられた複数の再配線および前記各再配線の一端部上に形成された柱状電極を有する半導体構成体と、該半導体構成体の前記柱状電極を除く上面全体および前記半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記柱状電極に接続されて設けられ且つ接続パッドを有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッドが前記絶縁膜上の前記半導体構成体の周側面より外側の前記延出部上に配置されていることを特徴とするものである。
請求項２に記載の発明は、各々が、半導体基板と、該半導体基板の上面に設けられた複数の再配線および前記各再配線の一端部上に形成された柱状電極を有し、互いに離間して配置された複数の半導体構成体と、該各半導体構成体の柱状電極を除く上面全体および前記各半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記柱状電極に接続されて設けられ且つ接続パッドを有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッドが前記絶縁膜上の前記いずれかの半導体構成体の周側面より外側の前記延出部上に配置されていることを特徴とするものである。
請求項３に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられていることを特徴とするものである。
請求項４に記載の発明は、請求項３に記載の発明において、前記半導体構成体の周側面を覆って設けられた前記絶縁膜の下面は前記半導体構成体の下面とほぼ同一の平面上に配置されていることを特徴とするものである。
請求項５に記載の発明は、請求項１または２に記載の発明において、前記上層再配線の中、最下層の上層再配線は前記記絶縁膜に形成された開口を介して直接前記柱状電極に電気的に接続され、前記絶縁膜に形成された前記開口は前記柱状電極の幅の１／２以下の幅を有することを特徴とするものである。
請求項６に記載の発明は、請求項１または２に記載の発明において、前記上層再配線の中、最下層の上層再配線は前記各柱状電極上および前記最下層の絶縁膜上に形成されためっき層を含むことを特徴とするものである。
請求項７に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記半導体構成体の柱状電極と前記上層再配線とを接続する層間再配線が設けられていることを特徴とするものである。
請求項８に記載の発明は、請求項１または２に記載の発明において、前記柱状電極は５０μｍ以上の高さを有することを特徴とするものである。
請求項９に記載の発明は、請求項１または２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面に前記上層再配線の前記接続パッドの少なくとも一部を除く部分に最上層絶縁膜が設けられていることを特徴とするものである。
請求項１０に記載の発明は、請求項９に記載の発明において、前記上層再配線の前記接続パッド上に突起状の接続端子が設けられていることを特徴とするものである。
請求項１１に記載の発明は、請求項９に記載の発明において、前記最上層絶縁膜上に電子部品がいずれかの前記上層再配線の接続パッド部に接続されて設けられていることを特徴とするものである。
請求項１２に記載の発明は、請求項９〜１１のいずれかに記載の発明において、前記半導体構成体およびその周側面に設けられた前記絶縁膜の下面に放熱層が設けられていることを特徴とするものである。
請求項１３に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられ、該半導体構成体の周側面に設けられた前記絶縁膜はベース板上に設けられていることを特徴とするものである。
請求項１４に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられ、該半導体構成体の周側面に設けられた前記絶縁膜上にフレキシブル配線板が配置され、該フレキシブル配線板に形成された接続端子がいずれかの前記上層再配線の前記接続パッドに接続されていることを特徴とするものである。
請求項１５に記載の発明は、請求項１または２に記載の発明において、前記半導体構成体上にフレキシブル配線板が配置され、前記フレキシブル配線板に形成された接続端子がいずれかの前記上層再配線の前記接続パッドに接続されていることを特徴とするものである。
請求項１６に記載の発明は、請求項１５に記載の発明において、前記フレキシブル配線板上に突起状の接続端子が導電接続されて設けられていることを特徴とするものである。
請求項１７に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられ、該半導体構成体の周側面に形成された前記絶縁膜を覆って最外周絶縁膜が設けられていることを特徴とするものである。
請求項１８に記載の発明は、請求項１７に記載の発明において、前記最外周絶縁膜は前記半導体構成体の周側面に形成された前記絶縁膜よりも厚く形成されていることを特徴とするものである。
請求項１９に記載の発明は、請求項１７に記載の発明において、前記最外周絶縁膜は前記半導体構成体の周側面に形成された前記絶縁膜よりも薄く形成されていることを特徴とするものである。
請求項２０に記載の発明は、請求項９に記載の発明において、前記最上層絶縁膜上に電子部品がいずれかの前記上層再配線の接続パッドに接続されて設けられ、他のいずれかの前記上層再配線の外部端子ににフレキシブル配線板に形成された接続端子が接続されていることを特徴とするものである。
請求項２１に記載の発明は、請求項１または２に記載の発明において、上面に前記絶縁膜および前記上層再配線が設けられた前記半導体構成体を複数個有し、前記各半導体構成体上面の上層再配線がフレキシブル配線板により接続されていることを特徴とするものである。
請求項２２に記載の発明は、請求項２１に記載の発明において、前記半導体構成体が互いの下面を対向して積層されていることを特徴とするものである。
請求項２３に記載の発明は、各々が、複数の再配線および前記各再配線上に設けられた柱状電極を有する複数の半導体構成体を相互に離間してベース板上に配置する工程と、前記複数の半導体構成体上を含む前記ベース板の上面全体に絶縁膜を形成する工程と、前記絶縁膜の上面に、接続パッドを有し且ついずれかの前記半導体構成体の対応する前記柱状電極に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッドが前記半導体構成体間に形成された前記絶縁膜上に配置されるように形成する工程と、前記各半導体構成体間における前記絶縁膜を切断して少なくともいずれかの前記上層再配線の接続パッドが前記半導体構成体の周側面を覆う前記絶縁膜上に形成された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とするものである。
請求項２４に記載の発明は、請求項２３に記載の発明において、前記絶縁膜を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項２５に記載の発明は、請求項２３に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の柱状電極とそれに対応する前記上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とするものである。
請求項２６に記載の発明は、請求項２３に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とするものである。
請求項２７に記載の発明は、請求項２６に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子を形成する工程を有することを特徴とするものである。
請求項２８に記載の発明は、請求項２６に記載の発明において、前記最上層絶縁膜上に電子部品を前記上層再配線の接続パッド部に接続させて設ける工程を有することを特徴とするものである。
請求項２９に記載の発明は、請求項２３に記載の発明において、前記絶縁膜を切断する工程は前記絶縁膜を切断するとともに前記ベース板を切断し、前記半導体装置としてベース板を備えたものを得ることを特徴とするものである。
請求項３０に記載の発明は、請求項２９に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とするものである。
請求項３１に記載の発明は、請求項２３に記載の発明において、前記各半導体構成体間における前記絶縁膜を切断する工程の前に、前記ベース板を取り除く工程を有することを特徴とするものである。
請求項３２に記載の発明は、請求項３１に記載の発明において、前記ベース板を取り除く工程に引き続き、前記半導体基板を薄くする工程を有することを特徴とするものである。
そして、この発明によれば、半導体基板上に再配線および柱状電極を有する複数または複数組の半導体構成体をベース板上に配置し、半導体構成体を含むベース板の上面全体に絶縁膜を形成し、絶縁膜の上面に上層再配線を半導体構成体の柱状電極に接続させて形成し、絶縁膜を少なくとも切断することにより、半導体構成体を１つまたは１組有し、その周囲に絶縁膜を有するとともに、周囲の絶縁膜上に上層再配線の一部が配置されてなる半導体装置を複数個一括して得ることができ、従来のようなボンディング工程がなく、したがってボンディングによることなく外部接続電極の配置間隔を大きくすることができ、また複数または複数組の半導体構成体に対して絶縁膜および上層再配線の形成を一括して行うことができるので、製造工程を簡略化することができる。
【００１４】
【発明の実施の形態】
（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示したものである。この半導体装置は、シリコン、ガラス、セラミックス、樹脂、金属などからなる平面正方形状のベース板２１を備えている。ベース板２１の上面には、接着剤、粘着シート、両面接着テープなどからなる接着層２２が設けられている。
【００１５】
接着層２２の上面中央部には、ベース板２１のサイズよりもやや小さいサイズの平面正方形状の半導体構成体２３の下面が接着されている。この場合、半導体構成体２３は、ＣＳＰ（ｃｈｉｐ　ｓｉｚｅ　ｐａｃｋａｇｅ）と呼ばれるものであり、接着層２２の上面中央部に接着されたシリコン基板（半導体基板）２４を備えている。シリコン基板２４の上面周辺部にはアルミニウムなどからなる複数の接続パッド２５が設けられ、接続パッド２５の中央部を除くシリコン基板２４の上面には酸化シリコンなどからなる絶縁膜２６が設けられている。
【００１６】
シリコン基板２４上に接続パッド２５および絶縁膜２６を設けてなるものは、通常、ウエハ状態の半導体基板をダイシングして個々のチップとなした場合に得られるものである。しかしながら、この発明では、ウエハ状態の半導体基板上に接続パッド２５および絶縁膜２６が形成された状態では、ダイシングを行わず、以下に説明するように、再配線を有する半導体構成体２３が得られる状態でウエハ状態の半導体基板をダイシングする。まず、半導体構成体２３の構成について説明する。
【００１７】
シリコン基板２４上に形成された絶縁膜２６上にはポリイミドなどからなる保護膜２７が設けられている。接続パッド２５の中央部は、絶縁膜２６および保護膜２７に形成された開口部２８を介して露出されている。開口部２８を介して露出された接続パッド２５の上面から保護膜２７の上面の所定の箇所にかけて銅からなる下地金属層３１ａが設けられている。下地金属層３１ａの上面には銅からなる上層金属層３１ｂが設けられており、下地金属層３１ａおよび上層金属層３１ｂにより再配線３２が構成される。
【００１８】
再配線３２のパッド部上面には銅からなる柱状電極３３が設けられている。再配線３２を含む保護膜２７の上面にはエポキシ系樹脂からなる封止膜（絶縁膜）３４がその上面が柱状電極３３の上面と面一となるように設けられている。このように、半導体構成体２３は、シリコン基板２４、接続パッド２５、絶縁膜２６を含み、さらに、保護膜２７、再配線３２、柱状電極３３、封止膜３４を含んで構成されている。
【００１９】
半導体構成体２３の周囲における接着層２２の上面にはエポキシ系樹脂からなる封止膜（絶縁膜）３５がその上面が封止膜３４の上面と面一となるように設けられている。両封止膜３４、３５および柱状電極３３の上面には感光性ポリイミドなどからなる第１の上層絶縁膜３６が設けられている。第１の上層絶縁膜３６の柱状電極３３の上面中央部に対応する部分には開口部３７が設けられている。開口部３７を介して露出された柱状電極３３の上面から第１の上層絶縁膜３６の上面の所定の箇所にかけて第１の下地金属層３８ａおよび該第１の下地金属層３８ａ上に設けられた第１の上層金属層３８ｂからなる第１の上層再配線３９が設けられている。
【００２０】
第１の上層再配線３９を含む第１の上層絶縁膜３６の上面全体には感光性ポリイミドなどからなる第２の上層絶縁膜４１が設けられている。第２の上層絶縁膜４１の第１の上層再配線３９の接続パッド部に対応する部分には開口部４２が設けられている。開口部４２を介して露出された第１の上層再配線３９の接続パッド部の上面から第２の上層絶縁膜４１の上面の所定の箇所にかけて第２の下地金属層４３ａおよびおよび該第２の下地金属層４３ａ上に設けられた第２の上層金属層４３ｂからなる第２の上層再配線４４が設けられている。
【００２１】
第２の上層再配線４４を含む第２の上層絶縁膜４１の上面全体には感光性ポリイミドなどからなる第３の上層絶縁膜４５が設けられている。第３の上層絶縁膜４５の第２の上層再配線４４の接続パッド部に対応する部分には開口部４６が設けられている。開口部４６内およびその上方には半田ボール（突起状の接続端子）４７が第２の上層再配線４４の接続パッド部に接続されて設けられている。複数の半田ボール４７は、第３の上層絶縁膜４５上にマトリクス状に配置されている。
【００２２】
ところで、ベース板２１のサイズを半導体構成体２３のサイズよりもやや大きくしているのは、シリコン基板２４上の接続パッド２５の数の増加に応じて、半田ボール４７の配置領域を半導体構成体２３のサイズよりもやや大きくし、これにより、接続パッド２５のサイズおよび配置間隔を柱状電極３３のサイズおよび配置間隔よりも大きくするためである。
【００２３】
このため、マトリクス状に配置された第２の上層再配線４４の接続パッド部（第３の上層絶縁膜４５の開口部４６内の部分）は、半導体構成体２３に対応する領域のみでなく、半導体構成体２３の周側面に設けられた絶縁膜３５の領域上にも配置されている。つまり、マトリクス状に配置された半田ボール４７のうち、少なくとも最外周の半田ボール４７は半導体構成体２３よりも外側に位置する周囲に配置されている。
【００２４】
この場合、変形例として、第２の上層再配線４４の接続パッド部を全て半導体構成体２３よりも外側に位置する周囲に配置するようにしてもよい。また、上層の再配線を１層として、つまり第１の再配線３９のみとして、少なくとも、最外周の接続パッド部を半導体構成体２３よりも外側に位置する周囲に配置することもできる。
【００２５】
このように、この発明は、シリコン基板２４上に、接続パッド２５、絶縁膜２６を有するのみでなく、保護膜２７、再配線３２、柱状電極３３、封止膜３４などをも形成した半導体構成体２３に、上面を覆う第１の上層絶縁膜３６および該第１の上層絶縁膜３６上に形成された開口部３７を介して柱状電極３３に接続される第１の上層再配線３９、および周側面を覆う封止膜３５を設ける構成を特徴としている。
【００２６】
通常、シリコン基板と回路基板の熱膨張係数の相違に起因して柱状電極に作用する応力を緩和するため、柱状電極の高さは１００〜２００μｍ必要であるが、上記の如く、この発明では、柱状電極３３上に第１の上層再配線３９および該第１の上層絶縁膜３６が形成されており、該第１の上層再配線３９および第１の上層絶縁膜３６が応力を緩和する作用を有するので、柱状電極３３の高さを５０〜１００μｍ程度と低いものにすることができる。勿論、柱状電極３３の高さを大きくするほど、応力緩和作用が大きくなるので、ボンディングする回路基板によっては、従来と同様の高さとしても差し支えない。
【００２７】
次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、図１に示すベース板２１を複数枚採取することができるベース板２１の上面全体に接着層２２が設けられたものを用意する。そして、接着層２２の上面の所定の複数箇所にそれぞれ半導体構成体２３のシリコン基板２４の下面を接着する。
【００２８】
半導体構成体２３は、上述の如く、ＣＳＰと呼ばれるものであり、予め製造されている。ここで、半導体構成体２３の製造方法の一例について簡単に説明する。まず、ウエハ状態の半導体基板（切断前のシリコン基板２４）上に接続パッド２５、絶縁膜２６および保護膜２７が設けられたものを用意する。次に、開口部２８を介して露出された接続パッド２５の上面を含む保護膜２７の上面全体に下地金属層３１ａを形成する。
【００２９】
次に、下地金属層３１ａの上面の所定の箇所に電解メッキにより上層金属層３１ｂを形成する。次に、再配線３２の接続パッド部上面に電解メッキにより柱状電極３３を形成する。次に、柱状電極３３および上層金属層３１ｂをマスクとして下地金属層３１ａの不要な部分をエッチングにより除去し、上層金属層３１ｂ下にのみ下地金属層３１ａを残存させ、該残存した下地金属層３１ａおよびこの下地金属層３１ａ上全面に形成された上層金属層３１ｂからなる再配線３２を形成する。
【００３０】
次に、柱状電極３３および再配線３２を含む保護膜２７の上面全体に封止膜３４をその厚さが柱状電極３３の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極３３の上面は封止膜３４によって覆われている。次に、封止膜３４および柱状電極３３の上面側を適宜に研磨し、柱状電極３３の上面を露出させる。次に、ダンシング工程を経ると、図２に示す半導体構成体２３が複数個得られる。
【００３１】
さて、図２に示すように、接着層２２の上面の所定の複数箇所にそれぞれ半導体構成体２３のシリコン基板２４の下面を接着したら、次に、図３に示すように、複数の半導体構成体２３を含む接着層２２の上面にポリイミドやエポキシ系樹脂などからなる封止膜３５を印刷によりその厚さが半導体構成体２３の高さよりもやや厚くなるように形成する。したがって、この状態では、半導体構成体２３の上面は封止膜３５によって覆われている。次に、封止膜３５および半導体構成体２３の上面側を適宜に研磨することにより、図４に示すように、柱状電極３３の上面を露出させる。
【００３２】
ここで、図２に示す半導体構成体２３を製造する場合も、上述の如く、柱状電極３３および再配線３２を含む保護膜２７の上面に封止膜３４をその厚さが柱状電極３３の高さよりもやや厚くなるように形成し、次いで封止膜３４および柱状電極３３の上面側を適宜に研磨することにより、柱状電極３３の上面を露出させている。したがって、研磨工程は２回となる。
【００３３】
そこで、次に、研磨工程を１回とすることができる場合について説明する。図２に示す状態において、半導体構成体２３として封止膜３４を備えていないものを用意する。つまり、接続パッド２５および絶縁膜２６が形成されたウエハ状態の半導体基板上に保護膜２７、再配線３２、柱状電極３３を形成した後、封止膜３４を形成することなく、これをダイシングする。
【００３４】
そして、図３に示す工程において、封止膜３４、３５を形成すべき領域に同一の封止材料によって同時に封止膜３４、３５を形成し、該封止膜３４、３５（但し、封止膜は一体化されており境界はない）と共に柱状電極３３の上面側を研磨すればよい。つまり、封止膜形成工程を１回とすることにより、研磨工程は１回とすることができる。
【００３５】
ただし、研磨工程を１回とする場合には、図２に示す状態における半導体構成体２３の柱状電極３３の高さに電解メッキによる形成に伴うばらつきが生じるのに対し、研磨工程を２回とする場合には、図２に示す状態における半導体構成体２３の高さが均一となり、図２に示す状態における半導体構成体２３の高さを予め揃えておくことができる。
【００３６】
さて、図４に示す研磨工程が終了したら、次に、図５に示すように、面一となった両封止膜３４、３５および柱状電極３３の上面に第１の上層絶縁膜３６を形成する。この第１の上層絶縁膜３６は、感光性ポリイミド、感光性ポリベンザオキサゾール、感光性エポキシ樹脂、感光性ノボラック樹脂、感光性アクリル系かカルゾ樹脂などからなり、ドライフィルム化されている。したがって、このドライフィルム化されたものをラミネータによりラミネートすると、第１の上層絶縁膜３６が形成される。なお、後述する第２および第３の上層絶縁膜４１、４５の場合も同様であるが、印刷などの塗布法により形成するようにしてもよい。
【００３７】
次に、第１の上層絶縁膜３６の柱状電極３３の上面中央部に対応する部分に、フォトリソグラフィにより、開口部３７を形成する。次に、図６に示すように、開口部３７を介して露出された柱状電極３３の上面を含む第１の上層絶縁膜３６の上面全体に第１の下地金属層３８ａを形成する。この場合、第１の下地金属層３８ａは、無電解メッキにより形成された銅層のみからなっているが、スパッタにより形成された銅層のみであってもよく、またスパッタにより形成されたチタンなどの薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する第２の下地金属層４３ａの場合も同様である。
【００３８】
次に、第１の下地金属層３８ａの上面にメッキレジスト膜５１をパターン形成する。この場合、第１の上層再配線３９形成領域に対応する部分におけるメッキレジスト膜５１には開口部５２が形成されている。次に、第１の下地金属層３８ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜５１の開口部５２内の第１の下地金属層３８ａの上面に第１の上層金属層３８ｂ第１の上層再配線３９を形成する。図１および図６において、第１の上層絶縁膜３６の開口部３７内には第１の下地金属層３８ａのみが形成されているが、これは図示の都合上であって、実際には、第１の上層金属層３８ｂも形成される。
【００３９】
ここで、第１の上層再配線３９は柱状電極３３上にメッキにより直接接合されるものであるため、第１の上層絶縁膜３６の開口部３７は、１０μｍ×１０μｍの方形または同面積の円形の面積を有していれば強度的に十分である。この種の露光機は数μｍの位置合わせ精度を有しており、通常、柱状電極３３の直径は１００〜１５０μｍ程度（ピッチは、通常、この２倍）であるので、従来の、柱状電極と再配線の接合をボンディングによる方法と比較すると、柱状電極のサイズおよび配置間隔が遙かに小さい場合にも適用でき、且つ、プロセスも効率的である。
【００４０】
このように、この発明の方法によれば、柱状電極に上層の再配線を接合するための絶縁膜の開口部の幅を柱状電極の幅の１／２以下とすることが可能であり、これにより半導体構成体の柱状電極のサイズおよび配置間隔も小さいものとすることができるので、上層の再配線を有する本発明の半導体装置のサイズを一層小さいものとすることができる。
【００４１】
次に、メッキレジスト膜５１を剥離し、次いで、第１の上層金属層３８ｂをマスクとして第１の下地金属層３８ａの不要な部分をエッチングして除去すると、図７に示すように、第１の下地金属層３８ａおよび第１の上層金属層３８ｂからなる第１の上層再配線３９が形成される。
【００４２】
次に、図８に示すように、第１の上層再配線３９を含む第１の上層絶縁膜３６の上面全体に感光性ポリイミドなどからなる第２の上層絶縁膜４１をパターン形成する。この場合、第２の上層絶縁膜４１の第１の上層再配線３９の接続パッド部に対応する部分には開口部４２が形成されている。次に、開口部４２を介して露出された第１の上層再配線３９の接続パッド部を含む第２の上層絶縁膜４１の上面全体に第２の下地金属層４３ａを無電解メッキにより形成する。
【００４３】
次に、第２の下地金属層４３ａの上面にメッキレジスト膜５３をパターン形成する。この場合、第２の上層再配線４４形成領域に対応する部分におけるメッキレジスト膜５３には開口部５４が形成されている。次に、第２の下地金属層４３ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜５３の開口部５４内の第２の下地金属層４３ａの上面に第２の上層金属層４３ｂを形成する。
【００４４】
次に、メッキレジスト膜５３を剥離し、次いで、第２の上層再配線４４をマスクとして第２の下地金属層４３の不要な部分をエッチングして除去すると、図９に示すように、第２の下地金属層４３および第２の上層金属層４３ｂからなる第２の上層再配線４４が形成される。
【００４５】
次に、図１０に示すように、第２の上層再配線４４を含む第２の上層絶縁膜４１の上面全体に感光性ポリイミドなどからなる第３の上層絶縁膜４５をパターン形成する。この場合、第３の上層絶縁膜４５の第２の上層再配線４４の接続パッド部に対応する部分には開口部４６が形成されている。次に、開口部４６内およびその上方に半田ボール４７を第２の上層再配線４４の接続パッド部に接続させて形成する。
【００４６】
次に、図１１に示すように、互いに隣接する半導体構成体２３間において、３層の絶縁膜４５、４１、３６、封止膜３５、接着層２２およびベース板２１を切断すると、図１に示す半導体装置が複数個得られる。
【００４７】
このようにして得られた半導体装置では、半導体構成体２３の柱状電極３３に接続される第１の下地金属層３８および第１の上層再配線３９を無電解メッキ（またはスパッタ）および電解メッキにより形成し、第１の上層再配線３９の接続パッド部に接続される第２の下地金属層４３および第２の上層再配線４４を無電解メッキ（またはスパッタ）および電解メッキにより形成しているので、ボンディングによらないで、半導体構成体２３の柱状電極３３と第１の上層再配線３９との間および第１の上層再配線３９と第２の上層再配線４４との間を導電接続することができる。
【００４８】
また、上記製造方法では、ベース板２１上の接着層２２上の所定の複数箇所にそれぞれ半導体構成体２３を接着して配置し、複数の半導体構成体２３に対して第１〜第３の上層絶縁膜３６、４１、４５、第１、第２の下地金属層３８、４３、第１、第２の上層再配線３９、４４および半田ボール４７の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。
【００４９】
また、ベース板２１と共に複数の半導体構成体２３を搬送することができるので、これによっても製造工程を簡略化することができる。さらに、ベース板２１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。
【００５０】
さらに、上記製造方法では、図２に示すように、再配線３２および柱状電極３３を備えたＣＳＰタイプの半導体構成体２３を接着層２２上に接着しているので、例えば、シリコン基板２４上に接続パッド２５、絶縁膜２６および保護膜２７を設けてなる通常の半導体チップを接着層２２上に接着して、半導体チップの周囲に設けられた封止膜上に再配線および柱状電極を形成する場合と比較して、コストを低減することができる。
【００５１】
例えば、切断前のベース板２１がシリコンウエハのように一定のサイズのほぼ円形状である場合、接着層２２上に接着された半導体チップの周囲に設けられた封止膜上に再配線および柱状電極を形成すると、処理面積が増大する。換言すれば、低密度処理になるため、一回当たりの処理枚数が低減し、スループットが低下するので、コストアップとなる。
【００５２】
これに対し、上記製造方法では、再配線３２および柱状電極３３を備えたＣＳＰタイプの半導体構成体２３を接着層２２上に接着した後に、ビルドアップしているので、プロセス数は増大するが、柱状電極３３を形成するまでは高密度処理のため、効率が良く、プロセス数の増大を考慮しても、全体の価格を低減することができる。
【００５３】
次に、図１に示す半導体装置の製造方法の他の例について説明する。まず、図１２に示すように、紫外線透過性の透明樹脂板やガラス板などからなる別のベース板５５の上面全体に紫外線硬化型の粘着シートなどからなる接着層５６を接着し、接着層５６の上面に上述のベース板２１および接着層２２を接着したものを用意する。
【００５４】
そして、図２〜図１０にそれぞれ示す製造工程を経た後に、図１３に示すように、３層の絶縁膜４５、４１、３６、封止膜３５、接着層２２、ベース板２１および接着層５６を切断し、別のベース板５５を切断しない。次に、別のベース板５５の下面側から紫外線を照射し、接着層５６を硬化させる。すると、分断されたベース板２１の下面に対する接着層５６による接着性が低下する。そこで、接着層５６上に存在する個片化されたものを１つずつ剥がしてピックアップすると、図１に示す半導体装置が複数個得られる。
【００５５】
この製造方法では、図１３に示す状態において、接着層５６上に存在する個片化された半導体装置がバラバラとならないので、専用の半導体装置載置用トレーを用いることなく、そのまま、図示しない回路基板上への実装時に１つずつ剥がしてピックアップすることができる。また、別のベース板５５の上面に残存する接着性が低下した接着層５６を剥離すると、別のベース板５５を再利用することができる。さらに、別のベース板５５の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。
【００５６】
なお、別のベース板５５として、膨張させることにより半導体装置を取り外す、通常のダイシングテープなどを用いることも可能であり、その場合には、接着層は紫外線硬化型でなくてもよい。また、別のベース板５５を研磨やエッチングにより除去するようにしてもよい。
【００５７】
次に、図１に示す半導体装置の製造方法のさらに他の例について説明する。この製造方法では、図５に示す工程後に、図１４に示すように、開口部３７を介して露出された柱状電極３３の上面を含む第１の上層絶縁膜３６の上面全体に銅の無電解メッキにより第１の下地金属層３８ａを形成する。次に、第１の下地金属層３８ａをメッキ電流路として銅の電解メッキを行うことにより、第１の下地金属層３８ａの上面全体に第１の上層金属形成用層３８ｃを形成する。次に、第１の上層金属形成用層３８ｃの上面の第１の上層再配線形成領域に対応する部分にレジスト膜５７をパターン形成する。
【００５８】
次に、レジスト膜５７をマスクとして第１の上層金属形成用層３８ｃおよび第１の下地金属層３８ａの不要な部分をエッチングして除去すると、図１５に示すように、レジスト膜５７下にのみ第１の上層配線層３９が残存される。この後、レジスト膜５７を剥離する。なお、これと同様の形成方法により、第２の上層再配線４４を形成するようにしてもよい。
【００５９】
ところで、図２に示すベース板２１あるいは図１２に示す別のベース板５５をトレイ状とすることもできる。つまり、ベース板を、半導体構成体２３を配列する領域が周囲より陥没した受け皿のような形状とする。そして、このトレイ状のベース板の半導体構成体２３配列領域を囲む周囲の上面にメッキ電流路用金属層を設け、このメッキ電流路用金属層とメッキ電流路用の下地金属層（３８、４３）とを導電部材で接続して、電解メッキを行うようにしてもよい。この場合、トレイの外形サイズを同一としておくことにより、製造する半導体装置のサイズが異なる場合でも、同一の製造装置の使用が可能となり効率的となる。
【００６０】
（第２実施形態）
図３に示す製造工程において、接着層２２を半導体構成体２３のシリコン基板２４の下面に設け、この接着層２２をベース板２１の上面の各所定の箇所に接着した場合には、図１６に示すこの発明の第２実施形態としての半導体装置が得られる。
【００６１】
このようにして得られた半導体装置では、シリコン基板２４の下面が接着層２２を介してベース板２１の上面に接着されているほかに、シリコン基板２４の側面などが封止膜３６を介してベース板２１の上面に接続されているので、半導体構成体２３のベース板２１に対する接合強度をある程度強くすることができる。
【００６２】
（第３、第４実施形態）
図１７はこの発明の第３実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、ベース板２１および接着層２２を備えていないことである。
【００６３】
この第３実施形態の半導体装置を製造する場合には、例えば図１０に示すように、半田ボール４７を形成した後に、ベース板２１を接着層２２から剥がしたりまたはベース板２１および接着層２２を研磨やエッチングなどにより除去するなどして取り除いた後に、互いに隣接する半導体構成体２３間において、３層の絶縁膜４５、４１、３６および封止膜３５を切断すると、図１７に示す半導体装置が複数個得られる。このようにして得られた半導体装置では、ベース板２１および接着層２２を備えていないので、その分だけ、薄型化することができる。
【００６４】
また、ベース板２１および接着層２２を研磨やエッチングなどにより除去した後に、シリコン基板２４および封止膜３５の下面側を適宜に研磨し、次いで互いに隣接する半導体構成体２３間において、３層の絶縁膜４５、４１、３６および封止膜３５を切断すると、図１８に示すこの発明の第４実施形態としての半導体装置が複数個得られる。このようにして得られた半導体装置では、さらに薄型化することができる。
【００６５】
なお、半田ボール４７を形成する前に、ベース板２１および接着層２２を研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４および封止膜３５の下面側を適宜に研磨し）、次いで半田ボール４７を形成し、次いで互いに隣接する半導体構成体２３間において、３層の絶縁膜４５、４１、３６および封止膜３５を切断するようにしてもよい。
【００６６】
（第５実施形態）
図１９はこの発明の第５実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、接着層２２の下面に放熱用の金属層６１が接着されていることである。金属層６１は、厚さ数十μｍの銅箔などからなっている。
【００６７】
この第５実施形態の半導体装置を製造する場合には、例えば図１０に示すように、半田ボール４７を形成した後に、ベース板２１を研磨やエッチングなどにより除去し、次いで接着層２２の下面全体に金属層６１を接着し、次いで互いに隣接する半導体構成体２３間において、３層の絶縁膜４５、４１、３６、封止膜３５、接着層２２および金属層６１を切断すると、図１９に示す半導体装置が複数個得られる。
【００６８】
なお、接着層２２も研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４および封止膜３５の下面側を適宜に研磨し）、シリコン基板２４および封止膜３５の下面に新たな接着層を介して金属層６１を接着するようにしてもよい。
【００６９】
（第６実施形態）
図１１に示す場合には、互いに隣接する半導体構成体２３間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２３を１組として切断し、例えば、図２０に示すこの発明の第６実施形態のように、３個の半導体構成体２３を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、３個で１組の半導体構成体２３は同種、異種のいずれであってもよい。
【００７０】
なお、図２０では、再配線３２、３９、４４下の下地金属層は、図示の都合上、省略している。また、第２の上層再配線４４の接続パッド部（半田ボール４７）が半導体構成体２３の周囲における封止膜３５上に配置されているか否か不明であるが、これは図示の都合上であり、実際には封止膜３５上に配置されている。このようなことは、後述する実施形態においても同様である。
【００７１】
ただし、例えば、図２０では、半導体構成体２３を接着層２２の上面に接着しているので、従来のようなボンディングと異なり、接着する際の位置合わせとしては高い精度は要求されず、したがって半導体構成体２３の配置間隔を可及的に小さくすることが可能となる。そこで、半導体構成体２３の配置間隔を可及的に小さくした場合には、第２の上層再配線４４の少なくとも一部が封止膜３５上に配置されるようにしてもよい。
【００７２】
（第７実施形態）
図２０に示す場合には、第２の上層再配線４４の接続パッド部上に半田ボール４７のみを設けているが、これに限らず、例えば、図２１に示すこの発明の第７実施形態のように、第２の上層再配線４４の接続パッド部上に接続パッド６２を形成し、その上に半田ボール４７、ＬＳＩなどからなる半導体チップ６３、コンデンサや抵抗などからなるチップ部品６４を設けるようにしてもよい。
【００７３】
この場合、半導体チップ６３およびチップ部品６４は第３の上層絶縁膜４５の上面中央部に配置され、半田ボール４７は第３の上層絶縁膜４５の上面周辺部に配置されている。半導体チップ６３は、チップ本体６３ａの下面周辺部に複数のバンプ電極６３ｂが設けられた構造となっている。そして、半導体チップ６３のバンプ電極６３ｂは接続パッド６２に半田（図示せず）を介して導電接続されている。また、チップ本体６３ａと第３の上層絶縁膜４５との間には封止材６５が充填されている。チップ部品６４の両側の電極は接続パッド６２上に半田６６で接続されている。
【００７４】
（第８実施形態）
図２１では、３個の半導体構成体２３を１組としたものの中央部上にチップ部品６４などを搭載し、周辺部上に半田ボール４７を形成しているが、これに限らず、例えば図２２に示すこの発明の第８実施形態のように、１個の半導体構成体２３の周囲における封止膜３５のサイズをある程度大きくし、第３の上層絶縁膜４５の中央部上に配置された接続パッド６２上にチップ部品６４などを搭載し、周辺部上に配置された接続パッド６２上に接続ピン６７の下部を半田（図示せず）を介して接続するようにしてもよい。この接続ピン６７は、接続パッド６２に半田付けされており、図示はしないが、回路基板に形成されたスルーホール内に挿入され、裏面側でスルーホールの周囲に形成されたパッド部に半田付けされるものである。
【００７５】
（第９実施形態）
図２３はこの発明の第９実施形態としての半導体装置の断面図を示したものである。次に、この半導体装置の構造についてその製造方法と併せ説明する。まず、図２０を参照して説明すると、図２０において、半田ボール４７を形成せず、ベース板２１を除去してなるものを用意する。以下、この用意したものを半導体ブロック７１という。
【００７６】
次に、半導体ブロック７１の接着層２２の下面に、半導体ブロック７１よりもある程度大きめの放熱用の金属板７２の上面中央部を接着する。次に、半導体ブロック７１の周囲における金属板７２の上面に封止膜７３をモールド法や印刷法によりその上面が半導体ブロック７１の第３の上層絶縁膜４５の上面と面一となるように形成する。なお、接着層２２を除去し、モールド用の金型内に金属板７２を配置し、その上面中央部に半導体ブロック７１を配置するようにしてもよい。
【００７７】
次に、第３の上層絶縁膜４５および封止膜７３の上面に第３の上層再配線（第３の下地金属層を含む）７４を第２の上層再配線４４の接続パッド部に接続させて形成する。次に、第３の上層再配線７４を含む第３の上層絶縁膜４５の上面に第４の上層絶縁膜７５を形成する。次に、第４の上層絶縁膜７５の第３の上層再配線７４の接続パッド部に対応する部分に開口部７６を形成する。次に、開口部７６内およびその周囲における第４の上層絶縁膜７５上に接続パッド７７を第３の上層再配線７４の接続パッド部に接続させて形成する。
【００７８】
次に、半導体ブロック７１上における接続パッド７７の上面にコンデンサや抵抗などからなるチップ部品７８の両側の電極を半田７９を介して接続する。また、封止膜７３上における接続パッド７７の上面に接続ピン８０の下部を半田（図示せず）を介して接続する。かくして、図２３に示す半導体装置が得られる。
【００７９】
（第１０実施形態）
図２４はこの発明の第１０実施形態としての半導体装置の断面図を示したものである。次に、この半導体装置の構造についてその製造方法と併せ説明する。まず、この場合も、図２０を参照して説明すると、図２０において、半田ボール４７を形成せず、ベース板２１および接着層２２を除去してなるものを用意する。以下、この用意したものを半導体ブロック８１という。ただし、第２の上層再配線（第２の下地金属層を含む）４４の配置は、図示の都合上、図２０と図２４とでは異なっている。また、図２４では、第３の上層絶縁膜４５の上面の各所定の箇所に接続パッド８２が第２の上層再配線４４の接続パッド部に接続されて形成されている。
【００８０】
次に、フレキシブル配線板８３を用意する。このフレキシブル配線板８３は、中央部に半導体ブロック８１よりもやや大きめの開口部８４を有するフィルム基板８５を備えている。フィルム基板８５の上面には配線８６が設けられている。配線８６の一端部は開口部８４内に突出され、接続端子８６ａとなっている。配線８６を含むフィルム基板８５の上面には保護膜８７が設けられている。保護膜８７の配線８６の他端部に対応する部分には開口部８８が設けられている。開口部８８を介して露出された配線８６の他端部上には半田ボール８９が設けられているが、フレキシブル配線板８３を用意した時点では半田ボール８９は形成されていない。
【００８１】
そして、フレキシブル配線板８３の接続端子８６ａを半導体ブロック８１上の周辺部に配置された接続パッド８２に半田（図示せず）を介して接続する。次に、半導体ブロック８１の周囲におけるフレキシブル配線板８３の下面に封止膜９０をモールド法や印刷法によりその下面が半導体ブロック７１のシリコン基板２４などの下面と面一となるように形成する。次に、半導体ブロック７１のシリコン基板２４などの下面および封止膜９０の下面に接着層９１を介して放熱用の金属板９２を接着する。
【００８２】
次に、半導体ブロック８１上の中央部に配置された接続パッド８２の上面にコンデンサや抵抗などからなるチップ部品９３の両側の電極を半田９４を介して接続する。また、フレキシブル配線板８３の開口部８８を介して露出された配線８６の他端部上に半田ボール８９を形成する。かくして、図２４に示す半導体装置が得られる。
【００８３】
（第１１実施形態）
なお、図２４に示す場合において、図２５に示すこの発明の第１０実施形態のように、周辺部の封止膜９０の厚さが半導体ブロック８１の周面近傍の封止膜９０の厚さよりも薄くなるようにしてもよい。この場合、封止膜９０はモールド法により形成する。
【００８４】
（第１２実施形態）
図２６はこの発明の第１２実施形態としての半導体装置の断面図を示したものである。次に、この半導体装置の構造についてその製造方法と併せ説明する。まず、この場合も、図２０を参照して説明すると、図２０において、ベース板２１および接着層２２を除去してなるものを用意する。以下、この用意したものを半導体ブロック１０１という。この場合、半田ボール４７は形成されているが、図２０に示す場合よりも径がやや小さい半田ボール（４７Ａ）が形成されている。
【００８５】
次に、フレキシブル配線板１０２を用意する。このフレキシブル配線板１０２は、半導体ブロック８１よりもある程度大きめのフィルム基板１０３を備えている。フィルム基板１０３の上面には配線１０４が設けられている。フィルム基板１０３の配線１０４の一端部に対応する部分にはスルーホール１０４が設けられている。配線１０４を含むフィルム基板１０３の上面には保護膜１０６が設けられている。保護膜１０６の配線１０４の他端部に対応する部分には開口部１０７が設けられている。開口部１０７を介して露出された配線１０６の他端部上には半田ボール１０８が設けられているが、フレキシブル配線板１０２を用意した時点では半田ボール１０８は形成されていない。
【００８６】
そして、半導体ブロック１０１の半田ボール（４７Ａ）をフレキシブル配線板１０２のスルーホール１０５内に挿入し、リフロー処理により、半田４７Ａをスルーホール１０５内の配線１０４の一端部下面に接続させる。次に、半導体ブロック１０１の周囲におけるフレキシブル配線板１０２の下面に封止膜１０９をモールド法や印刷法によりその下面が半導体ブロック１０１のシリコン基板２４などの下面と面一となるように形成する。
【００８７】
次に、半導体ブロック１０１のシリコン基板２４などの下面および封止膜１０９の下面に接着層１１０を介して放熱用の金属板１１１を接着する。次に、フレキシブル配線板８１０２の開口部１０７を介して露出された配線１０４の他端部上に半田ボール１０８を形成する。かくして、図２６に示す半導体装置が得られる。
【００８８】
（第１３実施形態）
図２７はこの発明の第１３実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図２０に示す半導体装置と大きく異なる点は、半田ボール４７を１つも備えておらず、その代わりに、フレキシブル配線板１２１を備えていることである。
【００８９】
この場合のフレキシブル配線板１２１は、フィルム基板１２２の一面に配線１２３が設けられ、配線１２３の両端部からなる接続端子１２３ａ（他方は図示せず）を除く部分を含むフィルム基板１２２の一面に保護膜１２４が設けられた構造となっている。一方、第３の上層絶縁膜４５の上面の一端部には複数の接続端子１２５が所定の第２の上層再配線４４の接続パッド部に接続されて形成されている。そして、フレキシブル配線板１２１の一方の接続端子１２３ａは接続端子１２５に図示しない異方性導電接着剤または半田を介して接続されている。
【００９０】
また、残りの第２の上層再配線４４の接続パッド部上には接続パッド１２６が形成され、その上にはコンデンサや抵抗などからなるチップ部品１２７、ＣＳＰタイプの半導体構成体１２８が搭載されている。この場合、半導体構成体１２８は半導体構成体２３とほぼ同じような構造となっている。そして、半導体構成体１２８の柱状電極１２９の下面は接続パッド１２６の上面に半田（図示せず）を介して接続されている。
【００９１】
（第１４実施形態）
図２８はこの発明の第１４実施形態としての半導体装置の断面図を示したものである。この半導体装置では、例えば図２０に示すものにおいてベース板２１を除去したものからなる半導体ブロック１３１と、例えば図２１に示すものにおいてベース板２１および接着層２２を除去し且つ半田ボール４７を形成しないものからなる半導体ブロック１３２とが接着層２２を介して接着されている。この場合、上側の半導体ブロック１３２上には複数の半導体チップ６３のみが搭載されている。
【００９２】
また、両半導体ブロック１３１は、例えば図２３に示す場合とほぼ同じフレキシブル配線板１２１を介して互いに接続されている。すなわち、上側の半導体ブロック１３２の第３の上層絶縁膜４５の上面の一端部には複数の接続端子１２５が所定の第２の上層再配線４４Ａの接続パッド部に接続されて形成されている。そして、フレキシブル配線板１２１の一方の接続端子１２３ａは接続端子１２５に図示しない異方性導電接着剤または半田を介して接続されている。
【００９３】
また、下側の半導体ブロック１３１の第３の上層絶縁膜４５の下面の一端部には所定の第２の上層再配線４４Ｂからなる接続端子が設けられている。そして、フレキシブル配線板１２１の他方の接続端子１２３ｂは所定の第２の上層再配線４４Ｂからなる接続端子に異方性導電接着剤（または半田）１３３を介して接続されている。
【００９４】
（第１５実施形態）
図２９はこの発明の第１５実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図２８に示す場合と大きく異なる点は、フレキシブル配線板１２１を長くして下側の半導体ブロック１３１の第３の上層絶縁膜４５の下面に接着層１５１を介して接着したことである。
【００９５】
この場合、半田ボール４７は、接着層１５１、保護膜１２４およびフィルム基板１２２に形成された開口部１５２を介してフィルム基板１２２の外側に突出されている。また、フレキシブル配線板１２１の他方の接続端子１２３ｂは、他方の半導体ブロック１３１の両端部の所定の第２の上層再配線４４Ｂからなる接続端子に、接着層１５１および保護膜１２４に形成された開口部１５３内に配置された半田１５４を介して接続されている。
【００９６】
【発明の効果】
以上説明したように、この発明によれば、半導体基板上に再配線および柱状電極を有する複数または複数組の半導体構成体をベース板上に配置し、半導体構成体を含むベース板の上面全体に絶縁膜を形成し、絶縁膜の上面に上層再配線を半導体構成体の柱状電極に接続させて形成し、絶縁膜を少なくとも切断することにより、半導体構成体を１つまたは１組有し、その周囲に絶縁膜を有するとともに、周囲の絶縁膜上に上層再配線の一部が配置されてなる半導体装置を複数個一括して得ることができ、従来のようなボンディング工程がなく、したがってボンディングによることなく外部接続電極の配置間隔を大きくすることができ、また複数または複数組の半導体構成体に対して絶縁膜および上層再配線の形成を一括して行うことができるので、製造工程を簡略化することができる。
【図面の簡単な説明】
【図１】この発明の第１実施形態としての半導体装置の断面図。
【図２】図１に示す半導体装置の製造方法の一例において、当初の製造工程の断面図。
【図３】図２に続く製造工程の断面図。
【図４】図３に続く製造工程の断面図。
【図５】図４に続く製造工程の断面図。
【図６】図５に続く製造工程の断面図。
【図７】図６に続く製造工程の断面図。
【図８】図７に続く製造工程の断面図。
【図９】図８に続く製造工程の断面図。
【図１０】図９に続く製造工程の断面図。
【図１１】図１０に続く製造工程の断面図。
【図１２】図１に示す半導体装置の製造方法の他の例において、当初用意したものの断面図。
【図１３】同他の例において、所定の製造工程の断面図。
【図１４】図１に示す半導体装置の製造方法のさらに他の例において、所定の製造工程の断面図。
【図１５】図１４に続く製造工程の断面図。
【図１６】この発明の第２実施形態としての半導体装置の断面図。
【図１７】この発明の第３実施形態としての半導体装置の断面図。
【図１８】この発明の第４実施形態としての半導体装置の断面図。
【図１９】この発明の第５実施形態としての半導体装置の断面図。
【図２０】この発明の第６実施形態としての半導体装置の断面図。
【図２１】この発明の第７実施形態としての半導体装置の断面図。
【図２２】この発明の第８実施形態としての半導体装置の断面図。
【図２３】この発明の第９実施形態としての半導体装置の断面図。
【図２４】この発明の第１０実施形態としての半導体装置の断面図。
【図２５】この発明の第１１実施形態としての半導体装置の断面図。
【図２６】この発明の第１２実施形態としての半導体装置の断面図。
【図２７】この発明の第１３実施形態としての半導体装置の断面図。
【図２８】この発明の第１４実施形態としての半導体装置の断面図。
【図２９】この発明の第１５実施形態としての半導体装置の断面図。
【図３０】従来の半導体装置の一例の断面図。
【符号の説明】
２１　ベース板
２２　接着層
２３　半導体構成体
２４　シリコン基板
２５　接続パッド
３１　下地金属層
３２　再配線
３３　柱状電極
３４　封止膜
３５　封止膜
３６　第１の上層絶縁膜
３８　第１の下地金属層
３９　第１の上層再配線
４１　第２の上層絶縁膜
４３　第２の下地金属層
４４　第２の上層再配線
４５　第３の上層絶縁膜
４７　半田ボール[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
For example, in a semiconductor device called a BGA (ball grid array), a semiconductor chip composed of an LSI or the like is mounted on the center of the upper surface of a relay substrate (interposer) slightly larger than the size of the semiconductor chip, and is mounted on the lower surface of the relay substrate. There is one in which connection terminals using solder balls are arranged in a matrix. Here, when bonding the external connection electrodes formed on the semiconductor chip to another circuit board, the relay board has a sufficiently large size and pitch by rewiring in order to obtain connection strength and reliability. Used for
[0003]
FIG. 30 is a sectional view showing an example of such a conventional semiconductor device. The semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 made of copper or the like are provided on a peripheral portion of a silicon substrate 2.
[0004]
The relay substrate 4 includes a base film 5 whose size is slightly larger than the size of the silicon substrate 2 of the semiconductor chip 1. On the upper surface of the base film 5, a rewiring 6 connected to the bump electrode 3 of the semiconductor chip 1 is provided.
[0005]
The rewiring 6 includes a first connection pad 7 provided corresponding to the bump electrode 3 of the semiconductor chip 1, a second connection pad 8 provided in a matrix, and first and second connection pads 7. , 8 are connected. A circular hole 10 is provided in the base film 5 at a portion corresponding to the center of the second connection pad 8.
[0006]
The semiconductor chip 1 is mounted on the center of the upper surface of the relay board 4 via the anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is made of a thermosetting resin 12 containing a large number of conductive particles 13.
[0007]
When the semiconductor chip 1 is mounted on the relay substrate 4, first, the semiconductor chip 1 is positioned at the center of the upper surface of the relay substrate 4 via the sheet-like anisotropic conductive adhesive 11 and simply placed. I do.
[0008]
Next, bonding is performed by applying a predetermined pressure at a temperature at which the thermosetting resin 12 is cured. Then, the bump electrode 3 pushes away the thermosetting resin 12 and is conductively connected to the upper surface of the first connection pad 7 through the conductive particles 13, and the lower surface of the semiconductor chip 1 is thermoset to the upper surface of the relay substrate 4. It is bonded via the conductive resin 12.
[0009]
Next, a resin sealing film 14 made of an epoxy resin is formed on the entire upper surface of the relay substrate 4 including the semiconductor chip 1. Next, a solder ball 15 is formed in and below the circular hole 10 so as to be connected to the second connection pad 8. In this case, since the second connection pads 8 are arranged in a matrix, the solder balls 15 are also arranged in a matrix.
[0010]
Here, the size of the solder balls 15 is larger than the size of the bump electrodes 3 of the semiconductor chip 1, and the interval between the solder balls 15 needs to be larger than the interval between the bump electrodes 3 to avoid contact between the solder balls 15. . Therefore, when the number of the bump electrodes 3 of the semiconductor chip 1 increases, it is necessary to make the arrangement area larger than the size of the semiconductor chip 1 in order to obtain a necessary arrangement interval between the solder balls 15. The size of the substrate 4 is slightly larger than the size of the semiconductor chip 1. Therefore, among the solder balls 15 arranged in a matrix, the peripheral solder balls 15 are arranged around the semiconductor chip 1.
[0011]
[Problems to be solved by the invention]
By the way, in the above-mentioned conventional semiconductor device, the lower surface of the bump electrode 3 of the semiconductor chip 1 is bonded to the first wiring of the relay substrate 4 by bonding after the alignment using the relay substrate 4 on which the redistribution 6 is formed. Is electrically connected to the upper surface of the connection pad 7 via the conductive particles 13 of the anisotropic conductive adhesive 11, the number of the bump electrodes 3 of the semiconductor chip 1 increases, and the size and arrangement of the bump electrodes 3 are increased. When the interval is small, there is a problem that alignment is extremely difficult. In this case, if the size of the semiconductor chip 1 is increased, it is natural that the size and the arrangement interval of the bump electrodes 3 can be increased. However, in this case, the number of semiconductor chips to be removed from the wafer state is drastically reduced. Would be extremely expensive. In addition, the semiconductor chips 1 must be bonded and mounted one by one on the relay substrate 4, and there is a problem that the manufacturing process is complicated. The same applies to a multi-chip module type semiconductor device including a plurality of semiconductor chips.
[0012]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device, which can increase the interval between external connection electrodes without using bonding.
Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can manufacture a plurality of semiconductor devices collectively.
[0013]
[Means for Solving the Problems]
The invention according to claim 1 is a semiconductor structure having a plurality of rewirings provided on an upper surface of a semiconductor substrate and a columnar electrode formed on one end of each of the rewirings, and the columnar structure of the semiconductor structure. An insulating film provided on the entire upper surface excluding the electrodes and on an extended portion outside the peripheral side surface of the semiconductor structure, and at least one layer provided on the insulating film so as to be connected to the columnar electrode and having a connection pad; An upper layer redistribution, wherein at least a part of an uppermost layer upper layer redistribution is formed on the extension portion outside the peripheral side surface of the semiconductor structure on the insulating film. Is characterized by being arranged in a.
The invention according to claim 2 has a semiconductor substrate, a plurality of rewirings provided on the upper surface of the semiconductor substrate, and columnar electrodes formed on one end of each of the rewirings, and are separated from each other. A plurality of semiconductor structures arranged in a manner as described above, an insulating film provided on the entire upper surface of each of the semiconductor structures excluding the columnar electrode, and an extension portion outside the peripheral side surface of each of the semiconductor structures, and the insulating film And at least one layer of upper-layer rewiring provided on the column electrode and having a connection pad, wherein at least a part of the upper-layer rewiring of the uppermost layer includes the connection pad. The semiconductor device is disposed on the extension portion outside a peripheral side surface of any of the semiconductor structures on the insulating film.
According to a third aspect of the present invention, in the first or second aspect of the invention, the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure.
According to a fourth aspect of the present invention, in the third aspect of the present invention, the lower surface of the insulating film provided to cover the peripheral side surface of the semiconductor structure is substantially flush with the lower surface of the semiconductor structure. It is characterized by being arranged.
According to a fifth aspect of the present invention, in the first or second aspect of the present invention, in the upper layer redistribution, the lower layer upper layer redistribution is directly provided through the opening formed in the insulating film. And the opening formed in the insulating film has a width equal to or less than half the width of the columnar electrode.
According to a sixth aspect of the present invention, in the first or second aspect of the invention, among the upper layer redistributions, the lower layer upper layer redistribution is formed on each of the columnar electrodes and the lowermost layer insulating film. Characterized in that it includes a plated layer that has been formed.
According to a seventh aspect of the present invention, in the first or second aspect, the insulating film has a plurality of layers, and an interlayer connecting the columnar electrode of the semiconductor structure and the upper layer rewiring is provided between the layers. A rewiring is provided.
The invention according to claim 8 is the invention according to claim 1 or 2, wherein the columnar electrode has a height of 50 μm or more.
According to a ninth aspect of the present invention, in the first or second aspect of the present invention, an uppermost layer is formed on an upper surface of the insulating film including the upper layer rewiring except for at least a part of the connection pad of the upper layer rewiring. An insulating film is provided.
According to a tenth aspect of the present invention, in the invention of the ninth aspect, a protruding connection terminal is provided on the connection pad of the upper layer rewiring.
According to an eleventh aspect of the present invention, in the ninth aspect of the invention, an electronic component is provided on the uppermost insulating film so as to be connected to one of the connection pad portions of the upper layer rewiring. It is assumed that.
According to a twelfth aspect of the present invention, in any one of the ninth to eleventh aspects, a heat radiation layer is provided on a lower surface of the semiconductor structure and the insulating film provided on a peripheral side surface thereof. It is a feature.
According to a thirteenth aspect of the present invention, in the first or second aspect, the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure, and the insulating film provided on the peripheral side surface of the semiconductor structure. The film is provided on a base plate.
According to a fourteenth aspect of the present invention, in the first or second aspect, the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure, and the insulating film provided on the peripheral side surface of the semiconductor structure. A flexible wiring board is disposed on the film, and connection terminals formed on the flexible wiring board are connected to the connection pads of any of the upper layer rewirings.
According to a fifteenth aspect of the present invention, in the first or the second aspect of the present invention, a flexible wiring board is disposed on the semiconductor structure, and a connection terminal formed on the flexible wiring board is connected to any one of the upper layers. It is characterized by being connected to the connection pad of a wiring.
According to a sixteenth aspect of the present invention, in the invention according to the fifteenth aspect, a protruding connection terminal is provided on the flexible wiring board in a conductive connection.
According to a seventeenth aspect, in the first or second aspect, the insulating film is provided to cover a peripheral side surface of the semiconductor structure, and the insulating film formed on the peripheral side surface of the semiconductor structure. An outermost peripheral insulating film is provided so as to cover the film.
The invention according to claim 18 is the invention according to claim 17, wherein the outermost peripheral insulating film is formed to be thicker than the insulating film formed on the peripheral side surface of the semiconductor structure. Things.
The invention according to claim 19 is characterized in that, in the invention according to claim 17, the outermost peripheral insulating film is formed thinner than the insulating film formed on the peripheral side surface of the semiconductor structure. Things.
According to a twentieth aspect of the present invention, in the ninth aspect, an electronic component is provided on the uppermost insulating film so as to be connected to one of the connection pads of the upper layer redistribution wiring. A connection terminal formed on a flexible wiring board is connected to an external terminal of the upper layer rewiring.
According to a twenty-first aspect of the present invention, in the first or second aspect of the present invention, a plurality of the semiconductor components having the insulating film and the upper-layer redistribution line provided on an upper surface thereof are provided. Are connected by a flexible wiring board.
The invention according to claim 22 is the invention according to claim 21, characterized in that the semiconductor structures are stacked with their lower surfaces facing each other.
An invention according to claim 23, wherein a plurality of semiconductor structures each having a plurality of rewirings and a columnar electrode provided on each of the rewirings are spaced apart from each other and arranged on a base plate; Forming an insulating film on the entire upper surface of the base plate including on the plurality of semiconductor structures; and connecting electrodes on the upper surface of the insulating film and corresponding columnar electrodes of any of the semiconductor structures Forming at least one of the connection pads of the upper layer rewiring connected to the insulating film formed between the semiconductor structures; and A semiconductor having at least one of the semiconductor components formed on the insulating film covering at least one of the connection pads of the upper layer rewiring by cutting off the insulating film between the semiconductor layers; It is characterized in that a step of obtaining a plurality of location.
According to a twenty-fourth aspect of the present invention, in the invention according to the twenty-third aspect, the step of cutting the insulating film is performed so as to include a plurality of the semiconductor structures.
According to a twenty-fifth aspect of the present invention, in the twenty-third aspect of the present invention, the insulating film has a plurality of layers, and a columnar electrode of each of the semiconductor structures and the corresponding upper layer rewiring are connected between the layers. A step of forming a plurality of sets of interlayer rewirings.
According to a twenty-sixth aspect of the present invention, in the invention according to the twenty-third aspect, a step of forming an uppermost-layer insulating film on a portion of the upper surface of the insulating film including the upper-layer rewiring except a connection pad portion of the upper-layer rewiring Which is characterized by having
The invention according to claim 27 is the invention according to claim 26, characterized by comprising a step of forming a protruding connection terminal on the connection pad portion of the upper layer rewiring.
The invention according to claim 28 is the invention according to claim 26, characterized by comprising a step of providing an electronic component on the uppermost insulating film by connecting the electronic component to the connection pad portion of the upper layer rewiring. It is.
The invention according to claim 29 is the invention according to claim 23, wherein the step of cutting the insulating film includes cutting the insulating film and cutting the base plate, and comprising a base plate as the semiconductor device. Is obtained.
According to a thirtieth aspect of the present invention, in the invention according to the twenty-ninth aspect, a step of disposing another base plate under the base plate before cutting, and removing the another base plate after cutting the base plate. Which is characterized by having
According to a thirty-first aspect of the present invention, in the twenty-third aspect of the present invention, before the step of cutting the insulating film between the respective semiconductor structures, a step of removing the base plate is provided. It is.
A thirty-second aspect of the present invention is characterized in that, in the thirty-first aspect, a step of thinning the semiconductor substrate is provided subsequent to the step of removing the base plate.
According to the present invention, a plurality or a plurality of sets of semiconductor components having rewiring and columnar electrodes are arranged on a semiconductor substrate, and an insulating film is formed on the entire upper surface of the base plate including the semiconductor components. Then, an upper layer rewiring is formed on the upper surface of the insulating film by connecting to the columnar electrode of the semiconductor structure, and at least the insulating film is cut to have one or one set of the semiconductor structure, and the insulating film is formed around the semiconductor structure. And a plurality of semiconductor devices in which a part of the upper-layer rewiring is arranged on the surrounding insulating film can be collectively obtained. Since the arrangement interval of the electrodes can be increased, and the insulating film and the upper layer rewiring can be collectively formed on a plurality or a plurality of sets of the semiconductor structures, the manufacturing process It can be simplified.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. This semiconductor device includes a square base plate 21 made of silicon, glass, ceramics, resin, metal, or the like. An adhesive layer 22 made of an adhesive, a pressure-sensitive adhesive sheet, a double-sided adhesive tape, or the like is provided on the upper surface of the base plate 21.
[0015]
At the center of the upper surface of the adhesive layer 22, the lower surface of a planar square semiconductor structure 23 slightly smaller than the size of the base plate 21 is bonded. In this case, the semiconductor structure 23 is called a CSP (chip size package), and includes a silicon substrate (semiconductor substrate) 24 bonded to the center of the upper surface of the bonding layer 22. A plurality of connection pads 25 made of aluminum or the like are provided around the upper surface of the silicon substrate 24, and an insulating film 26 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 24 except for the center of the connection pad 25. .
[0016]
The one in which the connection pads 25 and the insulating film 26 are provided on the silicon substrate 24 is usually obtained when a semiconductor substrate in a wafer state is diced into individual chips. However, in the present invention, in a state where the connection pads 25 and the insulating film 26 are formed on the semiconductor substrate in a wafer state, dicing is not performed, and the semiconductor structure 23 having rewiring is obtained as described below. In this state, the semiconductor substrate in a wafer state is diced. First, the configuration of the semiconductor component 23 will be described.
[0017]
On the insulating film 26 formed on the silicon substrate 24, a protective film 27 made of polyimide or the like is provided. The central portion of the connection pad 25 is exposed through an opening 28 formed in the insulating film 26 and the protective film 27. A base metal layer 31a made of copper is provided from the upper surface of the connection pad 25 exposed through the opening 28 to a predetermined position on the upper surface of the protective film 27. An upper metal layer 31b made of copper is provided on the upper surface of the base metal layer 31a, and a rewiring 32 is formed by the base metal layer 31a and the upper metal layer 31b.
[0018]
On the upper surface of the pad portion of the rewiring 32, a columnar electrode 33 made of copper is provided. A sealing film (insulating film) 34 made of epoxy resin is provided on the upper surface of the protective film 27 including the rewiring 32 so that the upper surface thereof is flush with the upper surface of the columnar electrode 33. As described above, the semiconductor structure 23 includes the silicon substrate 24, the connection pad 25, and the insulating film 26, and further includes the protective film 27, the rewiring 32, the columnar electrode 33, and the sealing film 34.
[0019]
A sealing film (insulating film) 35 made of an epoxy resin is provided on the upper surface of the adhesive layer 22 around the semiconductor structure 23 so that the upper surface thereof is flush with the upper surface of the sealing film 34. A first upper insulating film 36 made of photosensitive polyimide or the like is provided on the upper surfaces of the sealing films 34 and 35 and the columnar electrode 33. An opening 37 is provided in a portion of the first upper insulating film 36 corresponding to the center of the upper surface of the columnar electrode 33. The first base metal layer 38a and the first base metal layer 38a are provided on the first base metal layer 38a from the upper surface of the columnar electrode 33 exposed through the opening 37 to a predetermined portion of the upper surface of the first upper insulating film 36. A first upper layer redistribution line 39 made of a first upper layer metal layer 38b is provided.
[0020]
A second upper insulating film 41 made of photosensitive polyimide or the like is provided on the entire upper surface of the first upper insulating film 36 including the first upper wiring 39. An opening 42 is provided in a portion of the second upper insulating film 41 corresponding to the connection pad of the first upper rewiring 39. The second base metal layer 43a and the second base metal layer 43a extend from the upper surface of the connection pad portion of the first upper layer rewiring 39 exposed through the opening 42 to a predetermined portion of the upper surface of the second upper layer insulating film 41. A second upper layer redistribution layer 44 composed of a second upper layer metal layer 43b provided on the base metal layer 43a is provided.
[0021]
A third upper insulating film 45 made of photosensitive polyimide or the like is provided on the entire upper surface of the second upper insulating film 41 including the second upper wiring 44. An opening 46 is provided in a portion of the third upper insulating film 45 corresponding to the connection pad of the second upper wiring 44. Inside and above the opening 46, a solder ball (projection-like connection terminal) 47 is provided so as to be connected to the connection pad portion of the second upper layer rewiring 44. The plurality of solder balls 47 are arranged on the third upper insulating film 45 in a matrix.
[0022]
By the way, the reason why the size of the base plate 21 is made slightly larger than the size of the semiconductor component 23 is that the arrangement area of the solder balls 47 is changed according to the increase in the number of connection pads 25 on the silicon substrate 24. This is because the size and the arrangement interval of the connection pads 25 are made slightly larger than the size and the arrangement interval of the columnar electrodes 33.
[0023]
For this reason, the connection pad portions of the second upper layer rewirings 44 arranged in a matrix (portions in the openings 46 of the third upper layer insulating film 45) are not limited to the region corresponding to the semiconductor structure 23, It is also arranged on the region of the insulating film 35 provided on the peripheral side surface of the semiconductor structure 23. That is, among the solder balls 47 arranged in a matrix, at least the outermost solder balls 47 are arranged around the outside of the semiconductor structure 23.
[0024]
In this case, as a modified example, all the connection pad portions of the second upper layer rewiring 44 may be arranged around the outside located outside the semiconductor structure 23. Further, the upper layer rewiring may be formed as a single layer, that is, only the first rewiring 39, and at least the outermost connection pad portion may be disposed around the outer side of the semiconductor structure 23.
[0025]
As described above, the present invention provides a semiconductor configuration in which not only the connection pad 25 and the insulating film 26 but also the protective film 27, the rewiring 32, the columnar electrode 33, the sealing film 34, and the like are formed on the silicon substrate 24. A first upper layer rewiring 39 connected to the columnar electrode 33 via a first upper layer insulating film 36 covering the upper surface and an opening 37 formed on the first upper layer insulating film 36; It is characterized in that a sealing film 35 that covers the peripheral side surface is provided.
[0026]
Usually, the height of the columnar electrode is required to be 100 to 200 μm in order to reduce the stress acting on the columnar electrode due to the difference in the coefficient of thermal expansion between the silicon substrate and the circuit board. A first upper wiring layer 39 and the first upper insulating film 36 are formed on the columnar electrode 33. The first upper wiring layer 39 and the first upper insulating film 36 have a function of relaxing stress. Therefore, the height of the columnar electrode 33 can be reduced to about 50 to 100 μm. Of course, as the height of the columnar electrode 33 is increased, the stress relaxation effect is increased. Therefore, depending on the circuit board to be bonded, the height may be the same as the conventional height.
[0027]
Next, an example of a method for manufacturing the semiconductor device will be described. First, as shown in FIG. 2, a base plate 21 from which a plurality of base plates 21 shown in FIG. 1 can be obtained is provided with an adhesive layer 22 provided on the entire upper surface of the base plate 21. Then, the lower surface of the silicon substrate 24 of the semiconductor structure 23 is bonded to a plurality of predetermined locations on the upper surface of the bonding layer 22.
[0028]
As described above, the semiconductor structure 23 is called a CSP, and is manufactured in advance. Here, an example of a method of manufacturing the semiconductor structure 23 will be briefly described. First, a semiconductor substrate in which a connection pad 25, an insulating film 26, and a protective film 27 are provided on a semiconductor substrate in a wafer state (a silicon substrate 24 before cutting) is prepared. Next, a base metal layer 31a is formed on the entire upper surface of the protective film 27 including the upper surface of the connection pad 25 exposed through the opening 28.
[0029]
Next, an upper metal layer 31b is formed at a predetermined location on the upper surface of the base metal layer 31a by electrolytic plating. Next, a columnar electrode 33 is formed on the upper surface of the connection pad portion of the rewiring 32 by electrolytic plating. Next, unnecessary portions of the underlying metal layer 31a are removed by etching using the columnar electrode 33 and the upper metal layer 31b as a mask, and the underlying metal layer 31a is left only under the upper metal layer 31b. Then, a redistribution wiring 32 composed of an upper metal layer 31b formed on the entire surface of the base metal layer 31a is formed.
[0030]
Next, a sealing film 34 is formed on the entire upper surface of the protective film 27 including the columnar electrode 33 and the rewiring 32 so that the thickness thereof is larger than the height of the columnar electrode 33. Therefore, in this state, the upper surface of the columnar electrode 33 is covered with the sealing film 34. Next, the upper surfaces of the sealing film 34 and the columnar electrodes 33 are appropriately polished to expose the upper surfaces of the columnar electrodes 33. Next, through a dancing step, a plurality of semiconductor structures 23 shown in FIG. 2 are obtained.
[0031]
Now, as shown in FIG. 2, after bonding the lower surface of the silicon substrate 24 of the semiconductor structure 23 to a plurality of predetermined positions on the upper surface of the adhesive layer 22, respectively, as shown in FIG. A sealing film 35 made of polyimide, epoxy resin or the like is formed on the upper surface of the adhesive layer 22 including 23 by printing so that the thickness is slightly larger than the height of the semiconductor structure 23. Therefore, in this state, the upper surface of the semiconductor structure 23 is covered with the sealing film 35. Next, the upper surfaces of the sealing film 35 and the semiconductor structure 23 are appropriately polished to expose the upper surfaces of the columnar electrodes 33 as shown in FIG.
[0032]
Here, also when manufacturing the semiconductor structure 23 shown in FIG. 2, as described above, the sealing film 34 is formed on the upper surface of the protective film 27 including The upper surface of the columnar electrode 33 is exposed by appropriately forming the sealing film 34 and the columnar electrode 33 by polishing the sealing film 34 and the columnar electrode 33. Therefore, the polishing process is performed twice.
[0033]
Therefore, next, a case where the polishing step can be performed once will be described. In the state shown in FIG. 2, a semiconductor component 23 that does not include the sealing film 34 is prepared. That is, after the protective film 27, the rewiring 32, and the columnar electrode 33 are formed on the semiconductor substrate in a wafer state on which the connection pads 25 and the insulating film 26 are formed, the dicing is performed without forming the sealing film 34. .
[0034]
Then, in the step shown in FIG. 3, the sealing films 34 and 35 are simultaneously formed in the regions where the sealing films 34 and 35 are to be formed with the same sealing material, and the sealing films 34 and 35 (however, The film is integrated and has no boundary) and the upper surface of the columnar electrode 33 may be polished. That is, by performing the sealing film forming step once, the polishing step can be performed once.
[0035]
However, when the polishing step is performed once, the height of the columnar electrode 33 of the semiconductor structure 23 in the state shown in FIG. In this case, the height of the semiconductor structure 23 in the state shown in FIG. 2 becomes uniform, and the height of the semiconductor structure 23 in the state shown in FIG. 2 can be made uniform in advance.
[0036]
When the polishing step shown in FIG. 4 is completed, next, as shown in FIG. 5, a first upper insulating film 36 is formed on the upper surfaces of the sealing films 34 and 35 and the columnar electrode 33 which are flush with each other. I do. The first upper insulating film 36 is made of a photosensitive polyimide, a photosensitive polybenzoxazole, a photosensitive epoxy resin, a photosensitive novolak resin, a photosensitive acrylic resin or a calzo resin, and is formed into a dry film. Therefore, when this dry film is laminated by a laminator, the first upper insulating film 36 is formed. The same applies to the second and third upper insulating films 41 and 45 described later, but they may be formed by a coating method such as printing.
[0037]
Next, an opening 37 is formed in a portion of the first upper insulating film 36 corresponding to the center of the upper surface of the columnar electrode 33 by photolithography. Next, as shown in FIG. 6, a first base metal layer 38a is formed on the entire upper surface of the first upper insulating film 36 including the upper surface of the columnar electrode 33 exposed through the opening 37. In this case, the first base metal layer 38a is composed of only a copper layer formed by electroless plating, but may be composed of only a copper layer formed by sputtering, or a titanium layer formed by sputtering. A copper layer may be formed on the thin film layer by sputtering. This is the same in the case of a second base metal layer 43a to be described later.
[0038]
Next, a plating resist film 51 is pattern-formed on the upper surface of the first base metal layer 38a. In this case, an opening 52 is formed in the plating resist film 51 in a portion corresponding to the first upper layer rewiring 39 formation region. Next, copper electrolytic plating is performed using the first base metal layer 38a as a plating current path, so that the first upper metal layer 38a is formed on the upper surface of the first base metal layer 38a in the opening 52 of the plating resist film 51. 38b, a first upper layer rewiring 39 is formed. 1 and 6, only the first base metal layer 38a is formed in the opening 37 of the first upper insulating film 36, but this is for convenience of illustration, and actually, A first upper metal layer 38b is also formed.
[0039]
Here, since the first upper layer rewiring 39 is directly bonded to the columnar electrode 33 by plating, the opening 37 of the first upper layer insulating film 36 has a square shape of 10 μm × 10 μm or a circular shape having the same area. Is sufficient in terms of strength. This type of exposure machine has a positioning accuracy of several μm, and the diameter of the columnar electrode 33 is usually about 100 to 150 μm (the pitch is usually twice as large). Compared to the method of bonding by rewiring, the method can be applied even when the size and arrangement interval of the columnar electrodes are much smaller, and the process is more efficient.
[0040]
As described above, according to the method of the present invention, the width of the opening of the insulating film for joining the upper layer rewiring to the columnar electrode can be reduced to 以下 or less of the width of the columnar electrode. Accordingly, the size and arrangement interval of the columnar electrodes of the semiconductor structure can be reduced, so that the size of the semiconductor device of the present invention having the upper layer rewiring can be further reduced.
[0041]
Next, the plating resist film 51 is peeled off, and then unnecessary portions of the first base metal layer 38a are removed by etching using the first upper metal layer 38b as a mask. As shown in FIG. A first upper layer redistribution line 39 composed of the base metal layer 38a and the first upper layer metal layer 38b is formed.
[0042]
Next, as shown in FIG. 8, a second upper insulating film 41 made of photosensitive polyimide or the like is pattern-formed on the entire upper surface of the first upper insulating film 36 including the first upper wiring 39. In this case, an opening 42 is formed in a portion of the second upper insulating film 41 corresponding to the connection pad of the first upper wiring 39. Next, a second base metal layer 43a is formed by electroless plating over the entire upper surface of the second upper insulating film 41 including the connection pad portion of the first upper wiring layer 39 exposed through the opening. .
[0043]
Next, a plating resist film 53 is pattern-formed on the upper surface of the second base metal layer 43a. In this case, an opening 54 is formed in the plating resist film 53 in a portion corresponding to the second upper layer rewiring 44 forming region. Next, copper electrolytic plating is performed using the second base metal layer 43a as a plating current path, so that a second upper metal layer is formed on the upper surface of the second base metal layer 43a in the opening 54 of the plating resist film 53. 43b is formed.
[0044]
Next, the plating resist film 53 is peeled off, and then unnecessary portions of the second base metal layer 43 are removed by etching using the second upper layer redistribution mask as a mask, as shown in FIG. A second upper layer redistribution layer 44 composed of the base metal layer 43 and the second upper layer metal layer 43b is formed.
[0045]
Next, as shown in FIG. 10, a third upper insulating film 45 made of photosensitive polyimide or the like is pattern-formed on the entire upper surface of the second upper insulating film 41 including the second upper wiring 44. In this case, an opening 46 is formed in a portion of the third upper insulating film 45 corresponding to the connection pad portion of the second upper wiring 44. Next, a solder ball 47 is formed in and above the opening 46 so as to be connected to the connection pad portion of the second upper layer rewiring 44.
[0046]
Next, as shown in FIG. 11, when the three insulating films 45, 41, and 36, the sealing film 35, the adhesive layer 22, and the base plate 21 are cut between the semiconductor structures 23 adjacent to each other, FIG. A plurality of the semiconductor devices shown are obtained.
[0047]
In the semiconductor device thus obtained, the first base metal layer 38 and the first upper wiring 39 connected to the columnar electrodes 33 of the semiconductor structure 23 are formed by electroless plating (or sputtering) and electrolytic plating. Since the second base metal layer 43 and the second upper layer redistribution layer 44 to be connected to the connection pad portions of the first upper layer redistribution layer 39 are formed by electroless plating (or sputtering) and electrolytic plating. Conductive connection between the columnar electrode 33 of the semiconductor structure 23 and the first upper layer redistribution line 39 and between the first upper layer redistribution line 39 and the second upper layer redistribution line 44 without using bonding. Can be.
[0048]
Further, in the above-described manufacturing method, the semiconductor components 23 are respectively bonded and arranged at a plurality of predetermined locations on the adhesive layer 22 on the base plate 21, and the first to third upper layers are attached to the plurality of semiconductor components 23. The insulating films 36, 41, 45, the first and second base metal layers 38, 43, the first and second upper layer rewirings 39, 44, and the solder balls 47 are collectively formed, and then divided. Since a plurality of semiconductor devices are obtained, the manufacturing process can be simplified.
[0049]
In addition, since the plurality of semiconductor components 23 can be transported together with the base plate 21, the manufacturing process can be simplified. Furthermore, if the outer dimensions of the base plate 21 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.
[0050]
Further, in the above manufacturing method, as shown in FIG. 2, the CSP type semiconductor structure 23 having the rewiring 32 and the columnar electrode 33 is bonded on the bonding layer 22. A normal semiconductor chip provided with the connection pad 25, the insulating film 26, and the protective film 27 is adhered on the adhesive layer 22 to form a rewiring and a columnar electrode on a sealing film provided around the semiconductor chip. As compared with the case, the cost can be reduced.
[0051]
For example, when the base plate 21 before cutting has a substantially circular shape with a certain size like a silicon wafer, rewiring and columnar formation are performed on a sealing film provided around a semiconductor chip bonded on the bonding layer 22. Forming the electrodes increases the processing area. In other words, low-density processing results in a reduction in the number of processed sheets at one time and a decrease in throughput, resulting in an increase in cost.
[0052]
On the other hand, in the above-described manufacturing method, since the CSP type semiconductor structure 23 having the rewiring 32 and the columnar electrode 33 is adhered on the adhesive layer 22 and then built up, the number of processes is increased. Since the high-density processing is performed until the columnar electrode 33 is formed, the efficiency is high, and the overall cost can be reduced even if the number of processes is increased.
[0053]
Next, another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, as shown in FIG. 12, an adhesive layer 56 made of an ultraviolet-curable pressure-sensitive adhesive sheet or the like is adhered to the entire upper surface of another base plate 55 made of a transparent resin plate or a glass plate that is transparent to ultraviolet light. The base plate 21 and the adhesive layer 22 described above are bonded to the upper surface of the substrate.
[0054]
Then, after passing through the manufacturing steps shown in FIGS. 2 to 10, respectively, as shown in FIG. 13, three insulating films 45, 41, and 36, a sealing film 35, an adhesive layer 22, a base plate 21, and an adhesive layer 56. Is cut, and another base plate 55 is not cut. Next, ultraviolet rays are irradiated from the lower surface side of another base plate 55 to cure the adhesive layer 56. Then, the adhesiveness of the adhesive layer 56 to the separated lower surface of the base plate 21 is reduced. Then, when individual pieces existing on the adhesive layer 56 are peeled off one by one and picked up, a plurality of semiconductor devices shown in FIG. 1 are obtained.
[0055]
In this manufacturing method, in the state shown in FIG. 13, the individualized semiconductor devices existing on the adhesive layer 56 do not fall apart, so that a circuit (not shown) is used without using a dedicated semiconductor device mounting tray. At the time of mounting on a substrate, it can be peeled off and picked up one by one. In addition, when the adhesive layer 56 remaining on the upper surface of another base plate 55 and having reduced adhesiveness is peeled off, another base plate 55 can be reused. Furthermore, if the external dimensions of another base plate 55 are made constant, the transport system can be shared regardless of the external dimensions of the semiconductor device to be manufactured.
[0056]
It is also possible to use a normal dicing tape or the like for removing the semiconductor device by expanding it as another base plate 55, and in that case, the adhesive layer does not need to be an ultraviolet curing type. Further, another base plate 55 may be removed by polishing or etching.
[0057]
Next, still another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, after the step shown in FIG. 5, as shown in FIG. 14, the entire upper surface of the first upper insulating film 36 including the upper surface of the columnar electrode 33 exposed through the opening 37 is electrolessly coated with copper. The first base metal layer 38a is formed by plating. Next, a first upper metal forming layer 38c is formed on the entire upper surface of the first base metal layer 38a by performing copper electrolytic plating using the first base metal layer 38a as a plating current path. Next, a resist film 57 is pattern-formed on a portion of the upper surface of the first upper metal forming layer 38c corresponding to the first upper rewiring formation region.
[0058]
Next, unnecessary portions of the first upper metal forming layer 38c and the first base metal layer 38a are removed by etching using the resist film 57 as a mask, and as shown in FIG. The first upper wiring layer 39 remains. After that, the resist film 57 is peeled off. Note that the second upper layer rewiring 44 may be formed by a similar forming method.
[0059]
By the way, the base plate 21 shown in FIG. 2 or another base plate 55 shown in FIG. That is, the base plate is shaped like a saucer in which the region where the semiconductor components 23 are arranged is depressed from the surroundings. Then, a plating current path metal layer is provided on the upper surface of the tray-shaped base plate surrounding the semiconductor structure 23 arrangement region, and the plating current path metal layer and the plating current path base metal layer (38, 43) are provided. ) May be connected by a conductive member to perform electrolytic plating. In this case, by setting the outer dimensions of the trays to be the same, the same manufacturing apparatus can be used even when the sizes of the semiconductor devices to be manufactured are different, so that the efficiency is improved.
[0060]
(2nd Embodiment)
In the manufacturing process shown in FIG. 3, when the adhesive layer 22 is provided on the lower surface of the silicon substrate 24 of the semiconductor structure 23 and the adhesive layer 22 is bonded to each predetermined location on the upper surface of the base plate 21, FIG. A semiconductor device as a second embodiment of the present invention as shown is obtained.
[0061]
In the semiconductor device thus obtained, the lower surface of the silicon substrate 24 is bonded to the upper surface of the base plate 21 via the adhesive layer 22, and the side surface of the silicon substrate 24 is bonded via the sealing film 36. Since it is connected to the upper surface of the base plate 21, the bonding strength of the semiconductor structure 23 to the base plate 21 can be increased to some extent.
[0062]
(Third and fourth embodiments)
FIG. 17 is a sectional view of a semiconductor device according to a third embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that it does not include a base plate 21 and an adhesive layer 22.
[0063]
In the case of manufacturing the semiconductor device of the third embodiment, for example, as shown in FIG. 10, after forming the solder balls 47, the base plate 21 is peeled off from the adhesive layer 22 or the base plate 21 and the adhesive layer 22 are removed. After removal by polishing or etching or the like, three layers of insulating films 45, 41, and 36 and a sealing film 35 are cut between adjacent semiconductor structures 23, the semiconductor device shown in FIG. You can get more than one. Since the semiconductor device thus obtained does not include the base plate 21 and the adhesive layer 22, the thickness can be reduced accordingly.
[0064]
After the base plate 21 and the adhesive layer 22 are removed by polishing, etching, or the like, the lower surfaces of the silicon substrate 24 and the sealing film 35 are appropriately polished, and then three layers are formed between the semiconductor structures 23 adjacent to each other. By cutting the insulating films 45, 41, and 36 and the sealing film 35, a plurality of semiconductor devices according to the fourth embodiment of the present invention shown in FIG. 18 are obtained. The semiconductor device thus obtained can be further reduced in thickness.
[0065]
Before the formation of the solder balls 47, the base plate 21 and the adhesive layer 22 are removed by polishing, etching, or the like (if necessary, the lower surfaces of the silicon substrate 24 and the sealing film 35 are appropriately polished). Next, the solder balls 47 may be formed, and then the three layers of the insulating films 45, 41, 36 and the sealing film 35 may be cut between the adjacent semiconductor structures 23.
[0066]
(Fifth embodiment)
FIG. 19 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that a metal layer 61 for heat dissipation is adhered to the lower surface of the adhesive layer 22. The metal layer 61 is made of a copper foil having a thickness of several tens of μm or the like.
[0067]
In the case of manufacturing the semiconductor device of the fifth embodiment, for example, as shown in FIG. 10, after the solder balls 47 are formed, the base plate 21 is removed by polishing or etching, and then the entire lower surface of the adhesive layer 22 is formed. FIG. 19 shows a state in which the three insulating films 45, 41, and 36, the sealing film 35, the adhesive layer 22, and the metal layer 61 are cut between the semiconductor structures 23 adjacent to each other. A plurality of semiconductor devices are obtained.
[0068]
The adhesive layer 22 is also removed by polishing, etching, or the like (if necessary, the lower surfaces of the silicon substrate 24 and the sealing film 35 are appropriately polished), and new surfaces are formed on the lower surfaces of the silicon substrate 24 and the sealing film 35. The metal layer 61 may be bonded via an adhesive layer.
[0069]
(Sixth embodiment)
In the case shown in FIG. 11, cutting is performed between the semiconductor components 23 adjacent to each other. However, the present invention is not limited to this, and two or more semiconductor components 23 are cut as one set. As in the sixth embodiment of the present invention, three semiconductor components 23 may be cut into one set to obtain a multi-chip module type semiconductor device. In this case, the set of three semiconductor components 23 may be the same or different.
[0070]
In FIG. 20, the underlying metal layers below the rewirings 32, 39, and 44 are omitted for convenience of illustration. It is not known whether the connection pad portion (solder ball 47) of the second upper layer rewiring 44 is disposed on the sealing film 35 around the semiconductor structure 23, but this is for convenience of illustration. Yes, it is actually disposed on the sealing film 35. This is the same in the embodiment described later.
[0071]
However, for example, in FIG. 20, since the semiconductor structure 23 is adhered to the upper surface of the adhesive layer 22, high accuracy is not required for the alignment at the time of bonding unlike the conventional bonding, It is possible to make the arrangement interval of the components 23 as small as possible. Therefore, when the arrangement interval of the semiconductor structures 23 is made as small as possible, at least a part of the second upper layer rewiring 44 may be arranged on the sealing film 35.
[0072]
(Seventh embodiment)
In the case shown in FIG. 20, only the solder balls 47 are provided on the connection pad portions of the second upper layer rewiring 44. However, the present invention is not limited to this. For example, in the seventh embodiment of the present invention shown in FIG. As described above, the connection pad 62 is formed on the connection pad portion of the second upper layer rewiring 44, and the solder ball 47, the semiconductor chip 63 composed of an LSI or the like, and the chip component 64 composed of a capacitor or a resistor are provided thereon. It may be.
[0073]
In this case, the semiconductor chip 63 and the chip component 64 are arranged at the center of the upper surface of the third upper insulating film 45, and the solder balls 47 are arranged at the periphery of the upper surface of the third upper insulating film 45. The semiconductor chip 63 has a structure in which a plurality of bump electrodes 63b are provided around the lower surface of a chip body 63a. The bump electrodes 63b of the semiconductor chip 63 are conductively connected to the connection pads 62 via solder (not shown). Further, a sealing material 65 is filled between the chip body 63a and the third upper insulating film 45. The electrodes on both sides of the chip component 64 are connected to the connection pads 62 by solder 66.
[0074]
(Eighth embodiment)
In FIG. 21, the chip component 64 and the like are mounted on the central portion and the solder ball 47 is formed on the peripheral portion of a set of three semiconductor components 23, but the present invention is not limited to this. As in the eighth embodiment of the present invention shown in FIG. 22, the size of the sealing film 35 around one semiconductor structure 23 is increased to some extent, and the sealing film 35 is disposed on the central portion of the third upper insulating film 45. A chip component 64 or the like may be mounted on the connection pad 62, and the lower part of the connection pin 67 may be connected to the connection pad 62 arranged on the peripheral portion via solder (not shown). The connection pins 67 are soldered to the connection pads 62, not shown, but inserted into through holes formed in the circuit board, and soldered to pad portions formed around the through holes on the back side. Is what is done.
[0075]
(Ninth embodiment)
FIG. 23 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention. Next, the structure of this semiconductor device will be described together with its manufacturing method. First, a description will be given with reference to FIG. 20. In FIG. 20, a product is prepared in which the solder plate 47 is not formed and the base plate 21 is removed. Hereinafter, the prepared one is referred to as a semiconductor block 71.
[0076]
Next, the central part of the upper surface of the metal plate 72 for heat radiation, which is somewhat larger than the semiconductor block 71, is bonded to the lower surface of the adhesive layer 22 of the semiconductor block 71. Next, a sealing film 73 is formed on the upper surface of the metal plate 72 around the semiconductor block 71 by a molding method or a printing method so that the upper surface thereof is flush with the upper surface of the third upper insulating film 45 of the semiconductor block 71. I do. In addition, the adhesive layer 22 may be removed, the metal plate 72 may be arranged in a mold, and the semiconductor block 71 may be arranged in the center of the upper surface.
[0077]
Next, on the upper surfaces of the third upper-layer insulating film 45 and the sealing film 73, a third upper-layer rewiring (including a third base metal layer) 74 is connected to the connection pad portion of the second upper-layer rewiring 44. Formed. Next, a fourth upper insulating film 75 is formed on the upper surface of the third upper insulating film 45 including the third upper wirings 74. Next, an opening 76 is formed in a portion of the fourth upper insulating film 75 corresponding to the connection pad of the third upper rewiring 74. Next, a connection pad 77 is formed on the fourth upper insulating film 75 in and around the opening 76 so as to be connected to the connection pad portion of the third upper layer rewiring 74.
[0078]
Next, electrodes on both sides of a chip component 78 including a capacitor and a resistor are connected to the upper surface of the connection pad 77 on the semiconductor block 71 via solder 79. Further, the lower part of the connection pin 80 is connected to the upper surface of the connection pad 77 on the sealing film 73 via solder (not shown). Thus, the semiconductor device shown in FIG. 23 is obtained.
[0079]
(Tenth embodiment)
FIG. 24 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention. Next, the structure of this semiconductor device will be described together with its manufacturing method. First, also in this case, referring to FIG. 20, a device prepared by removing the base plate 21 and the adhesive layer 22 without forming the solder balls 47 in FIG. 20 is prepared. Hereinafter, the prepared one is referred to as a semiconductor block 81. However, the arrangement of the second upper layer rewiring (including the second underlying metal layer) 44 is different between FIGS. 20 and 24 for convenience of illustration. In FIG. 24, connection pads 82 are formed at predetermined positions on the upper surface of the third upper layer insulating film 45 so as to be connected to the connection pad portions of the second upper layer rewiring 44.
[0080]
Next, a flexible wiring board 83 is prepared. The flexible wiring board 83 includes a film substrate 85 having an opening 84 which is slightly larger than the semiconductor block 81 at the center. The wiring 86 is provided on the upper surface of the film substrate 85. One end of the wiring 86 protrudes into the opening 84 and serves as a connection terminal 86a. On the upper surface of the film substrate 85 including the wiring 86, a protective film 87 is provided. An opening 88 is provided in a portion of the protective film 87 corresponding to the other end of the wiring 86. A solder ball 89 is provided on the other end of the wiring 86 exposed through the opening 88, but when the flexible wiring board 83 is prepared, the solder ball 89 is not formed.
[0081]
Then, the connection terminals 86a of the flexible wiring board 83 are connected to the connection pads 82 arranged on the periphery of the semiconductor block 81 via solder (not shown). Next, a sealing film 90 is formed on the lower surface of the flexible wiring board 83 around the semiconductor block 81 by a molding method or a printing method so that the lower surface is flush with the lower surface of the semiconductor block 71 such as the silicon substrate 24. Next, a metal plate 92 for heat dissipation is bonded to the lower surface of the silicon substrate 24 and the like of the semiconductor block 71 and the lower surface of the sealing film 90 via an adhesive layer 91.
[0082]
Next, electrodes on both sides of a chip component 93 composed of a capacitor, a resistor, and the like are connected to the upper surface of a connection pad 82 arranged at the center of the semiconductor block 81 via solder 94. Further, a solder ball 89 is formed on the other end of the wiring 86 exposed through the opening 88 of the flexible wiring board 83. Thus, the semiconductor device shown in FIG. 24 is obtained.
[0083]
(Eleventh embodiment)
In the case shown in FIG. 24, as in the tenth embodiment of the present invention shown in FIG. 25, the thickness of the sealing film 90 in the peripheral portion is larger than the thickness of the sealing film 90 near the peripheral surface of the semiconductor block 81. May also be made thinner. In this case, the sealing film 90 is formed by a molding method.
[0084]
(Twelfth embodiment)
FIG. 26 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention. Next, the structure of this semiconductor device will be described together with its manufacturing method. First, also in this case, referring to FIG. 20, a device prepared by removing the base plate 21 and the adhesive layer 22 in FIG. 20 is prepared. Hereinafter, the prepared one is referred to as a semiconductor block 101. In this case, although the solder ball 47 is formed, a solder ball (47A) having a slightly smaller diameter than the case shown in FIG. 20 is formed.
[0085]
Next, the flexible wiring board 102 is prepared. The flexible wiring board 102 includes a film substrate 103 that is somewhat larger than the semiconductor block 81. The wiring 104 is provided on the upper surface of the film substrate 103. A through hole 104 is provided in a portion of the film substrate 103 corresponding to one end of the wiring 104. On the upper surface of the film substrate 103 including the wiring 104, a protective film 106 is provided. An opening 107 is provided in a portion of the protective film 106 corresponding to the other end of the wiring 104. A solder ball 108 is provided on the other end of the wiring 106 exposed through the opening 107, but the solder ball 108 is not formed when the flexible wiring board 102 is prepared.
[0086]
Then, the solder ball (47A) of the semiconductor block 101 is inserted into the through hole 105 of the flexible wiring board 102, and the solder 47A is connected to the lower surface of one end of the wiring 104 in the through hole 105 by a reflow process. Next, a sealing film 109 is formed on the lower surface of the flexible wiring board 102 around the semiconductor block 101 by molding or printing so that the lower surface thereof is flush with the lower surface of the semiconductor substrate 101 such as the silicon substrate 24.
[0087]
Next, a metal plate 111 for heat dissipation is bonded to the lower surface of the silicon substrate 24 and the like of the semiconductor block 101 and the lower surface of the sealing film 109 via an adhesive layer 110. Next, a solder ball 108 is formed on the other end of the wiring 104 exposed through the opening 107 of the flexible wiring board 8102. Thus, the semiconductor device shown in FIG. 26 is obtained.
[0088]
(Thirteenth embodiment)
FIG. 27 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention. This semiconductor device is significantly different from the semiconductor device shown in FIG. 20 in that it does not include any solder balls 47 but instead includes a flexible wiring board 121.
[0089]
In this case, the flexible wiring board 121 has the wiring 123 provided on one surface of the film substrate 122, and is protected on one surface of the film substrate 122 including a portion excluding the connection terminals 123 a formed at both ends of the wiring 123 (the other is not shown). The structure is such that a film 124 is provided. On the other hand, a plurality of connection terminals 125 are formed at one end of the upper surface of the third upper insulating film 45 so as to be connected to connection pad portions of predetermined second upper layer rewirings 44. The one connection terminal 123a of the flexible wiring board 121 is connected to the connection terminal 125 via an anisotropic conductive adhesive (not shown) or solder.
[0090]
A connection pad 126 is formed on the connection pad portion of the remaining second upper layer rewiring 44, and a chip component 127 including a capacitor and a resistor and a CSP type semiconductor structure 128 are mounted thereon. I have. In this case, the semiconductor component 128 has substantially the same structure as the semiconductor component 23. The lower surface of the columnar electrode 129 of the semiconductor structure 128 is connected to the upper surface of the connection pad 126 via solder (not shown).
[0091]
(14th embodiment)
FIG. 28 is a sectional view of a semiconductor device according to a fourteenth embodiment of the present invention. In this semiconductor device, for example, the semiconductor block 131 formed by removing the base plate 21 in the device shown in FIG. 20 and the base plate 21 and the adhesive layer 22 are removed and the solder ball 47 is not formed in the device shown in FIG. A semiconductor block 132 made of a material is bonded via an adhesive layer 22. In this case, only the plurality of semiconductor chips 63 are mounted on the upper semiconductor block 132.
[0092]
The two semiconductor blocks 131 are connected to each other via a flexible wiring board 121 substantially the same as that shown in FIG. 23, for example. That is, a plurality of connection terminals 125 are formed at one end of the upper surface of the third upper insulating film 45 of the upper semiconductor block 132 so as to be connected to the connection pad portion of the predetermined second upper layer rewiring 44A. The one connection terminal 123a of the flexible wiring board 121 is connected to the connection terminal 125 via an anisotropic conductive adhesive (not shown) or solder.
[0093]
At one end of the lower surface of the third upper insulating film 45 of the lower semiconductor block 131, a connection terminal including a predetermined second upper layer rewiring 44B is provided. The other connection terminal 123b of the flexible wiring board 121 is connected to a connection terminal formed of a predetermined second upper layer rewiring 44B via an anisotropic conductive adhesive (or solder) 133.
[0094]
(Fifteenth embodiment)
FIG. 29 is a sectional view of a semiconductor device according to a fifteenth embodiment of the present invention. This semiconductor device is significantly different from the case shown in FIG. 28 in that the flexible wiring board 121 is lengthened and adhered to the lower surface of the third upper insulating film 45 of the lower semiconductor block 131 via the adhesive layer 151. It is.
[0095]
In this case, the solder balls 47 protrude outside the film substrate 122 via the adhesive layer 151, the protective film 124, and the opening 152 formed in the film substrate 122. The other connection terminal 123b of the flexible wiring board 121 is connected to a connection terminal formed of a predetermined second upper layer redistribution 44B at both ends of the other semiconductor block 131 by an opening formed in the adhesive layer 151 and the protective film 124. The connection is made via a solder 154 arranged in the portion 153.
[0096]
【The invention's effect】
As described above, according to the present invention, a plurality or a plurality of sets of semiconductor components having rewiring and columnar electrodes are arranged on a semiconductor substrate, and the entire top surface of the base plate including the semiconductor components is arranged on the base plate. An insulating film is formed, an upper layer rewiring is formed on the upper surface of the insulating film by connecting to the columnar electrode of the semiconductor structure, and at least the insulating film is cut to have one or one set of the semiconductor structure. A plurality of semiconductor devices having a peripheral insulating film and a part of the upper layer rewiring disposed on the peripheral insulating film can be collectively obtained. It is possible to increase the arrangement interval of the external connection electrodes without the need, and to form the insulating film and the upper layer rewiring collectively on a plurality or a plurality of sets of semiconductor structures. , It is possible to simplify the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view of an initial manufacturing process in the example of the method for manufacturing the semiconductor device shown in FIG.
FIG. 3 is a sectional view of the manufacturing process following FIG. 2;
FIG. 4 is a sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a sectional view of the manufacturing process following FIG. 4;
FIG. 6 is a sectional view of the manufacturing process following FIG. 5;
FIG. 7 is a sectional view of the manufacturing process following FIG. 6;
FIG. 8 is a sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a sectional view of the manufacturing process following FIG. 8;
FIG. 10 is a sectional view of the manufacturing process following FIG. 9;
FIG. 11 is a sectional view of the manufacturing process continued from FIG. 10;
FIG. 12 is a cross-sectional view of another example of the method of manufacturing the semiconductor device shown in FIG. 1, which is initially prepared.
FIG. 13 is a sectional view of a predetermined manufacturing process in the other example.
14 is a cross-sectional view of a predetermined manufacturing step in still another example of the method of manufacturing the semiconductor device shown in FIG. 1;
FIG. 15 is a sectional view of the manufacturing process continued from FIG. 14;
FIG. 16 is a sectional view of a semiconductor device as a second embodiment of the present invention.
FIG. 17 is a sectional view of a semiconductor device according to a third embodiment of the present invention;
FIG. 18 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 19 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 20 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention;
FIG. 21 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention;
FIG. 22 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention.
FIG. 23 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention;
FIG. 24 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention;
FIG. 25 is a sectional view of a semiconductor device according to an eleventh embodiment of the present invention;
FIG. 26 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention;
FIG. 27 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention;
FIG. 28 is a sectional view of a semiconductor device according to a fourteenth embodiment of the present invention;
FIG. 29 is a sectional view of a semiconductor device according to a fifteenth embodiment of the present invention;
FIG. 30 is a cross-sectional view of an example of a conventional semiconductor device.
[Explanation of symbols]
21 Base plate
22 Adhesive layer
23 Semiconductor Structure
24 Silicon substrate
25 connection pads
31 Base metal layer
32 Rewiring
33 pillar electrode
34 sealing film
35 sealing film
36 First upper insulating film
38 First Underlying Metal Layer
39 1st upper layer rewiring
41 Second upper insulating film
43 Second Underlying Metal Layer
44 Second Upper Layer Rewiring
45 Third upper insulating film
47 Solder Ball

Claims (32)

半導体基板の上面に設けられた複数の再配線および前記各再配線の一端部上に形成された柱状電極を有する半導体構成体と、該半導体構成体の前記柱状電極を除く上面全体および前記半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記柱状電極に接続されて設けられ且つ接続パッドを有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッドが前記絶縁膜上の前記半導体構成体の周側面より外側の前記延出部上に配置されていることを特徴とする半導体装置。A semiconductor structure having a plurality of rewirings provided on an upper surface of a semiconductor substrate and a columnar electrode formed on one end of each of the rewirings; the entire upper surface of the semiconductor structure excluding the columnar electrodes; and the semiconductor structure An insulating film provided on an extended portion outside the peripheral side surface of the body, and at least one upper layer rewiring provided on the insulating film and connected to the columnar electrode and having a connection pad; In the rewiring, at least a part of the upper layer rewiring of the uppermost layer is characterized in that the connection pad is arranged on the extension portion outside the peripheral side surface of the semiconductor structure on the insulating film. Semiconductor device. 各々が、半導体基板と、該半導体基板の上面に設けられた複数の再配線および前記各再配線の一端部上に形成された柱状電極を有し、互いに離間して配置された複数の半導体構成体と、該各半導体構成体の柱状電極を除く上面全体および前記各半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記柱状電極に接続されて設けられ且つ接続パッドを有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッドが前記絶縁膜上の前記いずれかの半導体構成体の周側面より外側の前記延出部上に配置されていることを特徴とする半導体装置。A plurality of semiconductor structures each having a semiconductor substrate, a plurality of rewirings provided on the upper surface of the semiconductor substrate, and a columnar electrode formed on one end of each of the rewirings, and spaced apart from each other And an insulating film provided on the entire upper surface of each of the semiconductor structures except for the columnar electrodes and an extension outside the peripheral side surface of each of the semiconductor structures, and connected to the columnar electrodes on the insulating film. And at least one layer of upper-layer rewiring having connection pads, wherein at least a part of the upper-layer rewiring of the uppermost layer includes the connection pad on the insulating film. A semiconductor device, wherein the semiconductor device is disposed on the extension portion outside a peripheral side surface of a semiconductor structure. 請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the insulating film is provided to cover a peripheral side surface of the semiconductor structure. 4. 請求項３に記載の発明において、前記半導体構成体の周側面を覆って設けられた前記絶縁膜の下面は前記半導体構成体の下面とほぼ同一の平面上に配置されていることを特徴とする半導体装置。4. The semiconductor device according to claim 3, wherein a lower surface of the insulating film provided to cover a peripheral side surface of the semiconductor structure is arranged on substantially the same plane as a lower surface of the semiconductor structure. Semiconductor device. 請求項１または２に記載の発明において、前記上層再配線の中、最下層の上層再配線は前記記絶縁膜に形成された開口を介して直接前記柱状電極に電気的に接続され、前記絶縁膜に形成された前記開口は前記柱状電極の幅の１／２以下の幅を有することを特徴とする半導体装置。3. The invention according to claim 1, wherein, of the upper layer redistribution, the lower layer upper layer redistribution is electrically connected directly to the columnar electrode through an opening formed in the insulating film, and The semiconductor device according to claim 1, wherein the opening formed in the film has a width equal to or less than half the width of the columnar electrode. 請求項１または２に記載の発明において、前記上層再配線の中、最下層の上層再配線は前記各柱状電極上および前記最下層の絶縁膜上に形成されためっき層を含むことを特徴とする半導体装置。3. The invention according to claim 1, wherein, in the upper layer rewiring, the lower layer upper rewiring includes a plating layer formed on each of the columnar electrodes and the lowermost insulating film. Semiconductor device. 請求項１または２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記半導体構成体の柱状電極と前記上層再配線とを接続する層間再配線が設けられていることを特徴とする半導体装置。3. The invention according to claim 1, wherein the insulating film has a plurality of layers, and an interlayer rewiring for connecting the columnar electrode of the semiconductor structure and the upper layer rewiring is provided between the layers. Characteristic semiconductor device. 請求項１または２に記載の発明において、前記柱状電極は５０μｍ以上の高さを有することを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the columnar electrode has a height of 50 μm or more. 請求項１または２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面に前記上層再配線の前記接続パッドの少なくとも一部を除く部分に最上層絶縁膜が設けられていることを特徴とする半導体装置。3. The method according to claim 1, wherein an uppermost insulating film is provided on a portion of the insulating film including the upper layer rewiring except at least a part of the connection pad of the upper layer rewiring. 4. Characteristic semiconductor device. 請求項９に記載の発明において、前記上層再配線の前記接続パッド上に突起状の接続端子が設けられていることを特徴とする半導体装置。10. The semiconductor device according to claim 9, wherein a protruding connection terminal is provided on the connection pad of the upper layer rewiring. 請求項９に記載の発明において、前記最上層絶縁膜上に電子部品がいずれかの前記上層再配線の接続パッド部に接続されて設けられていることを特徴とする半導体装置。10. The semiconductor device according to claim 9, wherein an electronic component is provided on the uppermost insulating film so as to be connected to one of the connection pad portions of the upper rewiring. 請求項９〜１１のいずれかに記載の発明において、前記半導体構成体およびその周側面に設けられた前記絶縁膜の下面に放熱層が設けられていることを特徴とする半導体装置。12. The semiconductor device according to claim 9, wherein a heat dissipation layer is provided on a lower surface of the semiconductor structure and the insulating film provided on a peripheral side surface thereof. 請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられ、該半導体構成体の周側面に設けられた前記絶縁膜はベース板上に設けられていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the insulating film is provided to cover a peripheral side surface of the semiconductor structure, and the insulating film provided on the peripheral side surface of the semiconductor structure is provided on a base plate. A semiconductor device. 請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられ、該半導体構成体の周側面に設けられた前記絶縁膜上にフレキシブル配線板が配置され、該フレキシブル配線板に形成された接続端子がいずれかの前記上層再配線の前記接続パッドに接続されていることを特徴とする半導体装置。3. The invention according to claim 1, wherein the insulating film is provided to cover a peripheral side surface of the semiconductor structure, and a flexible wiring board is disposed on the insulating film provided on the peripheral side surface of the semiconductor structure. And a connection terminal formed on the flexible wiring board is connected to the connection pad of any of the upper layer rewirings. 請求項１または２に記載の発明において、前記半導体構成体上にフレキシブル配線板が配置され、前記フレキシブル配線板に形成された接続端子がいずれかの前記上層再配線の前記接続パッドに接続されていることを特徴とする半導体装置。3. The invention according to claim 1, wherein a flexible wiring board is disposed on the semiconductor structure, and a connection terminal formed on the flexible wiring board is connected to the connection pad of any of the upper layer rewirings. A semiconductor device. 請求項１５に記載の発明において、前記フレキシブル配線板上に突起状の接続端子が導電接続されて設けられていることを特徴とする半導体装置。16. The semiconductor device according to claim 15, wherein a protruding connection terminal is provided on the flexible wiring board so as to be conductively connected. 請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられ、該半導体構成体の周側面に形成された前記絶縁膜を覆って最外周絶縁膜が設けられていることを特徴とする半導体装置。3. The invention according to claim 1, wherein the insulating film is provided to cover a peripheral side surface of the semiconductor structure, and an outermost peripheral insulating film covers the insulating film formed on the peripheral side surface of the semiconductor structure. A semiconductor device, which is provided. 請求項１７に記載の発明において、前記最外周絶縁膜は前記半導体構成体の周側面に形成された前記絶縁膜よりも厚く形成されていることを特徴とする半導体装置。18. The semiconductor device according to claim 17, wherein the outermost peripheral insulating film is formed thicker than the insulating film formed on a peripheral side surface of the semiconductor structure. 請求項１７に記載の発明において、前記最外周絶縁膜は前記半導体構成体の周側面に形成された前記絶縁膜よりも薄く形成されていることを特徴とする半導体装置。18. The semiconductor device according to claim 17, wherein the outermost peripheral insulating film is formed thinner than the insulating film formed on a peripheral side surface of the semiconductor structure. 請求項９に記載の発明において、前記最上層絶縁膜上に電子部品がいずれかの前記上層再配線の接続パッドに接続されて設けられ、他のいずれかの前記上層再配線の外部端子ににフレキシブル配線板に形成された接続端子が接続されていることを特徴とする半導体装置。10. The invention according to claim 9, wherein an electronic component is provided on the uppermost insulating film so as to be connected to one of the connection pads of the upper layer rewiring, and is connected to an external terminal of the other upper layer rewiring. A semiconductor device, wherein connection terminals formed on a flexible wiring board are connected. 請求項１または２に記載の発明において、上面に前記絶縁膜および前記上層再配線が設けられた前記半導体構成体を複数個有し、前記各半導体構成体上面の上層再配線がフレキシブル配線板により接続されていることを特徴とする半導体装置。3. The invention according to claim 1, wherein a plurality of the semiconductor components provided with the insulating film and the upper layer redistribution on the upper surface are provided, and the upper layer redistribution on the upper surface of each semiconductor component is formed by a flexible wiring board. 4. A semiconductor device which is connected. 請求項２１に記載の発明において、前記半導体構成体が互いの下面を対向して積層されていることを特徴とする半導体装置。22. The semiconductor device according to claim 21, wherein the semiconductor structures are stacked with their lower surfaces facing each other. 各々が、複数の再配線および前記各再配線上に設けられた柱状電極を有する複数の半導体構成体を相互に離間してベース板上に配置する工程と、
前記複数の半導体構成体上を含む前記ベース板の上面全体に絶縁膜を形成する工程と、
前記絶縁膜の上面に、接続パッドを有し且ついずれかの前記半導体構成体の対応する前記柱状電極に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッドが前記半導体構成体間に形成された前記絶縁膜上に配置されるように形成する工程と、
前記各半導体構成体間における前記絶縁膜を切断して少なくともいずれかの前記上層再配線の接続パッドが前記半導体構成体の周側面を覆う前記絶縁膜上に形成された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。A step of arranging a plurality of semiconductor structures each having a plurality of rewirings and a columnar electrode provided on each of the rewirings on a base plate, separated from each other;
Forming an insulating film over the entire top surface of the base plate including the plurality of semiconductor structures;
On the upper surface of the insulating film, a connection pad is provided, and an upper layer rewiring connected to the corresponding columnar electrode of any of the semiconductor structures is connected to at least one of the connection pads of the upper layer rewiring. Forming it so as to be disposed on the insulating film formed between the bodies,
By cutting the insulating film between the respective semiconductor structures, at least one of the connection pads of the upper layer rewiring is formed on at least one of the semiconductor structures formed on the insulating film covering a peripheral side surface of the semiconductor structure. Obtaining a plurality of semiconductor devices having a plurality of semiconductor devices. 請求項２３に記載の発明において、前記絶縁膜を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。24. The method of manufacturing a semiconductor device according to claim 23, wherein the step of cutting the insulating film is performed so as to include a plurality of the semiconductor components. 請求項２３に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の柱状電極とそれに対応する前記上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とする半導体装置の製造方法。24. The invention according to claim 23, wherein the insulating film has a plurality of layers, and a plurality of sets of interlayer rewirings for connecting the columnar electrodes of the respective semiconductor structures and the corresponding upper layer rewirings are formed between the layers. A method for manufacturing a semiconductor device, comprising: 請求項２３に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。24. The semiconductor device according to claim 23, further comprising a step of forming an uppermost layer insulating film on a portion of the upper surface of the insulating film including the upper layer redistribution except a connection pad portion of the upper layer redistribution. Manufacturing method. 請求項２６に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子を形成する工程を有することを特徴とする半導体装置の製造方法。27. The method of manufacturing a semiconductor device according to claim 26, further comprising: forming a protruding connection terminal on the connection pad portion of the upper layer rewiring. 請求項２６に記載の発明において、前記最上層絶縁膜上に電子部品を前記上層再配線の接続パッド部に接続させて設ける工程を有することを特徴とする半導体装置の製造方法。27. The method of manufacturing a semiconductor device according to claim 26, further comprising a step of providing an electronic component on the uppermost insulating film so as to be connected to a connection pad portion of the upper rewiring. 請求項２３に記載の発明において、前記絶縁膜を切断する工程は前記絶縁膜を切断するとともに前記ベース板を切断し、前記半導体装置としてベース板を備えたものを得ることを特徴とする半導体装置の製造方法。24. The semiconductor device according to claim 23, wherein in the step of cutting the insulating film, the insulating film is cut and the base plate is cut to obtain a semiconductor device having a base plate. Manufacturing method. 請求項２９に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とする半導体装置の製造方法。30. The semiconductor device according to claim 29, further comprising a step of disposing another base plate below the base plate before cutting, and removing the another base plate after cutting the base plate. Manufacturing method. 請求項２３に記載の発明において、前記各半導体構成体間における前記絶縁膜を切断する工程の前に、前記ベース板を取り除く工程を有することを特徴とする半導体装置の製造方法。24. The method of manufacturing a semiconductor device according to claim 23, further comprising a step of removing the base plate before the step of cutting the insulating film between the semiconductor components. 請求項３１に記載の発明において、前記ベース板を取り除く工程に引き続き、前記半導体基板を薄くする工程を有することを特徴とする半導体装置の製造方法。32. The method according to claim 31, further comprising, following the step of removing the base plate, a step of thinning the semiconductor substrate.
JP2002232289A 2002-08-09 2002-08-09 Semiconductor device Expired - Fee Related JP3918681B2 (en)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP2002232289A JP3918681B2 (en) 2002-08-09 2002-08-09 Semiconductor device
EP03784529A EP1527480A2 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
AU2003253425A AU2003253425C1 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
KR1020047005322A KR100593049B1 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
CA2464078A CA2464078C (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
CN038012693A CN1568546B (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
PCT/JP2003/009958 WO2004015771A2 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
TW092121811A TWI231551B (en) 2002-08-09 2003-08-08 Semiconductor device and method of manufacturing the same
US10/826,039 US7294922B2 (en) 2002-08-09 2004-04-16 Semiconductor device and method of manufacturing the same
HK05105873.6A HK1073389A1 (en) 2002-08-09 2005-07-11 Semiconductor device and method of manufacturing the same
US11/671,318 US7547967B2 (en) 2002-08-09 2007-02-05 Semiconductor device and method of manufacturing the same
US11/671,268 US7618886B2 (en) 2002-08-09 2007-02-05 Semiconductor device and method of manufacturing the same
US12/415,782 US7737543B2 (en) 2002-08-09 2009-03-31 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002232289A JP3918681B2 (en) 2002-08-09 2002-08-09 Semiconductor device

Related Child Applications (4)

Application Number Title Priority Date Filing Date
JP2006275656A Division JP4337858B2 (en) 2006-10-06 2006-10-06 Semiconductor device
JP2006275658A Division JP4297153B2 (en) 2006-10-06 2006-10-06 Manufacturing method of semiconductor device
JP2006275657A Division JP4337859B2 (en) 2006-10-06 2006-10-06 Semiconductor device
JP2006275659A Division JP4337860B2 (en) 2006-10-06 2006-10-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2004071998A true JP2004071998A (en) 2004-03-04
JP3918681B2 JP3918681B2 (en) 2007-05-23

Family

ID=32017747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002232289A Expired - Fee Related JP3918681B2 (en) 2002-08-09 2002-08-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3918681B2 (en)

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004072032A (en) * 2002-08-09 2004-03-04 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP2005317867A (en) * 2004-04-30 2005-11-10 Sony Corp Manufacturing method of semiconductor device
JP2006173232A (en) * 2004-12-14 2006-06-29 Casio Comput Co Ltd Semiconductor apparatus and its manufacturing method
JP2006303700A (en) * 2005-04-18 2006-11-02 Shinko Electric Ind Co Ltd Reader/writer and manufacturing method thereof
JP2007005810A (en) * 2005-06-24 2007-01-11 Megic Corp Manufacturing method of line device
WO2007010863A1 (en) * 2005-07-15 2007-01-25 Ryo Takatsuki Integrated circuit chip part, multi-chip module, their integration structure, and their fabrication method
JP2007043194A (en) * 2006-10-06 2007-02-15 Casio Comput Co Ltd Semiconductor device
KR100695321B1 (en) 2004-03-31 2007-03-14 가시오게산키 가부시키가이샤 Semiconductor device incorporating semiconductor constructing body and method of fabricating the same
US7256496B2 (en) 2004-06-02 2007-08-14 Casio Computer Co., Ltd. Semiconductor device having adhesion increasing film to prevent peeling
JP2007250595A (en) * 2006-03-13 2007-09-27 Nec Corp Semiconductor device and its manufacturing process
JP2007294832A (en) * 2005-07-15 2007-11-08 ▲高▼築 良 Integrated circuit chip component, and multi-chip module and its manufacturing method
JP2007318059A (en) * 2006-04-26 2007-12-06 Sony Corp Semiconductor device, and manufacturing method thereof
JP2008186941A (en) * 2007-01-29 2008-08-14 Cmk Corp Semiconductor device and its manufacturing method
JP2008306071A (en) * 2007-06-08 2008-12-18 Nec Corp Semiconductor device and method for manufacturing the same
JP2008547206A (en) * 2005-06-14 2008-12-25 キュービック・ウエハ・インコーポレーテッド Chip cross-linking
US7563640B2 (en) 2003-11-10 2009-07-21 Casio Computer Co., Ltd. Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
JP2009182202A (en) * 2008-01-31 2009-08-13 Casio Comput Co Ltd Method of manufacturing semiconductor device
JP2009260165A (en) * 2008-04-21 2009-11-05 Casio Comput Co Ltd Semiconductor device
US7615411B2 (en) 2003-06-03 2009-11-10 Casio Computer Co., Ltd. Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof
JP2010118679A (en) * 2010-01-25 2010-05-27 Casio Computer Co Ltd Method of manufacturing semiconductor device
US7808073B2 (en) 2004-03-31 2010-10-05 Casio Computer Co., Ltd. Network electronic component, semiconductor device incorporating network electronic component, and methods of manufacturing both
JP2010245259A (en) * 2009-04-06 2010-10-28 Shinko Electric Ind Co Ltd Electronic device and method of manufacturing the same
JP2010251395A (en) * 2009-04-13 2010-11-04 Shinko Electric Ind Co Ltd Electronic device and method of manufacturing the same
KR101015704B1 (en) 2008-12-01 2011-02-22 삼성전기주식회사 Chip embedded printed circuit board and manufacturing method thereof
US7972903B2 (en) 2008-01-31 2011-07-05 Casio Computer Co., Ltd. Semiconductor device having wiring line and manufacturing method thereof
KR101053221B1 (en) 2008-01-31 2011-08-02 가시오게산키 가부시키가이샤 Semiconductor device and manufacturing method thereof
US8021922B2 (en) 2005-06-14 2011-09-20 Cufer Asset Ltd. L.L.C. Remote chip attachment
US8053903B2 (en) 2005-06-14 2011-11-08 Cufer Asset Ltd. L.L.C. Chip capacitive coupling
US8197627B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US8283778B2 (en) 2005-06-14 2012-10-09 Cufer Asset Ltd. L.L.C. Thermally balanced via
US8293574B2 (en) 2006-01-10 2012-10-23 Teramikros, Inc. Semiconductor device having a plurality of semiconductor constructs
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US8692391B2 (en) 2010-09-10 2014-04-08 Samsung Electro-Mechanics Co., Ltd. Embedded ball grid array substrate and manufacturing method thereof
KR20140043979A (en) * 2012-10-04 2014-04-14 엘지이노텍 주식회사 Semiconductor package substrate, package system using the same and method for manufacturing thereof
US8884433B2 (en) 2005-06-24 2014-11-11 Qualcomm Incorporated Circuitry component and method for forming the same
JP2018093221A (en) * 2016-09-26 2018-06-14 株式会社パウデック Semiconductor package, module, and electric device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326299A (en) * 2000-05-18 2001-11-22 Iep Technologies:Kk Semiconductor device and method for manufacturing the same
JP2001332643A (en) * 2000-05-19 2001-11-30 Iep Technologies:Kk Semiconductor device and its manufacturing method
JP2002016173A (en) * 2000-06-30 2002-01-18 Mitsubishi Electric Corp Semiconductor device
WO2002027786A1 (en) * 2000-09-25 2002-04-04 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
JP2004072032A (en) * 2002-08-09 2004-03-04 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP2004095836A (en) * 2002-08-30 2004-03-25 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP2004207306A (en) * 2002-12-24 2004-07-22 Casio Comput Co Ltd Semiconductor device and its manufacturing method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326299A (en) * 2000-05-18 2001-11-22 Iep Technologies:Kk Semiconductor device and method for manufacturing the same
JP2001332643A (en) * 2000-05-19 2001-11-30 Iep Technologies:Kk Semiconductor device and its manufacturing method
JP2002016173A (en) * 2000-06-30 2002-01-18 Mitsubishi Electric Corp Semiconductor device
WO2002027786A1 (en) * 2000-09-25 2002-04-04 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
JP2004072032A (en) * 2002-08-09 2004-03-04 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP2004095836A (en) * 2002-08-30 2004-03-25 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP2004207306A (en) * 2002-12-24 2004-07-22 Casio Comput Co Ltd Semiconductor device and its manufacturing method

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004072032A (en) * 2002-08-09 2004-03-04 Casio Comput Co Ltd Semiconductor device and its manufacturing method
US7709942B2 (en) 2003-06-03 2010-05-04 Casio Computer Co., Ltd. Semiconductor package, including connected upper and lower interconnections
US7615411B2 (en) 2003-06-03 2009-11-10 Casio Computer Co., Ltd. Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof
US7692282B2 (en) 2003-11-10 2010-04-06 Casio Computer Co., Ltd Semiconductor device including semiconductor element surrounded by an insulating member wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
US7563640B2 (en) 2003-11-10 2009-07-21 Casio Computer Co., Ltd. Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
US7279750B2 (en) 2004-03-31 2007-10-09 Casio Computer Co., Ltd. Semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion
US7808073B2 (en) 2004-03-31 2010-10-05 Casio Computer Co., Ltd. Network electronic component, semiconductor device incorporating network electronic component, and methods of manufacturing both
US7608480B2 (en) 2004-03-31 2009-10-27 Casio Computer Co., Ltd. Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion
KR100695321B1 (en) 2004-03-31 2007-03-14 가시오게산키 가부시키가이샤 Semiconductor device incorporating semiconductor constructing body and method of fabricating the same
JP2005317867A (en) * 2004-04-30 2005-11-10 Sony Corp Manufacturing method of semiconductor device
US7910405B2 (en) 2004-06-02 2011-03-22 Casio Computer Co., Ltd. Semiconductor device having adhesion increasing film to prevent peeling
CN100459125C (en) * 2004-06-02 2009-02-04 卡西欧计算机株式会社 Semiconductor device and method of fabricating the same
US7256496B2 (en) 2004-06-02 2007-08-14 Casio Computer Co., Ltd. Semiconductor device having adhesion increasing film to prevent peeling
JP2006173232A (en) * 2004-12-14 2006-06-29 Casio Comput Co Ltd Semiconductor apparatus and its manufacturing method
US7550833B2 (en) 2004-12-14 2009-06-23 Casio Computer Co., Ltd. Semiconductor device having a second semiconductor construction mounted on a first semiconductor construction and a manufacturing method thereof
JP4630114B2 (en) * 2005-04-18 2011-02-09 新光電気工業株式会社 Reader / writer and manufacturing method thereof
JP2006303700A (en) * 2005-04-18 2006-11-02 Shinko Electric Ind Co Ltd Reader/writer and manufacturing method thereof
US8846445B2 (en) 2005-06-14 2014-09-30 Cufer Asset Ltd. L.L.C. Inverse chip connector
US9324629B2 (en) 2005-06-14 2016-04-26 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US8283778B2 (en) 2005-06-14 2012-10-09 Cufer Asset Ltd. L.L.C. Thermally balanced via
US10340239B2 (en) 2005-06-14 2019-07-02 Cufer Asset Ltd. L.L.C Tooling for coupling multiple electronic chips
US8197626B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US8197627B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US8053903B2 (en) 2005-06-14 2011-11-08 Cufer Asset Ltd. L.L.C. Chip capacitive coupling
JP2008547206A (en) * 2005-06-14 2008-12-25 キュービック・ウエハ・インコーポレーテッド Chip cross-linking
US8021922B2 (en) 2005-06-14 2011-09-20 Cufer Asset Ltd. L.L.C. Remote chip attachment
US9754907B2 (en) 2005-06-14 2017-09-05 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US9147635B2 (en) 2005-06-14 2015-09-29 Cufer Asset Ltd. L.L.C. Contact-based encapsulation
JP2007005810A (en) * 2005-06-24 2007-01-11 Megic Corp Manufacturing method of line device
JP2016195263A (en) * 2005-06-24 2016-11-17 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Method of manufacturing circuitry device
JP2019047129A (en) * 2005-06-24 2019-03-22 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Method of manufacturing circuitry device
US8884433B2 (en) 2005-06-24 2014-11-11 Qualcomm Incorporated Circuitry component and method for forming the same
JP2007005809A (en) * 2005-06-24 2007-01-11 Megic Corp Manufacturing method of line device
JP2022019819A (en) * 2005-06-24 2022-01-27 クゥアルコム・インコーポレイテッド Method of manufacturing circuitry device
JP2013232671A (en) * 2005-06-24 2013-11-14 Megica Corp Manufacturing method of line device
US7977801B2 (en) 2005-07-15 2011-07-12 Ryo Takatsuki Integrated circuit chip component, multi-chip module, their integration structure, and their fabrication method
JP4699953B2 (en) * 2005-07-15 2011-06-15 ▲高▼築 良 Multichip module and manufacturing method thereof
US8076179B2 (en) 2005-07-15 2011-12-13 Ryo Takatsuki Fabrication method for integrated circuit chip component, multi-chip module, and their integration structure
JP2007294832A (en) * 2005-07-15 2007-11-08 ▲高▼築 良 Integrated circuit chip component, and multi-chip module and its manufacturing method
WO2007010863A1 (en) * 2005-07-15 2007-01-25 Ryo Takatsuki Integrated circuit chip part, multi-chip module, their integration structure, and their fabrication method
US8293574B2 (en) 2006-01-10 2012-10-23 Teramikros, Inc. Semiconductor device having a plurality of semiconductor constructs
JP2007250595A (en) * 2006-03-13 2007-09-27 Nec Corp Semiconductor device and its manufacturing process
JP2007318059A (en) * 2006-04-26 2007-12-06 Sony Corp Semiconductor device, and manufacturing method thereof
JP2007043194A (en) * 2006-10-06 2007-02-15 Casio Comput Co Ltd Semiconductor device
JP2008186941A (en) * 2007-01-29 2008-08-14 Cmk Corp Semiconductor device and its manufacturing method
JP2008306071A (en) * 2007-06-08 2008-12-18 Nec Corp Semiconductor device and method for manufacturing the same
US8975150B2 (en) 2007-06-08 2015-03-10 Renesas Electronics Corporation Semiconductor device manufacturing method
US8004089B2 (en) 2008-01-31 2011-08-23 Casio Computer Co., Ltd. Semiconductor device having wiring line and manufacturing method thereof
KR101053221B1 (en) 2008-01-31 2011-08-02 가시오게산키 가부시키가이샤 Semiconductor device and manufacturing method thereof
US7972903B2 (en) 2008-01-31 2011-07-05 Casio Computer Co., Ltd. Semiconductor device having wiring line and manufacturing method thereof
US7843071B2 (en) 2008-01-31 2010-11-30 Casio Computer Co., Ltd. Semiconductor device including wiring and manufacturing method thereof
JP2009182202A (en) * 2008-01-31 2009-08-13 Casio Comput Co Ltd Method of manufacturing semiconductor device
JP2009260165A (en) * 2008-04-21 2009-11-05 Casio Comput Co Ltd Semiconductor device
US8351215B2 (en) 2008-12-01 2013-01-08 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a chip embedded printed circuit board
KR101015704B1 (en) 2008-12-01 2011-02-22 삼성전기주식회사 Chip embedded printed circuit board and manufacturing method thereof
JP2010245259A (en) * 2009-04-06 2010-10-28 Shinko Electric Ind Co Ltd Electronic device and method of manufacturing the same
JP2010251395A (en) * 2009-04-13 2010-11-04 Shinko Electric Ind Co Ltd Electronic device and method of manufacturing the same
JP2010118679A (en) * 2010-01-25 2010-05-27 Casio Computer Co Ltd Method of manufacturing semiconductor device
US8692391B2 (en) 2010-09-10 2014-04-08 Samsung Electro-Mechanics Co., Ltd. Embedded ball grid array substrate and manufacturing method thereof
KR20140043979A (en) * 2012-10-04 2014-04-14 엘지이노텍 주식회사 Semiconductor package substrate, package system using the same and method for manufacturing thereof
KR101996935B1 (en) 2012-10-04 2019-07-08 엘지이노텍 주식회사 Semiconductor package substrate, Package system using the same and method for manufacturing thereof
JP2018093221A (en) * 2016-09-26 2018-06-14 株式会社パウデック Semiconductor package, module, and electric device

Also Published As

Publication number Publication date
JP3918681B2 (en) 2007-05-23

Similar Documents

Publication Publication Date Title
JP3918681B2 (en) Semiconductor device
JP3888267B2 (en) Semiconductor device and manufacturing method thereof
US7618886B2 (en) Semiconductor device and method of manufacturing the same
JP2004207306A (en) Semiconductor device and its manufacturing method
TW200303609A (en) Semiconductor device and manufacturing method thereof
JP2003298005A (en) Semiconductor device and method of manufacturing thereof
JP4135390B2 (en) Semiconductor device and manufacturing method thereof
JP3951854B2 (en) Semiconductor device and manufacturing method thereof
JP2005005632A (en) Chip-like electronic component, its manufacturing method, and its packaging structure
JP3618330B2 (en) Semiconductor device and manufacturing method thereof
JP4337859B2 (en) Semiconductor device
JP2004165193A (en) Semiconductor device and its manufacturing method
CN113725096B (en) Semiconductor packaging method and semiconductor packaging structure
JP4337860B2 (en) Semiconductor device
JP4337858B2 (en) Semiconductor device
JP4297154B2 (en) Manufacturing method of semiconductor device
JP4297153B2 (en) Manufacturing method of semiconductor device
CN113725097B (en) Semiconductor packaging method and semiconductor packaging structure
JP2004356649A (en) Method of manufacturing semiconductor device
JP2004320059A (en) Method for manufacturing semiconductor device
JP2005011856A (en) Chip-like electronic part, its manufacturing method, and its mounting structure
JP4214968B2 (en) Semiconductor device and manufacturing method thereof
JP2020113613A (en) Semiconductor device and method of manufacturing semiconductor device

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060208

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060406

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060808

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061006

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061107

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061221

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070123

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070205

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110223

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110223

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120223

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120223

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120223

Year of fee payment: 5

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120223

Year of fee payment: 5

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130223

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees