JP2004063629A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of wiring connected to a semiconductor integrated circuit in the case of individually transmitting data from a common line to a plurality of the semiconductor integrated circuits. <P>SOLUTION: The semiconductor integrated circuit comprises a power supply circuit 21 for generating a power supply voltage on the basis of a voltage supplied through first wiring, a data detection circuit 22 for detecting the data from the voltage supplied through the first wiring in synchronism with clock signals supplied through second wiring, a level detection circuit 23 for detecting a DC level in the first wiring, and a control circuit 27 for performing a control operation so as to selectively acquire the data supplied through the first wiring in the case that the DC level in the first wiring is within a voltage range determined corresponding to a data input mode set for the semiconductor integrated circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which a plurality of devices are simultaneously connected to a common line and data is individually transmitted.
[0002]
[Prior art]
Generally, in order to transmit data to a plurality of semiconductor integrated circuits (hereinafter, also referred to as “chips”), data and a clock signal are supplied to all chips, and a control signal is supplied to a chip to receive data. The identification has been done by: Therefore, conventionally, a data transmission line, a clock signal line, a power supply line, and a control line have been wired to these chips. Such a conventional semiconductor integrated circuit will be described with reference to FIGS.
[0003]
FIG. 5 shows an example of data transmission in a conventional memory IC. A data transmission line 110, a clock signal line 120, and a power supply (V _DD ) line 130 are connected to the plurality of chips 100. Further, the decoder 200 receives the control signal via the data bus, and supplies a plurality of decoded signals obtained by decoding the control signal to the plurality of chips 100 via the plurality of control lines 140, respectively. The decode signal indicates that data has reached each chip. The chip specified by the decode signal receives data in synchronization with the clock signal. In this way, a specific chip is designated from a plurality of chips, and selective data transmission is performed.
[0004]
FIG. 6 shows an example of data transmission in a conventional LCD driver. The LCD panel 300 is provided with a number of segment areas 310. Each of the plurality of chips 400 drives, for example, 80 segment regions 310. A data transmission line 410, a clock signal line 420, and a power supply (V _DD ) line 430 are connected to these chips 400. A chip enable signal is sequentially transmitted from one chip to the next via a control line 440 cascade-connected to these chips 400. The chip receiving the chip enable signal receives a predetermined number of data in synchronization with the clock signal, and drives the 80 segment areas 310 based on the data. In this way, a specific chip is designated from a plurality of chips, and selective data transmission is performed.
[0005]
However, in the above-described data transmission, it is necessary to wire all the control lines, data transmission lines, clock signal lines, and power supply lines to a plurality of chips, regardless of whether the data transfer speed is high or low. Therefore, there is a large burden in designing a pattern on a printed wiring board or the like.
[0006]
[Problems to be solved by the invention]
In view of the above, an object of the present invention is to significantly reduce the number of wirings when individually transmitting data from a common line connected to a plurality of semiconductor integrated circuits to individual semiconductor integrated circuits. .
[0007]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes a first wiring used to supply a DC voltage and data in a superimposed manner, and a second wiring used to supply a clock signal. A semiconductor integrated circuit connected to a wiring, the power supply circuit generating a power supply voltage based on a voltage supplied through a first wiring, and a clock signal supplied through a second wiring. And a data detection circuit for detecting data from a voltage supplied through the first wiring, and a DC level in the first wiring corresponding to a data input mode set for the semiconductor integrated circuit. A level detection circuit that detects whether the voltage is within a predetermined voltage range; and a voltage detection circuit that determines a DC level of the first wiring in accordance with a data input mode set for the semiconductor integrated circuit. If within the range, and a control circuit for controlling operation so that the data supplied via the first wiring selectively acquired.
[0008]
Here, the data input mode may be set based on the potential of at least one mode setting pin. In addition, it is preferable that a plurality of different voltage ranges higher than a power supply voltage generated by the power supply circuit are respectively defined corresponding to a plurality of data input modes. This semiconductor integrated circuit may further include a non-volatile storage element for storing selectively acquired data.
[0009]
According to the present invention configured as described above, when data is individually transmitted from a common line connected to a plurality of semiconductor integrated circuits to individual semiconductor integrated circuits, a data input mode is set for each semiconductor integrated circuit. In addition, by superimposing and supplying data to the DC voltage corresponding to the data input mode, the number of wirings connected to the semiconductor integrated circuit can be significantly reduced.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same components are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a diagram showing connections of a semiconductor integrated circuit according to one embodiment of the present invention. In the present embodiment, the present invention is applied to an LCD driver. As shown in FIG. 1, the LCD panel 10 is provided with a number of segment areas 11. Each of the plurality of chips 20 drives, for example, 80 segment regions 11. To these chips 20, a clock signal line 40 and a V _DD / data line 50 are connected. In this embodiment, the clock signal lines 40 are cascade-connected to the plurality of chips 20, but the clock signal lines may be connected to these chips 20 in parallel.
[0011]
In these chips 20, a plurality of different data detection voltage ranges are defined corresponding to the data input mode set for each chip. Data to be supplied to these chips 20 is superimposed on a DC voltage determined according to a data input mode set for each chip, and is supplied to the V _DD / data line 50. These chips 20 obtain power supply voltage V _DD from V _DD / data line 50, and selectively select data having a DC level within a data detection voltage range corresponding to the data input mode set for each chip. receive.
[0012]
In order to set a different data input mode for each chip, each chip 20 is provided with a mode setting pin 30. When two mode setting pins are provided as shown in FIG. 1, 2 ² = 4 data input modes can be set, so that four chips are simultaneously connected to a common V _DD / data line. It is possible to
[0013]
In this way, a specific chip is designated from among a plurality of chips, and selective data transmission is performed. Therefore, according to the present embodiment, it is not necessary to route data transmission lines and control lines as in the conventional example shown in FIG. 5 or FIG. 6, so that pattern design on a printed wiring board or the like can be facilitated.
[0014]
FIG. 2 is a block diagram showing a configuration of the chip shown in FIG. As shown in FIG. 2, the chip 20 includes a power supply circuit 21 that generates a power supply voltage V _DD based on a voltage supplied via a V _DD / data line 50, and a clock supplied via a clock signal line 40. It has a data detection circuit 22 that detects data from the V _DD / data line 50 in synchronization with a signal, and a level detection circuit 23 that detects a DC level of the V _DD / data line 50. Further, the chip 20 has a RAM 25 for storing data output from the data detection circuit 22 and an output for supplying to the electrodes of the plurality of segment areas 11 included in the LCD panel 10 based on the data stored in the RAM 25. It has an LCD interface circuit 26 for generating a signal, a control circuit 27 and a nonvolatile storage element 28.
[0015]
The control circuit 27 identifies the data input mode set in the chip 20 based on the potential of the mode setting pin 30. Here, when the level detection circuit 23 detects that the DC level in the V _DD / data line 50 is within the data detection voltage range corresponding to the data input mode, the control circuit 27 sets the data detection circuit 22 or the RAM 25 Is controlled so that the chip 20 selectively receives the data supplied from the V _DD / data line 50. Further, the control circuit 27 controls the operation of the LCD interface circuit 26.
[0016]
In the present embodiment, the chip 20 can be initialized by the control circuit 27 storing data selectively received from the V _DD / data line 50 in the nonvolatile memory element 28. Depending on the application of the chip, a plurality of data input modes may be used only for initial setting of the chip, and thereafter the chip may be operated by supplying a normal operating voltage to the chip. Even in that case, there is an effect that the initial setting of the chip becomes easy.
[0017]
Next, the operation of the chip shown in FIG. 2 will be described.
By connecting the mode setting pin 30 of each chip 20 to the V _DD / data line 50 or the ground potential GND, the data input mode of each chip 20 is set. Thereby, in each chip 20, the upper limit value and the lower limit value of the data detection voltage range allocated for detecting data based on the voltage supplied from V _DD / data line 50 are set. As a result, the plurality of chips have different data detection voltage ranges from each other.
[0018]
FIG. 3 is a diagram showing a data detection voltage range corresponding to a plurality of data input modes. Here, a case is shown in which data is individually transmitted to four chips by setting four types of data input modes using two mode setting pins. As shown in FIG. 3, four different data detection voltage ranges are set corresponding to data input modes 1, 2, 3, and 4. For example, if the normal operation voltage is 2.5 V ± 10%, the data detection voltage range in data input mode 1 is 3.0 V ± 0.1 V, and the data detection voltage range in data input mode 2 is 3.5 V ± 0.1 V. The data detection voltage range in data input mode 3 is set to 4.0 V ± 0.1 V, and the data detection voltage range in data input mode 4 is set to 4.5 V ± 0.1 V. By supplying the data on which the DC voltage is superimposed corresponding to these data detection voltage ranges to the _VDD / data line 50, the data can be individually transmitted to the four chips.
[0019]
FIG. 4 is a time chart showing timing when data is individually transmitted to a plurality of chips. N-bit data D ₁₁ , D ₁₂ , D ₁₃ ,..., D _1N , and D ₂₁ on which DC voltage is superimposed on the four chips according to the data input mode set for each chip. _{D 22, D 23, ...,} D 2N and the like are transmitted. The four chips selectively acquire data according to the data detection voltage corresponding to the data input mode set for each chip. That is, the chip in the data input mode 1 selectively obtains the N-bit data D ₁₁ , D ₁₂ , D ₁₃ ,..., D _1N, and the chip in the data input mode 2 selects the N-bit data D ₂₁ , D _{22, D} 23, ..., selectively acquires _{D 2N.} Thereby, each data can be transmitted to a desired chip.
[0020]
【The invention's effect】
As described above, according to the present invention, when data is individually transmitted from a common line connected to a plurality of semiconductor integrated circuits to individual semiconductor integrated circuits, the data is transmitted based on the potential of at least one mode setting pin. By setting the data input mode to each semiconductor integrated circuit in advance, and superimposing and supplying data to a DC voltage corresponding to the data input mode, the number of wirings connected to the semiconductor integrated circuit can be significantly reduced. Can be.
[Brief description of the drawings]
FIG. 1 is a diagram showing connections of a semiconductor integrated circuit according to one embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a chip shown in FIG.
FIG. 3 is a diagram showing a data detection voltage range corresponding to a plurality of data input modes.
FIG. 4 is a time chart showing timing when data is individually transmitted to a plurality of chips.
FIG. 5 is a diagram showing an example of data transmission in a conventional memory IC.
FIG. 6 is a diagram showing an example of data transmission in a conventional LCD driver.
[Explanation of symbols]
Reference Signs List 10 LCD panel 11 Segment area 20 Chip 21 Power supply circuit 22 Data detection circuit 23 Level detection circuit 25 RAM
26 LCD interface circuit 27 Control circuit 28 Non-volatile storage element 30 Mode setting pin 40 Clock signal line 50 V _DD / data line

Claims (4)

A semiconductor integrated circuit connected to a first wiring used to supply a DC voltage and data in a superimposed manner and a second wiring used to supply a clock signal,
A power supply circuit that generates a power supply voltage based on a voltage supplied via the first wiring;
A data detection circuit for detecting data from a voltage supplied through the first wiring in synchronization with a clock signal supplied through the second wiring;
A level detection circuit for detecting whether or not the DC level of the first wiring is within a voltage range determined according to a data input mode set for the semiconductor integrated circuit;
Data supplied via the first wiring when a DC level of the first wiring is within a voltage range defined corresponding to a data input mode set for the semiconductor integrated circuit; A control circuit that performs a control operation so as to selectively obtain
A semiconductor integrated circuit comprising: 2. The semiconductor integrated circuit according to claim 1, wherein a data input mode is set based on a potential of at least one mode setting pin. 3. The semiconductor integrated circuit according to claim 1, wherein a plurality of different voltage ranges higher than a power supply voltage generated by said power supply circuit are respectively defined corresponding to a plurality of data input modes. 4. The semiconductor integrated circuit according to claim 1, further comprising a nonvolatile storage element that stores selectively acquired data. 5.

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