JP2004045304A - Range finder and range-finding method using imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contrive a control method for a general CCD imaging element to realize an operation substantially equivalent to synchronous integration, and to realize inexpensive light wave range-finding, which requires an imaging element of specified structure in the prior art, using the general CCD imaging element. <P>SOLUTION: This range finder is constituted to have an imaging element 4 arrayed one-dimensionally or two-dimensionally with a plurality of photo-sensitive parts on a semiconductor substrate, and having structure capable of controlling sensitivity in each of the photo-sensitive parts by impressing a voltage to the semiconductor substrate, and to have a sensitivity control part 5 synchronized with a modulation signal for intensity-modulated light to impress the voltage for modulating the sensitivity of the each photo-sensitive part to the semiconductor substrate of the imaging element 4. The sensitivity of the each photo-sensitive part is able to get variable synchronized with the intensity-modulated irradiation light, and the light wave range-finding is realized thereby. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a distance measuring apparatus and a distance measuring method using an image sensor, and detects a delay of a phase of reflected light with respect to irradiation light for each pixel of the image sensor to detect a three-dimensional structure of an object. It is related to the technology to do.
[0002]
[Prior art]
FIG. 3 is a diagram for explaining the principle of a conventional TOF (Time Of Flight) type light wave ranging. In the figure, 1 is a light source, 2 is an object to be detected, 3 is an imaging optical system, and 4 is an image sensor. The light source 1 is composed of, for example, an LED array, and its output light is intensity-modulated at a high frequency. The reason why a plurality of LEDs are used for the light source 1 is to increase the intensity of output light, and the LEDs emit light in synchronization. When the light emitted from the light source 1 to the object 2 is intensity-modulated at a high frequency of, for example, 20 MHz, the wavelength is 15 m. Therefore, if the light reciprocates over a distance of 7.5 m, a phase delay of one cycle occurs. Will occur.
[0003]
The delay of the phase of the reflected light with respect to the irradiation light will be described with reference to FIG. In the figure, W is irradiation light, R is reflected light, and the reflected light has a phase delay of Ψ. The reflected light R is sampled four times for one cycle of the irradiation light W, and the detected values of the reflected light when the phase of the irradiation light is 0 °, 90 °, 180 °, and 270 ° are A0, A1, and A2, respectively. , A3, the phase delay Ψ is given by the following equation.
{= Arctan {(A3-A1) / (A0-A2)}
[0004]
The light reflected by the object 2 is imaged on the light receiving surface of the image sensor 4 via the imaging optical system 3. A plurality of pixels (X, Y) are two-dimensionally arranged on the light receiving surface of the imaging element 4, and the phase delay Ψ (X, Y) of each pixel is calculated by the above equation, so that the detection object 2 A three-dimensional structure can be detected.
[0005]
An image sensor used for the TOF lightwave distance measurement must be capable of sampling a plurality of times for one cycle of irradiation light. Conventionally, as shown in FIG. 5 or FIG. Structures have been proposed. The image sensor in FIG. 5 includes one photosensitive unit PD and four memory cells M0, M1, M2, and M3 for one pixel, and time division is performed between each of the memory cells M0, M1, M2, and M3 and the photosensitive unit PD. Electrical switches S0, S1, S2, and S3 that are turned on are provided. Each of the electric switches S0, S1, S2, S3 is turned on during a period of T0, T1, T2, T3 in FIG. By repeating this operation over a plurality of cycles, it is possible to improve the S / N ratio with respect to dark current noise, shot noise (noise due to variation in generation of electron-hole pairs), steady noise of the amplifier circuit, and the like. The detected values A0, A1, A2, A3 are stored in the memory cells M0, M1, M2, M3. Such an operation will be referred to as “synchronous integration”. The image sensor in FIG. 6 includes a shift register SR for reading data, and each memory cell of the shift register SR from one photosensitive unit PD via four electric switches S0, S1, S2, and S3 that are turned on in a time-division manner. Light receiving signals are accumulated in M0, M1, M2, and M3, and the light receiving signals are read out by the transfer function of the shift register SR.
[0006]
[Problems to be solved by the invention]
However, if an image sensor having a special structure as shown in FIG. 5 or FIG. 6 is separately manufactured, the manufacturing cost increases and the cost of the entire distance measuring apparatus increases. Therefore, various studies were conducted to determine whether synchronous integration could be achieved by devising a general control method for the CCD image sensor. It was found that the voltage applied to the overflow drain electrode or the vertical transfer electrode of the CCD image sensor was carefully controlled. It was found that the same operation as that of the synchronous integration can be realized.
[0007]
The present invention has been made based on such knowledge, and by devising a control method of a general CCD image pickup device, it is possible to realize substantially the same operation as performing synchronous integration. It is an object of the present invention to realize lightwave distance measurement, which conventionally requires an image sensor having a special structure, at low cost by using a general CCD image sensor.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, a distance measuring apparatus according to the present invention has a plurality of photosensitive units arranged one-dimensionally or two-dimensionally on a semiconductor substrate as shown in FIG. 1, and applies a voltage to the semiconductor substrate. And a voltage that modulates the sensitivity of each of the photosensitive units on the semiconductor substrate of the image sensor 4 in synchronization with a modulation signal of the intensity-modulated light. And a sensitivity control unit 5 for applying the voltage. More specifically, an imaging optical system 3 for imaging reflected light from the object 2 irradiated by the intensity-modulated light on a surface of the image sensor 4 on which sensor elements are arranged, and the intensity-modulated optical system 3. A sensitivity control unit 5 for applying a control voltage to the semiconductor substrate of the image sensor 4 to reduce the sensitivity of the photosensitive unit of the image sensor 4 in synchronization with the modulated light signal, and A storage unit 6 that reads out the charge stored in the storage unit of the imaging element 4 by the transfer unit and stores the measured value as a measurement value, and a control voltage for reducing the sensitivity of the photosensitive unit during one cycle of the intensity modulation is applied. A detection phase setting unit 7 that switches the phase of the low-sensitivity period every time a measured value is stored in the storage unit 6, and captures an image based on a plurality of measured values with different phases of the low-sensitivity period stored in the storage unit 6. For each sensor element of element 4 It is characterized in that it has a distance measuring arithmetic unit 8 for calculating the distance information up to the object 2.
[0009]
Here, as shown in FIG. 1B, the image pickup device 4 used in the distance measuring device of the present invention includes a photosensitive section PD for generating signal charges according to the amount of received light, and a signal charge generated in the photosensitive section PD. Sensor elements including a storage section M for storing and an electric switch S for opening and closing the transfer of signal charges from the photosensitive section PD to the storage section M are arranged one-dimensionally or two-dimensionally on a semiconductor substrate. An image pickup device having a structure in which a transfer portion T for reading out stored charges from the storage portion M is formed on the semiconductor substrate, and the electric switch S can be opened and closed at a high frequency by applying a voltage to a specific electrode (for example, a transfer electrode) of the semiconductor substrate. Although the electric switch S cannot be opened and closed at a high frequency, as shown in FIG. The imaging element having sensitivity variable photosensitive unit PD 'of the sensitivity by applying a voltage to the load lane electrode) can be increased or decreased at a high frequency. Specifically, it is an interline transfer CCD image pickup device having a vertical or horizontal overflow drain electrode, or a frame transfer CCD image pickup device having a vertical or horizontal overflow drain electrode, or a composite type thereof. A frame interline transfer type CCD image sensor can be used.
[0010]
FIG. 2 is a diagram illustrating the operation of the present invention. In the figure, (a) shows the phase of the irradiation light W, and (b) to (e) show the detection phase for synchronous integration set by the detection phase setting unit 7. In the related art, as shown in FIG. 5 or FIG. 6, one photosensitive element PD, a plurality of switches S0 to S3, and a plurality of memory cells M0 to M3 are provided for each sensor element, and switches S0 and S1 are provided. , S2, and S3 are turned on in a time-division manner at the detection phases shown in FIGS. 2B, 2C, 2D, and 2E, respectively. In the present invention, as shown in FIG. 1B, for each sensor element, a photosensitive portion PD for generating a signal charge according to the amount of received light, and a storage portion M for storing the signal charge generated in the photosensitive portion PD. And one electric switch S for opening and closing the transfer of the signal charge from the photosensitive unit PD to the storage unit M, and the electric switch S is repeatedly turned on at the detection phase of FIG. As a result, a measured value corresponding to A0 in FIG. 4 is obtained in the storage unit M, and this is read by the transfer unit T for one screen. At the time of the second, third, and fourth imagings, the electric switch S is repeatedly turned on at the detection phases of FIGS. 2C, 2D, and 2E, respectively, so that A1, A2, and A2 of FIG. A measurement value corresponding to A3 is obtained, and this is read out by the transfer unit T for each screen. The above operation is totally controlled by the control circuit 9. In this way, four times the measurement time is required as compared with the case of using the imaging device having the structure shown in FIG. 5 or FIG. Can be obtained, and lightwave distance measurement can be realized using a general CCD image pickup device. The distance calculation unit 8 may be any unit that can substantially calculate distance information, and may be constituted by any means such as a microcomputer, a DSP, and an operational amplifier.
[0011]
By the way, in the most common interline transfer type CCD image pickup device as the CCD image pickup device, the electrode constituting the electric switch S of FIG. 1B is also used as a vertical transfer electrode, and this electrode is formed on a semiconductor substrate. In this case, the capacitance is large in proportion to the shape, and it is extremely difficult to open and close at a high frequency of several tens of MHz when the capacitance is large. In such a case, it is not suitable for use in realizing short-distance lightwave distance measurement using a general CCD image pickup device.
[0012]
Therefore, as shown in FIG. 1C, while only the electric switch S between the photosensitive unit and the storage unit is kept in the ON state, only the sensitivity of the photosensitive unit is periodically reduced in synchronization with the irradiation light. We examined whether there is a means to do it. Since the sensitivity of the photosensitive portion is, in short, the efficiency of generation of photoelectrons with respect to the amount of received light, if a part of the generated photoelectrons can be discarded, the sensitivity is substantially reduced.
[0013]
As a means for discarding photoelectrons in such a photosensitive portion, some CCD image sensors have a structure called an overflow drain for discarding excess signal charges to a substrate. This overflow drain discards signal charges exceeding a predetermined level to the substrate in order to prevent excess signal charges generated from affecting the surrounding photosensitive parts when light that is originally too strong in the photosensitive area is obtained. However, if the overflow drain intentionally lowers the level at which the signal charge overflows, the signal charge is discarded as excessive even if the signal charge in the photosensitive portion is not excessive. As a result, the sensitivity of the photosensitive portion can be substantially reduced. In addition, since the overflow drain is directly connected to the substrate, the capacitance is small depending on the shape, and switching at several tens of MHz is possible. Therefore, if the level at which the overflow drain causes the signal charge to overflow in a phase in which light is not to be detected is set low, the sensitivity of the photosensitive portion can be modulated in accordance with the cycle of the irradiation light.
[0014]
Of course, the concept of using the overflow drain electrode for the electronic shutter of a CCD camera has existed in the past, but since it was intended for one-shot exposure, the charge in the storage unit was initialized. It was to start the integration. There is no known control method for realizing a plurality of exposures by controlling the voltage applied to the overflow drain electrode without initializing the charge in the storage section and leaving the residual image from the previous exposure.
[0015]
Hereinafter, as an embodiment of the present invention, an interline transfer type CCD image pickup device and a frame transfer type CCD image pickup device having a vertical or horizontal overflow drain electrode will be described specifically for realizing the same operation as synchronous integration. A detailed control method will be described in detail.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
FIG. 7 shows a configuration of an interline transfer type CCD (IT-CCD) having a vertical overflow drain (VOD) electrode. On the surface of the n-type substrate 10, a vertical overflow drain (VOD) electrode 11 made of an aluminum electrode is formed so as to directly contact the substrate without an insulating film. The control voltage Vs is applied to the VOD electrode 11. A p-type region 12 is formed in a portion of the surface of the n-type substrate 10 surrounded by the VOD electrode 11. In the p-type region 12, a plurality of photodiodes are formed separately. In the figure, the portion denoted by PD is a photodiode, and the surface other than the portion where the photodiode PD is formed is covered with a light shielding film (not shown). Although FIG. 7 shows three rows of photodiodes PD in the vertical direction and four rows of photodiodes in the horizontal direction, a larger number of photodiodes PD are actually formed. Electrodes a, b, c, d and a ', b', c ', d' formed adjacent to each photodiode PD are electrodes of a vertical transfer CCD, and are generated by the photodiode PD below these electrodes. The stored signal charges are accumulated, and the accumulated signal charges are transferred to the horizontal transfer CCD by the four-phase vertical transfer voltages V1, V2, V3, and V4. (The electrodes of the vertical transfer CCD formed adjacent to the photodiodes PD in each column are connected via wiring (not shown) so that the same vertical transfer voltage is applied to the electrodes arranged in the horizontal direction.) The horizontal transfer CCD has horizontal transfer electrodes e, f, e ', f', e ", f" for transferring electric charges by two-phase horizontal transfer voltages VH1, VH2. In an IT-CCD, it is very common that vertical transfer is performed by a four-phase clock and horizontal transfer is performed by a two-phase clock. The mechanism of the charge transfer is well known, and a detailed description thereof will be omitted.
[0017]
FIG. 8 shows a cross-sectional structure of the photodiode PD and the vertical transfer electrodes a and b. As described above, the p-type region 12 is formed on the surface of the n-type substrate 10, and a plurality of photodiodes PD are formed on the surface of the p-type region 12. Each photodiode PD includes an n + region 13 and a p-type region 12. A p + layer 14 is formed on the surface of the photodiode PD. Explaining the effect of the p + layer 14, the crystal structure of the substrate surface is poor in crystallinity and energy stability is poor (energy is active), so that electron-hole pairs are easily generated by thermal excitation. This becomes a dark current, which causes the S / N ratio of the signal charge to deteriorate. In order to prevent this effect, the role of the p + layer 14 is to prevent signal charges from passing near the surface, and a photodiode having this structure is called a buried photodiode or the like. An n-layer 15 constituting a vertical transfer CCD is formed on the surface of the p-type region 12 adjacent to each photodiode PD. On the surface of this n-layer 15, SiO ₂ Vertical transfer electrodes a and b made of a polysilicon gate electrode are formed via an insulating thin film 16 made of the same. Since the polysilicon gate electrode is formed with the insulating thin film 16 interposed therebetween, the capacitance is large for the shape, and when the capacitance is large, it is difficult to switch at a high frequency of several tens of MHz. The cross-sectional structure of the photodiode PD and the vertical transfer electrodes c and d is the same as that in FIG.
[0018]
FIG. 9 shows a cross-sectional structure of the vertical transfer electrodes a, b, c, and d of the vertical transfer CCD along line AA 'in FIG. The first vertical transfer electrodes a and c play a role of reading out charges from the photodiode PD to the vertical transfer CCD and performing vertical transfer. The second vertical transfer electrodes b and d play a role of vertical transfer. A light shielding film 17 is formed above the vertical transfer electrodes a, b, c, and d.
[0019]
FIG. 10 shows the electron potential along the thick broken line in FIG. That is, the n + layer 13 to the p + layer 14 'of the vertical transfer CCD (strictly formed in a separate process from the p + layer 14 on the substrate surface), the n + layer 13, the p-type region 12, and the n-type 3 shows the potential of electrons along the substrate 10. The potential barrier (shown by a broken line on the right side in FIG. 10) of the p + layer 14 between the photodiode PD and the vertical transfer CCD can be broken by increasing the voltage applied to the vertical transfer electrodes a and c. In addition, the potential barrier of the p-type region 12 between the photodiode PD and the n-type substrate 10 (shown by a broken line on the left side in FIG. 10) can be broken by increasing the voltage applied to the VOD electrode 11. In the figure, a white circle with a minus (-) sign means a photoelectron. Further, a photoelectron in a portion of the photodiode PD with a pattern such as "mane" around the photoelectron means a photoelectron generated by photoelectric conversion. The same applies to the following description.
[0020]
In the IT-CCD, the original reason for providing the VOD electrode is to release excessive signal charges to the n-type substrate 10 when very strong light enters the photodiode PD. If it is desired to lower the sensitivity of the photodiode PD even if the signal charge is not excessive, the sensitivity of the photodiode PD is made variable by making the signal charge excessive and causing overflow to the substrate. That is, when it is desired to lower the sensitivity of the photodiode PD, a high + voltage is applied to the VOD electrode 11 to lower the potential barrier of the p-type region 12 between the n + layer 13 of the photodiode PD and the n-type substrate 10. Thus, the charges generated by the photodiode PD are released to the n-type substrate 10. Although a potential barrier of the p + layer 14 'exists between the photodiode PD and the vertical transfer CCD, the potential barrier of the p + layer 14' is reduced by applying a predetermined + voltage to the first vertical transfer electrode a. The charges generated in the photodiode PD can be collected below the vertical transfer electrode a. When a high + voltage is applied to the VOD electrode 11, the charge generated by the photodiode PD slightly flows into the vertical transfer CCD, but mainly toward the n-type substrate 10 having a relatively low electron potential. Since the photodiode PD is discarded, the sensitivity (photoelectric conversion efficiency) of the photodiode PD is substantially reduced. This photoelectron discard period is defined as a synchronous integration pause period (non-detection phase). When the voltage applied to the VOD electrode 11 is reduced to stop discarding photoelectrons, the charge generated in the photodiode PD efficiently flows to the vertical transfer CCD and is accumulated below the vertical transfer electrode. This photoelectron accumulation period is referred to as a synchronous integration period (detection phase).
[0021]
The operation of the VOD type IT-CCD in each period of accumulation, disposal, and readout of photoelectrons will be described with reference to FIG. During the photoelectron accumulation period, the voltage applied to the VOD electrode 11 is low, and a sufficiently high voltage V1 is applied to the vertical transfer electrode a formed next to the photodiode PD, as shown in FIG. In addition, the potential of the n layer 15 below the vertical transfer electrode is lowered, and the potential barrier by the p + layer 14 'formed between the n layer 15 and the n + layer 13 is broken. This corresponds to that the electric switch S in FIG. 1C is closed. In this case, photoelectrons generated in the n + layer 13 are accumulated in the n layer 15 below the vertical transfer electrode.
[0022]
During the photoelectron discard period, a high + voltage Vs is applied to the VOD electrode 11 connected to the n-type substrate 10 to lower the potential of the n-type substrate 10. When the applied voltage Vs is sufficiently high, as shown in FIG. 11B, the potential barrier by the p-type region 12 formed between the n-type substrate 10 and the n + layer 13 is broken, and the photoelectrons generated in the n + layer 13 Most are discarded on the n-type substrate 10. At this time, the voltage V1 is kept applied to the vertical transfer electrode a, as in the photoelectron accumulation period. This corresponds to the electric switch S in FIG. 1 (c) being kept closed. When the applied voltage Vs of the VOD electrode 11 is set such that the potential of the n-type substrate 10 is lower than the potential of the n-layer 15 below the vertical transfer electrode, photoelectrons generated in the n + layer 13 are attracted to the lower potential. Therefore, most of them are discarded to the VOD electrode 11 (n-type substrate 10) without going to the vertical transfer electrode a side. Further, the photoelectrons accumulated in the n-layer 15 below the vertical transfer electrode during the photoelectron accumulation period are not discarded on the VOD electrode 11 (n-type substrate 10) side because of the potential barrier of the n + layer 13. .
[0023]
The photoelectron accumulation period (FIG. 11 (a)) and the photoelectron discard period (FIG. 11 (b)) alternate within one cycle of the irradiation light, and for example, as shown in FIG. Photoelectrons are accumulated only in the synchronous integration period), and in the remaining non-detection phase (integration pause), the photoelectrons (generated in the photosensitive portion while leaving the photoelectrons in the accumulation portion) are discarded. By repeating this operation over a plurality of cycles of the irradiation light, a detection value corresponding to A0 in FIG. 4 is obtained for each pixel. This detected value is read for the time being.
[0024]
In the readout period of the accumulated photoelectrons, as shown in FIG. 11C, a potential barrier is generated between the n layer 15 of the vertical transfer CCD and the n + layer 13 of the photodiode PD by the p + layer 14 '. The voltage V1 of the vertical transfer electrode a is set low, and four-phase transfer clocks are applied to the transfer voltages V1 to V4 to read out the stored signal charges. This corresponds to the state where the electric switch S in FIG. 1B is open.
[0025]
When a detection value corresponding to A0 in FIG. 4 is obtained for each pixel in this manner, the detection phase is shifted by 90 degrees to irradiate the accumulation and disposal of photoelectrons as shown in FIG. By repeating over a plurality of periods of light, a detection value corresponding to A1 in FIG. 4 is obtained for each pixel. When this detection value is read, the detection phase is shifted by 180 degrees and 270 degrees, as shown in FIG. 2D and FIG. By repeating over a plurality of cycles, detection values corresponding to A2 and A3 in FIG. 4 are obtained for each pixel. Needless to say, the number of times of synchronous integration is the same.
[0026]
The order in which the detection phases are shifted is not limited to the above. For example, a detection value of A3 is first obtained and stored in the first image memory in accordance with a calculation formula of the distance measurement operation: {= arctan {(A3-A1) / (A0-A2)}, and then A1 is obtained. (A3-A1) is overwritten on the same first image memory. Next, the detected value of A0 is obtained and stored in the second image memory, and the detected value of A2 is obtained and (A0-A2) is overwritten on the same second image memory. In this case, the storage capacity of the image memory is reduced to half.
[0027]
Further, the detection phase does not necessarily have to be a limited narrow period in one cycle as shown in FIGS. 2B to 2E, and the detection phase may be widened in order to increase the S / N ratio. Absent. For example, a first image in which a half of one cycle is measured as a detection phase and the other half as a non-detection phase, and a first image in which the detection phase and the non-detection phase are interchanged, Can be obtained by simply comparing.
[0028]
Furthermore, the intensity of the irradiation light is not necessarily a sine wave, and the irradiation light may be intensity-modulated by a rectangular wave or a triangular wave.
Further, the intensity-modulated irradiation light does not need to be visible light, and if it is invisible near-infrared light, it can be used for nighttime monitoring applications.
[0029]
By the way, the CCD having the vertical overflow drain electrode has a disadvantage that the light receiving area of the photodiode PD can be increased, but the n + region of the photodiode PD cannot be formed deep, so that the sensitivity to near infrared light is low. Therefore, in order to solve this drawback, an IT-CCD having a horizontal overflow drain (LOD) electrode capable of forming the n + region of the photodiode PD deep will be described below.
[0030]
(Embodiment 2)
FIG. 12 shows a configuration of an interline transfer type CCD (IT-CCD) having a horizontal overflow drain (LOD). A plurality of n-type regions 20 are formed on the surface of the p-type substrate 22 in the vertical direction, and each n-type region 20 is connected to a LOD electrode 21 made of an aluminum electrode. The control voltage Vs is applied to the LOD electrode 21. A plurality of photodiodes are formed separately on the surface of the p-type substrate 22 adjacent to each n-type region 20. In the drawing, the portion denoted by PD is a photodiode, and the surface other than the portion where the photodiode PD is formed is covered with a light shielding film. In FIG. 12, three columns of photodiodes PD in the vertical direction and four rows of photodiodes PD in the horizontal direction are shown, but actually, a larger number of photodiodes PD are formed. Electrodes a, b, c, d and a ', b', c ', d' formed adjacent to each photodiode PD are electrodes of a vertical transfer CCD, and are generated by the photodiode PD below these electrodes. The stored signal charges are accumulated, and the accumulated signal charges are transferred to the horizontal transfer CCD by the four-phase vertical transfer voltages V1, V2, V3, and V4. (The electrodes of the vertical transfer CCD formed adjacent to the photodiodes PD in each column are connected via wiring (not shown) so that the same vertical transfer voltage is applied to the electrodes arranged in the horizontal direction.) The horizontal transfer CCD has horizontal transfer electrodes e, f, e ', f', e ", f" for transferring electric charges by two-phase horizontal transfer voltages VH1, VH2. In an IT-CCD, it is very common that vertical transfer is performed by a four-phase clock and horizontal transfer is performed by a two-phase clock. The mechanism of the charge transfer is well known, and a detailed description thereof will be omitted.
[0031]
FIG. 13 shows a cross-sectional structure around the photodiode PD and the vertical transfer electrodes a and b. As described above, the n-type region 20 connected to the LOD electrode 21 is formed on the surface of the p-type substrate 22, and the photodiode PD is formed adjacent to the n-type region 20. Each photodiode PD includes an n + region 23 and a p-type substrate 22. A p + layer 24 is formed on the surface of the photodiode PD. Explaining the effect of the p + layer 24, the crystal structure of the substrate surface is poor in crystallinity and energy stability is poor (energy is active), so that electron-hole pairs are easily generated by thermal excitation. This becomes a dark current, which causes the S / N ratio of the signal charge to deteriorate. To prevent this effect, the role of the p + layer 24 is to prevent signal charges from passing near the surface, and a photodiode having this structure is called a buried photodiode or the like. An n-layer 25 constituting the vertical transfer CCD is formed on the surface of the p-type substrate 22 adjacent to each photodiode PD. On the surface of this n-layer 25, SiO ₂ Vertical transfer electrodes a and b made of a polysilicon gate electrode are formed with an insulating thin film 26 made of. Since the polysilicon gate electrode is formed with the insulating thin film 26 interposed therebetween, the capacitance is large for the shape, and when the capacitance is large, it is difficult to switch at a high frequency of several tens of MHz. The cross-sectional structure around the photodiode PD and the vertical transfer electrodes c and d is the same as that in FIG.
[0032]
The cross-sectional structure along the line AA ′ in FIG. 13 is the same as that in FIG. The first vertical transfer electrodes a and c play a role of reading out charges from the photodiode PD to the vertical transfer CCD and performing vertical transfer. The second vertical transfer electrodes b and d play a role of vertical transfer. A light shielding film 27 is formed above the vertical transfer electrodes a, b, c, and d. Further, a light-shielding film 27 is also formed above the n-type region 20 connected to the LOD electrode 21.
[0033]
FIG. 14 shows the electron potential along the thick broken line in FIG. That is, the n layer 25 to the p + layer 24 'of the vertical transfer CCD (strictly formed in a separate process from the p + layer 24 on the substrate surface), the n + layer 23, the p + layer 24' of the photodiode PD, and the LOD electrode 2 shows the potential of electrons along an n-type region 20 connected to 21. The potential barrier (shown by a broken line on the right side in FIG. 14) of the p + layer 24 'between the photodiode PD and the vertical transfer CCD can be broken by increasing the voltage applied to the vertical transfer electrodes a and c. Further, the potential barrier (indicated by the broken line on the left side in FIG. 14) of the p + layer 24 ′ between the photodiode PD and the n-type region 20 can be broken by increasing the voltage applied to the LOD electrode 21.
[0034]
The original reason for providing the LOD electrode in the LOD type IT-CCD is that when extremely strong light is incident on the photodiode PD, excess signal charges are released to the n-type region 20 adjacent to the photodiode PD. However, in the present invention, even if the signal charge is not excessive, when it is desired to lower the sensitivity of the photodiode PD, it is determined that the signal charge is excessive and overflows to the n-type region 20. The sensitivity of the photodiode PD is variable. That is, when it is desired to lower the sensitivity of the photodiode PD, a high + voltage is applied to the LOD electrode 21 to lower the potential barrier of the p + layer 24 ′ between the n + layer 23 and the n-type region 20 of the photodiode PD. Thus, the charges generated by the photodiode PD are released to the n-type region 20. Although a potential barrier of the p + layer 24 'exists between the photodiode PD and the vertical transfer CCD, the potential barrier of the p + layer 24' is reduced by applying a predetermined + voltage to the first vertical transfer electrode a. The charges generated in the photodiode PD can be collected below the vertical transfer electrode a. When a high + voltage is applied to the LOD electrode 21, the charge generated in the photodiode PD slightly flows to the vertical transfer CCD, but is mainly discarded toward the n-type region 20. The sensitivity (photoelectric conversion efficiency) of the photodiode PD substantially decreases. This photoelectron discard period is defined as a synchronous integration pause period (non-detection phase). When the voltage applied to the LOD electrode 21 is reduced to stop discarding photoelectrons, the charge generated in the photodiode PD efficiently flows to the vertical transfer CCD and is accumulated below the vertical transfer electrode. This photoelectron accumulation period is referred to as a synchronous integration period (detection phase).
[0035]
The operation of the LOD type IT-CCD in each period of accumulating, discarding, and reading out photoelectrons will be described with reference to FIG. During the photoelectron accumulation period, the voltage applied to the LOD electrode 21 is low, and a sufficiently high voltage V1 is applied to the vertical transfer electrode a formed next to the photodiode PD, as shown in FIG. The potential of the n layer 25 below the vertical transfer electrode is lowered, and the potential barrier by the p + layer 24 'formed between the n layer 25 and the n + layer 23 is broken. This corresponds to that the electric switch S in FIG. 1C is closed. In this case, photoelectrons generated in the n + layer 23 are accumulated in the n layer 25 below the vertical transfer electrode.
[0036]
During the photoelectron discard period, a high + voltage Vs is applied to the LOD electrode 21 connected to the n-type region 20 to lower the potential of the n-type region 20. When the applied voltage Vs is sufficiently high, as shown in FIG. 15B, the potential barrier by the p + layer 24 ′ formed between the n-type region 20 and the n + layer 23 collapses, and the photoelectrons generated in the n + layer 23 are broken. Most are discarded in the n-type region 20. At this time, the voltage V1 is kept applied to the vertical transfer electrode a, as in the photoelectron accumulation period. This corresponds to the electric switch S in FIG. 1 (c) being kept closed. When the voltage Vs applied to the LOD electrode 21 is set such that the potential of the n-type region 20 is lower than the potential of the n-layer 25 below the vertical transfer electrode, photoelectrons generated in the n + layer 23 are attracted to the lower potential. Therefore, most of the data is discarded to the LOD electrode 21 via the n-type region 20 without going to the side of the vertical transfer electrode a. The photoelectrons accumulated in the n-layer 25 below the vertical transfer electrode during the photoelectron accumulation period are not discarded on the LOD electrode 21 (n-type region 20) side because of the potential barrier of the n + layer 23. .
[0037]
The photoelectron accumulation period (FIG. 15A) and the photoelectron discard period (FIG. 15B) alternate within one cycle of the irradiation light, and for example, as shown in FIG. Photoelectrons are accumulated only in the synchronous integration period), and are discarded in the remaining non-detection phase (integration pause). By repeating this operation over a plurality of cycles of the irradiation light, a detection value corresponding to A0 in FIG. 4 is obtained for each pixel. This detected value is read for the time being.
[0038]
In the readout period of the accumulated photoelectrons, as shown in FIG. 15C, a potential barrier is generated between the n layer 25 of the vertical transfer CCD and the n + layer 23 of the photodiode PD by the p + layer 24 '. The voltage V1 of the vertical transfer electrode a is set low, and four-phase transfer clocks are applied to the transfer voltages V1 to V4 to read out the stored signal charges. This corresponds to the state where the electric switch S in FIG. 1B is open.
[0039]
When a detection value corresponding to A0 in FIG. 4 is obtained for each pixel in this manner, the detection phase is shifted by 90 degrees to irradiate the accumulation and disposal of photoelectrons as shown in FIG. By repeating over a plurality of periods of light, a detection value corresponding to A1 in FIG. 4 is obtained for each pixel. When this detection value is read, the detection phase is shifted by 180 degrees and 270 degrees, as shown in FIG. 2D and FIG. By repeating over a plurality of cycles, detection values corresponding to A2 and A3 in FIG. 4 are obtained for each pixel. Needless to say, the number of times of synchronous integration is the same.
[0040]
By the way, in the IT-CCD having the horizontal overflow drain electrode, the n + region 23 for forming the photodiode PD can be formed deep in the p-type substrate 22, so that there is an advantage that the detection sensitivity to near infrared rays can be increased. . On the other hand, there is a need for an area for providing the n-type region 20 connected to the LOD electrode 21 adjacent to the photodiode PD, and the light receiving area of the photodiode PD is reduced by that amount, so that the aperture ratio decreases. is there. In the IT-CCD, it is necessary to provide a vertical transfer CCD adjacent to the photodiode PD, so that the light receiving area of the photodiode PD is limited accordingly. Therefore, an FT-CCD in which the photodiode PD itself has a transfer function to increase the light receiving area will be described below.
[0041]
(Embodiment 3)
FIG. 16 shows a configuration of a frame transfer type CCD (FT-CCD) having a vertical overflow drain (VOD) electrode. On the surface of the n-type substrate 30, a vertical overflow drain (VOD) electrode 31 made of an aluminum electrode is formed so as to directly contact the substrate without interposing an insulating film. The control voltage Vs is applied to the VOD electrode 31. A p-type region 32 is formed in a portion of the surface of the n-type substrate 30 surrounded by the VOD electrode 31. In the p-type region 32, a plurality of vertically long n-type regions 35 are formed. A portion surrounded by a broken line in FIG. 16 constitutes a photodiode PD for one pixel, and a cross-sectional structure thereof is shown in FIG.
[0042]
On the surface of the n-type region 35, SiO ₂ A plurality of polysilicon gate electrodes a, b, and c are formed along the longitudinal direction of the n-type region 35 with the insulating thin film 36 formed therebetween. Each of the polysilicon gate electrodes a, b, and c is formed to extend in a direction perpendicular to the longitudinal direction of the n-type region 35, and one pixel is constituted by three gate electrodes a, b, and c. . Although only a limited number of pixels are shown in FIG. 16, actually, a number of pixels according to the horizontal and vertical resolutions are configured.
[0043]
Polysilicon gate electrodes a, b, c and SiO ₂ Since the insulating thin film 36 made of light transmits light, photoelectrons are generated in the n-type region 35. However, portions other than the imaging unit in FIG. 16 are covered with a light shielding film, and no photoelectrons are generated in the accumulation unit and the horizontal transfer unit. The storage unit transfers the signal charges of the imaging unit at a high speed during the vertical blanking period, and reads out the signal charges stored in the storage unit via the horizontal transfer unit until the next vertical blanking period. is there. Voltages φ1 to φ3 applied to the gate electrode of the storage unit are separated from voltages V1 to V6 applied to the gate electrode of the imaging unit, and image signals are being read from the storage unit via the horizontal transfer unit. , Signal charges can be accumulated in the imaging unit. Therefore, when the frame transfer type CCD is used, the accumulation time of the synchronous integration can be made longer than when the interline transfer type CCD is used. In this example, signal charges can be transferred from the imaging unit to the storage unit using six-phase transfer voltages V1 to V6. On the other hand, signal charges can be transferred from the storage unit to the horizontal transfer unit using three-phase transfer voltages φ1 to φ3. (The gate electrodes of the imaging unit and the storage unit are connected via wiring (not shown) so that the same transfer voltages V1 to V6 and φ1 to φ3 are applied to the electrodes arranged in the horizontal direction.) Is the same as the above-mentioned horizontal transfer CCD, and therefore detailed description is omitted, but also here, signal charges can be transferred using two-phase transfer voltages VH1 and VH2.
[0044]
FIG. 18 shows the electron potential along the broken line in FIG. Although a potential barrier due to the p-type region 32 exists between the n-type region 35 where photoelectrons are generated and the n-type substrate 30 as shown by a broken line in FIG. 18, the VOD electrode 31 connected to the n-type substrate 30 When a high + voltage is applied, the potential barrier can be broken, and signal charges (photoelectrons) from the n-type region 35 to the n-type substrate 30 can be discarded.
[0045]
In the photoelectron accumulation period, the voltage Vs applied to the VOD electrode 31 is kept low so that a potential barrier by the p-type region 32 exists between the n-type region 35 and the n-type substrate 30. Further, as shown in FIG. 19 (a), three gate electrodes a, b, and c are used for one pixel, and the highest + voltage is applied to the central gate electrode b. Not only photoelectrons but also photoelectrons generated under the gate electrodes a and c are accumulated in the potential well below the gate electrode b. This situation is shown in FIG. FIG. 19C shows the electron potential with respect to the thick alternate long and short dash line in FIG. FIG. 19D shows the electron potential for the thick broken line in FIG. 19B for each of the gate electrodes a, b, and c.
[0046]
In the photoelectron discard period, a high + voltage is applied to the VOD electrode 31 to reduce the height of the potential barrier by the p-type region 32 between the n-type region 35 and the n-type substrate 30 as shown in FIG. Lower from the broken line to the solid line. At this time, the voltage applied to the VOD electrode 31 is such that the potential of the n-type substrate 30 is higher than the potential of the n-type region 35 below the gate electrode b, and is higher than the potential of the n-type region 35 below the gate electrodes a and c. Set to lower. The voltage applied to the gate electrodes a, b, and c is the same as that during the accumulation period of photoelectrons, and a higher voltage is applied to the central gate electrode b than to the gate electrodes a and c on both sides. Under the gate electrodes a and c, the potential barrier due to the p-type region 32 is completely broken down, but below the central gate electrode b, the potential barrier due to the p-type region 32 is completely broken down only by decreasing the height. Not done. For this reason, most of the photoelectrons generated under the gate electrodes a and c on both sides are discarded to the n-type substrate 30, but the photoelectrons generated under the central gate electrode b are not discarded, and during the photoelectron accumulation period. Photoelectrons accumulated under the central gate electrode b are not discarded.
[0047]
When the above-mentioned accumulation and disposal of photoelectrons are repeated a plurality of times, the photoelectrons accumulated from the gate electrodes a and b on both sides to the central gate electrode b during the photoelectron accumulation period are accumulated under the central gate electrode b. Will be done. Since the central gate electrode b always accumulates photoelectrons, the average value obtained by the constant integration is added to the detection value obtained by the synchronous integration. However, the detection value obtained by the synchronous integration is obtained from the gate electrodes a and b on both sides. , Sufficient contrast can be obtained.
[0048]
Further, for example, in one cycle of the irradiation light, a plurality of images obtained by synchronizing and integrating the photoelectron accumulation period with half as the photoelectron accumulation period and the other half as the photoelectron discard period are observed while shifting the phase of the photoelectron accumulation period with respect to the irradiation light. In this case, the distance information can be calculated. Therefore, in an application in which the accumulation period of photoelectrons is long as in this example, the FT-CCD can be used because the contrast is increased.
[0049]
Furthermore, not only three gate electrodes but also a large number of gate electrodes, such as five or seven, constitute one pixel, and if photoelectrons are concentrated on one central gate electrode, the surrounding gate electrodes can be formed. The component of the detection value obtained by the synchronous integration collected from the above becomes relatively larger than the component of the average value obtained by the continuous integration at the center gate electrode, and the contrast can be further improved.
[0050]
Since the vertical overflow drain electrode 31 needs to form an aluminum electrode on the n-type substrate 30 surrounding the p-type region 32 so as to surround the p-type region 32, the p-type region 32 may not be formed by epitaxial growth. Can not. When formed by the diffusion method, the p-type region cannot be formed too deep. Therefore, the n-type region 35 serving as a photodiode is formed to be shallower than the p-type region 32, and the sensitivity to near infrared rays is low. In order to solve this disadvantage, an FT-CCD having a horizontal overflow drain (LOD) electrode capable of forming the n + region of the photodiode PD deep will be described below.
[0051]
(Embodiment 4)
FIG. 20 shows a configuration of a frame transfer type CCD (FT-CCD) having a horizontal overflow drain (LOD) electrode. A portion surrounded by a broken line in FIG. 20 constitutes a photodiode PD for one pixel, and a cross-sectional structure thereof is shown in FIG. On the surface of the p-type substrate 42, a p-type region 42 'is formed by epitaxial growth so that the n-type region 45 serving as a photodiode can be formed deep. The feature is that the sensitivity to near-infrared light can be increased by forming the n-type region 45 to be a photodiode deep. A p + region 44 is formed adjacent to an n-type region 45 serving as a photodiode, and an n-type region 40 serving as a horizontal overflow drain is formed in the p + region 44. An n-type region 45 serving as a photodiode and an n-type region 40 serving as a horizontal overflow drain extend adjacently in the vertical transfer direction of the substrate, and each n-type region 40 is formed of a horizontal overflow drain (LOD) made of an aluminum electrode. It is connected to the electrode 41. The control voltage Vs is applied to the LOD electrode 41.
[0052]
On the surface of the n-type region 45, SiO ₂ A plurality of polysilicon gate electrodes a, b, and c are formed along the longitudinal direction of the n-type region 45 with an insulating thin film 46 formed therebetween. Each of the polysilicon gate electrodes a, b, and c is formed to extend in a direction perpendicular to the longitudinal direction of the n-type region 45, and one pixel is constituted by three gate electrodes a, b, and c. . Although only a limited number of pixels are shown in FIG. 20, actually, a number of pixels are configured according to the horizontal and vertical resolutions.
[0053]
Polysilicon gate electrodes a, b, c and SiO ₂ Since the insulating thin film 46 made of light transmits light, photoelectrons are generated in the n-type region 45. However, portions other than the imaging unit in FIG. 20 are covered with a light-shielding film, and no photoelectrons are generated in the accumulation unit and the horizontal transfer unit. The storage unit transfers the signal charges of the imaging unit at a high speed during the vertical blanking period, and reads out the signal charges stored in the storage unit via the horizontal transfer unit until the next vertical blanking period. is there. Voltages φ1 to φ3 applied to the gate electrode of the storage unit are separated from voltages V1 to V6 applied to the gate electrode of the imaging unit, and image signals are being read from the storage unit via the horizontal transfer unit. , Signal charges can be accumulated in the imaging unit. Therefore, when the frame transfer type CCD is used, the accumulation time of the synchronous integration can be made longer than when the interline transfer type CCD is used. In this example, signal charges can be transferred from the imaging unit to the storage unit using six-phase transfer voltages V1 to V6. On the other hand, signal charges can be transferred from the storage unit to the horizontal transfer unit using three-phase transfer voltages φ1 to φ3. (The gate electrodes of the imaging unit and the storage unit are connected via wiring (not shown) so that the same transfer voltages V1 to V6 and φ1 to φ3 are applied to the electrodes arranged in the horizontal direction.) Is the same as the above-mentioned horizontal transfer CCD, and therefore detailed description is omitted, but also here, signal charges can be transferred using two-phase transfer voltages VH1 and VH2.
[0054]
FIG. 22 shows the potential of the electrons along the broken line in FIG. Although a potential barrier due to the p + region 44 exists between the n-type region 45 where photoelectrons are generated and the n-type region 40 adjacent thereto via the p + region 44 as shown by a broken line in FIG. When a high + voltage is applied to the LOD electrode 41 connected to the region 40, this potential barrier can be broken, and signal charges (photoelectrons) can be discarded from the n-type region 45 to the LOD electrode 41 via the n-type region 40. it can.
[0055]
During the photoelectron accumulation period, the voltage Vs applied to the LOD electrode 41 is kept low, and a potential barrier by the p + region 44 exists between the n-type region 45 and the n-type region 40. Also, as shown in FIG. 23 (a), three gate electrodes a, b, and c are used for one pixel, and the highest + voltage is applied to the central gate electrode b, thereby generating a voltage below the gate electrode b. Not only photoelectrons but also photoelectrons generated under the gate electrodes a and c are accumulated in the potential well below the gate electrode b. This state is shown in FIG. FIG. 23 (c) shows the electron potential for the thick dashed line in FIG. 23 (a). FIG. 23D shows the electron potential for the thick broken line in FIG. 23B for each of the gate electrodes a, b, and c.
[0056]
In the photoelectron discard period, a high + voltage is applied to the LOD electrode 41 to lower the height of the potential barrier by the p + region 44 between the n-type region 45 and the n-type region 40 as shown in FIG. . At this time, the voltage Vs applied to the LOD electrode 41 is such that the potential of the n-type region 40 is higher than the potential of the n-type region 45 under the gate electrode b and the potential of the n-type region 45 under the gate electrodes a and c. Is also set to be low. The voltage applied to the gate electrodes a, b, and c is the same as that during the accumulation period of photoelectrons, and a higher voltage is applied to the central gate electrode b than to the gate electrodes a and c on both sides. Under the gate electrodes a and c, the potential barrier due to the p + region 44 is completely broken, but under the central gate electrode b, the potential barrier due to the p + region 44 is not completely broken, only the height is reduced. Therefore, most of the photoelectrons generated under the gate electrodes a and c on both sides are discarded in the n-type region 40, but the photoelectrons generated under the central gate electrode b are not discarded. Photoelectrons accumulated under the central gate electrode b are not discarded.
[0057]
When the above-mentioned accumulation and disposal of photoelectrons are repeated a plurality of times, the photoelectrons accumulated from the gate electrodes a and b on both sides to the central gate electrode b during the photoelectron accumulation period are accumulated under the central gate electrode b. Will be done. Since the central gate electrode b always accumulates photoelectrons, the average value obtained by the constant integration is added to the detection value obtained by the synchronous integration. However, the detection value obtained by the synchronous integration is obtained from the gate electrodes a and b on both sides. , Sufficient contrast can be obtained.
[0058]
In the third and fourth embodiments shown in FIGS. 16 to 23, the case where one pixel is formed by three gate electrodes has been described. However, as shown in FIGS. 24 and 25, four or more gate electrodes are used. In the case where one pixel is formed, a potential barrier is preferably formed so that photoelectrons do not flow into the gate electrode storing photoelectrons from the surroundings during a period in which electric charges are discarded. 24 shows a case where one pixel is constituted by four gate electrodes, and FIG. 25 shows a case where one pixel is constituted by six gate electrodes. FIG. 24 (a) shows a charge accumulation period, and FIG. The potential of the electron under each gate electrode is shown. 24 and 25, photoelectrons are shown in gray, and in the charge accumulation period of (a), photoelectrons generated under the surrounding gate electrode flow in under the gate electrode having the lowest electron potential and are accumulated. , (B), a potential barrier is formed beneath an adjacent gate electrode so as to electrically isolate a portion where photoelectrons are accumulated under the gate electrode having the lowest electron potential from the surroundings. Controlling.
[0059]
In the case where one pixel is constituted by the six gate electrodes shown in FIG. 25, three-dimensionally showing the potential of electrons under each gate electrode during the charge accumulation period and the charge discard period, FIG. It becomes like b). V1 to V6 in the figure correspond to the vertical transfer voltage shown in FIG. 20, and LOD corresponds to the n-type region 40 which becomes a horizontal overflow drain. In the charge accumulation period of FIG. 27A, the photoelectrons under the gate electrode to which the voltages V2 and V6 are applied move under the gate electrode to which the voltages V3 and V5 are applied, and the voltages V3 and V5 are applied. The photoelectrons under the gate electrode thus moved move under the gate electrode to which the voltage of V4 is applied, and the photoelectrons are accumulated under the gate electrode to which the voltage of V4 is applied. In the charge discarding period in FIG. 27B, by lowering the voltages of V3 and V5 to about the same as V1, the portion where the photoelectrons are accumulated under the gate electrode to which the voltage of V4 is applied is electrically connected from the surroundings. It is isolated and the flow of photoelectrons is stopped. Further, the voltage of V4 was applied by setting the potential of the electrons of the LOD electrode higher than the gate electrode to which the voltage of V4 was applied and lower than the gate electrodes to which the voltages of V2 and V6 were applied. The photoelectrons accumulated under the gate electrode to which the voltages V2 and V6 are applied are discarded by the LOD electrode without discarding the photoelectrons accumulated under the gate electrode.
[0060]
By the way, in the example of FIG. 25, a part of the photoelectrons in the non-detection phase flows into the storage electrode portion (electrode at the position where the electron potential is deepest) to which the voltage of V4 is applied. Also, the storage electrode itself generates and stores photoelectrons in the non-detection phase. These photoelectrons in the non-detection phase become DC components with respect to the photoelectrons in the detection phase, and lower the S / N ratio. Therefore, as shown in FIG. 26, by providing a light-shielding film 47 on the surface of the photosensitive portion for forming a charge and the photosensitive portion forming a potential barrier, the ratio of the constant integration to the synchronous integration can be reduced, and the contrast of the synchronous integration can be reduced. Can be improved. In the example of FIG. 26, the surface of the gate electrode to which the voltages V1, V3, V4, and V5 are applied is covered with the light shielding film 47 so that photoelectrons are generated only under the gate electrode to which the voltages V2 and V6 are applied. ing.
[0061]
The present invention is not limited to the IT-CCD and the FT-CCD, and can be similarly applied to an FIT-CCD (frame-interline-transfer-type CCD) which is a composite of these. As shown in FIG. 28, the FIT-CCD has a storage unit for one screen added between the horizontal transfer unit and the image pickup unit of the IT-CCD, and requires two types of vertical transfer voltages, and the operation is complicated. However, there is an advantage that smear which is a disadvantage of the IT-CCD can be reduced.
[0062]
【The invention's effect】
According to the first aspect of the present invention, the sensitivity of the photosensitive section is made variable in synchronization with the intensity-modulated irradiation light, so that light wave ranging can be realized with a simple configuration.
According to the second aspect of the present invention, the sensitivity of the photosensitive portion is made variable in synchronization with the intensity-modulated irradiation light, so that there is no need for an electric switch capable of opening and closing the transfer of signal charges from the photosensitive portion to the storage portion at a high frequency. In addition, there is an advantage that it can be used in an image sensor for applications other than synchronous integration.
According to the third aspect of the present invention, the same operation as synchronous integration can be realized by using an interline transfer type CCD image sensor having a vertical overflow drain electrode which is the most common as a CCD image sensor. Lightwave distance measurement can be realized at low cost without using a simple image sensor.
[0063]
According to the fourth or sixth aspect of the present invention, the same operation as synchronous integration can be realized using a CCD image pickup device having a horizontal overflow drain electrode having high sensitivity to near-infrared light. Distance measurement becomes possible.
According to the fifth or sixth aspect of the present invention, since the frame transfer type CCD is used, it is possible to make the integration time of the synchronous integration longer than in the case of using the interline transfer type CCD.
[0064]
According to the seventh aspect of the present invention, in the charge discarding period, the potential barrier for electrically isolating the photosensitive portion for charge storage from other photosensitive portions is formed, so that the contrast of synchronous integration can be improved.
According to the eighth aspect of the present invention, since the light-shielding portion is provided on the surface of the photosensitive portion for charge accumulation and the photosensitive portion forming the potential barrier, the ratio of the constant integration to the synchronous integration can be reduced, and the contrast of the synchronous integration is improved. it can.
According to the ninth aspect of the present invention, since the electric switch capable of opening and closing the transfer of the signal charge from the photosensitive portion to the storage portion at a high frequency is provided for each sensor element, only the signal charge of the detection phase is selectively stored. Therefore, the contrast of the synchronous integration can be improved.
According to the tenth aspect of the present invention, the transfer electrode provided to serve also as the transfer unit is further used as an electric switch for opening and closing the transfer of the signal charge from the photosensitive unit to the storage unit at a high frequency. The operation of synchronous integration can be realized with a simple configuration.
[Brief description of the drawings]
FIGS. 1A and 1B are explanatory diagrams illustrating a basic configuration of the present invention, in which FIG. 1A is a block diagram illustrating an overall configuration, FIG. 1B is a main configuration diagram illustrating an example of an image sensor, and FIG. FIG. 3 is a configuration diagram of a main part showing an example of FIG.
FIG. 2 is an operation explanatory diagram showing the timing of synchronous integration by the image sensor of the present invention.
FIG. 3 is a schematic configuration diagram of an optical system used for conventional lightwave distance measurement.
FIG. 4 is a diagram illustrating the principle of conventional lightwave distance measurement.
FIG. 5 is a main part configuration diagram showing an example of an imaging element used for conventional lightwave distance measurement.
FIG. 6 is a main part configuration diagram showing another example of an imaging element used for conventional lightwave distance measurement.
FIG. 7 is a plan view showing the overall configuration of the image sensor according to Embodiment 1 of the present invention.
FIG. 8 is a perspective view illustrating a configuration of a main part of the image sensor according to Embodiment 1 of the present invention.
FIG. 9 is a cross-sectional view illustrating a main configuration of the imaging element according to the first embodiment of the present invention.
FIG. 10 is an explanatory diagram showing the electron potential of the image sensor according to the first embodiment of the present invention.
FIG. 11 is an explanatory diagram of the operation of the imaging element according to the first embodiment of the present invention;
FIG. 12 is a plan view illustrating an overall configuration of an image sensor according to Embodiment 2 of the present invention.
FIG. 13 is a perspective view illustrating a main configuration of an image sensor according to Embodiment 2 of the present invention.
FIG. 14 is an explanatory diagram showing electron potentials of the image sensor according to the second embodiment of the present invention.
FIG. 15 is an explanatory diagram of an operation of the imaging element according to the second embodiment of the present invention.
FIG. 16 is a plan view illustrating an overall configuration of an image sensor according to Embodiment 3 of the present invention.
FIG. 17 is a perspective view illustrating a main configuration of an image sensor according to Embodiment 3 of the present invention.
FIG. 18 is an explanatory diagram showing electron potentials of an image sensor according to Embodiment 3 of the present invention.
FIG. 19 is an explanatory diagram of an operation of the imaging element according to the third embodiment of the present invention.
FIG. 20 is a plan view illustrating an overall configuration of an image sensor according to Embodiment 4 of the present invention.
FIG. 21 is a perspective view illustrating a main configuration of an image sensor according to Embodiment 4 of the present invention.
FIG. 22 is an explanatory diagram showing electron potentials of an image sensor according to Embodiment 4 of the present invention.
FIG. 23 is an explanatory diagram illustrating an operation of the imaging element according to the fourth embodiment of the present invention.
FIG. 24 is an explanatory diagram showing an operation of the FT-CCD using four-phase gate voltages.
FIG. 25 is an explanatory diagram showing an operation of the FT-CCD using six-phase gate voltages.
FIG. 26 is an explanatory diagram showing an operation when a light-shielding film is added to a photosensitive portion of an FT-CCD using a six-phase gate voltage.
FIG. 27 is an explanatory diagram three-dimensionally illustrating an operation of the FT-CCD using six-phase gate voltages.
FIG. 28 is a plan view showing the overall configuration of a FIT-CCD.
[Explanation of symbols]
1 light source
2 Detected object
3 Imaging optical system
4 Image sensor
5 Sensitivity control section
6 storage unit
7 Detection phase setting section
8 Distance calculation section

Claims (10)

An image sensor having a structure in which a plurality of photosensitive units are arranged one-dimensionally or two-dimensionally on a semiconductor substrate, and having a structure capable of controlling the sensitivity of each photosensitive unit by applying a voltage to the semiconductor substrate; And a sensitivity control unit for applying a voltage for modulating the sensitivity of each of the photosensitive units to a semiconductor substrate of the image sensor in synchronization with a modulation signal. Sensor elements including a photosensitive portion for generating signal charges according to the amount of received light and a storage portion for storing signal charges generated in the photosensitive portion are arranged one-dimensionally or two-dimensionally on a semiconductor substrate, and each sensor element An image sensor having a structure in which a transfer unit that reads out accumulated charges from the accumulation unit is formed on the semiconductor substrate, and a sensitivity of the photosensitive unit can be substantially reduced by applying a voltage to the semiconductor substrate;
An imaging optical system for imaging reflected light from the object irradiated by the intensity-modulated light on a surface on which the sensor elements of the imaging element are arranged,
In synchronization with a modulation signal of the intensity-modulated light, a sensitivity control unit that applies a control voltage to reduce the sensitivity of the photosensitive unit to the semiconductor substrate,
A storage unit that reads out the charge accumulated in the accumulation unit of the imaging element over a plurality of cycles of the intensity modulation by the transfer unit and stores the charge as a measurement value,
A detection phase setting unit that switches a phase of a low sensitivity period in which a control voltage for reducing the sensitivity of the photosensitive unit is reduced during one cycle of the intensity modulation every time a measured value is stored in the storage unit.
An image sensor comprising: a distance measurement operation unit that calculates distance information to an object for each sensor element based on a plurality of measurement values having different phases in a low sensitivity period stored in a storage unit. Distance measuring device using. A sensor element including a photosensitive unit for generating signal charges according to the amount of received light and a storage unit for storing signal charges generated in the photosensitive unit is two-dimensionally arranged on a semiconductor substrate, and a storage unit for each sensor element is provided. A transfer unit for reading out the accumulated charge from the semiconductor substrate is formed on the semiconductor substrate, and a signal charge of the photosensitive unit is applied to the semiconductor substrate by applying a high voltage that breaks a potential barrier of the photosensitive unit in a direction perpendicular to the surface of the semiconductor substrate. A distance measuring method using an interline transfer type CCD imaging device having a vertical overflow drain electrode for discarding,
In a state where the reflected light from the object irradiated by the intensity-modulated light is focused on the surface on which the sensor elements of the image sensor are arranged, in synchronization with a modulation signal of the intensity-modulated light, An operation of applying a control voltage to the vertical overflow drain electrode for discarding the signal charges of the photosensitive portion to the semiconductor substrate in a predetermined period in one cycle of the intensity modulation is repeated over a plurality of cycles of the intensity modulation. The first stage;
A second step in which the charge stored in the storage unit of the image sensor in the first step is read by the transfer unit as a measured value;
A third step of switching the phase of the period in which the control voltage is applied to the vertical overflow drain electrode in the first step each time a measurement value is read in the second step;
After the first, second, and third steps are repeated a plurality of times, distance information to the object is calculated for each sensor element based on a plurality of measurement values having different phases during a period in which the control voltage is applied. A distance measuring method using an image sensor. A sensor element including a photosensitive unit for generating signal charges according to the amount of received light and a storage unit for storing signal charges generated in the photosensitive unit is two-dimensionally arranged on a semiconductor substrate, and a storage unit for each sensor element is provided. A transfer unit for reading out the accumulated charge from the semiconductor substrate is formed on the semiconductor substrate, and a signal charge of the photosensitive unit is applied to the semiconductor substrate by applying a high voltage that breaks a potential barrier of the photosensitive unit in a direction parallel to the surface of the semiconductor substrate. A distance measuring method using an interline transfer type CCD imaging device having a horizontal overflow drain electrode for discarding in a direction parallel to the surface of the
In a state where the reflected light from the object irradiated by the intensity-modulated light is focused on the surface on which the sensor elements of the image sensor are arranged, in synchronization with a modulation signal of the intensity-modulated light, A first step of repeating an operation of applying a control voltage to the horizontal overflow drain electrode for discarding the signal charges of the photosensitive section in a predetermined period in one cycle of the intensity modulation over a plurality of cycles of the intensity modulation; and ,
A second step in which the charge stored in the storage unit of the image sensor in the first step is read by the transfer unit as a measured value;
A third step of switching the phase of a period during which the control voltage is applied to the horizontal overflow drain electrode in the first step each time a measured value is read in the second step;
After the first, second, and third steps are repeated a plurality of times, distance information to the object is calculated for each sensor element based on a plurality of measurement values having different phases during a period in which the control voltage is applied. A distance measuring method using an image sensor. Equipped with three or more photosensitive units for generating signal charges in accordance with the amount of received light, and by applying a potential to the specific photosensitive unit excluding both ends to collect signal charges from other photosensitive units, the specific photosensitive unit An imager configured to two-dimensionally arrange sensor elements configured to accumulate signal charges on a semiconductor substrate, and a transfer unit configured to read out accumulated charges from each sensor element of the imager on the semiconductor substrate; A frame transfer type CCD having a vertical overflow drain electrode for discarding signal charges of the photosensitive portion to the semiconductor substrate by applying a high voltage that breaks a potential barrier of the photosensitive portion in a direction perpendicular to the surface of the substrate. A distance measuring method using an image sensor,
In a state where the reflected light from the object irradiated by the intensity-modulated light is focused on the surface on which the sensor elements of the image sensor are arranged, in synchronization with a modulation signal of the intensity-modulated light, The signal charges of the other photosensitive portions are retained while leaving the signal charges accumulated in the specific photosensitive portion among the three or more photosensitive portions constituting each of the sensor elements in a predetermined period in one cycle of the intensity modulation. A first step of repeating an operation of applying a control voltage to the vertical overflow drain electrode to be discarded to the semiconductor substrate over a plurality of cycles of the intensity modulation;
A second step of reading out the electric charge accumulated in the specific photosensitive portion of each of the sensor elements in the first stage as a measurement value by the transfer unit;
A third step of switching the phase of the period in which the control voltage is applied to the vertical overflow drain electrode in the first step each time a measurement value is read in the second step;
After the first, second, and third steps are repeated a plurality of times, distance information to the object is calculated for each sensor element based on a plurality of measurement values having different phases during a period in which the control voltage is applied. A distance measuring method using an image sensor. Equipped with three or more photosensitive units for generating signal charges in accordance with the amount of received light, and by applying a potential to the specific photosensitive unit excluding both ends to collect signal charges from other photosensitive units, the specific photosensitive unit An imager configured to two-dimensionally arrange sensor elements configured to accumulate signal charges on a semiconductor substrate, and a transfer unit configured to read out accumulated charges from each sensor element of the imager on the semiconductor substrate; A frame transfer type CCD imaging device having a horizontal overflow drain electrode for discarding signal charges of the photosensitive portion by applying a high voltage that breaks a potential barrier of the photosensitive portion in a direction parallel to the surface of the substrate was used. A distance measuring method,
In a state where the reflected light from the object irradiated by the intensity-modulated light is focused on the surface on which the sensor elements of the image sensor are arranged, in synchronization with a modulation signal of the intensity-modulated light, The signal charges of the other photosensitive portions are retained while leaving the signal charges accumulated in the specific photosensitive portion among the three or more photosensitive portions constituting each of the sensor elements in a predetermined period in one cycle of the intensity modulation. A first step of repeating an operation of applying a control voltage to be discarded to the horizontal overflow drain electrode over a plurality of cycles of the intensity modulation;
A second step of reading out the electric charge accumulated in the specific photosensitive portion of each of the sensor elements in the first stage as a measurement value by the transfer unit;
A third step of switching the phase of a period during which the control voltage is applied to the horizontal overflow drain electrode in the first step each time a measured value is read in the second step;
After the first, second, and third steps are repeated a plurality of times, distance information to the object is calculated for each sensor element based on a plurality of measurement values having different phases during a period in which the control voltage is applied. A distance measuring method using an image sensor. 7. The sensor section according to claim 5, wherein the sensor section comprises four or more photosensitive sections, and the signal charges of the other photosensitive sections are discarded while leaving the signal charges accumulated in the specific photosensitive section. In the period, the imaging device is characterized in that a voltage that forms a potential barrier that electrically isolates the specific photosensitive portion from other photosensitive portions is applied to the photosensitive portion adjacent to the specific photosensitive portion. The ranging method used. 8. The method according to claim 7, wherein a light-shielding portion is formed on a surface of the photosensitive portion where the specific photosensitive portion and the potential barrier are formed. The sensor element includes a photosensitive unit that generates signal charges according to the amount of received light, a storage unit that stores the signal charges generated in the photosensitive unit, and an electric switch that opens and closes the transfer of the signal charges from the photosensitive unit to the storage unit. A transfer section for one-dimensionally or two-dimensionally arranging the semiconductor elements on the semiconductor substrate and reading out the accumulated charges from the accumulation section of each sensor element is formed on the semiconductor substrate, and the electric power is applied by applying a voltage to a specific electrode of the semiconductor substrate. An image sensor having a structure capable of opening and closing a switch at a high frequency;
An imaging optical system for imaging reflected light from the object irradiated by the intensity-modulated light on a surface on which the sensor elements of the imaging element are arranged,
Synchronous with the modulation signal of the intensity-modulated light, a synchronous integration control unit that applies a control voltage for closing the electric switch to the specific electrode of the semiconductor substrate, and a plurality of cycles of the intensity modulation. A storage unit that reads out the charge stored in the storage unit of the imaging element by the transfer unit and stores the charge as a measured value,
A detection phase setting unit that switches a phase of a synchronous integration period in which a control voltage for closing the electric switch is applied during one cycle of the intensity modulation every time a measured value is stored in the storage unit.
An image sensor comprising: a distance measurement operation unit that calculates distance information to an object for each sensor element based on a plurality of measurement values having different phases of a synchronous integration period stored in a storage unit. Distance measuring device using. 10. The transfer unit according to claim 9, wherein a transfer electrode for sequentially transferring signal charges stored in the storage unit to an adjacent storage unit is formed on a surface of the storage unit, and the transfer electrode is formed on the transfer electrode. During a period in which a voltage for transferring signal charges is not applied, a voltage for transferring the signal charges generated in the photosensitive section to the transfer electrode to the storage section and a signal charge generated in the photosensitive section are stored in the storage section. A distance measuring device using an image sensor, wherein an electric switch is configured to open and close the transfer of signal charges from the photosensitive section to the storage section at a high frequency by alternately applying a voltage not to be transferred.

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