JP2003520967A - Printed circuit assembly with configurable boundary scan path - Google Patents

Abstract

A printed circuit assembly (PCA) with a configurable boundary scan path. A printed circuit assembly having a plurality of integrated circuits configured for boundary scan testing includes a plurality of switches. The use of these switches allows a plurality of boundary scan paths to be combined into a common boundary scan path. These switches can be used to combine various configurations of scan paths, such as multiple independent scan paths and parallel shared scan paths. The type of switch used can include a multiplexer, demultiplexer, relay, or other type. The PCA can be tested on an automated test equipment (ATE), such as a bed of nail in-circuit tester, configured to perform a boundary scan test.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates to testing electronic circuits, and more particularly to the use of boundary scan to test printed circuit assemblies.

Description of Related Art Boundary scan is one of the solutions for testing integrated circuits with large numbers of gates and pins. As the gate and pin counts of integrated circuits have increased, device level testing of integrated circuits on printed circuit assemblies (PCAs) has become increasingly difficult and, in many cases, impractical. Device level testing involves driving logic stimuli to the input of the device and monitoring the resulting output. Such tests may require the production of very large numbers of test vectors. Despite the difficulties of device level testing, there is a continuing need to ensure that the correct device is mounted on the printed circuit board in the correct orientation with the correct solder connections. Boundary scans may provide a solution to this problem.

Boundary scan testing is performed between the core logic of the device and its external pin connections. Boundary scan device configurations typically include boundary scan cells, each of which is located between a signal pin and the device's core logic. Multiple of these boundary scan cells can be connected together to form a boundary scan chain or boundary scan path. FIG. 1 is a diagram of an exemplary integrated circuit (IC) configured for boundary scan testing. This I
C includes a plurality of boundary scan cells connected in a chain.
During normal IC operation, data is transferred to the core through the boundary scan cell.
It can pass unimpeded between logic and signal pins. During a boundary scan test operation, test data enters the IC via the TDI (test data in) pin and passes through the chain of boundary scan cells to the TDO (
The test data out) pin can be used to exit the chip. In essence, a chain of boundary scan cells acts as a shift register, as data bits can be shifted from one cell to the next. The state of each boundary scan cell can be monitored during the scan shift via a signal pin associated with the output signal or the bidirectional signal. For example, during a boundary scan test of the exemplary IC shown in FIG. 1 (assuming all pins are bidirectional), when data bits are shifted through the boundary scan path. An automated test equipment (ATE) can monitor the status of each boundary scan cell via its associated signal pin. During the shifting of data through the boundary scan path, each cell typically makes multiple transitions between a logic high level and a logic low level. In the presence of defects (such as unsoldered signal pins), the ATE cannot detect the expected state for a given cell at a given time, causing a test failure. In this way, defective signal connections can be detected. For input signals, test data can be driven into the boundary scan cell via its associated signal pin and monitored via the TDO pin after shifting through the scan chain.

Boundary scan tests are often performed at the PCA level, where multiple boundary scan ICs are mounted on a printed circuit board (PCB). For this purpose, a long board level scan path is created by coupling the TDO output of one boundary scan IC to the TDI input on another PCA. As boundary scan tests were developed, several different types of substrate level scan paths were used. Figure 2
FIG. 6 is a block diagram of a single scan pass. In this figure, multiple boundary scan ICs are chained together by coupling the TDO output to the TDI input. The TMS (test mode select) signal is used to put the chip in test mode and the TCK (test clock) provides the clock signal necessary to shift the data through the scan chain.

Multiple independent scan paths are shown in FIG. The illustrated arrangement includes two separate single scan paths, each with its own set of test signals (TDI and TDO) and control signals (TMS and TCK). These scan paths can be tested either sequentially or simultaneously.

Another common configuration is the parallel shared scan path shown in FIG. In this configuration, two separate scan paths share the TDI and TDO signal connections. Each path has its own TMS and TCK signals. Since the TDI and TDO signals are shared, only one scan path can be examined at any given time.

In general, many scan path configurations are possible, with each configuration having certain advantages and disadvantages. Some configurations are simpler to implement during the design of the printed circuit assembly, but make the test vector generation more difficult. Other configurations result in simpler test solutions, but longer test times or lower test coverage.

SUMMARY OF THE INVENTION The problems outlined above are primarily solved by a printed circuit assembly (PCA) designed with a configurable boundary scan path. In one embodiment, the PCA is designed with multiple boundary scan paths. These paths can have different configurations. A switch is attached to the printed circuit assembly in a manner that allows the boundary scan paths to be connected together. These switches can be used to configure multiple boundary scan paths into a single common boundary scan path. PCA is
You can take the boundary scan test with an automatic test equipment (ATE) such as a bed of nail type in-circuit tester. During test, the tester can drive control signals to the UUT (unit under test or PCA under test) to configure the boundary scan path. Boundary scan testing can be performed when the UUT is properly configured.

The switches used to construct the boundary scan path can be in various forms. In one implementation, multiple 2-to-1 multiplexers and 1-to-2 multiplexers may be used to form a boundary scan path. Various other types of switches may be used in other implementations. Control of the switch is done by the ATE during the test.

Thus, in various implementations, a configurable boundary scan path may provide greater flexibility in creating a boundary scan test solution for the PCA in which it is implemented. Since multiple scan path configurations are available, the test engineer can choose among multiple test solutions, which allows for maximum test coverage. Such a test solution may be easier to implement than the solution for non-configurable boundary scan paths.

Other objects and advantages of the present invention will become apparent when reading the following detailed description and referring to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. However, the drawings and the detailed description thereto are not intended to limit the invention to the particular forms disclosed, but on the contrary, the spirit and scope of the invention as defined by the claims It is to be understood that it includes all modifications, equivalents, and alternatives included in.

DETAILED DESCRIPTION OF THE INVENTION Turning to FIG. 5, a bed of nail in-circuit test (on which a printed circuit assembly having a configurable boundary scan path is tested).
An embodiment of an ICT) system 100 is shown. The ICT system 100 includes an instrument bay 101 and a test fixture 102. The fixture interface 103 on top of the instrument bay 101 is configured to electrically couple the test fixture 102 to the instrument bay 101. The test fixture 102 includes a plurality of test probes 1 configured to make electrical contact with test points located on the printed circuit assembly 200.
04 is included. The test probe 104 is electrically coupled to the fixture interface 103 via a fixture wire 105,
The wires 105 are usually arranged as twisted pairs. Retainer 106 is configured to secure printed circuit assembly 200 in place during testing.

During testing, the instrument bay 101 is configured to drive test signals to the printed circuit assembly 200 via the fixture interface 103, the fixture wires 105, and the test probes 104. Measuring instrument bay 101
Can also receive a response signal from the printed circuit assembly 200. The signals driven from the instrument bay 101 to the printed circuit assembly (PCA) 200 can include analog and / or digital signals. Specifically, the instrument bay 101 drives the test data in (TDI) node on the PCA to drive a digital signal for a boundary scan test, so that the PCA test data
Signals can be received from the Out (TDO) node. The instrument bay 101 is configured to determine pass / fail status for a given test of PCA.
The measuring instrument bay 101 sends control signals such as a TMS (test mode selection) signal and a TCK (test clock) signal necessary for the boundary scan test to the PCA under test
It is also configured to drive. In addition, the instrument bay 101 can also drive control signals for switch positioning to a PCA that has switches to connect the boundary scan paths together.

Turning to FIG. 6, a diagram of one embodiment of a PCA 200 that includes two independent scan paths with switches that reconfigure the paths is shown. Integrated circuit (IC) 300
Mounted on a printed circuit board (PCB) 250. Each IC300 is
Configured for boundary scan testing. In the illustrated embodiment, there are two independent scan paths, represented by signal lines 400A and 400B, respectively (this configuration is shown in more detail with respect to FIG. 7). Signal line 450 connects two independent scan paths through switch 350S to form a single common scan path. Switch 350S in this embodiment includes both a multiplexer and a demultiplexer. When testing with the path connected, test data is driven into PCA 200 via test point 420TDI, which test data exits the scan chain via test point 420TDO. The TMS control signal and the TCK control signal are driven to test points 420TMS and 420TCK, respectively. These control signals are common to both independent scan paths when they are connected to form a common scan path. The individual control signals of each path are connected via the switch 350T and internal signal lines.

FIG. 7 is a block diagram illustrating an embodiment that uses switches to configure two independent scan paths into a single scan path. In the illustrated embodiment, the IC
300 is configured for boundary scan testing. The scan path is formed by connecting the tdo output of a given IC 300 to the tdi input of the next IC 300 in the path. Two switches 350S and a single path (indicated by a dashed line) can be used to connect the two boundary paths together to form a common boundary scan path. Similarly, when forming a single boundary scan path, separate TMS and TCK signals (ie, TMS1 and TMS2 and TCK1 and TCK2) are provided to switch 350.
T and signal paths can be used to connect. The type of switch used can include multiplexers, demultiplexers, relays, and / or various other types of switches.

When performing the boundary scan test in the embodiment shown in FIG. 7, the switch control signal causes the switch to connect two independent scan paths to form a common scan path. It constitutes 350S. Similarly, switch 350T is configured such that the entire scan chain is controlled by test control signals TMS1 and TCK1. With the switches properly configured, test data can be shifted in through the TDI-1 signal path of the first scan chain. Each IC 300 has a plurality of boundary scan cells 33.
Contains 0, through which test data is shifted. During the shift, the status of each boundary scan cell can be monitored via signal pin 320 by an automatic tester (such as that described with respect to FIG. 5). Test data is TDO
It can be shifted out of the scan path via the -2 signal path. The test result can be determined based on the state of each boundary scan cell during the shift of the test data.

FIG. 8 is a block diagram illustrating an embodiment that uses switches to configure two parallel shared scan paths into a single scan path. The illustrated embodiment includes a plurality of ICs 300 configured for boundary scan testing.
Each C300 includes a plurality of boundary scan cells 330, which are monitored during testing via signal pin 320. Two separate scan paths share a common TDI input and TDO output. The switch 350S allows the two boundary scan paths to be electrically coupled, thus forming a single common boundary scan path. Similarly, when forming a common boundary scan path, separate TMS and TCK signals (ie, TMS1 and TMS2,
TCK1 and TCK2) can be connected using a switch 350T and a signal path. With the switch properly configured, test data can
It can be shifted into the boundary scan path via the DI signal path. When the switches are configured to form a common scan path, the test data goes through the first path (the upper path in the figure) before the test data exits the chain through the common TDO signal path, then , The test data can be shifted via the second pass.

In general, switches can be used to connect the paths, and any number of scan paths can be combined to form a common scan path. Further, the combined boundary scan paths can have different configurations. For example, embodiments are contemplated in which multiple independent scan paths are combined with parallel shared scan paths to form a common boundary scan path. Moreover, other scan path configurations not explicitly described herein can also be combined to form a single scan path.

Although the present invention has been described with respect to particular embodiments, the embodiments are illustrative and
It should be understood that the scope of the invention is not so limited. All variations, modifications, additions and improvements of the described embodiments are possible. These variations, modifications, additions and improvements can fall within the scope of the invention as detailed in the claims.

[Brief description of drawings]

FIG. 1 is a block diagram of an exemplary integrated circuit configured for boundary scan testing (prior art).

[Fig. 2]   FIG. 3 is a block diagram of a single scan path configuration (prior art).

[Figure 3]   FIG. 3 is a block diagram of multiple independent scan path configurations (prior art).

[Figure 4]   FIG. 3 is a block diagram of a parallel shared scan path configuration (prior art).

FIG. 5 is a diagram of one embodiment of an in-circuit test system capable of performing a boundary scan test.

FIG. 6 is a diagram of an embodiment of a printed circuit assembly including two independent scan paths with switches to reconfigure the paths.

FIG. 7 is a block diagram illustrating an embodiment that uses switches to configure two independent scan paths into a common scan path.

FIG. 8 is a block diagram illustrating an embodiment that uses switches to configure two parallel shared scan paths into a common scan path.

[Procedure for Amendment] Submission for translation of Article 34 Amendment of Patent Cooperation Treaty

[Submission date] April 4, 2002 (2002.4.4)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Contents of correction]

[Claims]

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Claims (22)

[Claims] 1. A printed circuit board including a plurality of boundary scan signal paths for a boundary scan test, and a plurality of integrated circuits mounted on the printed circuit board and including signal connections for supporting the boundary scan test. A circuit mounted on the printed circuit board and configured to selectively connect one of the plurality of boundary scan signal paths to another of the plurality of boundary scan signal paths, thereby providing a common A printed circuit assembly including at least one switch that produces a boundary scan signal path. 2. The printed circuit assembly of claim 1, wherein the printed circuit assembly includes a plurality of test points for testing on an automatic test equipment (ATE). 3. The printed circuit assembly according to claim 2, wherein the automatic test device is a bed of nail type in-circuit tester. 4. The printed circuit assembly of claim 3, wherein a plurality of test points are configured to receive control signals for positioning the switch from the bed of nails in-circuit tester. 5. The printed circuit assembly of claim 3, wherein a test data in force signal is driven to the printed circuit assembly by the bed of nail in-circuit tester. 6. The printed circuit assembly of claim 3, wherein a test data out force signal is received by the bed of nail in-circuit tester. 7. The printed circuit assembly of claim 1, wherein the boundary scan signal path is an independent scan path. 8. The printed circuit assembly of claim 1, wherein the boundary scan signal paths are shared parallel scan paths. 9. The printed circuit assembly of claim 1, wherein the switch is a multiplexer. 10. The printed circuit assembly of claim 1, wherein the switch is a demultiplexer. 11. The printed circuit assembly of claim 1, wherein the switch is a relay. 12. Each of the integrated circuits has a test data in (TDI).
The printed circuit assembly of claim 1, including signal connections for signals. 13. Each of said integrated circuits has a test data out (TDO).
The printed circuit assembly of claim 1 including signal connections for signals. 14. The printed circuit assembly of claim 1, wherein each of the integrated circuits includes a signal connection for a test clock (TCK) signal. 15. The printed circuit assembly of claim 1, wherein each of the integrated circuits includes a signal connection for a test mode select (TMS) signal. 16. A unit under test, comprising a printed circuit board having a plurality of test points, comprising a plurality of boundary scan signal paths and at least one switch mounted on said printed circuit board, said switch comprising: ,
A printed circuit assembly (PCA) configured to selectively connect one of the plurality of boundary scan paths to the other of the plurality of boundary scan paths to create a common boundary scan signal path. A test fixture that includes a plurality of test probes configured to make electrical contact with the test points, the test fixture mounting the PCA during a test, and driving a test signal to the PCA during the test. A test system that receives a response signal from the PCA and a fixture interface that couples the test fixture to the instrument bay. 17. The test system of claim 16, wherein the instrument bay is further configured to drive a control signal to the PCA during the test. 18. The test system of claim 17, wherein the control signal comprises a signal that controls the switch. 19. The test system of claim 17, wherein the control signal comprises a test mode select (TMS) signal. 20. The test system of claim 17, wherein the control signal comprises a test clock (TCK) signal. 21. The test system of claim 16, wherein the test fixture includes a plurality of wires configured to couple the test probe to the fixture interface. 22. A method of testing a printed circuit assembly (PCA) having a plurality of boundary scan signal paths, wherein one of the plurality of boundary scan signal paths is provided to create a common boundary scan signal path. Driving a switch control signal to at least one switch configured to selectively connect one to another of the plurality of boundary scan signal paths, each having a plurality of boundary scan cells. Driving test control signals to the integrated circuit, driving test data to the printed circuit assembly via a test data in force (TDI), and driving the test data to the common boundary scan path. Shifting the state of the boundary scan cell during the shift. How it, and comprises determining a test result based on the state of the boundary-scan cells in the shift to view.