JP2003512716A - Multi-metal layer assembly for wire bond tape ball grid array package - Google Patents

Abstract

(57) Abstract: An apparatus for packaging a semiconductor device that provides a flexible trace placement circuit having a first dielectric substrate. The first dielectric substrate has a first conductive layer thereon and at least one solder ball receiving passage formed through the first dielectric substrate. The first conductive layer includes a plurality of conductive traces having solder ball pads adjacent to the individual solder ball receiving passages to form a closed end. The first adhesive layer is attached to the first conductive layer. The flexible reference plane circuit includes a second dielectric substrate having at least one reference voltage plane. The reference voltage plane is joined to the first adhesive layer and is electrically connected to the first conductive layer via the first adhesive layer. The semiconductor device receiving passage extends through the trace placement circuit, the first adhesive layer, and the first reference voltage plane circuit. The stiffener member is bonded to the second dielectric substrate.

Description

Detailed Description of the Invention

TECHNICAL FIELD The disclosure herein relates generally to tape ball grid arrays (TBGAs) and, more particularly, using insulation displacement vias (IDVs), solder filled vias or other known connection techniques. A flexible circuit having a ground plane circuit electrically connected to the ground plane.

BACKGROUND Tape ball grid array (TBGA) packages offer outstanding electrical and thermal performance, high reliability, and proven compatibility with wire bond die assembly and subsequent card assembly methods. provide. One of the salient features of some TBGA package constructions is the use of a carrier film as a solder mask by inverting the tape. The current cost of TBGA wirebond supports is significantly higher than the cost of flexible circuits alone. Significant cost drivers for this assembly are stiffer materials, flexible circuit fabrication, adhesive patterning, and alignment / lay up. A close examination of the value proposition of TBGA wirebond supports reveals that the market requirements currently met by wirebond support products are better met by new, more cost-effective product configurations.

To design an effective TBGA circuit, the ground plane must be closely spaced adjacent to the fine pitch traces on the TBGA tape. This ground plane provides electromagnetic damping and heat dissipation for the circuit. In the prior art, stiffeners are often metal parts that are grounded to form the required ground plane. In a typical prior art device, a polyimide tape has fine pitch traces placed on the tape and attached with adhesive to a rigid metal stiffener. A problem with prior art solutions is cost. The patterned adhesive layer must be precisely registered when laminating the flexible circuit to the stiffener. When possible and practical, it is desirable to avoid patterning, deposition and registration steps. These steps add significant cost to the manufacturing process.

IDV is less reliable than other connection methods such as solder bumps or solder filled vias. However, IDVs are substantially cheaper to manufacture than other types of connections. Reliability issues with IDV interconnections make them unsuitable for signal via connections. IDV connections are suitable for use in power and ground circuit connections where redundant vias or connections are formed. If one IDV interconnect is defective or unusable, this interconnect will not adversely affect overall device performance. In this case, the IDV can be used to connect the ground plane to the flexible circuit.

British Patent No. 2,157,085 to Caton discloses a first circuit layer having at least one first conductive layer thereon and a second circuit layer having at least one conductive trace thereon. A circuit layer, the first and second traces each having an enlarged connection pad of a predetermined configuration in opposed positions, the ultrasonic welding means interconnecting the first and second traces at the enlarged connection pad. A multi-metal layer circuit arrangement is disclosed.

US Pat. No. 5,379,512 to Ingle et al. Discloses a method of coupling the ends of conductors to a circuit pad in which a cable is placed over the circuit pad. It The bond tool is then pressed against the top surface of the cable with sufficient pressure to compress the substrate beyond the elastic limit of the substrate. Ultrasonic energy is applied to the bonding tool and transmitted through the substrate to affect the metallic bond between the conductor and the circuit pad.

In US Pat. No. 5,661,088, a method of packaging electronic components includes forming holes in a substrate having a first surface opposite a second surface. The method also includes disposing and patterning the malleable layer on the first surface and the holes in the substrate. The malleable layer has a third surface opposite the fourth surface. Part of the fourth surface is exposed by the holes in the substrate. The conductive layers are simultaneously disposed on different parts of the third surface of the malleable layer. The semiconductor die is then bonded to the malleable layer and the encapsulant material is placed under the semiconductor die and over the holes.

US Pat. No. 5,519,936 and US Pat. No. 5,561,323 each include a rigid support member, such as a copper sheet, to which both the semiconductor chip of the package and the circuitized substrate member are joined. Electronic packages are disclosed. The chip is bonded using a thermally conductive adhesive and the circuitized substrate, preferably a flexible circuit, is
Bonded using an electrically insulating adhesive. The chip is electrically coupled to a designated portion of the substrate circuit, preferably by wire bonding, thermocompression bonding or thermosonic bonding. The encapsulant is used to cover and protect the connection between the chip and the substrate. As a result, the package is electrically coupled to another second substrate, such as a PCB.

US Pat. No. 5,585,162 separates from the other parts of the ground plane, but separates it from the first via by circuit traces on the side of the flexible circuit that faces the ground plane. Flexibility that allows mass reflow bonding of solder balls to the ground plane of a double-sided flexible circuit by forming a first via that is electrically connected to the ground plane through only a second via. A circuit configuration is disclosed. In this device, metallized through holes or metallized blind vias interconnect the layers on the TBGA.

None of the current product configurations or design techniques adequately address cost-effective methods for manufacturing circuit assemblies with reference planes. Therefore, there is an increasing need for substrate packages and manufacturing methods that overcome the shortcomings of the prior art. More specifically, there is an increasing need for PCB constructions in which trace placement circuits and ground plane circuits can be manufactured separately using methods that optimize the specific design and functional requirements of the circuits. The reference plane circuit lacks the fine pitch details of the trace placement circuit. Therefore, the reference plane circuit can be manufactured using a cheaper method than the trace placement circuit. The use of low cost interconnect technology, such as isolation displacement vias, is one of the technologies that helps provide a cost effective product configuration.

DISCLOSURE OF THE INVENTION Accordingly, in one embodiment, a multi-layer circuit is provided for attaching a semiconductor die to a substrate, such as a printed circuit board, for cost sensitive applications. For this purpose, the multilayer circuit assembly comprises a trace placement circuit having a first dielectric substrate. The first conductive layer is formed on the first surface of the first dielectric substrate. The first adhesive layer is attached to the trace placement circuit and the reference plane circuit is attached to the first adhesive layer. The reference plane circuit comprises a second dielectric substrate having at least one conductive reference plane formed thereon. Each conductive reference plane is electrically connected to the first conductive layer via the first adhesive layer.

The main advantage of this embodiment is that the reference plane circuits can be manufactured, mounted and electrically connected in a more cost-effective manner than previous reference plane construction techniques. The reference plane circuit and the trace placement circuit can be manufactured separately using the most cost effective techniques and later bonded together. Part of the cost effectiveness results from patterning the ground plane at the same time as the reference plane circuit is manufactured. In addition, unlike the prior art, ground plane circuits are bonded using readily available adhesives and electrically connected to trace placement circuits using inexpensive interconnection methods such as insulation displacement vias. Can be interconnected.

Detailed Description of the Preferred Embodiments In one embodiment, as shown in FIGS. 1-3, trace placement circuit 2 comprises a first dielectric layer having a first conductive layer 8 formed on a first side thereof. A substrate 4 is provided. The plurality of solder ball storage passages 6 are formed so as to penetrate the first dielectric substrate 4. The first conductive layer 8 is patterned such that the solder ball pad 12 comprises a plurality of traces 10 formed adjacent the solder ball receiving passage 6 to form a closed end 14. The reference plane circuit 16 comprises a second dielectric substrate 18 having at least one reference plane 20 formed on its first side. To assemble the circuit assembly 1 shown in FIG. 3, an adhesive layer 22 is formed between the trace placement circuit 2 and the reference plane circuit 16 to bond these circuits together.

The trace placement circuit and the reference plane circuit can be assembled in any of the many different ways well known in the prior art. The preferred method is Klun
No. 5,227,008 to U.S. Pat. This patent discloses a method of etching features in or through a dielectric substrate to plate a conductive material onto the dielectric substrate. The following is a brief overview illustrating the main aspects of the circuit assembly method disclosed in this patent.

Photoresists are formed on both sides of the dielectric substrate. If desired, the photoresist on the first side of the dielectric substrate can be patterned using photolithographic techniques to provide features to be plated onto the dielectric substrate. The photoresist on the opposite side of the dielectric substrate can also be patterned using photolithographic techniques to include features formed on the dielectric substrate by such means as chemical etching. Once the features to be plated are thus formed, they are then plated. If features are to be formed in or through the dielectric substrate, then the second side of the substrate is etched or otherwise processed. The photoresist is stripped, if necessary, to complete subsequent processing steps such as coating plating and the like.

The reference plane circuit 16 mainly has only macroscopic features as compared with the features of the trace placement circuit 2. Thus, the advantages of the exemplary embodiments described herein are:
The reference plane circuit 16 can be manufactured separately from the trace placement circuit 2. Kl
Reference plane circuit 16 can be assembled using a variety of inexpensive assembly techniques different from those disclosed in U.S. Pat. No. 5,227,008 to Un et al. These types of techniques include direct screen printing of a conductive material in a desired pattern on a dielectric substrate, laminating a die cut conductive foil pattern onto a dielectric substrate using an adhesive, and Other technologies can be mentioned.

FIG. 4 shows a circuit assembly 1 having a trace placement circuit 2 having a second conductive layer 21 formed on a second side of a first dielectric substrate 4. The second conductive layer 21 is patterned to include a plurality of traces 23. One or more conductive vias 25 are
At least a portion of trace 23 of second conductive layer 21 is interconnected with trace 10 of first conductive layer 8. Although conductive vias 25 are shown, other interconnection technologies such as IDV and the like may be used. The solder mask 27 is formed on the second conductive layer in which the via 6 is formed. Solder mask 27 is manufactured from a photoimageable material so that vias 6 can be formed using photolithographic techniques.

5A and 5B show the basic method of forming the IDV connection 28 between the trace 10 of the first conductive layer 8 and the reference plane 20. The tip 24 of the bonding tool exerts pressure and / or heat on the solder ball pad 12. The first adhesive layer 22 is displaced from underneath the bonding tool tip 24 and the trace 12 is bonded to the reference plane 20.

Next, referring to FIG. 6, the circuit assembly 1 is attached to the stiffener member 32. One technique for attaching the stiffener member 32 to the circuit assembly 1 is to use the second adhesive layer 30 to adhere the stiffener member 32 to the second dielectric substrate 18. Depending on the particular application, the second adhesive layer 30 may be bonded to the circuit assembly 1 by the party making the circuit assembly 1. Alternatively, the second adhesive layer 30 may be integrated with the stiffener member 32. The second party may later apply the stiffener member 32. In either case, joining of the stiffener member 32 at a time different from the time of manufacturing the circuit assembly 1 is simplified.

In a preferred embodiment, the first and second dielectric substrates 4, 18 are DuPont.
May be a polyimide film sold under the trademark KAPTON E. The first adhesive layer 22 may be a polyimide-based adhesive commercially available from DuPont under the KJ trademark. A preferred material for the second adhesive layer 30 is Minnesota Mini.
ng and Manufacturing Co. Can be any pressure sensitive adhesive sold under the trademark VHB. While the above materials are preferred, it will be apparent to those skilled in the art that many other commercially available materials suitable for various dielectric substrates and adhesive layers will be apparent.

In FIG. 7, solder plugs 38 are formed in solder plug vias 40 to interconnect the traces 10 of the first conductive layer 8 to the reference plane 20. Solder plug via 40 can be formed using any of the many techniques well known in the prior art. For example, chemical etching, laser cutting, plasma etching, mechanical drilling or other known methods can be used to form solder plug vias through the reference plane circuit. The first adhesive layer 22 is
The vias may be bonded to the circuit assembly prior to forming the vias to form a passage through the adhesive layer. At the same time that the solder plug via 40 is formed, the first adhesive layer 22
By forming the vias, problems associated with the alignment of the first adhesive layer 22 with respect to the trace placement circuit 2 and the reference plane circuit 16 can be avoided.

Trace placement circuit 2 using commercially available and well known stacking techniques.
, The first adhesive layer 22 and the reference plane circuit 16 are aligned and held and laminated to form the circuit assembly 1 having the solder plug vias 40 shown in FIG. 7. After this laminating method, screen the solder paste in vias,
A solder reflow operation is performed on the circuit assembly to form the solder plug 38. Alternatively, via 38 may be formed using any of the many electroless plating methods known in the art.

As shown in FIG. 8, the circuit assemblies 1 can be formed continuously or in a panel manner, but two or more circuit assemblies 1 are separated from each other using a cutting method. There is a need. A significant advantage of the exemplary embodiments described herein is the reference plane 20.
And is configured to withstand a short circuit between the plating bus 58. In the conventional construction technique using the stiffener member as the reference plane, the plating bath 58 may be deformed and contaminated by the cutting process, and as a result, the plating bath 58 may come into contact with the stiffener member to cause a short circuit. The ablation process and instruments are well known in the prior art and will not be described in detail herein.

The plating bath 58 maintains electrical continuity between two adjacent circuit assemblies 1 to facilitate panel and roll-to-roll electroplating. By providing an appropriate space between the reference planes 20 of two adjacent circuit assemblies 1 at a position where the cutting tool 58 contacts the platen 59 to separate the circuit assemblies 1, the bus trace 58 and the reference plane 20 are separated from each other. The possibility of a short circuit between them can be greatly reduced, if not eliminated. The space between two adjacent reference planes 20 allows the first adhesive layer 22 to effectively insulate each reference plane 20 from the isolated plating bath 58.

FIG. 9 shows a circuit assembly, generally designated 100, having a second reference plane 120 ′ on the side of the second dielectric substrate 118 opposite the first reference plane 120. In many electronic component packaging applications, the first reference plane 120 is used to provide the first reference voltage,
It is desirable to use the second reference plane 120 'to provide the second reference voltage. The solder plugs 138, 138 'connect the reference planes 120, 120' to the individual traces 11
Can be used to interconnect 0. As shown, solder plug 1
38, 138 ′ are located adjacent to the solder ball pad 112. This is desirable in that the area of the solder ball pad 112 is significantly larger than the other areas of the trace 110. The reference plane 120 ′ may have a recessed area 141 so that the solder plug 138 for the first reference plane 120 is formed from the same plane as the solder plug 138 ′ for the second reference plane 120 ′. Recessed area 141
Is the solder plug 138 connected to the first reference plane 120.
Prevent contact with 0 '.

In practice, the exemplary embodiments described herein include a circuit assembly in which the trace placement circuit is attached to a separate reference plane circuit by a dielectric material such as a non-conductive adhesive or the like. I will provide a. At least a portion of the conductive traces of the trace placement circuit are connected to a reference plane on the reference plane circuit. These traces send and receive signals and power between devices packaged on the PCB. The reference plane is P
A desired voltage is maintained to provide a reference voltage to one or more devices packaged on the CB. Depending on the application, the voltage across the reference plane is generally 0.
． It is 0V to 5.0V. If the two circuits with the plating bath in between are mechanically separated from each other, it is preferable that there is a gap between the reference planes where the circuits are separated.

As a result, one embodiment provides a multilayer circuit assembly having a trace placement circuit that includes a first dielectric substrate. The at least one solder ball receiving passage has a first
It is formed penetrating the dielectric substrate. The first conductive layer is formed on the first surface of the first dielectric substrate. The first adhesive layer is attached to the trace placement circuit, and the reference plane circuit is attached to the first adhesive layer on the surface facing the trace placement circuit. The reference plane circuit comprises a second dielectric substrate having at least one conductive reference plane formed thereon. Each of the at least one reference plane is electrically connected to the first conductive layer via the first adhesive layer.

Another embodiment provides an apparatus for packaging a semiconductor device having a trace placement circuit with a flexible first dielectric substrate. At least one solder ball receiving passage is formed through the flexible first dielectric substrate. The first conductive layer is formed on the first surface of the flexible first dielectric substrate. The first adhesive layer is affixed to the trace placement circuit and the flexible reference plane circuit is on the first side of the surface facing the trace placement circuit.
It is attached to the adhesive layer. The reference plane circuit comprises a flexible second dielectric substrate having at least one conductive reference plane formed thereon. Each of the at least one reference plane is electrically connected to the first conductive layer via the first adhesive layer. The semiconductor device accommodating passage is formed so as to extend through the trace arrangement circuit, the first adhesive layer and the reference plane circuit. The stiffener member is attached to the flexible second dielectric substrate.

Yet another embodiment provides a multilayer circuit assembly having a trace placement circuit that includes a first dielectric substrate. At least 1 is included in the traces of the first dielectric substrate.
One solder ball receiving passage is formed through the first dielectric substrate, and a first conductive layer is formed on the first surface. The first conductive layer comprises a plurality of traces having patterned solder ball pads adjacent the respective solder ball receiving passages and forming closed ends with the passages. The first adhesive layer is attached to the first conductive layer and the reference plane circuit is attached to the first adhesive layer. The reference plane circuit comprises a second dielectric substrate having at least one reference plane formed thereon. Each of the at least one reference plane is electrically connected to the first conductive layer via the first adhesive layer.

Yet another embodiment provides a multilayer circuit assembly including a trace placement circuit having a first dielectric substrate. At least one solder ball receiving passage is formed through the first dielectric substrate in the first dielectric substrate. The first conductive layer is formed on the first surface of the first dielectric substrate and the second conductive layer is formed on the second surface of the first dielectric substrate. The first and second conductive layers are patterned to include a plurality of traces. The traces on the first side have solder ball pads adjacent to the individual solder ball receiving passages and form a closed end with the passages. At least a portion of the traces on the first side are electrically connected to the traces on the second side. The first adhesive layer is the first
Affixed to the conductive layer and the reference planar circuit is affixed to the first adhesive layer. The reference plane circuit comprises a second dielectric substrate having at least one reference plane formed thereon. Each reference plane is electrically connected to at least a portion of the traces on the first side via the first adhesive layer.

As is well known, a major advantage of these implementations is that the trace placement circuit and the reference plane circuit can be manufactured separately. As a result, the process selected to manufacture each circuit can be better optimized. Another important advantage is that the process for manufacturing the reference plane circuit essentially provides the desired patterning of the reference plane. For example, the reference plane may be 2 by a single conductive layer.
It can be patterned to be a split reference plane provided with a kind of reference voltage. The reference plane circuit mainly has only macroscopic features as compared with the features of the trace placement circuit. In this case, cost benefits are obtained using low cost assembly techniques for manufacturing reference plane circuits.

While exemplary embodiments have been shown and described, there are wide variations on the above disclosure,
Modifications and substitutions are possible, and in some cases some features of the embodiments may be used without corresponding use of other features. Therefore, it is appropriate that the appended claims be construed broadly to correspond to the scope of the embodiments disclosed herein.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an exemplary implementation of a trace placement circuit.

FIG. 2 is a cross-sectional view showing an exemplary implementation of a reference plane circuit.

FIG. 3 is a cross-sectional view illustrating an exemplary embodiment of a circuit assembly in which an adhesive layer is formed between a trace placement circuit and a reference plane circuit.

FIG. 4 is a cross-sectional view of an exemplary implementation of a circuit assembly having a two metal layer trace placement circuit.

FIG. 5A is a cross-sectional view illustrating an exemplary implementation of an insulation displacement via interconnection method.

FIG. 5B is a cross-sectional view of an exemplary implementation of an insulation displacement via interconnection method.

6 is a cross-sectional view showing an electronic package including the circuit assembly of FIG.

FIG. 7 is a cross-sectional view illustrating an exemplary embodiment of a circuit assembly that uses a solder plug to form an interconnect between a trace placement circuit and a reference plane circuit.

FIG. 8 is a cross-sectional view illustrating an exemplary embodiment of a circuit assembly having a reference plane circuit with reference planes on both sides of a dielectric substrate.

FIG. 9 is a cross-sectional view illustrating an exemplary embodiment of a circuit assembly excision method.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, SD, SL, SZ, UG, ZW), E A (AM, AZ, BY, KG, KZ, MD, RU, TJ , TM), AE, AL, AM, AT, AU, AZ, BA , BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GD, G E, GH, GM, HR, HU, ID, IL, IN, IS , JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, M N, MW, MX, NO, NZ, PL, PT, RO, RU , SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZA, Z W (72) Inventor Anthony Earl Prepis             United States 55133-3427 Ce, Minnesota             Don't Paul, Post Office Bock             SU 33427 (72) Inventor Kevin Wai Chen             United States 55133-3427 Ce, Minnesota             Don't Paul, Post Office Bock             SU 33427

Claims (5)

[Claims] 1. A multilayer circuit assembly comprising: a trace placement circuit comprising a first dielectric substrate having a first conductive layer formed thereon; and a first adhesive layer affixed to the trace placement circuit. A reference plane circuit attached to the first adhesive layer, comprising a second dielectric substrate having at least one reference plane formed thereon, each of the at least one reference planes having the first adhesion. A reference plane circuit electrically connected to the first conductive layer through an agent layer, wherein an insulation displacement via electrically connects the reference plane to the first conductive layer; A multilayer circuit assembly, wherein the multilayer circuit assembly is formed so as to penetrate the first adhesive layer. 2. The first dielectric substrate is a flexible polymeric material, and the first dielectric substrate is a flexible polymer material.
The conductive layer comprises a plurality of conductive traces having solder ball pads, at least one solder ball receiving passage being formed through the first dielectric layer, the solder ball pad being an individual solder ball receiving passage. The multi-layer circuit assembly of claim 1, wherein said multi-layer circuit assembly is formed adjacent to and establishes a closed end with said passage. 3. A plating bath extending to an edge of the circuit assembly,
The multi-layer circuit assembly of claim 4, wherein the reference plane has a portion adjacent the plating bath that is offset from an individual edge of the circuit assembly. 4. An apparatus for packaging a semiconductor device having the multilayer circuit assembly of claim 1, wherein the trace placement circuit comprises a flexible first dielectric substrate, the at least one solder ball receiving passage. Are formed through the substrate, a first conductive layer is formed on the substrate, the first conductive layer having solder ball pads adjacent to the individual solder ball receiving passages, and A trace placement circuit comprising a plurality of conductive traces forming a closed end, a first adhesive layer affixed to the trace placement circuit, and a reference plane circuit bonded to the first adhesive layer, A flexible second dielectric substrate having at least one reference plane formed thereon, each of the at least one reference planes electrically connected to at least a portion of the trace through the first adhesive layer. A reference plane circuit that is electrically connected, the trace placement circuit, the first adhesive layer, a semiconductor device accommodating passage extending through the reference plane circuit, and the first adhesive layer. A stiffener member bonded to the second dielectric substrate on an opposing surface; 5. A multi-layer circuit assembly, comprising: a trace placement circuit comprising a first dielectric substrate, wherein at least one solder ball receiving passage is formed through the substrate and wherein the first conductive layer is formed. A trace placement circuit having a plurality of traces formed on a first side, the first conductive layer patterned to have solder ball pads adjacent to individual solder ball receiving passages, and with which a closed end is formed. A first adhesive layer attached to the first conductive layer, and a reference plane circuit attached to the first adhesive layer, the second dielectric layer having at least one reference plane formed thereon. A planar substrate, each of the at least one reference planes electrically connecting to at least a portion of the traces of the first conductive layer through the first adhesive layer. Featuring Multi-layer circuit assembly that.