JP2003508921A - New easily shrinkable non-volatile semiconductor storage device cell using split dielectric floating gate and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] A nonvolatile semiconductor memory device 100 that stores 2-bit information is disclosed. The device comprises a semiconductor substrate of one conductivity type and a right diffusion region 104 and a left diffusion region formed on a semiconductor substrate of the opposite conductivity type. A channel region 108 is formed between the left and right diffusion regions. A control gate 114 having a thin gate oxide film 110 is formed on the central channel portion 112 of the channel region. The device further includes a control gate electrode formed on the gate insulating film. A dielectric composite 132 substantially covers the semiconductor substrate and the control gate electrode. A right charge storage region is formed in a portion of the dielectric complex between the control gate electrode and the right diffusion region. Similarly, a left charge storage region is formed in a portion of the dielectric complex between the control gate electrode and the left diffusion region. Word line 130 substantially covers the dielectric composite. A method of making this novel cell is also disclosed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION The present invention relates generally to non-volatile digital storage devices, and more specifically,
Programmable non-volatile storage device that stores 2-bit information (conventional EEPR
An improved cell structure for OM or flash EEPROM) and a method of manufacturing the same.

2. BACKGROUND Nonvolatile storage devices, such as EPROM, EEPROM, and flash EPROM devices, generally include a series of transistors that function as storage cells that store a single bit of information. Each of the transistors has a source region and a drain region formed on an n- or p-type semiconductor substrate, and a thin tunnel dielectric formed on a surface of the semiconductor substrate disposed between the source region and the drain region. A layer, a floating gate (made of polysilicon) disposed on the insulating layer to retain charge, a control gate, and an interpoly dielectric disposed between the floating gate and the control gate. I have it.

The most commonly used EPROM cells have an electrically floating gate surrounded by an insulator and generally located between source and drain regions formed in a silicon substrate. In the early versions of these cells, avalanche injection causes charge to be injected through the insulator. Large EPROMs utilize channel injection to charge the floating gate. Exposing these arrays to ultraviolet radiation erases these EPROMs.

An electrically erasable EPROM (EEPROM) is also very common. In some cases, the charge is placed in the floating gate and removed by implanting the charge through a thin oxide region formed on the substrate. In other cases, the charge is removed through the upper electrode.

Another type of general EPROM / EEPROM is a flash EPROM.
Alternatively, it is called a flash EEPROM. These flash storage cells can electrically erase, program, or read the storage cells in the chip. The floating gate used herein is typically a conductive material made of polysilicon, which is isolated from the channel of the transistor by a thin layer of oxide or other insulating material and is It is insulated from the control gate or word line of the transistor by a layer of insulating material.

A “program” step for a flash memory cell involves a large positive voltage, such as 12 volts, between the gate and source and a positive voltage, such as 7 volts, between the drain and source. By establishing, so-called thermionic injection injection (h
The OT electron injection method is used.

The act of discharging the floating gate is referred to as the "erase" function for flash devices. This erase function is typically performed by an FN tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase). For example, the source erase step is performed by establishing a large positive voltage from the source to the gate while floating the drain of each memory cell. This positive voltage can be as high as 12 volts.

In a conventional stacked nonvolatile semiconductor memory device, an insulating film that insulates a floating gate and a control gate from each other (hereinafter, “second gate insulating film”).
Is a single layer of silicon oxide. There is an ever-increasing need for ultra-small semiconductor devices, and in this situation, the second gate insulating film needs to be thinner.

Traditionally, interpoly dielectrics have consisted of a single silicon dioxide (SiO ₂ ). To meet this need, oxide /
Nitride / oxide compositions (sometimes referred to as ONO structures) have been used because the layers are thinner and still have less charge leakage than a single oxide layer. (See Chang et al., US Pat. No. 5,619,052).

US Pat. No. 5,768,192 to Eitan discloses the use of ONO structures (and other charge trapping dielectrics) as both insulators and floating gates. Eitan puts this transistor device in the opposite direction (
That is, programming and reading "source" and "drain" in reverse) results in a shorter programming time, resulting in a significant increase in the provided threshold voltage. Eitan, this result prevents "punch through" (ie, the state where the lateral charge becomes strong enough to attract electrons through the drain, regardless of the applied threshold level). However, it suggests that it is useful for shortening the programming time.

The semiconductor storage device industry is investigating various techniques and approaches to reduce the bit cost of non-volatile storage devices. 2 of the more important approaches
The first is dimensional shrinkage and multilevel preservation.

Dimensional shrinkage is an attempt to design cells using smaller dimensions.
However, significant improvements in technology are needed before dimensional shrinkage can reach its full cost saving effect.

Multilevel storage (often referred to as multilevel cells) means that a single cell can represent one or more bits of data. In conventional memory cell designs, 0V and 5V where only one bit represents 0 or 1.
It is represented by two different voltage levels, such as (in relation to some voltage margin). Wider voltage / current ranges are required to encode multiple bits of data in multi-level storage. As a result of the large number of ranges, the margin between the ranges is reduced and sophisticated design techniques are required. As a result, multilevel storage cells are difficult to design and manufacture. Some are less reliable. Some read times are slower than in the case of conventional single bit cells.

Accordingly, one object of the present invention is to provide a structure capable of storing 2-bit data, thereby realizing a cost reduction by doubling the size of a nonvolatile memory device. Manufacturing a non-volatile memory device structure. A related object of the invention is to allow this cell structure to work without the use of tight margin techniques, i.e. advanced design techniques.

Another object of the present invention is to manufacture a cell configuration that is significantly simpler in design than conventional EEPROM or flash EEPROM by employing a dielectric floating gate. A related object of the invention is to have a gate coupling ratio (GCR) of 100% so that an EEPROM or flash EEPR
It is an object of the invention to provide a cell structure which has a read current significantly higher than that of an OM, while at the same time allowing lower voltages to be used for both programming and erase functions than conventional EEPROM or flash EEPROM cells.

An additional object of the present invention is to provide a method of manufacturing a 2-bit storage cell that can be easily adapted for system-on-a-chip (SOC) applications.

The above and other objects will become apparent to those skilled in the art with reference to the drawings, the specification and the claims.

[0018]

SUMMARY OF THE DISCLOSURE The present application discloses a nonvolatile semiconductor memory device that stores 2-bit information. The device has a semiconductor substrate of one conductivity type and right and left diffusion regions formed in a semiconductor substrate of the opposite conductivity type. A channel region is formed between the left and right diffusion regions. A control gate having a thin gate oxide film is formed on the central channel portion of the channel region. The device further has a control gate electrode formed on the gate insulating film. The dielectric composite substantially covers the semiconductor substrate and the control gate electrode. A right charge storage region is formed in a portion of the dielectric composite between the control gate electrode and the right diffusion region. Similarly, a left charge storage region is formed within a portion of the dielectric composite between the control gate electrode and the left diffusion region. Word lines substantially cover the dielectric composite.

The present invention also provides a method of manufacturing this novel memory cell, comprising: (1) forming a gate oxide layer on a semiconductor substrate of one conductivity type; and (2) a gate. Forming a control gate on the oxide insulating layer, and (3) attaching a right spacer and a left spacer adjacent to the right and left edges of the control gate so as to cover a portion of the gate oxide insulating layer. (4) forming left and right diffusion regions in the semiconductor substrate, (5) removing spacers, and (6) a dielectric composite disposed on the control gate and the semiconductor substrate, A dielectric composite comprising a bottom layer of silicon dioxide formed on a substrate and a control gate, a silicon nitride layer formed on the bottom layer of silicon dioxide and a top layer of silicon dioxide formed on the nitride layer. Form It also includes a method including the above.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

Although the device of the present invention may be embodied in many different forms and manufactured in a variety of different manufacturing methods, this disclosure is merely an example of the principles of the invention.
With the understanding that the invention is not intended to be limited only to the described embodiments, one specific embodiment and a particular manufacturing method are described below.

FIG. 1 illustrates a 2-bit non-volatile memory structure or cell 100 according to the present invention. The memory device structure 100 is formed on a semiconductor substrate 102. As shown, the semiconductor substrate 102 can be doped in the art to form a p-type or n-type substrate. For purposes of this description of the features of the present invention, only cells based on p-type semiconductor substrates will be described. However, as will be appreciated by those skilled in the art, the present invention is equally applicable to cells based on n-type semiconductor substrates, with adjustments that will also be understood.

The right diffusion region or channel 104 is formed in the semiconductor substrate 102 and has a conductivity type opposite to that of the substrate 102. The left diffusion region or channel 106 is formed in the semiconductor substrate 102 separately from the right diffusion region 104, thereby forming a channel region 108 between the right and left diffusion regions 104, 106, the left diffusion region 106 being the region 104. They have the same conductivity type (n + in the disclosed embodiment).

The cell 100 further includes a gate insulating film layer 110 (gate oxide layer) formed on the central channel portion 112 of the channel region 108. Control gate electrode 1
14 is formed on layer 110 using polysilicon. As described in detail below, the control gate 114 also serves to insulate the left and right storage "cells" from each other.

Thin (tunnel) oxide layer 120, nitride layer 122 and insulating oxide layer 124
1 is uniformly layered over the substrate 102 and the control electrode 114 to form an ONO dielectric composite layer 132, as shown in FIG. In one preferred embodiment, the oxide layers 120, 124 are each about 100Å thick, while the nitride layers are about 50Å thick. Although these dielectric structures are shown as being formed by sandwiching a nitride layer between a thin tunnel oxide and an insulating oxide, SiO ₂ / Al ₂ O ₃ / SiO ₂ Other dielectric structures such as can also be used.

A right charge storage region 116 is formed on the right portion 118 of the channel region 108 between the central channel portion 112 and the right diffusion region 104. A left charge storage region 126 is formed on the left portion 128 of the central region 108 between the central channel portion 112 and the left diffusion region 106. Each of the right side region 116 and the left side region 126 can store 1-bit data. Polysilicon 130 is used as a word line and substantially covers the ONO dielectric composite layer 132.

As known to those skilled in the art, the diffusion regions 104, 106 in a MOS transistor are indistinguishable at zero bias. The role of each of the diffusion regions becomes apparent after the terminal voltage is applied (ie after biasing the drain more than the source).

Compared to conventional EEPROM or flash EEPROM, this method is much simpler because no floating gate is required. Therefore, the cost is significantly reduced by the double density and the simple method.

4A and 4B illustrate the operating principle of the 2-bit non-volatile memory device structure of the present invention. As described above, in the 2-bit nonvolatile memory cell 100, 1-bit data is stored and arranged in each of the charge storage regions 116 and 126. As will be described below, by reversing the programming and reading directions of the cell, it is possible to prevent interference between storing charges in each of the two charge storage regions.

In FIG. 4A, programming and reading states of the right bit are illustrated. To program the right bit, the right diffusion region 104 is treated as a drain (by applying a voltage of about 4-6V) and the left diffusion region 106 is treated as a source (0V for a thermal-e program). Or by applying a low voltage). At the same time, about 3-5V is applied to the control gate electrode 114 to activate the central channel portion 112 and the word line 130 receives about 8-10V. To read the right bit, the left diffusion 106 is treated as a drain (by applying a voltage of about 1.5 to 2.5V) and the right diffusion 104 is treated as a source (0V). By applying a voltage). At the same time, about 2-4V is applied to control gate 114 and word line 130 to activate central channel 112. As shown in FIG. 4B, the left storage cell 1
Similar steps can be used to program and read 26.

The reason for reversing the programming and reading directions is that the locally collected electrons exhibit different threshold voltages if read in different directions. FIG. 5 shows the difference in Vt as trapped electrons are collected on the right side, indicating that the right diffusion region 104 is used as a drain during programming. Line 1 is the threshold voltage read from the right side (right diffusion channel 104 is used as a drain and is in the same direction as the program) and line 2 is the threshold voltage read from the left side (left diffusion channel 106 is the drain). Used and in the opposite direction to the program). As shown in FIG. 5, reversing the programming and reading directions results in a more efficient Vt operation. Thus, the threshold voltage of a single bit is read, even if both sides are programmed to store 2 bits. In this way, by reversing the direction, two bits can be programmed and read without interfering with each other.

Erasing the storage of 2 bits can be done bit by bit or simultaneously by 2 bits at a time. If a high voltage is applied at the two spreading terminals corresponding to zero or an invalid gate voltage, these two bits will be erased together. If the high voltage is applied only at a single diffusion terminal corresponding to zero or an invalid gate voltage, then only a single bit is erased. Furthermore, due to the presence of the central gate oxide layer 110, no overerasure occurs in this structure. The actual threshold is determined by the area of the central gate oxide 110, even if the threshold voltage of the storage regions 116, 126 is over-erased. For this reason, the erased Vt of structure 100 is exceptional and thus suitable for low power applications.

In addition to the 2-bit storage and simple operating principle, the GCR (gate coupling ratio) of the present invention is 100% due to the absence of floating gate. Performance is significantly improved by increasing the read current. In addition, the program and erase voltages are reduced, thus reducing the indirect cost of circuits and processes. Another advantage of this structure is its fast programming speed. FIG. 5 shows the programmed Vt versus programming time for two different central gate oxide 110 thicknesses. By employing a thinner layer of central gate oxide 110, faster programming speeds are achievable. In one preferred embodiment, the thinner central gate oxide 110 thickness is about 50-100 Å depending on the power supply voltage and cell size.

There are various possible ways of manufacturing the 2-bit cells of the present invention. With the understanding that these methods merely exemplify possible methods for manufacturing the 2-bit non-volatile memory device structures of the present invention, they are disclosed below with particular reference to one preferred method.

As shown in FIG. 1, by combining oxidation at 800 ° C. in an H ₂ / O ₂ atmosphere and oxynitridation at 950 ° C. in an N ₂ O atmosphere, a p-type silicon substrate 102 is formed.
A gate oxide film 110 is formed on the surface of the. After adjusting Vt and growing the gate oxide, the polysilicon layer 114 is patterned using a bit line mask, as illustrated in FIG. 3A. Next, a layer of TEOS is deposited and then the deposited TEOS is etched back to form the spacers to the desired width,
Form oxide spacers as illustrated in FIG. 3B.

As shown in FIG. 3C, arsenic (70K
eV / 1.5 ^* 10 ^ 15), followed by a rapid heating step to activate the implanted atoms and form right diffusion region 104 and left diffusion region 106.

Next, the oxide spacers are removed and ONO (oxide / nitride / oxide) is deposited on the tunnel oxide as illustrated in FIG. 3D by methods well known in the art. Let the thickness be 100/50 / 100Å. ONO complex 132
Are the thermal electrons traversing the layers and the top silicon dioxide layer 124 and the silicon nitride layer 122.
It has a bottom silicon dioxide layer 120 that is thick enough to prevent trapping at the interface between and. The minimum thickness required for layer 120 depends on the integrity of the bottom oxide layer and the ability of the bottom oxide layer to conform to the morphology of the underlying poly substrate 102 and provide a bottom oxide layer of uniform thickness. Dependent. Whether or not the bottom oxide layer has these features depends on the method of forming the bottom oxide layer.

The bottom oxide layer 120 is formed, for example, by thermal growth in an O ₂ atmosphere, thermal growth in an N ₂ O atmosphere environment, low temperature chemical vapor deposition (CVD) method (400 ° C.), and high temperature CVD method ( 8
Can be deposited on the substrate 102 by a variety of methods known in the art, including 00 ° C. to 1000 ° C.). The bottom silicon dioxide layer 120 is a high temperature CVD that produces a low defect density oxide film that conforms to the surface of the underlying substrate 102.
It is preferably deposited by the method.

The silicon silicon nitride layer 122 used in the ONO composite of the present invention must be thinner than either the bottom oxide layer 120 or the top oxide layer 124 in the composite formed.

Next, a second polysilicon layer 130 is deposited on layer 124 using a CVD method and polysilicon is employed using a word line mask, as shown in FIGS. 3E-3F. Pattern.

The above description and drawings merely explain and illustrate the present invention,
The present invention is not limited to these. Those of ordinary skill in the art having reference to the above disclosure will be able to make modifications and variations thereof without departing from the scope of the invention.

[Brief description of drawings]

FIG. 1 is a cross-sectional view along a word line of a 2-bit non-volatile memory cell according to the present invention.

[Fig. 2]   FIG. 3 is a plan view showing an arrangement of a part of cells according to the present invention.

FIG. 3A is a cross-sectional view along a word line of steps performed in a method of manufacturing a 2-bit non-volatile memory cell according to the present invention. 3B is a cross-sectional view taken along a word line in a step different from that of FIG. 3A. 3C is a cross-sectional view taken along a word line in a step different from that of FIG. 3A. 3D is a sectional view taken along a word line in a step different from that of FIG. 3A. 3E is a plan view showing a pattern of a second layer of polysilicon deposited after the steps illustrated in FIG. 3D in a method of manufacturing a memory cell. 3F is a cross-sectional view along a word line showing a cell manufactured according to the steps illustrated in FIGS. 3A to 3E.

FIG. 4A is a cross-sectional view taken along the word line showing the action of the split floating gate for storing charges in the right side charge storage region. FIG. 4B is a cross-sectional view taken along the word line showing the action of the split floating gate for storing charges in the left charge storage region.

FIG. 5 is a graph showing the effect of reversing the direction of program and read steps on the threshold voltage provided by the 2-bit non-volatile cell structure of the present invention.

[Figure 6]   FIG. 6 is a graph showing the relationship between gate oxide programming speed and thickness.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SK, SL, TJ, TM , TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW (72) Inventor Le Tao Chen             San-Min District, Kaohsiung, Taiwan             To, New-Chan Street, Rain               1, number 36 (72) Inventor Wang, Mom Tsun             Hsinchu City, Taiwan Science-Park Law             De Rain 162, Ally 3, Number               18 F term (reference) 5F083 EP17 EP18 EP27 EP32 EP33                       EP34 EP35 EP37 EP43 ER02                       ER05 ER16 ER19 GA09 KA08                       LA12 LA16 ZA21                 5F101 BA45 BB02 BC11 BD22 BE02                       BE05 BE07 BF05

Claims (4)

[Claims] 1. A nonvolatile semiconductor memory device, comprising: a semiconductor substrate of one conductivity type, and a right diffusion region formed on the semiconductor substrate, the conductivity type being opposite to the conductivity type of the semiconductor substrate. And a right diffusion region, which is formed on the semiconductor substrate separately from the right diffusion region, thereby forming a channel region between the right diffusion region and the left diffusion region. The left diffusion region having the same conductivity type, a gate insulating film formed on a central channel portion of the channel region, a control gate electrode formed on the gate insulating film, the substrate and the control gate A dielectric composite substantially covering an electrode; a right charge storage region within a portion of the dielectric composite between the control gate electrode and the right diffusion region; and the control gate. Wherein comprising a left charge storage region in a portion of the dielectric composite, and a word line substantially covering the dielectric composite, non-volatile semiconductor storage device between the gate electrode and the left diffusion region. 2. The non-volatile semiconductor memory device of claim 1, wherein the dielectric composite comprises a silicon nitride layer sandwiched between two silicon dioxide layers.
Nonvolatile semiconductor memory device. 3. The non-volatile semiconductor memory device of claim 1, wherein the dielectric composite comprises an aluminum oxide layer sandwiched between two silicon dioxide layers. 4. A method of manufacturing a non-volatile memory device cell, comprising: forming a gate oxide insulating layer on a semiconductor substrate of one conductivity type; and forming a control gate on the gate oxide insulating layer. Attaching right and left spacers adjacent to the right and left edges of the control gate so as to cover a portion of the gate oxide insulating layer; and forming left and right diffusion regions in the semiconductor substrate. A dielectric composite disposed on the control electrode and the semiconductor substrate, the bottom silicon dioxide layer formed on the substrate and the control gate, and the bottom silicon dioxide layer. Forming a dielectric composite comprising a silicon nitride layer formed thereon and a top silicon dioxide layer formed on the silicon nitride layer. Storage cell manufacturing method.