JP2003330985A - Circuit design aid device, circuit design method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit design aid device, a circuit design method and a program which reduce the influence of arrangement or wiring of a macro cell on a result of timing analysis and can accurately determine whether a circuit after arrangement and wiring satisfy a timing condition. <P>SOLUTION: Information on the macro cell is extracted at an extraction part 30 from information on a plurality of cells contained in a supplied net list, and a cell library with information substituted by information on a cell having a function equivalent to this extracted macro cell information and a smaller area is prepared at a substitution part 40. Then, based on the prepared cell library and the net list, arrangement design and wiring design of the cell are made, and based on the circuit information given this arrangement/wiring processing, a transmission delay time in each path in the circuit is analyzed. And it is determined whether the analyzed transmission delay time of each path satisfies a predetermined standard. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit design support device, a circuit design method and a program, for example, a circuit design support device and a circuit design method for a semiconductor integrated circuit, and a process for supporting the circuit design of the semiconductor integrated circuit. It relates to the program of the device.

[0002]

2. Description of the Related Art Due to advances in integration technology, semiconductor integrated circuits are becoming larger and more highly integrated, and clock signals are becoming faster. For this reason,
The design of semiconductor integrated circuits is becoming increasingly difficult. This tendency is particularly noticeable in timing design, and it is a major problem in circuit design to make the timing converge within the range of the determined conditions.

One of the typical causes of timing violation is wiring of cells (standard cells) having basic functions such as AND circuits and OR circuits that occupy most of the circuits.
It may be lengthened by bypassing or straddling a large area cell (macro cell) having a special function such as ROM or RAM. If the propagation delay time becomes long due to the long wiring, the signal path (path) passing through this wiring becomes the path with the strictest timing (critical path), which causes timing violation.

When a timing violation due to such a cause occurs at the layout designing stage, the arrangement of macro cells is usually changed, or a cell on a path having a timing violation is changed to a cell having a high driving capability. It is possible to converge the timing within the condition range by repeating trials such as changing or inserting a buffer on the path.

[0005]

On the other hand, since the cause of the timing violation is a problem in logic design, there are cases where the timing cannot be converged within the condition range even if such trial work in layout design is repeated. is there.
In such a case, it is necessary to return to the logic design again and redo the circuit design, and as a result, there is a problem that the work of the layout design performed up to that point is wasted.

Therefore, it is necessary to inspect the existence of such a problem in the logic design in advance at the stage before the layout design. Normally, in this inspection, after performing automatic placement and routing using a CAD tool, the placement position of the macro cell is considered while considering the routing route so that the occurrence of the critical path due to the layout of the macro cell is minimized. After fine adjustment, timing analysis is performed. However, the fine adjustment work of this macro cell is conventionally done manually, and after all, the same work as the actual layout work performed after this inspection is required, which is a major cause of prolonging the circuit design period. Has become.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the influence of the layout and wiring of specific circuit elements on the analysis result of the propagation delay time, and to reduce the influence after the layout and wiring. (EN) Provided are a circuit design support device capable of accurately determining whether or not a circuit satisfies a predetermined criterion regarding a propagation delay time, a circuit design method, and a program of a processing device supporting such circuit design. .

[0008]

In order to achieve the above object, a circuit design support apparatus according to a first aspect of the present invention selects from among a plurality of circuit element information included in supplied circuit information, The extraction means for extracting the information of the specific circuit element and the information of the specific circuit element extracted by the extraction means have the same function as the specific circuit element and have an area larger than that of the specific circuit element. Replacing means for replacing the circuit element information with smaller information, placement and wiring means for performing layout design and wiring design of the circuit element based on the circuit information obtained by replacing the circuit element information by the replacing means, and the placement and wiring means. Analysis means for analyzing the propagation delay time in each signal path in the circuit based on the circuit information on which the layout design and wiring design of the circuit elements are performed, and the analysis means Propagation delay time of each signal path which has a determination means whether it meets a predetermined criterion.

According to the circuit design support apparatus of the first aspect of the present invention, in the extraction means, information on a specific circuit element is selected from information on a plurality of circuit elements included in the supplied circuit information. To be extracted. In the replacing means, the information of the specific circuit element extracted by the extracting means is replaced with information of a circuit element having a function equivalent to that of the specific circuit element and having an area smaller than that of the specific circuit element. To be done. In the above position wiring means, the layout design and wiring design of the circuit elements are performed based on the circuit information obtained by replacing the information of the circuit elements. In the analysis means, the propagation delay time in each signal path in the circuit is analyzed based on the circuit information on which the layout design and wiring design of the circuit elements have been performed. The determining means determines whether or not the propagation delay time of each analyzed signal path satisfies a predetermined criterion.

Further, in the replacing means, the information of the specific circuit element may be replaced with the information of the circuit element having a constant area smaller than that of the specific circuit element.

A circuit designing method according to a second aspect of the present invention extracts information on a specific circuit element from information on a plurality of circuit elements included in supplied circuit information, and extracts the specified information. The information of the circuit element is replaced with the information of the circuit element having the same function as that of the specific circuit element and having a smaller area than the specific circuit element, and the information of the circuit element is replaced with the replaced circuit information. Based on the circuit information on which the layout design and wiring design of the circuit elements are performed, the propagation delay time in each signal path in the circuit is analyzed, and the above-mentioned analysis is performed. It is determined whether or not the propagation delay time of each signal path satisfies a predetermined criterion.

According to a third aspect of the present invention, there is provided a circuit design method, wherein a processing device for processing supplied circuit information selects a specific circuit element from among information of a plurality of circuit elements included in the circuit information. A step of extracting information and a step of replacing the extracted information of the specific circuit element with information of a circuit element having a function equivalent to that of the specific circuit element and having an area smaller than that of the specific circuit element. And a step of performing a layout design and a wiring design of the circuit element based on the circuit information in which the information of the circuit element is replaced, and a circuit based on the circuit information on which the layout design and the wiring design of the circuit element are performed. And a step of analyzing the propagation delay time in each of the signal paths therein, and a step of determining whether or not the propagation delay time of each of the analyzed signal paths satisfies a predetermined criterion. To perform the management.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration example of a circuit design support device according to an embodiment of the present invention. The circuit design support device shown in FIG. 1 includes a netlist storage unit 10, a cell library storage unit 20,
Extraction unit 30, replacement unit 40, layout wiring unit 50, analysis unit 6
0, the determination unit 70 and the display unit 80.

The netlist storage unit 10 stores each component of the circuit (hereinafter simply referred to as a cell) and information indicating a connection relationship between them (hereinafter simply referred to as a netlist). This netlist is circuit design information obtained by digital circuit design or analog circuit design before layout design, and includes information on cell placement and wiring on the semiconductor chip (or circuit board) to be mounted. Absent. The cell library storage unit 20 stores information on various types of cells used as constituent elements in a circuit as a library. For example, information about signals input to and output from the cell, information about the circuit configuration (connection of transistors, etc.) in the cell, information about the shape and size of the cell, information about characteristics such as delay time are stored.

The extraction unit 30 identifies the information of a plurality of cells included in the net list supplied from the net list storage unit 10 by referring to the information of various cells stored in the cell library storage unit 20. Extract the cell information. For example, the types of cells are standard cells having basic functions such as AND circuits and OR circuits, ROM and RAM,
When divided into a macro cell having a special function such as a D / A converter, information of the latter macro cell having an area larger than that of the former standard cell is extracted.
This extraction is performed, for example, by comparing the type name of the macro cell stored in the cell library storage unit 20 with the type name of each cell and searching for a cell that matches them.

The replacing unit 40 replaces the information on the specific cell extracted by the extracting unit 30 with the information on the cell having the same function as the specific cell and having a smaller area than the specific cell. For example, the information on the shape of the cell in the information on the macro cell extracted by the extraction unit 30 is rewritten to change the macro cell to a cell having a smaller shape than it should be. In this way, a new cell library in which the cell shape is changed is created and supplied to the placement and routing section 50 together with the netlist.

The placement and routing unit 50 designs the placement and wiring of cells on the semiconductor chip to be mounted, based on the new cell library and netlist in which the cell information has been replaced by the replacement unit 40. For this layout design and wiring design, the automatic placement and routing design method used in a general CAD tool for circuit design can be applied.

The analysis unit 60 analyzes the propagation delay time in each path in the circuit based on the circuit information in which the layout and wiring of the cells have been designed by the layout and wiring unit 50. This circuit information includes, in addition to the netlist, information about cell placement and wiring. As a method of analyzing the propagation delay time, for example, STA (static timing an
alysis). The STA simply analyzes the propagation delay time of all paths existing between the output and the input of the flip-flop in the circuit, and is simpler but faster than the actual operation simulation. It can be performed.

The determination unit 70 determines whether or not the propagation delay time of each path analyzed by the analysis unit 60 satisfies a predetermined acceptance criterion. Normally, the propagation delay time of the path is limited by the cycle of the clock signal and also by the setup time and hold time for the flip-flop. The determination unit 70 compares the pass delay time pass criterion set for each path based on these restrictions with the analysis result of the propagation delay time set by the analysis unit 60 so that each path satisfies the timing condition. Determine whether or not.

The display unit 80 processes information relating to the determination result of the propagation delay time of each path in the determination unit 70 to create display data, and displays this on an image display device such as a CRT or LCD. The information to be displayed may include not only an image but also a sound, for example. Further, in addition to the information on the determination result, information indicating the difference between the analysis result of the propagation delay time and the acceptance criterion for each path may be displayed.

Next, the operation of the circuit design support device having the above-mentioned configuration will be described. FIG. 2 is a flowchart for explaining an example of the operation of the circuit design support device shown in FIG. Step ST10: By referring to the information of the various cells stored in the cell library storage unit 20 from the information of the plurality of cells included in the netlist supplied from the netlist storage unit 10, the information of the macro cell is obtained. To be extracted. That is, a cell having a type name that matches the type name of the macro cell stored in the cell library storage unit 20 is extracted from the supplied netlist.

Step ST20: In step ST10, it is judged whether or not the macro cell is extracted from the net list. If the supplied netlist does not include a macro cell and the extraction in step ST10 is not executed, the process of step ST30 is skipped and the process proceeds to step ST40.
When the macro cell is extracted, the process proceeds to step ST30.

Step ST30: The information of the macro cell extracted in step ST20 is replaced with the information of the cell having a function equivalent to that of the macro cell and having a smaller area. As a result, a new cell library is created in which the information about the cell shape in the macro cell information extracted by the extraction unit 30 is rewritten so that the information has a shape smaller than the original size.

Step ST40: Based on the supplied netlist and cell library, layout design and wiring design of cells on the semiconductor chip to be mounted are performed. However, when the macro cell is extracted and replaced, the cell library referred to in this placement and routing processing is the cell library newly created in step ST30, and the macro library is added to the netlist.
When the cell is not included, the cell library is the original cell library stored in the cell library storage unit 20.

Step ST50: Analysis of the propagation delay time in each path in the circuit, for example, STA is executed based on the circuit information for which the cell layout design and wiring design have been performed in step ST40. Step ST60: It is determined whether or not the propagation delay time of each path analyzed in step ST50 satisfies a predetermined acceptance criterion. Step ST70: Data for display is created from the information regarding the result of determination of the propagation delay time of each path in step ST60, and information such as an image corresponding to this is displayed to the user.

Here, the change in layout after the placement and routing processing according to the size of the macro cell will be described. FIG. 3 is a diagram showing a layout example when optimal macro cell placement is performed. In FIG. 3, reference numeral LA indicates a layout area on the semiconductor chip, and reference numeral MC indicates a macro area.
A cell and a symbol SA indicate an area in which a standard cell is arranged.

In the optimum layout example of FIG. 3, four macro cells MC are arranged side by side on one side of the rectangular layout area LA, and four macro cells MC are also arranged on the other side of the layout area LA facing this side.・ Cell MC
Are arranged side by side. The standard cells are arranged in the area SA sandwiched by the macro cells facing each other. For example, such an arrangement makes it difficult for the standard cell wiring to bypass the macro cell in order to avoid it or to extend over the macro cell. Situations that occur will be suppressed as much as possible.

FIG. 4 is a diagram showing a layout example when the placement and routing processing is performed without changing the size of the macro cell in FIG. The same symbols in FIG. 4 and FIG. 3 indicate the same components. In the layout example of FIG. 4, contrary to the layout example of FIG. 3, a rectangular standard cell area SA is formed on each of two opposite sides of the layout area LA, and the standard cell area SA is sandwiched between the two standard cell areas SA. Then, eight macro cells MC are arranged. Due to such an arrangement, the wiring SIG that crosses between two facing standard cell areas SA is wired so as to bypass or straddle the macro cell. Therefore, the wiring length of these wirings SIG is longer than that in the optimum layout example of FIG. 3, and becomes a factor that causes timing violation.

On the other hand, FIG. 5 is a diagram showing a layout example after the placement and wiring process is performed by the circuit design support device shown in FIG. The same reference numerals in FIG. 5 and FIG. 3 indicate the same components. In the layout example of FIG. 5, the macro cell MC having a large area in FIGS. 3 and 4 is replaced with a macro cell MC ′ having a small area.
The macro cell MC 'is arranged in the cell area SA. That is, standard cells and macro cells are arranged without distinction. Therefore, the macro cell M
Although there are wirings that bypass or cross C ',
Since the wiring lengths thereof are shorter than those in the case where the macro cell has a large area as shown in FIG. 4, an increase in propagation delay time due to this is suppressed. As described above, since the increase of the propagation delay time due to the influence of the layout of the macro cell is suppressed, the probability that the timing violation occurs due to this can be reduced. If a timing violation occurs even though the influence of the layout of the macro cell is removed in this way, it is suspected that the timing violation is caused by a logic design problem.

As described above, according to the circuit design support apparatus shown in FIG. 1, the information of a specific cell is extracted from the information of a plurality of cells included in the supplied netlist, and this extracted information is extracted. A cell library is created in which the information of a specific cell is replaced with the information of a cell having a function equivalent to this and having a small area. Then, the cell layout design and wiring design are performed based on the created cell library and netlist, and the propagation delay time in each path in the circuit is analyzed based on the circuit information on the placement and routing processing. To be done. Then, it is determined whether the analyzed propagation delay time of each path satisfies a predetermined criterion. Therefore, the timing analysis of the designed circuit can be performed while suppressing the probability that the timing violation will occur due to the influence of the layout of the macro cell having a large area. As a result, it is possible to accurately detect a timing violation due to a problem in logic design, and prevent a situation in which a design period is prolonged due to wasteful layout design.

Further, as compared with the conventional method in which the influence of the layout of the macro cell on the timing analysis is removed while manually adjusting the placement of the macro cell after the placement and routing processing as in the conventional method, It is possible to reduce the work burden on the person. Furthermore, since the wiring length does not increase due to the wraparound of the wiring, which cannot be solved simply by moving the macro cell layout, the influence of the macro cell layout on the timing analysis can be further reduced, and the logic design problem can be solved more accurately. Can be detected.

The present invention is not limited to the above embodiment. For example, the shape of the macro cell after being changed by the replacement unit 40 may be made uniform to a constant shape regardless of the type of macro cell. That is, the macro cells after replacement may all have the same shape or may have similar shapes. As a result, the amount of calculation of the placement and routing process is reduced, and the processing time can be shortened. Also, the macro after the change by the replacement unit 40
If the shape of the cell is the same as the standard cell,
Further, it is possible to shorten the time for the placement and wiring process.

For example, a program including a part or all of the processing shown in the flowchart of FIG. 2 is stored in a storage device such as a hard disk, and the program is read and executed by a processing device such as a computer. Then, a part or all of the configuration shown in FIG. 1 can be replaced with such a processing device. This program
It can be held in a fixed storage device such as a hard disk, or may be read from a removable recording medium such as a CD-ROM or DVD and executed by a processing device, or via a network. It may be read by the processing device at any time and executed by the processing device.

Similarly, the netlist storage unit 10 and cells
The library storage unit 20 can be realized by a fixed storage device such as a hard disk, or a CD-R.
It can also be realized by a removable recording medium such as OM or DVD and its reading device.

Instead of the display unit 80, a unit for creating data in a file format and outputting it to a storage device or the like may be provided.

[0036]

According to the present invention, the influence of the placement and wiring of a specific circuit element on the analysis result of the propagation delay time is reduced, and the circuit after the placement and routing meets a predetermined criterion for the propagation delay time. It is possible to accurately determine whether or not the condition is satisfied.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a configuration example of a circuit design support device according to an embodiment of the present invention.

2 is a flowchart for explaining an example of the operation of the circuit design support device shown in FIG.

FIG. 3 is a diagram showing a layout example when optimum macro cell placement is performed.

FIG. 4 is a diagram showing a layout example when a placement and routing process is performed without changing the size of the macro cell in FIG.

5 is a diagram showing a layout example after the placement and wiring process is performed by the circuit design support device shown in FIG. 1;

[Explanation of symbols]

10 ... Net list storage unit, 20 ... Cell library storage unit, 30 ... Extraction unit, 40 ... Substitution unit, 50 ... Placement / wiring unit, 60 ... Analysis unit, 70 ... Judgment unit, 80 ... Display unit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Genji Ebisawa             134, Kobe-cho, Hodogaya-ku, Yokohama-shi, Kanagawa               Sony LSI Design Stock Association             In-house F-term (reference) 5B046 AA08 BA05 BA06 JA01 KA06                 5F064 AA04 DD02 DD07 EE02 EE08                       EE47 HH06 HH10 HH12 HH14

Claims (6)

[Claims] 1. Extracting means for extracting information of a specific circuit element from information of a plurality of circuit elements included in supplied circuit information, and information of the specific circuit element extracted by the extracting means. Replacing the information of a circuit element having a function equivalent to that of the specific circuit element and having an area smaller than that of the specific circuit element, and circuit information in which the information of the circuit element is replaced by the replacing means. Based on the circuit element layout design and wiring design based on the above, and circuit information on the circuit element layout design and wiring design performed by the layout and routing means, propagation in each signal path in the circuit An analysis unit that analyzes the delay time and a determination unit that determines whether or not the propagation delay time of each signal path analyzed by the analysis unit satisfies a predetermined criterion. Circuit design support apparatus to be. 2. The circuit design according to claim 1, wherein the replacing means replaces the information on the specific circuit element with information on a circuit element having a small constant area as compared with the specific circuit element. Support device. 3. Information of a specific circuit element is extracted from information of a plurality of circuit elements included in the supplied circuit information, and the extracted information of the specific circuit element is used as the specific circuit element. Substituting information of a circuit element having a function equivalent to and having a smaller area than the specific circuit element, based on the circuit information in which the information of the circuit element is replaced,
The layout design and wiring design of the circuit elements are performed, and the propagation delay time in each signal path in the circuit is analyzed based on the circuit information on which the layout design and the wiring design of the circuit elements are performed. A circuit design method for determining whether or not a propagation delay time of a path satisfies a predetermined criterion. 4. The replacement of the circuit element according to claim 3, wherein the information of the specific circuit element is replaced with the information of the circuit element having a constant area smaller than that of the specific circuit element. Circuit design method. 5. A processing device for processing supplied circuit information, extracting information of a specific circuit element from information of a plurality of circuit elements included in the circuit information, and the extracted specific information. Replacing the information of the circuit element with information of a circuit element having a function equivalent to that of the specific circuit element and having an area smaller than that of the specific circuit element, and a circuit in which the information of the circuit element is replaced. Based on the information
A step of performing a layout design and a wiring design of the circuit element; a step of analyzing a propagation delay time in each signal path in the circuit based on the circuit information on which the layout design and the wiring design of the circuit element are performed; And a step of determining whether the propagation delay time of each signal path satisfies a predetermined criterion. 6. The circuit element replacement step,
The program according to claim 5, wherein the information on the specific circuit element is replaced with information on a circuit element having a constant area smaller than that of the specific circuit element.