JP2003323399A - Data transfer control device, electronic device, and data transfer control method - Google Patents

Abstract

(57) [Problem] To provide a data transfer control device, an electronic device, and a data transfer control method capable of improving transfer efficiency at the time of aperiodic transfer. SOLUTION: When a first mode (mode with SOF) is set, data transfer is performed while transferring an SOF packet at a frame cycle, and a second mode (mode without SOF) is set and a non-cycle mode is set. When performing (bulk) transfer, the periodic transfer of the SOF packet is invalidated, and the aperiodic data is transferred. If there is no aperiodic data to be transferred, even if the second mode is set, the SOF
Transfer packets at frame intervals. USB OTG
During the (On-The-Go) host operation, a pipe area is secured in the packet buffer, and the non-periodic data is automatically transferred between the pipe area and the end point of the aperiodic transfer while disabling the periodic transfer of the SOF packet. When all the automatic transfer instruction signals in the pipe area are inactive, the SOF packet is periodically transferred even when the second mode is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device, an electronic device and a data transfer control method.

[0002]

BACKGROUND AND PROBLEMS TO BE SOLVED BY THE INVENTION USB
While the market for (Universal Serial Bus) 2.0 is steadily expanding, the USB Implementers Forum (USB-I
F) allows USB On-The-Go (OTG)
The interface standard called as. USB
The OTG standard (OTG) developed in the form of extending 2.0
1.0) has the potential to create new added value for the USB interface, and the emergence of applications that take advantage of its characteristics is awaited.

According to this OTG, a peripheral (peripheral device) which has been connected to a host (personal computer or the like) via a USB can have a host function. This allows the peripherals to
It becomes possible to connect by B and transfer data, and for example, it becomes possible to directly connect a digital camera and a printer and print an image of the digital camera. In addition, it becomes possible to connect a digital camera or a digital video camera to a storage device to store data.

However, a low-performance CPU (processing unit) is used as a peripheral which has a host function by OTG.
Is generally incorporated. Therefore, when the host function is added, the processing load of the CPU (firmware) of the peripheral becomes heavy, or the processing becomes complicated, other processing is hindered, and the device design period becomes long. Occurs.

In addition, USB1.1, USB2.0, OT
The USB standard such as G defines four types of transfer types: isochronous transfer, bulk transfer, control transfer, and interrupt transfer. The USB host is
Manage the transfer order of packets of each of these transfer types,
The packets of each transfer type are transferred while considering the remaining time of the frame. For this reason, in USB, the host manages frames, and FS (Full Speed) and LS (Low Sp
eed) every 1ms, HS (High Speed) 125
The host transfers an SOF (Start Of Frame) packet to the peripheral (device) every μs.

However, in aperiodic transfer such as bulk transfer and control transfer, it has been found that such transfer of SOF packets results in narrowing the bus band, resulting in a decrease in transfer efficiency.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a data transfer control device capable of improving transfer efficiency during aperiodic transfer,
An object is to provide an electronic device and a data transfer control method.

[0008]

SUMMARY OF THE INVENTION The present invention is a data transfer control device for data transfer via a bus, comprising a buffer controller for controlling access to a packet buffer for storing transfer data, and data in the packet buffer. And a transfer controller for controlling the transfer of the first transfer mode, the transfer controller, when the first mode is set,
When data transfer is performed while transferring an SOF (StartOfFrame) packet at a frame cycle, and when the second mode is set and aperiodic transfer is performed, the periodic transfer of the SOF packet is disabled and the aperiodic data transfer is performed. And a data transfer control device that performs

According to the present invention, when the first mode is set,
Data transfer is performed while the SOF packet is transferred at the frame cycle. This makes it possible to properly perform periodic transfer such as isochronous transfer. On the other hand, when the second mode is set, the SOF packet transfer is disabled and the aperiodic data transfer is performed. As a result, it is possible to generate transactions that cross the boundaries of a plurality of frames, and improve the transfer efficiency of aperiodic transfer such as bulk transfer and control transfer.

In the present invention, the transfer controller may transfer the SOF packet at the frame cycle even when the second mode is set when there is no aperiodic data to be transferred. .

By doing so, it is possible to prevent a situation in which another device connected to the bus shifts to an inappropriate state. Whether there is aperiodic data to be transferred or not can be determined by, for example, a transfer start instruction signal, a packet buffer full, an empty signal, or the like.

Further, according to the present invention, a state controller for controlling a plurality of states including a host operation state operating as a host role and a peripheral operation state operating as a peripheral role is included, and the packet buffer includes: A plurality of pipe areas in which data transferred to and from each endpoint are stored in the respective pipe areas are secured, and the transfer controller performs a data transfer as a host during the host operation, and a peripheral operation. Sometimes, the host controller includes a peripheral controller that transfers data as a peripheral, and the host controller automatically generates a transaction for the endpoint, and automatically transfers data between the pipe area and the endpoint corresponding to the pipe area. Turning It may be.

According to the present invention, for example, when the state controlled by the state controller becomes the state of the host operation, the host controller performs the data transfer as the role of the host. When the state controlled by the state controller becomes the state of peripheral operation, the peripheral controller performs data transfer as the role of the peripheral. This allows the so-called dual roll device function to be realized.

According to the present invention, a plurality of pipe areas are allocated to the packet buffer during host operation, and data is automatically transferred between the allocated pipe areas and the end points. This allows
The dual roll device function can be realized, and the processing load on the processing unit during host operation can be reduced.

Further, according to the present invention, when the second mode is set, the host controller periodically transfers the SOF packet between the pipe region and the aperiodic transfer endpoint corresponding to the pipe region. The non-periodic data may be automatically transferred while invalidating.

In this way, using the pipe region,
The aperiodic data can be automatically transferred to and from the aperiodic transfer endpoint, and the data transfer can be made efficient. At this time, in the present invention, the periodic transfer of the SOF packet is invalidated, so that the data transfer can be made more efficient. When invalidating the SOF packet transfer (when setting the second mode), cyclic transfer (isochronous transfer, etc.) is performed in the pipe area secured in the packet buffer.
It is desirable to assign endpoints of transfer types other than.

Also, in the present invention, when the host controller automatically sets the second mode when all the automatic transfer instruction signals in the pipe area are inactive,
The F packet may be automatically transferred at the frame cycle.

With this configuration, it is possible to determine whether or not there is data to be transferred based on the automatic transfer instruction signal, so that the determination process can be simplified. Then, when all the automatic transfer instruction signals are inactive (when there is no data to be transferred), by transferring the SOF packet, another device connected to the bus shifts to an inappropriate state. Etc. can be prevented.

Further, in the present invention, when the host controller activates the SOF transfer start trigger for each frame period and the transfer of the SOF packet is completed, the S
An SOF transfer start trigger generation circuit for deactivating the OF transfer start trigger, an automatic transfer instruction signal for the pipe region, a state information signal from the state controller,
The signal indicating the first or second mode is received, and the SO
An SOF invalid signal generation circuit that generates a signal for invalidating the F transfer start trigger may be included.

With this configuration, the processing for invalidating the transfer of the SOF packet can be realized with a simple circuit. In addition,
For example, when the state indicated by the state information signal is the host operation, the second mode is instructed, and at least one of the automatic transfer instruction signals is active, the invalid signal of the SOF transfer start trigger is activated and the SOF transfer is performed. Start trigger generation can be disabled. On the other hand, the state indicated by the state information signal is the host operation, and the second
When all the automatic transfer instruction signals are inactive even when the mode is instructed (when there is no data to be transferred)
In addition, the SOF transfer start trigger invalidation signal can be deactivated so that the generation of the SOF transfer start trigger is not invalidated.

Further, according to the present invention, at the time of peripheral operation, a plurality of endpoint areas in which data to be transferred to and from the host are stored in the respective endpoint areas are secured in the packet buffer, and the peripheral controller causes the endpoint controller to operate. Data may be transferred between the area and the host.

With this configuration, the buffer area of the packet buffer can be used as a pipe area during host operation and as an endpoint area during peripheral operation. This makes it possible to effectively use the resources of the packet buffer and reduce the processing load of the processing unit.

In the present invention, the aperiodic transfer is USB.
(Universal Serial Bus) standard bulk transfer or control transfer, and the aperiodic data may be bulk data or control data.

Further, according to the present invention, a USB (Universal Seri
Data may be transferred in conformity with the OTG (On-The-Go) standard of al Bus).

The present invention also provides any one of the above-mentioned data transfer control devices, a device for performing an output process, a fetch process, or a storage process of data transferred via the data transfer control device and a bus, and the data transfer The present invention relates to an electronic device including a processing unit that controls data transfer of a control device.

The present invention is also a data transfer control method for data transfer via a bus, which performs access control of a packet buffer for storing transfer data, controls data transfer of the packet buffer, and When the mode 1 is set, the data transfer is performed while transferring the SOF (Start Of Frame) packet at the frame cycle, and when the second mode is set and the aperiodic transfer is performed, the SOF packet The present invention relates to a data transfer control method that disables cyclic transfer and transfers aperiodic data.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION The present embodiment will be described below.

The present embodiment described below does not unduly limit the contents of the present invention described in the claims. Further, not all of the configurations described in the present embodiment are essential as the solving means of the present invention.

1. OTG First, OTG (USB On-The-Go) will be briefly described.

1.1 In the A device and B device OTG, Mini-A plugs and Mini-B plugs as shown in FIG. 1A are defined as connector standards. In addition, as a connector that can connect both of these Mini-A plugs and Mini-B plugs (broadly speaking, the first and second plugs of the cable), a Mini-AB receptacle (rec
eptacle) is defined.

Then, for example, as shown in FIG.
Electronic device P is connected to the Mini-A plug of the cable, and Min
When the electronic device Q is connected to the i-B plug, the electronic device P is set to the A device and the electronic device Q is set to the B device. On the other hand, as shown in FIG. 1C, when the Mini-B plug and the Mini-A plug are connected to the electronic devices P and Q,
The electronic devices P and Q are set to the B device and the A device, respectively.

In the Mini-A plug, the ID pin is connected to GND, and in the Mini-B plug, the ID pin is in a floating state. The electronic device uses the built-in pull-up resistor circuit to detect the voltage level of this ID pin to determine whether it is connected to the Mini-A plug or the Mini-B plug. To do.

In OTG, the A device (master) is
The power supply (VBUS) is the supply side (supply source), and the B device (slave) is the supply side (supply destination). The default state of the A device is the host, and the default state of the B device is the peripheral (peripheral device).

1.2 Dual-Role Device OTG defines a dual-role device capable of having both a role as a host (simple host) and a role as a peripheral.

The dual role device can be a host or a peripheral. Then, when the partner connected to the dual roll device is a host or peripheral in the conventional USB standard, the role of the dual roll device is uniquely determined. That is, if the connection partner is a host, the dual role device becomes a peripheral, and if the connection partner is a peripheral, the dual role device becomes a host.

On the other hand, when the connection partner is a dual role device, both dual role devices can exchange the roles of the host and the peripheral with each other.

1.3 SRP, HNP The dual roll device has a session start request procedure SRP (Session Requence) as shown in FIGS. 2 (A) and 2 (B).
est Protocol) and host exchange procedure HNP (HostNegotiat)
ion protocol) function.

Here, the session start request procedure SRP is
This is a protocol in which the B-device requests the A-device to supply VBUS (power supply).

In the OTG when the bus is not used, the A device can stop supplying VBUS. This gives A
When the device is, for example, a small mobile device, it is possible to prevent unnecessary power consumption. And A device is VBU
When the B device wants to supply VBUS after stopping the supply of S, the SRP is used to request the A device to restart the supply of VBUS.

FIG. 2 (A) shows the flow of SRP. Figure 2
As shown in (A), the B device has a data line
By performing pulsing and VBUS pulsing, supply of VBUS is requested to the A device. Then, after the supply of VBUS by the A device is started, the peripheral operation (peripheral operation) of the B device and the host operation (host operation) of the A device are started.

As described with reference to FIGS. 1 (A) to 1 (C), when connecting dual-role devices, Mini-
The A device on the side to which the A plug is connected becomes the default host, and the B device on the side to which the Mini-B plug is connected becomes the default peripheral. Then, in the OTG, the roles of the host and the peripheral can be exchanged without plugging and unplugging. HNP is a protocol for exchanging the roles of this host and peripherals.

The flow of HNP is shown in FIG. When the A device, which acts as the default host, finishes using the bus, the bus goes idle. After that,
When the B device disables the pull-up resistor of the data signal line DP (D +), the A device enables the pull-up resistor of DP. As a result, the role of the A device is changed from the host to the peripheral, and the operation as the peripheral is started. The role of the B device is changed from the peripheral to the host, and the operation as the host is started.

After that, when the B device finishes using the bus and the A device disables the DP pull-up resistor, the B device enables the DP pull-up resistor. As a result, the role of the B device returns from the host to the peripheral, and the operation as the peripheral is restarted.
The role of the A device returns from the peripheral to the host and resumes the operation as the host.

According to the OTG described above, it is possible to operate a mobile device such as a mobile phone or a digital camera as a USB host and connect the mobile devices peer-to-peer to transfer data. Become. This makes U
The SB interface can create new added value and create applications that have never existed before.

2. OHCI In the conventional USB, the data transfer control device (host controller) of the personal computer that is the host is the OHCI (Open
Host Controller Interface) and UHCI (Universa
l Host Controller Interface). Also, the OS (Operating System) used
Was limited to Microsoft's Windows and Apple's Macintosh OS.

However, in the small portable device which is the target application of OTG, the C
The architecture of the PU and the OS used vary widely. Furthermore, OHCI and UHCI standardized for host controllers of personal computers are USB
Assuming that the host functions are fully implemented, it is difficult to say that it is optimal for small portable devices.

For example, FIG. 3A shows an example of a descriptor having a list structure used in OHCI.

In FIG. 3A, the endpoint descriptors ED1, ED2, and ED3 are linked by a link pointer, and include information necessary for communication with the endpoints 1, 2, and 3. Then, transfer descriptors TD11 to TD13, TD21, TD31 to ED1, ED2 and ED3 are provided.
The TD 32 is further linked by the link pointer. Then, these transfer descriptors include information necessary for packet data transferred between the endpoints 1, 2, and 3.

The descriptor having the list structure of FIG. 3A is created by the firmware (host controller driver) operating on the CPU 610 (broadly speaking, processing unit) of FIG. 3B and written in the system memory 620. That is, the firmware allocates the endpoint descriptor to the endpoint in the system, and creates the endpoint descriptor and the transfer descriptor based on the endpoint information and the like. Then, these descriptors are linked by the link pointer and written in the system memory 620.

The data transfer control device 600 (host controller) reads the descriptor of the list structure written in the system memory 620 and executes the data transfer based on the information described in the endpoint descriptor and the transfer descriptor.

Specifically, the data transfer control device 600
The (host controller) sets the information of the endpoint 1 based on ED1, and TD1 linked to ED1
Based on 1, data transfer is performed with the endpoint 1. Next, set the information of the endpoint 2 based on ED2, and based on TD21 linked to ED2,
Data transfer is performed with the endpoint 2. Similarly, the data transfer control device 600 uses the TD31 and TD1.
2, data transfer is executed based on TD32 and TD13.

As described above, in the OHCI-compliant data transfer control device (host controller), the firmware (host controller driver) that operates on the CPU
However, it is necessary to create a descriptor having a complicated structure as shown in FIG. Therefore, the processing load of the CPU is very heavy.

In this case, in the conventional USB, only the personal computer is assigned the role of host, and this personal computer has a high-performance CPU. Therefore, it is possible to prepare a descriptor having a complicated structure as shown in FIG. 3A with a margin.

However, a CPU (embedded CPU) incorporated in a small portable device (digital camera, mobile phone, etc.), which is a target application of OTG, generally has much lower performance than the CPU of a personal computer. is there. Therefore, when the portable device is made to perform the host operation of the OTG, the CPU incorporated in the portable device is overloaded, which causes problems such as hindering other processing and degrading the data transfer performance.

3. Configuration Example FIG. 4 shows a configuration example of the data transfer control device of the present embodiment that can solve the above problems. The data transfer control device of this embodiment does not need to include all the circuit blocks in FIG. 4, and some of the circuit blocks may be omitted.

The transceiver 10 (hereinafter, appropriately referred to as Xcvr) uses the differential data signals DP and DM for USB.
A circuit that sends and receives data (bus in a broad sense)
It includes an SB physical layer (PHY) circuit 12. More specifically, the transceiver 10 generates DP, DM line states (J, K, SE0, etc.), serial / parallel conversion, parallel / serial conversion, bit stuffing,
Bit unstuffing, NRZI decoding, NRZ
Performs I encoding and the like. The transceiver 10 may be provided outside the data transfer control device.

The OTG controller 20 (state controller in a broad sense; hereinafter referred to as OTGC as appropriate) is an OT controller.
Various processes for realizing the SRP function and the HNP function of G (see FIGS. 2A and 2B) are performed. That is, OTG
The controller 20 controls a plurality of states including a host operation state operating as a host role and a peripheral operation state operating as a peripheral role.

More specifically, according to the OTG standard, the dual roll device A device (FIG. 1B,
(See (C)) and the state transition at the time of B device are defined. The OTG controller 20 includes a state machine for realizing these state transitions. The OTG controller 20 also includes a circuit that detects (monitors) the USB data line state, the VBUS level, and the ID pin state. And OT
The state machine included in the G controller 20 changes its state (for example, a state such as host, peripheral, suspend or idle) based on the detection information. The state transition in this case may be realized by a hardware circuit, or may be realized by the firmware setting a state command in a register. Then, when the state transitions, the OTG controller 20 determines the VB based on the state after the transition.
It controls US and controls connection / disconnection of pull-up / pull-down resistors of DP and DM. It also controls enable / disable of the host controller 50 (hereinafter appropriately referred to as HC) and the peripheral controller 60 (hereinafter appropriately referred to as PC).

HC / PC switching circuit 30 (HC / PC
The common circuit controls switching of the connection between the transceiver 10 and the host controller 50 or the peripheral controller 60. In addition, USB data (D
The transceiver 10 is instructed to generate the line state (P, DM). In addition, the connection switching control is H
This is realized by the C / PC selector 32, and the line state generation instruction is realized by the line state controller 34.

For example, when the OTG controller 20 activates the HC enable signal during the host operation (in the host state), the HC / PC switching circuit 30 (HC
The / PC selector 32) connects the transceiver 10 and the host controller 50. On the other hand, when the OTG controller 20 activates the PC enable signal during the peripheral operation (during the peripheral state), the HC
The / PC switching circuit 30 connects the transceiver 10 and the peripheral controller 60. By doing so, the host controller 50 and the peripheral controller 60 can be operated exclusively.

The transfer controller 40 is a circuit for controlling data transfer via USB (broadly speaking: bus), and includes a host controller 50 (HC) and a peripheral controller 60 (PC).

Here, the host controller 50 is a circuit that performs data transfer control as the role of the host during host operation (when the HC enable signal from the OTG controller 20 is active).

That is, the host controller 50 is connected to the transceiver 10 by the HC / PC switching circuit 30 during host operation. And the host controller 50
Automatically generates a transaction for the endpoint based on the transfer condition information set in the transfer condition register unit 72 of the register unit 70. Then, the pipe area (P) allocated in the packet buffer 100 is allocated.
IPE0 to PIPEe. Hereinafter referred to as PIPE as appropriate)
And automatic transfer of data (packet) (data transfer by a hardware circuit without a processing unit) between the end point and the end point corresponding to the pipe area.

More specifically, the host controller 50
Performs arbitration between multiple pipe transfers, time management in frames, transfer scheduling, and retransmission management. Further, transfer condition information (operation information) of pipe transfer is managed via the register unit 70. It also manages transactions, generates / disassembles packets, and issues suspend / resume / reset state generation instructions.

On the other hand, the peripheral controller 60 is
During peripheral operation (P from OTG controller 20)
This circuit performs data transfer control as a role of a peripheral when the C enable signal is active.

That is, the peripheral controller 60 is
During the peripheral operation, the HC / PC switching circuit 30 connects to the transceiver 10. Then, based on the transfer condition information set in the transfer condition register unit 72 of the register unit 70, data is transferred between the endpoint area (EP0 to EPe; hereinafter referred to as EP as appropriate) secured in the packet buffer 100 and the host. To transfer.

More specifically, the peripheral controller 60 manages transfer condition information (operation information) for endpoint transfer via the register unit 70. It also manages transactions, generates / disassembles packets, and issues remote wakeup signal generation instructions.

The end point is a point (portion) on the peripheral (device) to which a unique address can be assigned. All data transfer between the host and peripherals (devices) is done via this endpoint. The transaction is composed of a token packet, an optional data packet, and an optional handshake packet.

The register section 70 includes various registers for performing data transfer (pipe transfer, endpoint transfer) control, buffer access control, buffer management, interrupt control, block control, DMA control and the like.
The register included in the register unit 70 may be realized by a memory such as a RAM or a D flip-flop. Further, the registers of the register unit 70 are not combined into one, but each block (HC, PC,
(OTGC, Xcvr, etc.).

The register section 70 is a transfer condition register section 7
Including 2. The transfer condition register unit 72 stores transfer condition information (transfer control information) for data transfer between the pipe area (PIPE0 to PIPEe) secured in the packet buffer 100 during host operation and the endpoint. including. Each of these transfer condition registers is provided corresponding to each pipe area of the packet buffer 100.

During the peripheral operation, the packet buffer 100 stores the endpoint areas (EP0 to EP).
e) is secured. Then, based on the transfer condition information set in the transfer condition register unit 72, data transfer is performed between the data transfer control device and the host.

The buffer controller 80 (FIFO manager) controls access (read / write) to the packet buffer 100 and area management. More specifically, CPU (processor in a broad sense), DMA (Direct Mem)
ory Access), and generates and manages an access address to the packet buffer 100 by USB. Also, CP
It arbitrates access to the packet buffer 100 by U, DMA, and USB.

For example, when the host is operating, the buffer controller 80 uses the interface circuit 110 (CPU
(Or DMA) and the data transfer path between the packet buffer 100 and the data transfer path between the packet buffer 100 and the host controller 50 (USB).
To do.

On the other hand, during the peripheral operation, the buffer controller 80 uses the interface circuit 110 (C
The data transfer path between the PU or DMA) and the packet buffer 100 and the data transfer path between the packet buffer 100 and the peripheral controller 60 (USB) are set.

The packet buffer 100 (FIFO, packet memory, buffer) temporarily stores (buffers) data (transmission data or reception data) transferred via the USB. The packet buffer 100 is, for example, a RAM (Random Access Memory).
Etc. The packet buffer 100
May be provided outside the data transfer control device (may be an external memory).

During host operation, the packet buffer 10
0 is used as a FIFO (First-In First-Out) for pipe transfer. That is, in the packet buffer 100,
To correspond to each endpoint of USB (bus),
Pipe areas PIPE0 to PIPEe (buffer areas in a broad sense) are secured. In addition, each pipe area PIPE0 to
The PIPEe stores data (transmission data or reception data) transferred to and from each corresponding endpoint.

On the other hand, during the peripheral operation, the packet buffer 100 is used as a FIFO for endpoint transfer. That is, the endpoint areas EP0 to EPe (buffer areas in a broad sense) are secured in the packet buffer 100. In addition, each endpoint area EP0
The data (transmission data or reception data) transferred with the host is stored in to EPe.

The buffer area secured in the packet buffer 100 (the area set in the pipe area during the host operation and set in the endpoint area during the peripheral operation) outputs the previously input information first. Such a storage area (FIFO area) is set.

PIPE0 is a pipe area dedicated to control transfer endpoint 0,
Ea to PIPEe are general-purpose pipe areas that can be assigned to arbitrary endpoints.

That is, in the USB, the endpoint 0 is set as the dedicated endpoint for control transfer.
Therefore, by making PIPE0 a pipe area dedicated to control transfer as in the present embodiment, it is possible to prevent the user from being confused. In addition, PIPEa to PIPEe are
By setting the pipe area that can be assigned to an arbitrary endpoint, the pipe area corresponding to the endpoint can be dynamically changed. As a result, the flexibility of pipe transfer scheduling can be improved, and the efficiency of data transfer can be improved.

In this embodiment, the buffer area (pipe area or endpoint area) has the maximum packet size MaxPktSize (page size in a broad sense) and the number of pages.
The area size RSize is set by BufferPage (RSize = MaxPktSize × BufferPage). By doing so, it becomes possible to arbitrarily set the area size and the number of pages (the number of pages) of the buffer area.
The effective use of the resources can be achieved.

The interface circuit 110 is a circuit for transferring data between the packet buffer 100 and a DMA (system memory) bus or a CPU bus which is another bus different from the USB. The interface circuit 110 includes a DMA handler circuit 112 for performing DMA transfer between the packet buffer 100 and an external system memory. In addition, the packet buffer 10
A CPU interface circuit 114 for performing PIO (Parallel I / O) transfer between 0 and an external CPU is included. The CPU (processing unit) may be built in the data transfer control device.

The clock controller 120 has a built-in PL
Based on L or an external input clock, various clocks used inside the data transfer control device are generated.

4. Pipe Area In the present embodiment, as shown in FIG. 5A, the pipe areas PIPE0 to PIPE0 are stored in the packet buffer 100 during host operation.
PIPEe is allocated. Then, data is transferred between each of the pipe regions PIPE0 to PIPEe and each end point of the peripheral.

Here, the “pipe” in the pipe area of the present embodiment is a “pipe” defined by USB (a logical abstraction representing the relationship between the endpoint on the device and the software on the host, (Logical path) has a slightly different meaning.

As shown in FIG. 5A, the pipe area of this embodiment is secured on the packet buffer 100 corresponding to each endpoint of the peripheral connected to the USB (bus). For example, in FIG.
The pipe region PIPEa corresponds to the endpoint 1 of the peripheral 1 (bulk IN), and the PIPEb corresponds to the endpoint 2 of the peripheral 1 (bulk OUT).
PIPEc is the endpoint 1 of peripheral 2.
Corresponding to (Bulk IN), PIPEd is peripheral 2
End point 2 (bulk OUT). PIPEe is the end point 1 of peripheral 3.
Corresponds to (Interrupt IN). PIPE0
Is a pipe area dedicated to the endpoint 0 of control transfer.

In the example of FIG. 5A, the pipe area P
Bulk IN transfer of USB is performed between the IPEa and the end point 1 of the peripheral 1, and bulk OUT transfer is performed between the PIPEb and the end point 2 of the peripheral 1. Further, bulk IN transfer is performed between PIPEc and the endpoint 1 of the peripheral 2, and P
Bulk OUT transfer is performed between the IPEd and the endpoint 2 of the peripheral 2. Further, the interrupt IN transfer is performed between the PIPEe and the endpoint 1 of the peripheral 3.

As described above, in this embodiment, between the pipe area (general-purpose) and the corresponding endpoint,
Arbitrary data transfer (isochronous transfer, bulk transfer,
Interrupt transfer) can be performed.

In the present embodiment, data of a given data unit (data unit designated by total size) is transferred between the pipe area and the endpoint corresponding thereto. The data unit in this case is, for example, I
A data unit requested to be transferred by an RP (I / O request packet) or a data unit obtained by dividing the data unit into an appropriate size can be considered. The data transfer (a series of transactions) of this data unit to the endpoint can be called a "pipe" in this embodiment. An area for storing such "pipe" data (transmission data, reception data) becomes a pipe area.

When the transfer of a given data unit using the pipe area is completed, the pipe area can be released. Then, the released pipe area can be allocated to an arbitrary endpoint. As described above, in the present embodiment, the correspondence between the pipe area and the endpoint is
It can be changed dynamically.

Further, in this embodiment, as shown in FIG. 5B, the packet buffer 100 is operated during the peripheral operation.
The endpoint areas EP0 to EPe are secured (set) in the. Then, each of these end point regions EP0 to EP
Data is transferred between e and the host (host controller, system memory).

As described above, in this embodiment, the buffer area of the packet buffer 100 is allocated to the pipe area during the host operation and to the endpoint area during the peripheral operation. As a result, the resources of the packet buffer 100 can be shared (shared) between the host operation and the peripheral operation, and the storage capacity used by the packet buffer 100 can be saved.

The number of pipe areas and endpoint areas is not limited to six, and is arbitrary.

5. SOF-less mode (Transfer mode without SOF only bulk) USB standard (USB1.1, USB2.0, OT
(G, etc.), four types of transfer types (isochronous, bulk, control, interrupt) are defined. The USB host controls and manages the transfer order of these transfer type packets, and instructs the transfer of each transfer type packet. Therefore, in the USB, the host manages the frame, and as shown in FIG. 6A, the SOF (Start Of Fram) is performed for each frame (1 ms, 125 μs).
e) Issue the packet to the peripheral.

The SOF is a token packet for indicating the beginning of the frame and includes the PID, frame number and CRC. This SOF is transmitted by the host. The host manages scheduling so that one transaction does not span multiple frames. Also, a frame is the interval between an SOF and the next SOF. Bulk transfer is a method of transferring a large amount of data such as print data and image data aperiodically.

In isochronous transfer and interrupt transfer, which are cyclic (synchronous) transfers, information such as frame timing and frame number is important. Therefore, an SOF packet is required to convey this information.

On the other hand, in bulk transfer and control transfer, which are aperiodic transfers, it is considered that such information is not particularly necessary. However, in USB, the host transfers the SOF packet even in the case of such aperiodic transfer. Are demanding to do so.

However, when the SOF packet is transferred in the non-periodic transfer such as the bulk transfer, the transfer of the SOF packet itself consumes the bus band. Further, as shown in FIG.
The presence of the packet causes a transfer prohibited period (transfer prohibited area) at the end of the frame, further narrowing the bus band.

The USB is widely used for transfer of print data of a printer, transfer of image data of a digital camera, transfer of storage data of a storage device, etc., and bulk transfer is used for transfer of these data. . Therefore, in this bulk transfer, SO that is not originally necessary
If the bus bandwidth is narrowed by the F packet, resources are wasted.

Therefore, in this embodiment, a method of canceling the transfer of the SOF packet (packet instructing the start of the frame) in the non-periodic transfer such as bulk transfer is adopted.

More specifically, when the SOF mode (first mode in a broad sense) is set, data transfer is performed while transferring the SOF packet (SOF token packet) at the frame cycle. On the other hand, when the SOF-less mode (second mode in a broad sense) is set and the aperiodic transfer (bulk transfer or control transfer) is performed, the cyclic transfer of the SOF packet is disabled and the asynchronous data (bulk data Or control data, etc.).

FIG. 7, FIG. 8 and FIG. 9 show examples of signal waveforms of data transfer by the method of this embodiment.

For example, in FIG. 7, when an instruction to start an automatic transaction is issued by the firmware (processing unit), PipeXTranGo (a transfer request signal from the firmware for PipeX) becomes active, as indicated by C1. As a result, the automatic transaction processing by the host controller 50 for the PipeX (X = 0 to e) is started.

Here, in FIG. 7, EnNoSOFMode (SOF
No mode, SOF no bulk only transfer mode specified) is inactive (L level),
It is set to the existence mode (first mode). Therefore, in this case, the host controller 50 (transfer controller in a broad sense, the same applies in the following description) generates an SOF packet as indicated by C2 and transfers it to the peripheral.

Next, as shown in C3, PipeTranGo (transfer request signal from the HC sequence management circuit in the host controller 50) becomes active, and the host controller 50 automatically generates a transaction to send a packet as shown in C4. Forward. This transaction consists of a token packet, an optional data packet,
It consists of optional handshake packets. Then, when the transaction is completed, TranCmpACK becomes active as shown in C5. Next, PipeTranGo becomes active as shown in C6, the next transaction is made as shown in C7, and when the transaction ends, TranCmpACK becomes active as shown in C8.

As described above, the host controller 50
Automatically generates transactions one after another and automatically transfers the packets constituting the transaction. Then, when the remaining frame time becomes short and the transfer prohibited period is reached as indicated by C9, the generation of the transaction in the frame is ended.

That is, the USB defines a transfer prohibition period at the end of the frame, and packet transfer is prohibited during this period. Therefore, the host controller 5
0 does not generate a transaction during this transfer prohibition period. Then, after one frame (1 ms) interval has passed from the previous SOF transfer shown in C2, C1
The next SOF is transferred as indicated by 0. As a result, the next frame starts, and the host controller 50 sets the C1
As shown in 1, a transaction is automatically generated in the next frame.

As described above, in this embodiment, when the mode with SOF is set, SOF packets are periodically generated for each frame and transferred to the peripheral, as indicated by C2 and C10. This makes it possible to properly perform periodic transfer such as isochronous transfer.

On the other hand, in this embodiment, as shown in FIG.
When EnNoSOFMode becomes active (H level), SO
The F-free mode (second mode) is set. Then,
The host controller 50 does not perform the periodic transfer of the SOF packet as indicated by D1, D2, and D3. Then, as shown in D4 to D15, bulk transfer transactions are continuously executed without interruption.

That is, in the SOF mode of FIG. 7, no transaction is executed (no packet is transferred) during the transfer prohibition period shown at C9.

On the other hand, the SOF-less mode (S
In the bulk mode without OF only transfer mode), as shown in D7, the transaction is executed even during the transfer prohibited period. Further, at the frame start timing shown in D2, SO
Without transferring the F packet, the transaction is executed during the SOF transfer period as shown in D8.

In this way, as is clear from a comparison between FIGS. 7 and 8, during the bulk transfer (when transferring only the bulk), the transfer period of the SOF packet and the transfer prohibition period (prohibition area) at the end of the frame. ) Combined period (band)
Can be assigned to a bulk transfer. That is,
Transactions that span multiple frames can be generated. As a result, the bus band is widened and the transfer efficiency can be improved.

When the SOF-free mode is set, it is desirable to set the transfer type of the pipe area in FIG. 5A to bulk transfer (aperiodic transfer). That is, the firmware or the like does not set the transfer type of the pipe area to the periodic transfer such as isochronous transfer or interrupt transfer. As a result, proper periodic transfer can be realized.

6. Issuing SOF when there is no data to be transferred In some cases, depending on the situation of the application, continuous bulk transfer without interruption as shown in FIG. 8 may not be possible, and the data to be transferred may not exist for a certain period of time.

In such a case, if the SOF-less mode is set, there is a risk that the bus activity will be lost and the peripheral (device) state will shift to suspend or the like.

Therefore, in this embodiment, when there is no bulk (aperiodic) data to be transferred, the SOF packet is transferred at the frame cycle even when the SOF-less mode (second mode) is set. I have to.

That is, in FIG. 9, EnNoBulkMode is active (H level), and the SOF-less mode is set. Therefore, the SOF packet is not issued as indicated by E1 and E2, and the bulk transfer transactions are continuously executed as indicated by E3 to E6.

However, at E7 in FIG. 9, there is no data to be transferred (transaction to be executed) due to continuous execution of transactions. In such a case, in the present embodiment, the host controller 50 automatically transfers the SOF packet to the peripheral, as indicated by E8, E9, and E10, even though the SOF-less mode is set. The transfer of the SOF packet can prevent a situation in which bus activity occurs and the peripheral shifts to the suspend, and proper data transfer can be realized.

Whether or not there is data to be transferred can be detected, for example, by the automatic transaction start instruction signal or by monitoring the state (full or empty signal) of the packet buffer 100. .

More specifically, for example, in FIG. 5A, when the automatic transfer start instruction signals (PipeXTranGo: X = 0 to e) of the pipe regions PIPE0 to PIPEe are all inactive, the data to be transferred is Judge that there is no. When such a determination is made, the SOF packet is automatically transferred even if the SOF-less mode is set. By doing so, it is possible to easily determine whether or not there is data to be transferred, by processing with a small load.

7. Circuit Example FIG. 10 shows a specific example of a circuit that invalidates the periodic transfer of SOF packets. The circuit of FIG. 10 is included in the host controller 50 of FIG.

The SOF transfer start trigger generation circuit 200
SOFTranGo (SOF transfer start trigger) every frame cycle
Is made active (logical value “1” = H level), and SOF
It is a circuit that makes SOFTranGo inactive (logical value “0” = L level) when packet transfer is completed.

Specifically, the SOF transfer start trigger generation circuit 200 receives RemainCount (frame remaining time count value) and CLK (clock signal) from the OTG controller 20 (state controller) of FIG. In addition, SOFTranComp (SOF
Receive a transfer completion signal). Then, SOFTranGo is activated (“1”) every frame cycle based on RemainCount. When SOFTranComp becomes active and the CLR (clear signal) output from the AND circuit AND1 becomes active (“0”), SOFTranGo
To inactive (“0”). As a result, a pulse-shaped trigger signal SOFT that becomes active every frame period
Can generate ranGo.

The SOF invalid signal generation circuit 210 (SOF-less mode condition determination circuit) operates in Pipe0TranGo to PipeeTranGo.
(Transfer start instruction signals for the pipe areas PIPE0 to PIPEe), HCState [1], [0] (state information signals from the OTG controller 20), and EnNoSOFMode (SOF-less mode instruction signal, SOF-less bulk transfer only mode instruction signal) In a broad sense, receive a signal indicating the first or second mode). And a signal to disable SOFTranGo (SOFTran
SOFCancel which is a signal that sets Go to always be inactive. The SOF invalid signal generation circuit 210 includes OR circuits OR1 and OR2 and an AND circuit AN.
D2, AND3, AND4, inverter circuit INV2,
Includes INV3.

Here, Pipe0TranGo to PipeeTr is set to OR1.
anGo is input. This PipeXTran (X = 0 ~ e) is shown in Fig. 7.
As indicated by C1 and C12 in FIG. 1, the firmware (processing unit) becomes active (“1”) when the automatic transfer of each pipe area is instructed, and the automatic transfer by the host controller 50 for the pipe area is completed. This signal is sometimes inactive ("0").

HCState [1] and [0] are input to AND2. As shown in FIG. 11 (A), these HCStates [1] and [0] are the states in which the states of the data transfer control device controlled by the OTG controller 20 of FIG. 4 (OTG states of the A device and B device) are suspended. , Reset, Resume, Host Operation (Host Operation)
The signals are "00", "01", "10", and "11".

EnNoSOFMode is input to INV2.
This EnNoSOFMode is SOF as shown in C13 of FIG.
It becomes inactive ("0") in the presence mode (first mode), and active ("1") in the SOF-less mode (second mode) as shown in D16 of FIG.
Is a signal that becomes.

AND1, AND2, INV are applied to AND3.
2 outputs Q1, Q2, Q3 are input, and INV3 has Q
1 is input. The output Q4 of INV3 and the output Q2 of AND2 are input to AND4. AND for OR2
3, output of AND4 Q5, Q6 is input, SOFCancel
Is output.

FIG. 11B shows a truth table of the SOF invalid signal generation circuit 210.

As shown in F1 of FIG. 11 (B), HCStat
When e [1] and [0] are "00", "01", or "10", SOFCancel becomes "0". That is, when the state of the data transfer control device (host controller 50) is suspend, reset, or resume, SOFCance
Since l becomes “0” and SOFTranGo always becomes “0”, the periodic transfer of SOF packets is invalidated.

As shown in F2 of FIG. 11 (B), HCStat
When e [1] and [0] are “11” and EnNoSOFMode is “0”, SOFCancel is “1”. That is, when the state is the host operation (Host Operation) and the SOF mode is set (EnNoSOFMode = "0"),
As shown by C2 and C10 in FIG. 7, data transfer is performed while the SOF packet is transferred at the frame cycle.

As shown in F3 of FIG. 11 (B), HCStat
When e [1] and [0] are “11”, EnNoSOFMode is “1”, and at least one of Pipe0TranGo to PipeeTranGo is “1”, SOFCancel becomes “0”. That is,
State is host operation, SOF-less mode (EnNo
When SOFMode = “1”) is set and there is data to be transferred, the periodic transfer of SOF packets is invalidated as indicated by D1, D2, and D3 in FIG. And FIG.
As indicated by D4 to D15, the bulk data transaction is continuously executed without interruption over the frames. That is, the host controller 50 automatically transfers bulk data (packet) between the pipe area and the bulk (aperiodic) transfer endpoint corresponding to the pipe area while disabling the periodic transfer of the SOF packet.

As shown in F4 of FIG. 11 (B), HCStat
When e [1] and [0] are “11”, EnNoSOFMode is “1”, and all of Pipe0TranGo to PipeeTranGo are “0”, SOFCancel becomes “1”. That is, the state is the host operation, and the SOF-less mode (EnNoSOFMode =
Even if it is set to "1", if there is no data to be transferred (Pipe0TranGo to PipeeTranGo = "0"), the SOF packet is periodically transferred as shown in E8, E9, and E10 of FIG. To be done. That is, the host controller 50
Is a pipe area automatic transfer start instruction signal Pipe0TranGo to P
If all ipeeTranGo are inactive (“0”),
Judge that there is no data to transfer. In this case, the SOF packet is automatically transferred at the frame cycle even if the SOF-less mode is set. As a result, it is possible to prevent a situation in which the peripheral accidentally shifts to the suspend state.

8. Transfer condition register (shared register) In the present embodiment, as shown in FIG. 12, transfer condition information (transfer direction, transfer type, maximum) of data transfer performed between the pipe areas PIPE0 to PIPEe and the endpoint during host operation. The packet size or the number of pages) is set in the transfer condition registers TREG0 to TREGe. That is, PIPE0, PIPEa, PIPE
The transfer condition information of b, PIPEc, PIPEd, PIPEe is TREG0, TREGa, TREGb, T, respectively.
It is set (stored) in REGc, TREGd, and TREGe. This setting is performed by firmware (CPU), for example.

The host controller 50 (transfer controller in a broad sense) transfers the transfer condition registers TREG0 to TREG0.
A transaction for the endpoint is generated based on the transfer condition information set in TREGe. Then, data (packet) is automatically transferred between the pipe area and the corresponding endpoint.

As described above, in this embodiment, each transfer condition register is provided corresponding to each pipe region (buffer region), and based on the transfer condition information set in each transfer condition register, each pipe region Pipe transfer (transfer of a given data unit) is automatically performed by the host controller 50. Therefore, after setting the transfer condition information in the transfer condition register, the firmware (driver, software) does not need to be involved in the data transfer control until the data transfer is completed. Then, when the pipe transfer of the given data unit is completed, an interrupt is generated and the completion of the transfer is notified to the firmware. As a result, the processing load on the firmware (CPU) can be significantly reduced.

In this embodiment, as shown in FIG. 13, during the peripheral operation, the end point regions EP0 to EP0.
Transfer condition information (transfer direction, transfer type, max packet size, number of pages, etc.) of data transfer performed between the EPe and the host is transfer condition registers TREG0 to TREG.
It is set to EGe. Then, the peripheral controller 60 (transfer controller in a broad sense) performs data transfer between the endpoint area and the host based on the transfer condition information set in the transfer condition registers TREG0 to TREGe.

As described above, in this embodiment, the transfer condition registers TREG0 to TREGe are shared (shared) between the host operation and the peripheral operation. As a result, the resources of the register unit 70 can be saved and the data transfer control device can be downsized.

FIG. 14 shows a register configuration example of the register section 70. In addition, a part of the registers of the register unit 70 is
It may be included in each block (OTGC, HC, PC, Xcvr, etc.).

As shown in FIG. 14, the transfer condition registers (each of TREG0 to TREGe) of the register section 70 are
It includes an HC / PC shared register (shared transfer condition register) shared during host operation (HC, PIPE) and peripheral operation (PC, EP). It also includes an HC (PIPE) register (host transfer condition register) used only during host operation. Further, it includes a PC (EP) register (peripheral transfer condition register) used only during peripheral operation. Further, it is a register for performing access control of the packet buffer (FIFO) and the like, and includes an access control register shared during host operation and peripheral operation.

For example, during host operation of the dual roll device, the host controller 50 (HC)
/ Transfer data (packet) based on the transfer condition information set in the PC shared register and the HC register.

On the other hand, during the peripheral operation, the peripheral controller 60 (PC) transfers data (packet) based on the transfer condition information set in the HC / PC shared register and the PC register.

In both the host operation and the peripheral operation, the buffer controller 80 uses the shared access control register to determine whether the packet buffer 10 is to be operated.
Access control to 0 (generation of read / write address, data read / write, access arbitration, etc.) is performed.

In the HC / PC shared register of FIG. 14, the data transfer direction (IN, OUT, SETUP, etc.), transfer type (transaction type such as isochronous, bulk, interrupt, control), end point number (each USB). The maximum packet size (maximum payload size of packets that the endpoint can send or receive. Page size) is set. Further, the number of pages (number of faces of the buffer area) of the buffer area (pipe area, endpoint area) is set. In addition, information indicating the presence / absence of a DMA connection (presence / absence of use of DMA transfer by the DMA handler circuit 112) is set.

In the HC (PIPE) register, a token issue cycle (interrupt transaction activation cycle, interval) of interrupt transfer is set. In addition, the number of continuous executions of transactions (information for setting the transfer ratio between pipe areas. The number of continuous executions of transactions in each pipe area) is set. Further, a function address (USB address of a function having an end point) and a total size of transfer data (total size of data transferred through each pipe area, data unit such as IRP) are set. In addition, an automatic transaction start instruction (an automatic transaction process start instruction to the host controller) is set. Further, an instruction of the automatic control transfer mode (instruction of a mode for automatically generating a control transfer setup stage, data stage, and status stage transaction) is set.

Endpoint enable (endpoint enable or disable instruction) and handshake designation (handshake designation performed in each transaction) are set in the PC (EP) register.

The shared access control register for the packet buffer (FIFO) includes a buffer / I / O port (C
The I / O port for PIO transfer by the PU is set. In addition, buffer full / empty (notification of full / empty of each buffer area) and buffer / remaining data size (remaining data size of each buffer area) are set.

The register section 70 also includes an interrupt system register, a block system register, a DMA control register and the like.

The interrupt system registers include an interrupt status register for indicating the status (factor) of the interrupt to the CPU, and an interrupt enable register for setting interrupt enable and disable (non-mask, mask). For interrupts, the OTG controller 20 system and the host controller 5
There are interrupts of the 0 system and the peripheral controller 60 system.

Block-related registers include inter-block shared registers shared between blocks and each block (Xcv
r, OTGC, HC, PC).

The inter-block shared register includes a register for instructing reset of each block. The block register includes a register for controlling the transceiver 10 (Xcvr) and an OTG controller 20 (OTG).
There are a C) state command register, a host controller 50 (HC) state command register, a frame number setting register, and the like.

As described above, according to the present embodiment, the register (HC / HC) shared between the host operation and the peripheral operation is used.
A PC shared register and a shared access control register) are provided in the register unit 70. As a result, the register unit 70 can be made smaller than in the case where the register for host operation and the register for peripheral operation are provided separately. Further, the access address of the shared register viewed from the firmware (driver) operating on the CPU can be made the same during the host operation and the peripheral operation. Therefore, the firmware can manage these shared registers at the same address, and the firmware processing can be simplified.

By providing the HC register and the PC register, it is possible to set transfer conditions specific to the transfer during the host operation (PIPE) and the transfer during the peripheral operation (EP). For example, by setting the token issue period, it becomes possible to issue the interrupt transfer token at a desired period during host operation. Further, by setting the number of continuous executions, it is possible to arbitrarily set the transfer ratio between the pipe regions during host operation. Further, by setting the total size, it is possible to arbitrarily set the size of data that is automatically transferred through the pipe area during host operation. Further, the firmware can instruct the start of the automatic transaction and the on / off of the automatic control transfer mode when the host operates.

9. Automatic Transaction FIG. 15 shows an example of a flowchart of firmware processing during automatic transaction (IN, OUT) processing of the host controller 50.

First, the firmware (processing unit, driver) sets transfer condition information (pipe information) in the transfer condition register described in FIG. 14 and the like (step S1). More specifically, the total size of transfer data, the maximum packet size (MaxPktSize), and the number of pages (BufferPag
e), transfer direction (IN, OUT, or SETUP), transfer type (isochronous, bulk, control, interrupt), endpoint number, number of consecutive executions of pipe area transactions (transfer ratio), interrupt issue token issue period, etc. , Set in transfer condition register.

Next, a transfer path is set between the external system memory and the packet buffer 100 (step S
2). That is, D via the DMA handler circuit 112 of FIG.
Set MA transfer path.

Next, the firmware issues a DMA transfer start instruction (step S3). That is, the DMA of FIG.
The DMA transfer start instruction bit of the control register is activated. In the transfer by the CPU, the packet buffer 100 can be accessed by accessing the buffer / I / O port of FIG.

Next, the firmware gives an instruction to start an automatic transaction (step S4). That is, FIG.
4 activates the automatic transaction start instruction bit of the HC register (pipe register). As a result, the host controller 50 performs automatic transaction processing, packet processing (packet generation and disassembly), and scheduling processing. That is, the host controller 50 automatically transfers the data specified by the total size in the direction (IN, OUT) specified by the transfer direction using the packet of the payload of the maximum packet size.

The order of the processes of steps S3 and S4 does not matter, and the DMA transfer start instruction may be issued after the automatic transaction start instruction.

Next, the firmware waits for the generation of an interrupt indicating the completion of the pipe transfer (step S
5). When an interrupt occurs, the firmware checks the interrupt status (factor) of the interrupt system register in FIG. Then, the process ends normally or ends in error (step S6).

As described above, according to the present embodiment, the firmware sets transfer condition information for each pipe area (step S1), and gives a DMA transfer start instruction (step S3).
By simply instructing to start the automatic transaction (step S4), the subsequent data transfer processing is automatically performed by the hardware circuit of the host controller 50. Therefore, the OH described in FIGS.
As compared with the CI-compliant method, the processing load of the firmware is reduced, and it is possible to provide the optimum data transfer control device for the mobile device incorporating the low-performance CPU.

10. Detailed configuration example of each block Next, a detailed configuration example of each block will be described.

10.1 OTG Controller FIG. 16 shows a configuration example of the OTG controller 20.

The OTG controller 20 includes an OTG register section 22. The OTG register unit 22 is
It includes a monitor register and a control register of the controller 20. It also includes a circuit for decoding the OTG state command written by the firmware (CPU).

The OTG controller 20 also includes an OTG control circuit 23. Then, the OTG control circuit 23
OTG management circuit 24 for managing the OTG state, ID
ID detection circuit 25 for detecting the voltage level of the pin, VBU
VBUS detection circuit 26 for detecting the voltage level of S, DP
And a line state detection circuit 27 for detecting the line state of DM.

Further, the OTG controller 20 includes a timer 28 for measuring the time which is one of the conditions for judging the transition of the OTG state.

Information to be detected in order to transit the OTG state is ID, voltage level of VBUS, DP / DM.
Is the line state of. The OTG controller 20 of the present embodiment detects these pieces of information and transmits them to the firmware (CPU) via the monitor register.

The firmware transits its own state on the basis of these detection information, and uses the OTG state command to OT the next state to transit to.
Notify the G controller 20.

The OTG controller 20 decodes the OTG state command and performs drive control of VBUS, connection control of pull-up / pull-down resistors, etc. based on the decoding result, which will be described with reference to FIGS. 2 (A) and 2 (B). It realizes SRP and HNP.

As described above, in this embodiment, the OTG controller 20 takes charge of OTG control for each state, and the firmware can concentrate on state transition management. As a result, the processing load of the firmware (CPU) can be reduced and efficient firmware development can be performed as compared with the case where all state control is realized by firmware.

The determination of the OTG state transition may be made by the hardware circuit instead of the firmware. Alternatively, almost all the processing of the OTG controller 20 (for example, processing other than VBUS control, pull-up / pull-down resistance control, ID detection, VBUS detection, line state detection) may be implemented by firmware (software).

10.2 Host Controller, Peripheral Controller FIG. 17A shows a configuration example of the host controller 50.

The host controller 50 includes an HC sequence management circuit 52. This HC sequence management circuit 52
Performs pipe transfer (data transfer using a pipe area) arbitration, time management, pipe transfer scheduling, retransmission management, and the like.

More specifically, the HC sequence management circuit 5
2 is the frame number count and SOF (Start-Of-F
rame) Send a packet. Also, processing for preferentially executing isochronous transfer at the beginning of each frame, and processing for preferentially handling interrupt transfer next to isochronous transfer are performed. In addition, processing for instructing each pipe transfer is performed according to the pipe transfer order. It also manages the number of consecutive executions of transactions and confirms the remaining frame time. In addition, the handshake packet (AC
K, NAK) are processed. It also performs error handling during transaction execution.

The host controller 50 includes a target pipe management circuit 54. The target pipe management circuit 54 performs handling processing of transfer condition information set in the transfer condition register of the register unit 70.

More specifically, the target pipe management circuit 54 performs transfer condition information selection processing and interrupt signal generation processing. When the start of an automatic transaction is instructed, the total size of transfer data in the pipe area is loaded. Then, the remaining transfer data size is counted (decremented). Further, when transmitting / receiving data to / from the buffer controller 80, a process of confirming the state of the buffer (FIFO) area is performed. Also,
A transfer instruction is issued to the transaction management circuit 56. In addition, judgment processing of unexpected short packet reception,
The judgment processing of the reception of the packet of the maximum packet size or more is performed. When the mode for automatically transferring the zero-length packet is set, the transaction management circuit 56 is instructed to transmit the last zero-length packet. It also manages sequences in the automatic control transfer mode.

The host controller 50 includes a transaction management circuit 56. The transaction management circuit 56 manages the types of transfer packets and the transfer sequence (transaction sequence management). In addition, it monitors the timeout. It also performs transaction end notification processing.

The host controller 50 includes a packet handler circuit 58. This packet handler circuit 58 is
Generates and decomposes packets. It also checks the PID and decodes and encodes the CRC. In addition, the payload of the packet in the buffer area is read and written, and the SOF packet is transmitted. Also, the transmission / reception data counting process is performed.

FIG. 17B shows a configuration example of the peripheral controller 60.

The peripheral controller 60 includes a transaction management circuit 62 and a packet handler circuit 64. The transaction management circuit 62 and the packet handler circuit 64 are the transaction management circuit 56 and the packet handler circuit 58 of the host controller 50.
Performs almost the same processing as.

10.3 Buffer Controller FIG. 18 shows a configuration example of the buffer controller 80.

The buffer controller 80 reserves the area (al
location) circuit 82. This area securing circuit 82
It is a circuit that secures a buffer area (area set in the pipe area during host operation and set in endpoint area during peripheral operation) in the packet buffer 100.

The area reservation circuit 82 includes an area calculation circuit 83. The area calculation circuit 83 is a circuit for calculating the area size, start address, end address, etc. of the buffer area based on the maximum packet size (page size in a broad sense) and the number of pages.

For example, the buffer area P shown in FIG.
IPE0 / EP0, PIPEa / EPa, PIPEb /
In EPb and PIPEc / EPc, the maximum packet size (MaxPktSize) is 32, 64, 64, 64, respectively.
The number of pages (BufferPage) is set to bytes,
It is set to pages 1, 1, 3, and 2. The area calculation circuit 83 determines the buffer area PIPE0 / EP0 / PI0-PI based on the maximum packet size, the number of pages, and the like.
The area size of PEc / EPc, start address, and end address are calculated. For example, in FIG. 19 (A),
PIPE0 / EP0, PIPEa / EPa, PIPEb
The area sizes of / EPb and PIPEc / EPc are
32 (= 32 × 1), 64 (= 64 × 1), 192 (=
It is calculated as 64 × 3) and 128 (= 64 × 2) bytes.

The pointer allocation circuit 84 uses the write pointers WP (WP0, WPa, WP) of the respective buffer areas.
b, WPc), read pointer RP (RP0, RP
a, RPb, RPc) are assigned to the DMA pointer, the CPU pointer, and the USB pointer.

For example, as shown in FIG. 19B, during data transmission (from DMA or CPU to packet buffer 100
(When data is transferred to the USB side via USB) and when DMA transfer is used, the write pointer WP of the buffer area is assigned to the pointer for DMA (DMA access), and the read pointer RP is USB (U).
It is assigned to a pointer for SB access). Also,
During data transmission and when using CPU (PIO) transfer, the write pointer WP of the buffer area is the CPU
The pointer for (CPU access) is assigned, and the read pointer RP is assigned to the pointer for USB.

On the other hand, as shown in FIG. 19C, when data is received (from the USB via the packet buffer 100, D
When data is transferred to the MA or CPU side) and when DMA transfer is used, the write pointer WP of the buffer area is assigned to the USB pointer and the read pointer RP is assigned to the DMA pointer. When receiving data and using CPU transfer, the write pointer WP of the buffer area is USB.
Assigned to the read pointer RP and the read pointer RP is assigned to C
It is assigned to the PU pointer.

The pointer information (positional information) of the write pointer WP and the read pointer RP of each buffer area is stored in each transfer condition register (PIP) of the register unit 70.
E / EP register).

The pointer management circuit 86 is a circuit for generating a real address for accessing the packet buffer 100 while updating the pointer.

The pointer management circuit 86 includes a CPU address generation circuit 87, a DMA address generation circuit 88, and a US
A B address generation circuit 89 is included. These generation circuits 8
Reference numerals 7, 88, and 89 denote CPU addresses based on the CPU pointer, the DMA pointer, and the USB pointer assigned by the pointer assigning circuit 84, respectively.
The DMA address and the USB address are generated. In addition, CPU (CPU interface circuit), DMA
Each access from (DMA handler circuit) or U
SB (HC or PC) transaction end (AC
The pointer is updated for each handshake (K, NAK, etc.). The updated pointer information is written back to each transfer condition register of the register unit 70 via the area securing circuit 82.

The buffer management circuit 90 is a circuit for managing access to the packet buffer 100.

The buffer management circuit 90 includes a buffer interface circuit 92. The buffer interface circuit 92 receives a CPU address, a DMA address, a USB address, etc. from the pointer management circuit 86, and inputs / outputs data to / from the packet buffer 100, and addresses, output enable, write enable, read enable, etc. Is output.

The buffer management circuit 90 includes an arbitration circuit 93. The arbitration circuit 93 includes a CPU (CPU interface circuit), a DMA (DMA handler circuit), and a USB.
(Host controller or peripheral controller)
It is a circuit that arbitrates access from. Based on the arbitration result, the CPU address, the DMA address, the US
One of the B addresses is output as the access address of the packet buffer 100, and the data transfer path between the CPU, DMA or USB and the packet buffer 100 is set.

The HC / PC selector 94 includes a buffer management circuit 90 (buffer controller 80) and a host controller 50 (HC) or a peripheral controller 60.
Controls switching of connection with (PC). For example, during host operation, the host controller 50 and the buffer management circuit 90 are connected, and during peripheral operation, the peripheral controller 60 and the buffer management circuit 90 are connected. The connection switching control is performed based on the HC / PC enable signal from the OTG controller 20 (OTGC).

11. Electronic Device Next, examples of electronic devices including the data transfer control device of the present embodiment will be described.

For example, FIG. 20A shows an internal block diagram of a printer which is one of the electronic devices, and FIG. 21A shows its external view. The CPU 510 (processing unit) controls the entire system. The operation unit 511 is for the user to operate the printer. The ROM 516 stores a control program, fonts, etc., and a RAM 517.
The (system memory) functions as a work area of the CPU 510. The DMAC 518 is a DMA controller for performing data transfer without going through the CPU 510. The display panel 519 is for notifying the user of the operating state of the printer.

Personal computer via USB,
Serial print data (print data, sent from other devices such as digital cameras and digital video cameras)
The image data) is converted into parallel print data by the data transfer control device 500. Then, the converted parallel print data is sent to the print processing unit (printer engine) 512 by the CPU 510 or the DMAC 518. Then, a given process is performed on the parallel print data in the print processing unit 512, and a print unit (device that performs data output processing) 514 including a print header and the like.
Is printed on paper and output.

FIG. 20B shows an internal block diagram of a digital camera which is one of the electronic devices, and FIG. 21B shows its external view. The CPU 520 controls the entire system. The operation unit 521 (shutter button, operation button, etc.) is for the user to operate the digital camera. A control program and the like are stored in the ROM 526, and the RAM 527 functions as a work area of the CPU 520. The DMAC 528 is a DMA controller.

An image is picked up by an image pickup section 522 (device for performing a data fetching process) including a CCD and a lens, and the data of the picked up image is processed by an image processing section 524. The processed image data is stored in the CPU.
520 or DMAC 528 for data transfer control device 5
Sent to 00. The data transfer control device 500 converts this parallel image data into serial data,
To other devices such as a printer, storage device, personal computer, etc.

FIG. 20C shows a CD which is one of the electronic devices.
An internal block diagram of the RW drive (storage device) is shown, and an external view thereof is shown in FIG. CPU 530
Controls the entire system. The operation unit 531 is a CD
-For the user to operate the RW. ROM5
36 stores a control program and the like, and a RAM 537
Functions as a work area of the CPU 530. DMAC
Reference numeral 538 is a DMA controller.

A reading and writing unit (a device for performing a data acquisition process or a device for performing a data storage process) 533 including a laser, a motor, an optical system, etc.
The data read from the D-RW 532 is input to the signal processing unit 534, and given signal processing such as error correction processing is performed. Then, the signal-processed data is
It is sent to the data transfer control device 500 by the CPU 530 or the DMAC 538. The data transfer control device 500
This parallel data is converted to serial data and US
Send to another device via B.

On the other hand, the serial data sent from another device via the USB is the data transfer control device 500.
Is converted into parallel data by. Then, this parallel data is sent to the signal processing unit 534 by the CPU 530 or the DMAC 538. Then, the signal processing unit 5
At 34, the given signal processing is applied to the parallel data, and the reading and writing unit 533 performs CD-
It is stored in RW532.

20A, 20B and 20C, CPUs for controlling data transfer in the data transfer control device 500 may be provided separately in addition to the CPUs 510, 520 and 530. Good.

If the data transfer control device of this embodiment is used in an electronic device, an electronic device having an OTG function can be realized. That is, the electronic device can be made to have a role as a host or a device, and an application that has never existed can be created.

If the data transfer control device of this embodiment is used in an electronic device, the processing load of the CPU (processing section) incorporated in the electronic device can be reduced and an inexpensive CPU can be used. In addition, the CPU can perform other processing other than the data transfer control processing with a margin,
It is possible to improve the performance of electronic devices and reduce costs. Also, CP
The firmware program operating on the U can be simplified, and the development period of the electronic device can be shortened.

As the electronic equipment to which the data transfer control device of this embodiment can be applied, other than the above, for example, various optical disk drives (CD-ROM, DVD), magneto-optical disk drives (MO), hard disk drives, digital devices. Video camera, mobile phone, scanner, T
V, VTR, audio equipment, telephone, projector,
Various things such as a personal computer, an electronic notebook, or a word processor can be considered.

The present invention is not limited to this embodiment,
Various modifications can be made within the scope of the present invention.

For example, the configuration of the data transfer control device of the present invention is not limited to the configuration described with reference to FIG. 4 and the like, and various modifications can be implemented.

The configuration of each block (HC, PC, OTGC, etc.) of the data transfer control device is not limited to that described in the present embodiment, and various modifications can be made.

The circuit for invalidating the SOF packet periodic transfer is not limited to the configuration shown in FIG. 10, and various modifications can be made.

The SOF packet of the present invention may have any name, as long as it has a function equivalent to that of the SOF packet (packet for instructing and managing frame start).

Also, in the description in the specification, it is referred to as a broad term (aperiodic transfer, cyclic transfer, first mode, second mode, state controller, processing unit, transfer controller, bus, buffer area, etc.). Terms (bulk transfer, isochronous transfer, SOF mode, S
(OFF mode, OTG controller, CPU / firmware, host controller / peripheral controller, USB, pipe area / endpoint area, etc.)
Can be replaced with a broad term in other descriptions in the specification.

In the invention according to the dependent claim of the present invention, a part of the constituent elements of the claim on which the invention is dependent can be omitted. Further, a main part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

Further, although an example of applying the USB to the OTG standard has been described in the present embodiment, the present invention is applied to the OT.
It is not limited to the G standard. That is, the present invention can be applied not only to the OTG of USB, but also to the data transfer according to the conventional USB1.1, USB2.0, and the standards developed from these standards.

[Brief description of drawings]

FIG. 1A, FIG. 1B, and FIG. 1C are USB O
It is a figure for demonstrating a TG standard.

FIG. 2A and FIG. 2B are diagrams for explaining the procedure of SRP and HNP.

FIG. 3A and FIG. 3B are views for explaining a descriptor having a list structure of OHCI and the like.

FIG. 4 is a diagram showing a configuration example of a data transfer control device of the present embodiment.

5A and 5B are diagrams for explaining a pipe region and an endpoint region.

6A and 6B are diagrams for explaining an SOF packet.

FIG. 7 is an example of a signal waveform when a mode with SOF (first mode) is set.

FIG. 8 is an example of a signal waveform when the SOF-less mode (second mode) is set.

FIG. 9 is an example of a signal waveform when the SOF-less mode is set and there is no data to be transferred.

FIG. 10 is a configuration example of a circuit that invalidates the periodic transfer of the SOF packet.

11A and 11B are truth table for explaining the operation of the circuit of FIG.

FIG. 12 is a diagram for explaining an operation of the data transfer control device at the time of a host.

FIG. 13 is a diagram for explaining an operation of the data transfer control device at the time of peripheral.

FIG. 14 is a diagram for explaining a register unit.

FIG. 15 is a flowchart illustrating an example of firmware processing.

FIG. 16 is a diagram showing a detailed configuration example of an OTG controller.

17A and 17B are diagrams showing a detailed configuration example of a host controller and a peripheral controller.

FIG. 18 is a diagram showing a detailed configuration example of a buffer controller.

19 (A), (B), and (C) are diagrams for explaining an area securing method and a pointer allocating method.

20A, 20B, and 20C are examples of internal block diagrams of various electronic devices.

21A, 21B, and 21C are examples of external views of various electronic devices.

[Explanation of symbols]

PIPE0 to PIPEe Pipe (buffer) area EP0 to EPe Endpoint (buffer)
Area TREG0 to TREGe Transfer condition register (shared register) 10 Transceiver, 12 Physical layer circuit, 20 O
TG controller (state controller), 30
HC / PC switching circuit, 32 HC / PC selector, 34 line state controller, 40 transfer controller, 50 host controller, 60
Peripheral controller, 70 register section, 7
2 transfer condition register section (shared register), 80 buffer controller, 100 packet buffer (F
IFO, RAM), 110 interface circuit,
112 DMA handler circuit, 114 CPU interface circuit, 120 clock controller

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshiyuki Kambara             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation (72) Inventor Kuniaki Matsuda             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation F term (reference) 5B077 AA22 AA41 MM01 MM02 NN02

Claims (11)

[Claims] 1. A data transfer control device for data transfer via a bus, comprising: a buffer controller that controls access to a packet buffer that stores transfer data; and a transfer controller that controls transfer of data in the packet buffer. In the case where the first mode is set, the transfer controller includes an SOF (Start Of
(Frame) When data transfer is performed while transferring packets at a frame cycle, and when the second mode is set and aperiodic transfer is performed, the periodic transfer of the SOF packet is invalidated and the aperiodic data is transferred. And a data transfer control device. 2. The transfer controller according to claim 1, wherein, when there is no aperiodic data to be transferred, the SOF packet is transferred at a frame cycle even when the second mode is set. And a data transfer control device. 3. The host operation state according to claim 1, which operates as a host,
The packet buffer includes a state controller that controls a plurality of states including states of peripheral operations that operate as a role of the peripheral, and the packet buffer stores a plurality of data stored in each pipe area for transfer to and from each endpoint. The pipe area is secured, and the transfer controller includes a host controller that transfers data as a host during host operation, and a peripheral controller that transfers data as a peripheral during peripheral operation. , A data transfer control device characterized by automatically generating a transaction for an endpoint and automatically transferring data between a pipe region and an endpoint corresponding to the pipe region. 4. The SOF packet according to claim 3, wherein when the second mode is set, the host controller transmits an SOF packet between the pipe area and an aperiodic transfer endpoint corresponding to the pipe area. A data transfer control device characterized by automatically transferring aperiodic data while disabling cyclic transfer. 5. The SOF packet according to claim 3, wherein the host controller sets the SOF packet to the frame cycle even when the second mode is set when all the automatic transfer instruction signals in the pipe area are inactive. A data transfer control device characterized by automatic transfer by. 6. The SOF transfer method according to claim 3, wherein the host controller activates an SOF transfer start trigger for each frame period and the SOF packet transfer is completed.
The SOF transfer start trigger generation circuit for deactivating the transfer start trigger, the automatic transfer instruction signal for the pipe region, the state information signal from the state controller, and the signal for instructing the first or second mode are received, and the SOF is received. A data transfer control device comprising: an SOF invalid signal generation circuit that generates a signal that invalidates a transfer start trigger. 7. The packet buffer according to claim 3, wherein at the time of peripheral operation, a plurality of endpoint areas in which data transferred to and from the host are stored in each endpoint area are secured in a packet buffer, The data transfer control device, wherein the peripheral controller transfers data between the endpoint area and the host. 8. The method according to claim 1, wherein the aperiodic transfer is bulk transfer or control transfer of USB (Universal Serial Bus) standard, and the aperiodic data is bulk data or control data. Characteristic data transfer control device. 9. The OTG (On-Th) of USB (Universal Serial Bus) according to claim 1.
e-Go) A data transfer control device characterized by performing data transfer conforming to the standard. 10. The data transfer control device according to claim 1, a device for performing an output process, a fetch process, or a storage process of data transferred via the data transfer control device and a bus, and the data. An electronic device comprising: a processing unit that controls data transfer of a transfer control device. 11. A data transfer control method for data transfer via a bus, comprising: controlling access of a packet buffer for storing transfer data, controlling data transfer of the packet buffer; and a first mode. Is set, SOF (Start Of
(Frame) When data transfer is performed while transferring packets at a frame cycle, and when the second mode is set and aperiodic transfer is performed, the periodic transfer of the SOF packet is invalidated and the aperiodic data is transferred. And a data transfer control method.