JP2003323152A - Driver circuit and el (electroluminescence) display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver circuit having a shift register circuit with clock stoppage whose blanking period is short. <P>SOLUTION: This driver circuit is the source driver circuit of a matrix type display device. The source driver is provided with a latch circuit for latching display data by the rising of a fundamental clock and a shift register with clock stoppage and only the shift register of the first stage is provided with a circuit which does not output shift register output but outputs a start pulse whose length is adjusted to a length equivalent to two clocks of the fundamental clock. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to an EL display panel which displays an image by self-luminous display and an information display device such as a mobile phone which uses these EL display panels. The present invention also relates to a drive circuit that drives an EL display panel and the like.

[0002]

2. Description of the Related Art Liquid crystal display panels are widely used in portable devices and the like because of their thinness and low power consumption. Therefore, devices such as word processors, personal computers, televisions (TV), and viewfinders for video cameras are used. It is also used for monitors.

[0003]

However, since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to form the backlight, there is a problem that the display module becomes thick. Further, in order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. Therefore, there is a problem that the light utilization efficiency is low. There is also a problem that the color reproduction range is narrow.

In recent years, organic EL (electroluminescence) display panels have been developed. The organic EL display panel is a low temperature polysilicon TFT (thin film transistor)
A panel is constructed using the array. However, since the organic EL device emits light by electric current, there is a problem that display unevenness occurs if the TFT characteristics vary.

[0005]

A first aspect of the present invention (corresponding to claim 1) for solving the above-mentioned problems is a driver circuit for driving a source signal line, wherein display data is displayed at a rising edge of an original clock. And a shift register with a clock stop, the shift register output of the first stage shift register and the original clock 2
The driver circuit includes a circuit that outputs a start pulse adjusted to the length of a clock.

According to a second aspect of the present invention (corresponding to claim 2), the logical product of the normal output signal of the shift register of its own stage and the inverted output signal of the latter stage shift register is used as the output signal of the shift register. It is a driver circuit of the present invention.

A third aspect of the present invention (corresponding to claim 3) is the driver circuit according to the first aspect of the present invention, which is provided with a dummy shift register in a subsequent stage of the final stage shift register.

According to a fourth aspect of the present invention (corresponding to claim 4), the clock signal of the shift register of the self stage is obtained by the logical sum of the normal output signal of the shift register and the normal output signal of the shift register of the self stage. It is a driver circuit according to the first aspect of the present invention that cuts off an input.

According to a fifth aspect of the present invention (corresponding to claim 5), in a reset circuit for generating a reset signal having one clock length of an original clock, the input start pulse is held at the rising edge of the original clock. Driver according to the first aspect of the present invention, which is configured by inverting AND of the non-inverted output of the D-type flip-flop and the inversion output of the second D-type flip-flop that holds the non-inverted output at the rising edge of the original clock. Circuit.

According to a sixth aspect of the present invention (corresponding to claim 6), a third D-type flip-flop for dividing the original clock by the falling edge of the original clock and one clock length of the original clock. 2 is a driver circuit of the first aspect of the present invention generated by the reset signal of FIG.

According to a seventh aspect of the present invention (corresponding to claim 7), an inversion signal of a reset signal of one clock length of an original clock,
The driver circuit according to the first aspect of the present invention is constituted by a logical sum of the inverted signal and the non-inverted output of the fourth D-type flip-flop which holds the inverted signal at the rising edge of the original clock.

An eighth aspect of the present invention (corresponding to claim 8) is the driver circuit according to the seventh aspect of the present invention, wherein the shift clock is stopped during the blanking period.

In a ninth aspect of the present invention (corresponding to claim 9), the fifth aspect of the present invention is to hold the output signal of the shift register at the final stage at the rising of the original clock as means for stopping the shift clock during the blanking period. The normal output of the D-type flip-flop stops the frequency dividing operation of the first D-type flip-flop, and the fifth signal is reset by the reset signal.
Is a driver circuit according to the seventh aspect of the present invention, wherein the frequency dividing operation of the first D-type flip-flop is started by resetting the D-type flip-flop.

The tenth invention of the present invention (corresponding to claim 10) is
An EL display device including the driver circuit according to any one of the first to ninth aspects of the present invention and EL elements arranged in a matrix.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present specification, each drawing has a portion omitted or / and enlarged or reduced in order to facilitate understanding and / or drawing. For example, in FIG.
In the cross-sectional view of the display panel shown in FIG. 1, the sealing film 111 and the like are shown sufficiently thick. On the other hand, in FIG. 10, the sealing lid 85 is thinly illustrated. In addition, some parts are omitted. For example, in the display panel and the like of the present invention, a phase film or the like for preventing reflection of unnecessary light is omitted, but it is desirable to add it at a proper time. The above also applies to the following drawings. Further, the parts having the same numbers or symbols have the same or similar forms or materials or functions or operations.

The contents described in the drawings and the like can be combined with other embodiments, etc., unless otherwise specified. For example, a touch panel or the like may be added to the display panel of FIG. 8 to provide the information display device illustrated in FIGS. 19 and 59 to 61. Further, a viewfinder (see FIG. 58) to which a magnifying lens 582 is attached and which is used in a video camera (see FIG. 59 or the like) can be configured. In addition, FIG. 4, FIG. 15, FIG.
The driving method of the present invention described with reference to FIG. 1 and FIG. 23 can be applied to any display device or display panel of the present invention. That is, the driving method described in this specification can be applied to the display panel of the present invention. Further, the present invention mainly describes an active matrix type display panel in which a transistor is formed in each pixel, but the present invention is not limited to this, and it goes without saying that it can be applied to a simple matrix type.

As described above, even if not specifically illustrated in the specification, matters described or explained in the specification and drawings,
The contents and specifications can be combined with each other and described in the claims. This is because it is impossible to describe all combinations in the specification or the like.

In recent years, as a display panel which has low power consumption and high display quality and can be further thinned, an organic EL display panel constituted by arranging a plurality of organic electroluminescence (EL) elements in a matrix form. Attention has been paid. As shown in FIG. 10, the organic EL display panel has a glass plate 7 on which transparent electrodes 105 as pixel electrodes are formed.
1 (array substrate) on which at least one organic functional layer (EL layer) including an electron transport layer, a light emitting layer, a hole transport layer, etc.
15 and a metal electrode (reflection film) (cathode) 106 are laminated. A positive electrode (anode) which is a transparent electrode (pixel electrode) 105, and a metal electrode (reflection electrode) 1
By applying a negative voltage to the cathode of 06, that is, by applying a direct current between the transparent electrode 105 and the metal electrode 106, the organic functional layer (EL layer) 15 emits light. By using an organic compound, which can be expected to have good light emitting characteristics, in the organic functional layer, the EL display panel can be put to practical use. Although the present invention is described by taking an organic EL display panel as an example, the present invention is not limited to this and can be applied to an inorganic EL display panel. In addition, there are some items such as structures and circuits that can be applied to other display panels such as a TN liquid crystal display panel and an STN liquid crystal display panel.

The cathode electrode, the anode electrode or the reflection film may be formed by forming an optical interference film made of a dielectric multilayer film on the ITO electrode. The dielectric multilayer film is formed by alternately forming a low refractive index dielectric film and a high refractive index dielectric film. That is, it is a dielectric mirror. This dielectric multilayer film has a function of improving the color tone of light emitted from the organic EL structure (filter effect). The ITO of the transparent electrode may be another material such as IZO. The same applies to the pixel electrode.

Wiring for supplying current to the anode or cathode (cathode wiring 86, anode wiring 87 in FIG. 8)
A large current flows through. For example, when the screen size of the EL display device becomes 40 inches, a current of about 100 (A) flows. Therefore, the resistance value of these wirings must be made sufficiently low. With respect to this problem, in the present invention, first, the wiring such as the anode is formed of a thin film.
Then, the thin-film wiring is formed with a thick conductor by electrolytic plating or electroless plating. Examples of the plating metal include chromium, nickel, gold, copper, aluminum, alloys thereof, amangum, and a laminated structure. If necessary, the wiring itself or a metal wiring made of thin copper is added to the wiring. Also,
A copper paste or the like is screen-printed on the wiring and the paste or the like is laminated to increase the thickness of the wiring and reduce the wiring resistance. Alternatively, the wiring may be formed redundantly by a bonding technique to reinforce the wiring. Further, if necessary, a ground pattern may be formed by stacking on the wiring to form a capacitor (capacitance) between the wiring and the wiring.

Further, in order to supply a large current to the anode or cathode wiring, a high-voltage, small-current power wiring is connected from the current supply means to the vicinity of the anode wiring or the like, and a low voltage is supplied by using a DCDC converter or the like. The power is converted into a high current and supplied. That is, the power supply is wired to the power consumption target with a high voltage, small current wiring, and converted into a large current and a low voltage near the power consumption target. As such a thing, a DCDC converter, a transformer, etc. are illustrated.

As the metal electrode 106, it is preferable to use one having a small work function such as lithium, silver, aluminum, magnesium, indium, copper or an alloy of each. In particular, it is preferable to use, for example, an Al-Li alloy. Further, for the transparent electrode 105, a conductive material having a large work function such as ITO or gold can be used. When gold is used as the electrode material, the electrode becomes semitransparent. The ITO may be another material such as IZO. The same applies to the other pixel electrodes 105.

When depositing a thin film on the pixel electrode 105 or the like, the organic EL film 15 may be formed in an argon atmosphere. Further, by forming a carbon film with a thickness of 20 nm or more and 50 nm or less on ITO as the pixel electrode 105,
The stability of the interface is improved, and the emission brightness and emission efficiency are also improved. Further, it goes without saying that the EL film 15 is not limited to being formed by vapor deposition and may be formed by inkjet. This inkjet method is particularly effective for high molecular weight organic EL materials. in this case,
It is advisable to form a hydrophilic film at the location where the high molecular weight organic EL material is applied.

In order to facilitate understanding of the structure of the EL display panel of the present invention, a method of manufacturing the organic EL display panel of the present invention will be described first.

In order to improve the heat dissipation of the substrate 85 and the substrate 71, the substrate may be made of sapphire glass. Also,
A thin film or a thick film having good thermal conductivity may be formed. For example, it is exemplified to use a substrate on which a diamond thin film (DLC or the like) is formed. Of course, a quartz glass substrate or a soda glass substrate may be used. Alternatively, a ceramic substrate such as alumina may be used, a metal plate made of copper or the like may be used, or a metal film or a carbon film may be coated on the insulating film by vapor deposition or coating. When the pixel electrode 105 is of a reflective type, the substrate material emits light from the surface direction of the substrate. Therefore, in addition to transparent or translucent materials such as glass, quartz and resin, non-transmissive materials such as stainless steel can be used.

Further, microlenses may be formed or arranged on the outside or inside of the substrates 85 and 71 in accordance with the pixel shape. By configuring the microlens, the directivity of the light emitted from the EL film is narrowed and high brightness can be realized.

In the embodiment of the present invention, the cathode electrode 106 is used.
Although the above is formed of a metal film, it is not limited to this and may be formed of a transparent film such as ITO or IZO. Thus, a transparent EL display panel can be constructed by using both the anode and cathode electrodes of the EL element 15 as transparent electrodes (of course, one of them may be formed of a light-transmissive metal film. Alternatively, an extremely thin metal film may be used as a cathode electrode, and a transparent conductor material such as ITO may be laminated on the cathode electrode). By increasing the transmittance to about 80% without using a metal film, it is possible to display characters and pictures while allowing the other side of the display panel to be almost transparent.

Needless to say, the substrates 85 and 71 may be plastic substrates. Since the plastic substrate is hard to break and is lightweight, it is optimal as a substrate for a display panel of a mobile phone. The plastic substrate is preferably used as a laminated substrate by adhering an auxiliary substrate to one surface of a base substrate which is a core material with an adhesive. of course,
These substrates and the like are not limited to plates and have a thickness of 0.
A film having a thickness of 05 mm or more and 0.3 mm or less may be used.

An alicyclic polyolefin resin is preferably used as the base substrate. As such an alicyclic polyolefin resin, ARTON manufactured by Japan Synthetic Rubber Co., Ltd.
An example is a single plate having a thickness of 200 μm. From a polyester resin, polyethylene resin or polyether sulfone resin, etc., on one surface of the base substrate, a hard coat layer having heat resistance, solvent resistance or moisture permeation resistance function and a gas barrier layer having air permeation resistance function are formed. Place an auxiliary substrate (or film or membrane) that will become.

When the substrate 71 and the like are made of plastic as described above, the substrate 71 and the like are made up of a base substrate and an auxiliary substrate. On the other surface of the base substrate, an auxiliary substrate (or film or film) made of polyethersulfone resin or the like having a hard coat layer and a gas barrier layer formed thereon is arranged as described above. It is preferable that the angle formed by the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate be 90 degrees. Note that the base substrate and the auxiliary substrate are attached to each other with an adhesive or a pressure-sensitive adhesive to form a laminated substrate.

As the adhesive, it is preferable to use a UV (ultraviolet) curing type acrylic resin.
Further, it is preferable to use an acrylic resin having a fluorine group. Besides, an epoxy adhesive or pressure-sensitive adhesive may be used. It is preferable to use an adhesive or pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. Further, it is preferable that the difference between the refractive index of the substrate and the refractive index of the substrate is 0.03 or less. In particular, it is preferable that the adhesive be added with a light diffusing material such as titanium oxide as described above to function as a light scattering layer.

When the auxiliary substrate and the auxiliary substrate are attached to the base substrate, the angle between the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate should be 45 degrees or more and 120 degrees or less. preferable. More preferably 80 degrees or more 1
It is preferable to set it to 00 degrees or less. Within this range, the phase difference generated in the auxiliary substrate and the auxiliary substrate, such as polyethersulfone resin, can be completely canceled in the laminated substrate. Therefore, the plastic substrate for the display panel can be treated as an isotropic substrate having no phase difference. Therefore, in the configuration using the circularly polarizing plate, unevenness of the display panel due to different phase states does not occur. Needless to say, the matters relating to the circularly polarizing plate are not limited to the plastic substrate, and are valid for a glass substrate. This is because it is possible to effectively suppress deterioration of contrast due to external light reflected on the substrate surface.

With this structure, versatility is remarkably widened as compared with a film substrate or a film laminated substrate having a phase difference. That is, by combining with a retardation film, it becomes possible to convert linearly polarized light into elliptically polarized light as designed. If there is a phase difference on the substrate, etc., an error from the design value will occur due to this phase difference.

Here, as the hard coat layer, polyester resin, epoxy resin, urethane resin, acrylic resin or the like can be used, and stripe electrodes (simple matrix type EL display panel) or pixel electrodes (active matrix). The mold display panel) also serves as the first undercoat layer of the transparent conductive film.

Further, as the gas barrier layer, SiO ₂ ,
An inorganic material such as SiO _x or an organic material such as polyvinyl alcohol or polyimide can be used. As the pressure-sensitive adhesive, the adhesive or the like, an epoxy-based adhesive, a polyester-based adhesive, or the like can be used in addition to the acrylic-based adhesive described above. The thickness of the adhesive layer is 1
It is set to 00 μm or less. However, it is preferably 10 μm or more in order to smooth the surface irregularities of the substrate and the like.

Further, as an auxiliary substrate constituting the substrates 71 and 85 and an auxiliary substrate, a thickness of 40 μm or more and 400 μm or more
It is preferable to use m. Further, by setting the thickness of the auxiliary substrate and the auxiliary substrate to 120 μm or less,
It is possible to suppress unevenness or phase difference at the time of melt extrusion molding called a die line of polyethersulfone resin. Preferably, the thickness of the auxiliary substrate is 50 μm or more 8
It is set to 0 μm or less.

Next, on this laminated substrate, SiOx is formed as an auxiliary undercoat layer of a transparent conductive film, and if necessary, a transparent conductive film made of ITO to be a pixel electrode is formed by a sputtering technique. In addition, an ITO film is formed as necessary to prevent static electricity. The transparent conductive film of the plastic substrate for a display panel manufactured as described above can realize a sheet resistance value of 25Ω / □ and a transmittance of 80% as its film characteristics.

The thickness of the base substrate is 50 μm to 100 μm
When m is thin, the display panel plastic substrate is curled by heat treatment in the manufacturing process of the display panel. Also, good results cannot be obtained when connecting circuit components. When the thickness of the base substrate is 200 μm or more and 500 μm or less with one plate, the substrate is not deformed, the smoothness is excellent, the transportability is good, and the transparent conductive film characteristics are stable. Moreover, the connection of the circuit components can be performed without any problem. Furthermore, the thickness is particularly preferably 250 μm or more and 450 μm or less. This is probably because it has appropriate flexibility and flatness. The ITO may be another material such as IZO. The same applies to the pixel electrode.

When an organic material such as the above-mentioned plastic substrate is used as the substrate or the like, it is preferable to form a thin film made of an inorganic material as a barrier layer also on the surface in contact with the light modulation layer. The barrier layer made of this inorganic material is
It is preferable to use the same material as the AIR coat. Needless to say, the sealing lid 85 and the substrate 71 can be manufactured by the same technique or configuration.

When the barrier film is formed on the pixel electrode or the stripe-shaped electrode, it is preferable to use a low dielectric constant material in order to reduce the loss of the voltage applied to the light modulation layer as much as possible. For example, an amorphous carbon film containing fluorine (relative dielectric constant of 2.0 to 2.5) is exemplified. In addition, the LKD series (LKD-T200 series (dielectric constant 2.5-
2.7), LKD-T400 series (relative permittivity 2.0
~ 2.2)) are exemplified. LKD series is MSQ
(Methy-silsesquioxane) based spin coating type, with a relative dielectric constant of 2.0-2.
It is as low as 7, which is preferable. In addition, organic materials such as polyimide, urethane and acrylic, and inorganic materials such as SiN _x and SiO ₂ may be used. It goes without saying that these barrier film materials may be used for the auxiliary substrate.

By using the substrate 85 or 71 formed of plastic, it is possible to exert the advantages that it does not break and the weight can be reduced. Another advantage is that it can be pressed. That is, a substrate having an arbitrary shape can be manufactured by pressing or cutting. Further, it can be processed into any shape and thickness by melting or chemical treatment. For example, it can be formed into a circle or a sphere (curved surface, etc.)
It is illustrated that it is formed into a circular shape or is processed into a conical shape.
Further, by press working, at the same time as manufacturing the substrate, it is possible to form a concavo-convex shape on one surface of the substrate and form a scattering surface or embossing.

It is also easy to form the positioning pin of the sealing lid 85 into the hole (not shown) of the substrate 71 formed by pressing the plastic. Further, an electric circuit such as a capacitor or a resistor formed by the thick film technique or the thin film technique may be formed in the substrate 71. Further, by forming a concave portion (not shown) in the substrate 71 and the like, forming a convex portion in the substrate 85, and forming the concave portion and the convex portion so that they can be fitted exactly,
The substrate 71 and the substrate 85 may be configured to be integrated by fitting.

When a glass substrate was used, a bank used when depositing EL was formed around the pixel 16. The bank (rib) is made of a resin material and is formed in a convex shape with a thickness of 1.0 μm or more and 3.5 μm or less. More preferably, the height is 1.5 μm or more and 2.5 μm or less. Embankment Embankment 101 made of this resin is used as the substrate 7
It can also be manufactured at the same time as the formation of 1. In addition, bank 1
01 material is acrylic resin, polyimide resin, SOG
Material may be used. It is preferable that the bank 101 is formed at the same time as the convex portion of the resin when the substrate 71 is pressed. This is a great effect generated by forming the substrate 71 and the like with resin.

By thus forming the resin portion at the same time as the substrate, the manufacturing time can be shortened and the cost can be reduced. In addition, when manufacturing the substrate 71 or the like, a dot-shaped convex portion is formed in the display area portion. This convex portion may be formed between adjacent pixels. This convex portion becomes the bank 101.

In the above embodiments, the convex portion functioning as a bank is formed, but the present invention is not limited to this. For example, the pixel portion may be dug down (recessed portion) by pressing or the like. In addition, a method of forming the flat substrate 71 first and then pressing it by reheating to form the unevenness is also included.

Alternatively, a mosaic color filter may be formed by directly coloring the substrates 71 and 85. Dyes, pigments, etc. are applied to the substrate by a technique such as ink jet printing and made to penetrate. After permeation, it may be dried at a high temperature, and the surface may be coated with a resin such as a UV resin or an inorganic material such as silicon oxide or nitric oxide.
Further, a color filter is formed by a gravure printing technique, an offset printing technique, a semiconductor pattern forming technique of applying and developing a film with a spinner. Similarly, a black matrix (BM) may be directly formed by a technique using a color filter or coloring by a black or dark color or a complementary color of modulated light. Alternatively, a recess may be formed on the surface of the substrate so as to correspond to the pixel, and a color filter, BM, or transistor may be embedded in the recess. In particular, it is preferable to coat the surface with an acrylic resin. This configuration also has an advantage that the pixel electrode surface and the like are flattened.

Alternatively, the pixel electrode 105 or the cathode electrode 106 may be directly constructed by making the resin on the substrate surface conductive by using a conductive polymer or the like. More broadly, a configuration in which a hole is formed in a substrate and an electronic component such as a capacitor is inserted into this hole is also exemplified. The advantage is that the substrate can be made thin.

By cutting the surface of the substrate,
The pattern may be freely formed. Alternatively, it may be formed by melting the peripheral portion of the substrate 71 or the like. Also,
In the case of an organic EL display panel, in order to prevent moisture from entering from the outside, the peripheral portion of the substrate may be melted and sealed.

As described above, by forming the substrate with resin, it is easy to make a hole in the substrate. Further, the substrate shape can be freely configured by pressing or the like. It is also possible to make a hole in the substrate 71 and fill the hole with a conductive resin or the like to electrically connect the front and back of the substrate. The board 71 or the like can be used as a multilayer circuit board or a double-sided board.

A conductive pin or the like may be inserted instead of the conductive resin. You may comprise so that the terminal of electronic components, such as a capacitor, can be inserted in the formed hole. Further, circuit wiring, a capacitor, a coil or a resistor made of a thin film may be formed in the substrate. That is, the substrate 71 or the like may be a multilayer wiring substrate. Multi-layering consists of laminating thin substrates. One or more substrates (films) to be laminated may be colored.

Further, the substrate itself can be colored by adding a dye or pigment to the substrate material, or a filter can be formed. Further, the serial number can be formed at the same time when the substrate is manufactured. Further, by coloring only the portion other than the display area, it is possible to prevent malfunction due to irradiation of light on the mounted IC chips.

Further, half of the display area of the substrate can be colored with different colors. For this, a resin plate processing technique (injection processing, complexion processing, etc.) may be applied. Further, by using the same processing technique, half of the display area can have different EL layer thicknesses. Further, the display portion and the circuit portion can be formed at the same time. It is also easy to change the substrate thickness between the display area and the driver loading area.

Further, microlenses can be formed on the substrate 71 or the substrate 85 so as to correspond to pixels or display regions. Also, the substrate 7
The diffraction grating may be formed by processing 1, 85. In addition, it is possible to improve the viewing angle or to provide the viewing angle dependency by forming unevenness finer than the pixel size. It should be noted that such arbitrary shape processing and fine processing technology can be realized by the stamper technology developed by OMRON Corporation for forming microlenses.

An antireflection film (AIR coat) is formed on the surfaces of the substrates 71 and 85 which come into contact with air. When a polarizing plate or the like is not attached to the substrate 71 or the like, the substrate 71
An antireflection film (AIR coat) is directly formed on the above. When another constituent material such as a polarizing plate (polarizing film) is attached, an antireflection film (AIR coat) is formed on the surface of the constituent material.

In the above embodiments, the substrate 71 and the like are mainly made of plastic, but the present invention is not limited to this. For example, the substrates 71 and 859
Even if it is a glass substrate or a metal substrate, it is possible to form or configure the uneven portion such as the bank 101 by pressing or cutting. Further, it is possible to color the substrate. Therefore, the matters described are not limited to plastic substrates. Further, it is not limited to the substrate. For example, it may be a film or a sheet.

Further, in order to prevent or suppress the adhesion of dust to the surface of the polarizing plate, it is effective to form a thin film made of fluororesin. Further, in order to prevent static electricity, a thin film having a hydrophilic group, a conductive polymer film, a conductive film such as a metal film may be applied or deposited.

The polarizing plate (polarizing film) arranged or formed on the light incident surface or the light emitting surface of the display panel is not limited to a linearly polarized light, but may be an elliptically polarized light. Further, a plurality of polarizing plates may be laminated, a polarizing plate and a retardation plate may be combined, or a laminated structure may be used.

TAC film (triacetyl cellulose film) is the main material for the polarizing film.
Is the best. This is because the TAC film has excellent optical properties, surface smoothness and processability.

The AIR coat is exemplified by a dielectric single layer film or a multilayer film. Others, 1.35
A resin having a low refractive index of 1.45 may be applied. For example, a fluorinated acrylic resin is exemplified. In particular, those having a refractive index of 1.37 or more and 1.42 or less have good characteristics.

The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide visible wavelength band. This is called a multi coat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band. This is called a V coat. The multi coat and the V coat are used properly according to the use of the display panel. The number of layers is not limited to two or more, and one layer may be used.

In the case of multi-coating, aluminum oxide (Al2O3) is laminated to have an optical film thickness of nd = λ / 4, zirconium (ZrO2) is nd1 = λ / 2, and magnesium fluoride (MgF2) is nd1 = λ / 4. To form. Usually, a thin film is formed with λ of 520 nm or a value in the vicinity thereof.

In the case of V coat, silicon monoxide (Si
O) is an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF ₂ ) is nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride (MgF ₂ ) are n.
d1 = λ / 4 stacked layers are formed. Since SiO has an absorption band on the blue side, it is preferable to use Y ₂ O ₃ when modulating blue light. In addition, Y ₂ O ₃ is more stable in terms of the stability of the substance, which is preferable. Alternatively, a SiO ₂ thin film may be used. Of course, the AIR coat may be made by using a resin having a low refractive index. For example, acrylic resin such as fluorine is exemplified. It is preferable to use an ultraviolet curing type of these.

In order to prevent the display panel from being charged with static electricity, a hydrophilic resin is applied to the surface of the light guide plate such as the cover substrate or the display panel,
Alternatively, it is preferable that the substrate material such as the panel is made of a material having a good hydrophilicity.

A thin film transistor (transistor) as a plurality of switching elements or current control elements is formed in one pixel. The transistors to be formed may be transistors of the same type or may be transistors of different types such as P-channel type and N-channel type transistors, but preferably the switching transistor and the driving transistor have the same polarity. The thing of is desirable. In addition, the structure of the transistor is not limited to the planar type transistor, and may be a stagger type or an inverted stagger type, or a structure in which the impurity region (source, drain) is formed by using the self-alignment method, A non-self-aligned method may be used.

The EL display element 15 of the present invention is formed on a substrate by
It has an EL structure in which ITO serving as a hole injection electrode (pixel electrode), one or more kinds of organic layers, and an electron injection electrode are sequentially stacked. Transistors are provided on the substrate.

To manufacture the EL display element of the present invention, first, an array of transistors is formed in a desired shape on a substrate. Then, ITO, which is a transparent electrode, is formed as a pixel electrode on the flattening film by a sputtering method and patterned. Then, an organic EL layer, an electron injection electrode, etc. are laminated.

As the transistor, an ordinary polycrystalline silicon transistor may be used. The transistor is E
It is provided at the end of each pixel of the L structure and has a size of 10
It is about 30 μm. The pixel size is 20 μm
It is about 20 μm to 300 μm × 300 μm.

On the substrate 71, wiring electrodes of transistors are provided. The wiring electrode has a low resistance and has a function of electrically connecting the hole injecting electrode to keep the resistance value low. Generally, the wiring electrode is made of Al, Al and a transition metal (excluding Ti), Ti or Titanium nitride (Ti
Materials containing any one or more of N) are used, but the present invention is not limited to this material. The total thickness of the hole injecting electrode, which is the base of the EL structure, and the wiring electrode of the transistor is not particularly limited, but it is usually about 100 to 1000 nm.

An insulating layer is provided between the wiring electrode of the transistor 11 and the organic layer of the EL structure. The insulating layer is SiO
Silicon oxide such as _{2 and} silicon nitride, inorganic material such as silicon nitride formed by sputtering or vacuum deposition, SOG (spin on glass) formed silicon oxide layer, photoresist,
Any film having insulation properties such as a coating film of a resin material such as polyimide or acrylic resin may be used. Of these, polyimide is preferable. The insulating layer also plays a role of a corrosion / water resistant film that protects the wiring electrodes from moisture and corrosion.

The EL structure may have two or more emission peaks. In the EL display element of the present invention, the green and blue light emitting portions are obtained by, for example, combining a blue green light emitting EL structure with a green transmission layer or a blue transmission layer. The red light emitting portion is composed of a blue green light emitting EL structure and this E structure.
It can be obtained by a fluorescence conversion layer that converts the blue-green emission of the L structure into a wavelength close to red.

Next, the EL structure which constitutes the EL display element 15 of the present invention will be described. The EL structure of the present invention has an electron injection electrode which is a transparent electrode, at least one organic layer, and a hole injection electrode. The organic layer has at least one hole transport layer and at least one light emitting layer, for example, an electron injecting and transporting layer, a light emitting layer, a hole transporting layer, and a hole injecting layer in that order. The hole transport layer may be omitted. The organic layer of the EL structure of the present invention can have various constitutions, such as omitting the electron injecting / transporting layer or integrating with the light emitting layer, or by mixing the hole injecting / transporting layer and the light emitting layer. May be. The electron injection electrode is made of a metal, compound or alloy having a small work function, which is preferably formed by a vapor deposition method such as a vapor deposition method or a sputtering method.

Since the hole injecting electrode has a structure in which light emitted from the hole injecting electrode side is taken out, for example,
ITO (tin-doped indium oxide), IZO (zinc-doped indium oxide), ZnO, SnO ₂ , In ₂ O ₃
Etc., but ITO and IZO are particularly preferable. The thickness of the hole injecting electrode may be a certain thickness or more capable of sufficiently injecting holes, and normally, it is preferably about 10 to 500 nm. It is necessary that the driving voltage is low in order to improve the reliability of the element, but a preferable value is 10 to 30 Ω / □ (film thickness 50 to 300 nm).
TO is mentioned. In actual use, the film thickness and optical constants of the electrodes may be set so that the interference effect due to reflection at the hole injection electrode interface such as ITO sufficiently satisfies the light extraction efficiency and color purity.

The hole injecting electrode can be formed by a vapor deposition method or the like, but is preferably formed by a sputtering method. The sputtering gas is not particularly limited, and an inert gas such as Ar, He, Ne, Kr, Xe, or a mixed gas thereof may be used.

The electron injecting electrode is made of a metal, compound or alloy having a small work function, which is preferably formed by vapor deposition, sputtering or the like. The constituent material of the electron injection electrode to be formed is, for example, K, Li, Na, Mg, L.
a, Ce, Ca, Sr, Ba, Al, Ag, In, S
It is preferable to use a simple metal element such as n, Zn, or Zr, or a two-component or three-component alloy system containing them in order to improve stability. As an alloy system, for example, Ag · M
g (Ag: 1 to 20 at%), Al.Li (Li: 0.
3 to 14 at%), In.Mg (Mg: 50 to 80 at)
%), Al.Ca (Ca: 5 to 20 at%) and the like are preferable.

The thickness of the electron injecting electrode thin film may be a certain thickness or more capable of sufficiently injecting electrons, and may be 0.1 nm or more, preferably 1 nm or more. The upper limit value is not particularly limited, but usually the film thickness is 100 to 50.
It may be about 0 nm.

The hole injecting layer has a function of facilitating injection of holes from the hole injecting electrode, and the hole transporting layer has a function of transporting holes and a function of hindering electrons, and injects charge. It is also called a layer or a charge transport layer.

The electron injecting and transporting layer is provided when the compound used for the light emitting layer does not have a very high electron injecting and transporting function, and the function of facilitating the injection of electrons from the electron injecting electrode,
It has a function of transporting electrons and a function of hindering holes.
The hole injection layer, the hole transport layer, and the electron injection transport layer increase and confine holes and electrons injected into the light emitting layer, optimize the recombination region, and improve the light emission efficiency. Note that the electron injecting and transporting layer may be separately provided in a layer having an injecting function and a layer having a transporting function.

The thickness of the light emitting layer, the combined thickness of the hole injecting layer and the hole transporting layer, and the thickness of the electron injecting and transporting layer are not particularly limited and may vary depending on the forming method.
It is preferably about nm.

The thickness of the hole injecting layer, the hole transporting layer and the thickness of the electron injecting and transporting layer are the same as the thickness of the light emitting layer or about 1/10 to 10 times, depending on the design of the recombination / light emitting region. And it is sufficient. The thicknesses of the hole injection layer and the hole transport layer, and the thicknesses of the electron injection layer and the electron transport layer when separated, are preferably 1 nm or more for the injection layer and 20 nm or more for the transport layer. At this time, the upper limit of the thickness of the injection layer and the transport layer is usually about 100 nm in the injection layer and 1 in the transport layer.
It is about 00 nm. Such a film thickness is the same when two injecting and transporting layers are provided.

Further, the recombination is performed by controlling the film thickness while considering the carrier mobility and carrier density (determined by the ionization potential and electron affinity) of the light emitting layer, electron injecting and transporting layer and hole injecting and transporting layer to be combined. It is possible to freely design the area and the light emitting area, and it is possible to design the light emitting color, control the light emitting luminance and the light emitting spectrum by the interference effect of both electrodes, and control the spatial distribution of light emission.

The light emitting layer of the EL element 15 of the present invention contains a fluorescent substance which is a compound having a light emitting function. Examples of the fluorescent substance include metal complex dyes such as tris (8-quinolinolato) aluminum [Alq3], phenylanthracene derivatives, tetraarylethene derivatives, and blue-green light emitting materials.

It is preferable to use CuPc in which 2% phthalcyanine is added to the material of the hole injection layer. CuPc
The heat resistance is remarkably improved as compared with the case of using alone.

The luminance after driving at 85 ° C. for 1000 hours is C with respect to the initial luminance (set to 400 cd / m 2).
With uPc alone, there is a decrease of about 45%, but with addition of phthalcyanine, the decrease is only about 35%. It is presumed that this is because the addition of phthalcyanine suppressed the crystallization of CuPc. If CuPc remains in the amorphous state, it is possible to suppress the decrease in brightness. The effect of improving the heat resistance due to the addition of phthalcyanine is maximized at 1% or more and 5% or more. Particularly, 1% or more and 3% or less is suitable. It should be noted that the effect of addition is up to about 20%, but if the amount of addition is further increased, the heat resistance is rather lowered.

The organic EL element 15 for emitting blue light is made of "DMPhen (Tr
iphenylamine) "may be used. At this time, an electron injection layer (Bath
and the hole injection layer (M-MTDATX)
It is preferable to adopt a material having the same band gap as that of the light emitting layer in A). If only DMPhen having a large band gap of 3.4 eV is used in the light emitting layer, the electrons remain in the electron injecting layer and the holes remain in the hole injecting layer, so that recombination of electrons and holes is unlikely to occur in the light emitting layer. is there. DMPhe
The problem that the structure of the light-emitting material having an amine group such as n is unstable and it is difficult to prolong the life can be solved by transferring energy excited in DMPhen to the dopant and causing the dopant to emit light.

The luminous efficiency can be improved by using a phosphorescent material as the EL material. The external quantum efficiency of the fluorescent light emitting material is about 2 to 3%. The fluorescent material has an internal quantum efficiency (efficiency of converting energy by excitation into light) of 25%, whereas the phosphorescent material has a quantum efficiency of nearly 100%, and thus the external quantum efficiency is high.

C is used as the host material of the light emitting layer of the organic EL device.
It is preferable to use BP. Red (R) and green (G),
It is doped with a blue (B) phosphorescent material. All doped materials contain Ir. R material is Btp
2Ir (acac), G material is (ppy) 2Ir (ac
It is preferable to use FIrpic as the ac) and B materials.

Various organic compounds can be used for the hole injection layer / hole transport layer. For forming the hole injecting and transporting layer, the light emitting layer and the electron injecting and transporting layer, it is preferable to use the vacuum deposition method because a uniform thin film can be formed.
Hereinafter, the manufacturing method and structure of the EL display panel of the present invention will be described in more detail. As described above, first, the transistor 11 for driving the pixel is formed on the array substrate 71. One pixel is composed of two or more transistors, preferably four or five transistors. Also, the pixel is current programmed and the programmed current is EL
It is supplied to the element 15. Usually, the current programmed value is held in the storage capacitor 19 as a voltage value. The pixel configuration such as the combination of the transistors 11 will be described later. Next, a pixel electrode as a hole injecting electrode is formed in the transistor 11. The pixel electrode 105 is patterned by photolithography. The transistor 1
A light-shielding film is formed or arranged in the lower layer or the upper layer of 1 in order to prevent image quality deterioration due to a photoconductor phenomenon (hereinafter referred to as photocon) that occurs when light is incident on the transistor 11. The current program is
A program current is applied to the pixel from the source driver circuit 14 (or is absorbed by the source driver circuit 14 from the pixel), and a signal value corresponding to this current is held in the pixel. EL the current corresponding to the held signal value
It flows into the element 15 (or it flows in from the EL element 15). That is, the current is programmed, and the current corresponding to (corresponding to) the programmed current is passed through the EL element 15. On the other hand, voltage programming means applying a program voltage from the source driver circuit 14 to a pixel,
The pixel holds a signal value corresponding to this voltage. A current corresponding to the held voltage is applied to the EL element 15
Shed on. In other words, programming with voltage, converting voltage into current value within the pixel, equivalent to the programmed voltage (corresponding)
The current to be applied is passed through the EL element 15.
To form a transistor on a plastic substrate,
By processing the surface on which the organic semiconductor is formed, an electronic thin film may be formed by utilizing pentacene molecules composed of carbon and hydrogen. This thin film has 20 times to 100 times the size of conventional crystal grains.
It has double the size and has sufficient semiconductor characteristics suitable for electronic device manufacturing. Pentacene tends to adhere to surface impurities as it grows on a silicon substrate. This results in irregular growth and grain sizes that are too small to produce high quality devices. In order to grow the crystal grains larger, a single layer of molecules called cyclohexene “molecular buffer” is first formed on a silicon substrate.
Should be applied. This layer is "stick" on silicon.
to cover "y sites"
A clean surface is formed and pentacene grows to very large crystal grains. By using these new thin film of large crystal grains, a flexible transistor (transistor) using pentacene of large crystal grains can be manufactured. For mass production of such flexible transistors, transistors can be manufactured by applying a liquid material at low temperature. Alternatively, a semiconductor thin film may be formed by forming an island shape with a metal thin film to be a gate on a substrate, vapor-depositing or coating an amorphous silicon film on this, and then heating. The semiconductor film is excellently crystallized in the island-shaped portion. Therefore, the mobility becomes good. As the organic transistor (transistor), it is preferable to adopt a structure called a static induction transistor (SIT). Amorphous pentacene is used. Hole mobility is 1 × 10 cm
² / Vs, which is lower than that of crystallized pentacene. But,
The frequency characteristic can be improved by adopting the SIT structure. The thickness of pentacene is 100 to 300 nm
It is preferable that

A p-type field effect transistor may be used as the organic transistor. The transistor can be formed on a plastic substrate. Since the plastic substrate can be bent together, it is preferable that pentacene, which can form a flexible transistor type display panel, be in a polycrystalline state. It is preferable to use PMMA as the material of the gate insulating film. You may use naphthacene for the active layer of an organic transistor. If oxygen plasma and O 2 asher are used during cleaning, the flattening film 102 around the pixel electrode 105 is also ashed at the same time, and the peripheral portion of the pixel electrode 105 is scooped out. In order to solve this problem, an edge protection film (basically the bank 101) made of acrylic resin is formed around the pixel electrode 105.
As a constituent material of the edge protection film 105, the flattening film 10 is used.
Examples of the same material as the organic material such as acrylic resin and polyimide resin that composes 2 include SiO ₂ , Si
An inorganic material such as N _x is exemplified. In addition, Al ₂ O ₃ ,
It goes without saying that it may be Ta ₂ O ₃ or the like. The edge protection film 101 is formed after patterning the pixel electrode 105.
It is formed so as to fill the space between the pixel electrodes 105. of course,
The edge protection film 101 may be formed to a height of 2 μm or more and 4 μm or less to serve as a bank of a metal mask (spacer that prevents the metal mask from directly contacting the pixel electrode 105) when the organic EL materials are separately applied. Needless to say.

Ta having a high relative dielectric constant of 24 in the gate insulating film
_{It is} recommended to use ₂ O ₅ . The thickness of the gate insulating film is 129n
Although the thickness is as thick as m and the channel length is long as 500 μm, the P-type transistor operates well at a power supply voltage of −5V. An organic material called pentacene is used for the material of the channel layer. The mobility of holes as carriers is 0.40 cm ² / Vs or more, and the ratio of the drain current when the transistor is on to the leakage current when the transistor is off can be 10 ⁴ .

An EL film (15R) is formed on the pixel electrode 105.
(Red), 15G (green), 15B (blue)) are formed.
Each EL film 15 is formed with a slight gap, or the peripheral portions are overlapped. Almost no light is emitted at the overlapped portions. The aluminum film 10 serving as a cathode is formed on the EL film 15.
6 is formed. As the vacuum vapor deposition device, a device obtained by modifying a commercially available high vacuum vapor deposition device (EBV-6DA type manufactured by Nippon Vacuum Technology Co., Ltd.) is used. The main exhaust system is exhaust speed 1500
It is a turbo molecular pump (TC1500, manufactured by Osaka Vacuum Co., Ltd.) of liter / min, and the ultimate vacuum is about 1 × 10.
e ^-6 Torr or less, all vapor depositions are 2-3 × 10e
-Perform in the range of ^-6 Torr. In addition, all vapor deposition may be performed by connecting a DC power source (PAK10-70A, manufactured by Kikusui Electronics Co., Ltd.) to a resistance heating type vapor deposition boat made of tungsten.

A carbon film of 20 to 50 nm is formed on the array substrate thus arranged in the vacuum layer. Then, 4- (N, N-bis (p-methylphenyl) amino) -α-phenylstilbene is used as a hole injection layer in an amount of 0.3.
The film is formed to a thickness of about 5 nm at a vapor deposition rate of nm / sec. As the hole transport layer, N, N′-bis (4′-diphenylamino-4-biphenylyl) -N, N′-diphenylbenzidine (manufactured by Hodogaya Chemical Co., Ltd.) and 4-N, N-diphenylamino-α. -Phenylstilbene was co-deposited at a deposition rate of 0.3 nm / s and 0.01 nm / s to form a film thickness of about 80 nm. As a light emitting layer (electron transport layer), tris (8-quinolinolato) aluminum (manufactured by Dojindo Co., Ltd.) is formed at a deposition rate of 0.3 nm / sec to a film thickness of about 40 nm. Next, as an electron injection electrode, an AlLi alloy (manufactured by Kojundo Chemical Co., Ltd., Al / L
i weight ratio is 99/1), and only Li at low temperature is about 0.1n
It is formed to a film thickness of about 1 nm at a vapor deposition rate of m / sec, and then the AlLi alloy is further heated. From the state where Li was exhausted, only Al was formed to a film thickness of about 100 nm at a vapor deposition rate of about 1.5 nm / s to form a laminated electron injection electrode. Organic thin-film EL device 15 thus prepared
After leaking the inside of the vapor deposition tank with dry nitrogen, in a dry nitrogen atmosphere, a sealing lid 85 made of Corning 7059 glass is used as a sealing adhesive (sealant) (manufactured by ANELVA CORPORATION, trade name Super Back Seal 953-7000). ) To paste it as a display panel. A desiccant 107 is placed in the space between the sealing lid 85 and the array substrate 71. This is because the organic EL film 15 is weak against humidity. The desiccant 107 absorbs moisture that permeates the sealant to prevent the deterioration of the organic EL film 15. In order to suppress the permeation of water from the sealant 15, it is a good measure to lengthen the path from the outside. Therefore, in the display panel of the present invention, fine irregularities are formed in the peripheral portion of the display area. At least two concave and convex portions formed on the periphery of the array substrate 71
Form in multiple layers. The distance between the protrusions (formation pitch) is 100.
It is preferable to form it in the range of not less than μm and not more than 500 μm, and the height of the protrusion is preferably not less than 30 μm and not more than 300 μm. This convex portion is formed by a stamper technique. This stamper technology applies the method adopted by Omron as a method for forming a microlens, the method used by Matsushita Electric as a method for forming a minute lens in a pickup lens of a CD, and the like. On the other hand, a concave portion or a convex portion is also formed on the sealing lid 85. The formation pitch of the concave portions or the convex portions is the same as the formation pitch of the convex portions formed on the substrate 71. In this way, by making the formation pitches of the concave portions or the convex portions of the substrate 71 and the substrate 85 the same, the concave portions just fit into the convex portions. Therefore, when the display panel is manufactured, the sealing lid 85 and the array substrate 7 are
No positional deviation from 1 occurs. A sealant is placed between the convex portion and the concave portion. The sealing agent is the sealing lid 85 and the array substrate 7.
1 and are bonded together, and moisture is prevented from entering from the outside.

As the sealant, it is preferable to use a UV (ultraviolet) curable type acrylic resin. Further, it is preferable to use an acrylic resin having a fluorine group. Besides, an epoxy adhesive or pressure-sensitive adhesive may be used. It is preferable to use an adhesive or pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. Particularly, as the seal adhesive, it is preferable to add fine powder of titanium oxide, fine powder of silicon oxide or the like in a ratio of 65% or more and 95% or less by weight. The particle size of the fine powder is preferably 20 μm or more and 100 μm or less in average diameter. The larger the weight ratio of the fine powder, the higher the effect of suppressing the entry of humidity from the outside. However, if the amount is too large, bubbles and the like tend to enter, and the space becomes rather large and the sealing effect decreases. The weight of the desiccant 107 is 0.04 g or more per 10 mm of the seal length 0.2
It is preferably g or less. Especially the length of the seal is 10m
It is desirable that the amount is 0.06 g or more and 0.15 g or less per m. If the amount of the desiccant is too small, the effect of preventing moisture is small and the organic EL layer 15 is deteriorated immediately. If the amount is too large, the desiccant becomes a hindrance in sealing, and good sealing cannot be performed. Note that the desiccant 107 is preferably formed in a sheet shape and placed between the lid 85 and the EL film. At that time, it is preferable that a UV curable resin is applied to the desiccant 107, and after the arrangement, ultraviolet rays are irradiated to cure the UV resin and fix it. Although FIG. 10 shows a configuration in which the glass lid 85 is used for sealing, a film (thin film may be used as shown in FIG. 11).
That is, the sealing may be performed using the thin film sealing film) 111. For example, as the sealing film (thin film sealing film) 111, a film of an electrolytic capacitor on which DLC (diamond-like carbon) is deposited is used. This film has extremely poor water permeability (moisture proof). This film is used as the sealing film 111. Also,
It goes without saying that a structure in which a DLC film or the like is directly vapor-deposited on the surface of the electrode 106 may be used. In this case, the positional relationship between the cathode and the anode may be reversed. The thickness of the thin film is n · d (where n is the refractive index of the thin film, and when a plurality of thin films are laminated, the total refractive index of the thin films (n.
Calculate d). d is a film thickness of a thin film, and when a plurality of thin films are laminated, their refractive indexes are comprehensively calculated. ) Is preferably the emission main wavelength λ of the EL element 15 or less. By satisfying this condition,
The light extraction efficiency from the EL element 15 is more than double that in the case of sealing with a glass substrate. Also, an alloy or mixture of aluminum and silver or a laminate may be formed. As described above, without using the lid 85, the sealing film 11
The configuration of sealing with 1 is called thin film sealing. The thin film sealing in the case of “downward extraction (see FIG. 10, the light extraction direction is the direction of the arrow in FIG. 10)” for extracting light from the substrate 71 side is
After forming the EL film, an aluminum electrode serving as a cathode is formed on the EL film. Next, a resin layer as a buffer layer is formed on this aluminum film. Examples of the buffer layer include organic materials such as acrylic and epoxy. The film thickness is 1 μm or more 1
A thickness of 0 μm or less is suitable. More preferably, the film thickness is 2 μm or more and 6 μm or less. A sealing film 74 on this buffer film is formed. Without a buffer film, stress causes E
The structure of the L film collapses, causing streak-like defects. Sealing film 11
As mentioned above, 1 is DLC (Diamond-like).
Carbon) or a layered structure of an electric field capacitor (structure in which dielectric thin films and aluminum thin films are alternately deposited in multiple layers) is exemplified. In the case of "outcoupling is shown in FIG. 11, the light extraction direction is the direction of the arrow in FIG. 11" for extracting light from the EL layer 15 side, thin film sealing is performed after forming the EL film 15
An Ag—Mg film serving as a cathode (anode) is formed on the film 15 with a film thickness of 20 angstroms or more and 300 angstroms. A transparent electrode made of ITO or the like is formed thereon to reduce the resistance. Next, a resin layer as a buffer layer is formed on this electrode film. The sealing film 111 is formed on this buffer film. Half of the light generated from the organic EL layer 15 is reflected by the reflective film 106, transmitted through the array substrate 71, and emitted. However, external light is reflected on the reflective film 106 to cause reflection, which lowers the display contrast. As a countermeasure, a λ / 4 plate 108 and a polarizing plate (polarizing film) 109 are arranged on the array substrate 71. When the pixel is a reflective electrode, the light generated from the EL layer 15 is emitted upward. Therefore, the phase plate 108 and the polarizing plate 1
It goes without saying that 09 is arranged on the light emitting side. In the reflective pixel, the pixel electrode 105 is made of aluminum,
It is made of chrome, silver, etc. Also, the pixel electrode 1
By providing a convex portion (or a concave-convex portion) on the surface of 05, the interface with the organic EL layer 15 is widened, the light emitting area is increased, and the luminous efficiency is improved. The cathode 106
If a reflective film to be the (anode 105) is formed on the transparent electrode or the reflectance can be reduced to 30% or less,
A circularly polarizing plate is unnecessary. This is because the reflection is significantly reduced. In addition, light interference is reduced, which is desirable.

Further, the external light reflection realized by forming the two-layer thin film inside the display is canceled by the optical interference, so that the contrast of the organic EL display panel can be improved. The cost can be reduced as compared with the case where the conventional circularly polarizing plate is used. In addition, the problem of diffuse reflection that the circularly polarizing plate had, the viewing angle dependence of the display color, and the organic EL
The problem of the thickness dependence of the light emitting layer can be solved.

The substrate 71 and the polarizing plate (polarizing film) 109
One or more phase films 108 (phase plate, phase rotating means, phase difference plate, phase difference film) are arranged in between. It is preferable to use polycarbonate as the phase film. The phase film generates a phase difference between the incident light and the emitted light and contributes to efficient light modulation.

In addition, as the phase film, an organic resin plate or an organic resin film of polyester resin, PVA resin, polysulfone resin, vinyl chloride resin, Zeonex resin, acrylic resin, polystyrene resin or the like may be used. Alternatively, crystals such as quartz may be used.
The phase difference of one phase plate is 50 nm or more in the uniaxial direction 350
The thickness is preferably not more than nm, more preferably not less than 80 nm and not more than 220 nm. It goes without saying that a circularly polarizing plate (circularly polarizing film) in which a phase film and a polarizing plate are integrated may be used. It is preferable that the phase film 108 be colored with a dye or a pigment to have a function as a filter. In particular, the organic EL 15 has poor red (R) purity. Therefore, the colored phase film 108 cuts a certain wavelength range to adjust the color temperature. The color filter is generally provided by a pigment dispersion type resin as a dyeing filter. The pigment absorbs light in a specific wavelength band and transmits light in the unabsorbed wavelength band.

As described above, a part or the whole of the phase film 108 may be colored, or a part or the whole may have a diffusion function. In addition, the surface may be embossed or an antireflection film may be formed to prevent reflection. In addition, it is preferable to form a light-shielding film or a light-absorbing film at a position that is not effective for image display or a position that does not hinder the display, thereby reducing the black level of the display image and exhibiting a contrast improving effect by preventing halation. Further, the microlenses may be formed in a semicylindrical shape or a matrix shape by forming irregularities on the surface of the phase film. The microlenses are arranged so as to correspond to one pixel electrode or pixels of three primary colors, respectively.

As described above, the color filter may have the function of the phase film. For example, the phase difference can be generated by rolling when forming the color filter or by causing the phase difference to occur in a certain direction by photopolymerization. Alternatively, the smoothing film 102 may be photopolymerized to have a phase difference. With this structure, it is not necessary to form or dispose the phase film outside the substrate, the structure of the display panel is simplified, and cost reduction can be expected. Needless to say, the above items may be applied to the polarizing plate.

A TAC film (triacetyl cellulose film) is most suitable as a main material constituting the polarizing plate (polarizing film) 109. This is because the TAC film has excellent optical properties, surface smoothness and processability. For the production of TAC film, it is optimal to produce it by the solution casting film forming technique.

The polarizing plate 109 is exemplified by a resin film in which iodine or the like is added to polyvinyl alcohol (PVA) resin. The polarizing plates 109 of the pair of polarization separation means perform polarization separation by absorbing the polarization component of the incident light in a direction different from the specific polarization axis direction, and thus the light utilization efficiency is relatively poor. Therefore, the polarization component (reflective p) of the incident light in a direction different from the specific polarization axis direction
It is also possible to use a reflective polarizer that performs polarized light separation by reflecting an optical polarizer (reflecting polarizer). According to this structure, the light utilization efficiency is increased by the reflective polarizer, and a brighter display can be performed as compared with the above example using the polarizing plate.

In addition to such a polarizing plate and a reflective polarizer, as the polarization separating means of the present invention, for example, a combination of a cholesteric liquid crystal layer and a (1/4) λ plate 108, and a Brewster angle are set. It is also possible to use a polarization beam splitter (PBS) or the like that uses reflected light and transmitted polarized light to separate it, uses a hologram.

Although not shown in FIG. 10, the polarizing plate 10
The surface of 9 has an AIR coat. The AIR coat is exemplified by a structure formed of a dielectric single layer film or a multilayer film. In addition, a resin having a low refractive index of 1.35 to 1.45 may be applied. For example, a fluorinated acrylic resin is exemplified. In particular, those having a refractive index of 1.37 or more and 1.42 or less have good characteristics.

The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide wavelength band of visible light, and this is called multicoat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band, and this is called a V coat. The multi coat and the V coat are used properly according to the use of the display panel. The number of layers is not limited to two or more, and one layer may be used.

Aluminum oxide in case of multi-coat
(Al₂O₃) Has an optical film thickness of nd = λ / 4, zirconium
Mu (ZrO₂) Nd1 = λ / 2, magnesium fluoride
(MgF₂) Is formed by stacking nd1 = λ / 4. Communication
Normally, λ is 520 nm or a thin value near 520 nm
The film is formed. In the case of V coat, silicon monoxide (S
iO) with an optical film thickness of nd1 = λ / 4 and magnesium fluoride
Mu (MgF₂) Is nd1 = λ / 4, or it is oxidized
Rium (Y₂O₃) And magnesium fluoride (MgF₂)
It is formed by stacking n d1 = λ / 4. SiO is on the blue side
Y when modulating blue light because of the absorption band₂O₃For
You had better stay. Also, from the stability of the substance, Y ₂O₃Is better
It is preferable because it is stable. Also, SiO₂Use thin film
You may. Of course, using a low refractive index resin, etc.
It may be an R coat. For example, acrylic trees such as fluorine
An example is fat. These must be UV curable types.
And are preferred.

In order to prevent the display panel from being charged with static electricity, it is preferable to apply a hydrophilic resin to the surface of the display panel or the like. In addition, in order to prevent surface reflection, the surface of the polarizing plate 54 may be embossed. Further, although the transistor is connected to the pixel electrode 105, the invention is not limited to this. The active matrix means a thin film transistor (transistor) as a switching element, a diode type (TFD), a varistor, a thyristor, a ring diode, a photodiode, a phototransistor, an FET, and an M.
Needless to say, it may be an OS transistor, a PLZT element, or the like. That is, the switch element 11 and the drive element 1
Any of these can be used as the one configured as 1. Further, a simple matrix type pixel configuration in which a plurality of substantially striped electrodes are arranged may be used. Further, the transistor preferably has an LDD (low doping drain) structure. Note that the transistor is FE
It means all elements in general that perform transistor operations such as switching such as T. Further, it goes without saying that the structure of the EL film, the panel structure and the like can be applied to the simple matrix type display panel. Further, in this specification, an organic EL element (OEL, PEL, PLED, OL
15 described by various abbreviations such as ED) will be described as an example, but the present invention is not limited to this, and it goes without saying that the invention is also applied to an inorganic EL element.

First, the active matrix system used for the organic EL display panel is as follows. To be able to select specific pixels and be given the necessary display information. It is necessary to satisfy the two conditions that a current can be passed through the EL element during 2 and 1 frame periods.

In order to satisfy these two conditions, FIG.
In the conventional organic EL pixel configuration shown in FIG. 1, the first transistor 11b is a switching transistor for selecting a pixel, and the second transistor 11a is a driving transistor for supplying a current to the EL element (EL film) 15. Use as a transistor.

Compared to the active matrix system used for liquid crystal, the switching transistor 11b is also required for liquid crystal, but the driving transistor 11a is necessary for lighting the EL element 15.
The reason for this is that in the case of liquid crystal, the ON state can be maintained by applying a voltage, but in the case of the EL element 15,
This is because the lighting state of the pixel 16 cannot be maintained unless current is continuously supplied.

Therefore, in the EL display panel, the transistor 11a must be kept on in order to keep the current flowing. First, when both the scanning line and the data line are turned on, charges are accumulated in the capacitor 19 through the switching transistor 11b. This capacitor 1
Since 9 continues to apply voltage to the gate of the driving transistor 11a, even if the switching transistor 11b is turned off, current continues to flow from the current supply line (Vdd) and the pixel 16 can be turned on for one frame period.

When displaying gradation using this structure,
It is necessary to apply a voltage according to the gradation as the gate voltage of the driving transistor 11a. Therefore, the variation in the on-current of the driving transistor 11a appears on the display as it is.

The on-current of a transistor is extremely uniform if it is a transistor formed of a single crystal, but the formation temperature at which it can be formed on an inexpensive glass substrate is 45.
In the low temperature polycrystalline transistor formed by the low temperature poly-silicon technique of 0 degrees or less, the variation in the threshold value is ± 0.2V to
There are variations in the range of 0.5V. Therefore, the on-current flowing through the driving transistor 11a varies correspondingly, and display unevenness occurs. These irregularities occur not only in the variation of the threshold voltage but also in the mobility of the transistor and the thickness of the gate insulating film. The characteristics also change due to deterioration of the transistor 11. In addition,
The present invention is not limited to the low-temperature polysilicon technology, and may be formed by using a high-temperature polysilicon technology with a process temperature of 450 degrees Celsius or higher, or by using a semiconductor film grown by solid phase (CGS). You may use what formed TFT etc. Alternatively, an organic TFT may be used. In this specification, a TFT formed by the low temperature polysilicon technique will be mainly described. However, the problems such as the variation of the TFT are the same in other methods.

Therefore, in the method of displaying gray scales in an analog manner, it is necessary to strictly control the characteristics of the device in order to obtain a uniform display. In the current low temperature polycrystal polysilicon transistor, this variation is within a predetermined range. I can't satisfy the specifications to keep within. In order to solve this problem, four or more transistors are provided in one pixel, and the variation in threshold voltage is compensated by a capacitor to obtain a uniform current. A constant current circuit is formed for each pixel. It is possible to consider a method for making the temperature uniform.

However, in these methods, since the programmed current is programmed through the EL element 15, the transistor controlling the drive current becomes the source follower for the switching transistor connected to the power supply line when the current path changes. The drive margin becomes narrow. Therefore, there is a problem that the driving voltage becomes high.

Further, it is necessary to use the switching transistor connected to the power source in the region of low impedance, and there is also a problem that this operating range is affected by the characteristic variation of the EL element 15. In addition, when the kink current occurs in the voltage-current characteristics in the saturation region, or when the threshold voltage of the transistor changes, the stored current value also changes.

In the EL device structure of the present invention, in order to solve the above problems, even if the transistor 11 for controlling the current flowing through the EL device 15 does not have the source follower structure and the transistor has a kink current, the kink current is It is possible to minimize the influence of the above and reduce the fluctuation of the stored current value.

The pixel structure of the EL display device of the present invention is specifically formed by a plurality of transistors 11 each having at least four unit pixels and an EL element as shown in FIG. Note that the pixel electrode is formed so as to overlap with the source signal line. That is, an insulating film or a flattening film made of an acrylic material is formed on the source signal line 18 for insulation, and the pixel electrode 105 is formed on this insulating film. Such a structure in which the pixel electrode is overlapped on the source signal line 18 is called a high aperture (HA) structure.

By activating the gate signal line (first scanning line) 17a (applying the ON voltage), the transistor (transistor or switching element) 11a for driving the EL element 15 and the transistor (transistor or switching element) 11c are passed. , Said E
The current value to be passed through the L element 15 is set to the source driver circuit 14
Shed from. Further, the transistor 11b is opened by activating the gate signal line 17a (applying an ON voltage) so that the gate and the drain of the transistor 11a are short-circuited, and the capacitor (capacitor, which is connected between the gate and the source of the transistor 11a). Storage capacitor, additional capacitor 19 so that the current value flows through the transistor 1
The gate voltage (or drain voltage) of 1a is stored (see FIG. 3A).

The source (S) of the transistor 11a
-Capacitance (capacitor) 19 between gate (G) is 0.2 pF
It is preferable to set the capacity to the above. As another configuration, a configuration in which the capacitor 19 is separately formed is also exemplified. That is, the storage capacitor is formed from the capacitor electrode layer, the gate insulating film, and the gate metal. From the viewpoint of preventing a decrease in luminance due to the leakage of the transistor 11c and stabilizing the display operation, it is preferable to separately form the capacitor in this way. The size of the capacitor (storage capacity) 19 is 0.2 pF or more and 2 pF or more.
The following is preferable, and above all, capacitors (storage capacity)
The size of 19 is preferably 0.4 pF or more and 1.2 pF or less.

It is preferable that the capacitor 19 is generally formed in the non-display area between adjacent pixels. Generally, when creating a full-color organic EL15, organic E
Since the L layer 15 is formed by mask vapor deposition using a metal mask, the EL layer formation position occurs due to the mask position shift.
When the displacement occurs, the organic EL layer 15 (15R,
15G, 15B) may overlap. Therefore, the non-display area between adjacent pixels of each color must be separated by 10 μm or more. This portion does not contribute to light emission. Therefore, forming the storage capacitor 19 in this region is an effective means for improving the aperture ratio.

The metal mask is made of a magnetic material, and the metal mask is magnetically attracted from the back surface of the substrate 71 with a magnet. Due to the magnetic force, the metal mask adheres to the substrate without any gap. The matters regarding the above manufacturing method are also applied to the other manufacturing methods of the present invention.

Next, the gate signal line 17a is made inactive (OFF voltage is applied) and the gate signal line 17b is made active, and the current flow path is connected to the first transistor 11a and the transistor 1 connected to the EL element 15.
It switches to a path including 1d and the EL element 15, and operates so that the stored current flows through the EL element 15 (see FIG. 3B).

This circuit has four transistors 11 in one pixel, and the gate of the transistor 11a is connected to the source of the transistor 11b. The gates of the transistors 11b and 11c are connected to the gate signal line 17a. Transistor 1
The drain of 1b is connected to the source of the transistor 11c and the source of the transistor 11d, and the drain of the transistor 11c is connected to the source signal line 18. The gate of the transistor 11d is the gate signal line 17b.
The drain of the transistor 11d is connected to the anode electrode of the EL element 15.

In FIG. 1, all the transistors are P
It consists of channels. The mobility of P-channel is somewhat lower than that of N-channel transistor,
It is preferable because it has a large withstand voltage and is less likely to deteriorate. However, the present invention is not limited to the configuration of the EL device including P channels. You may comprise only N channels. Further, both N channel and P channel may be used.

In FIG. 1, the transistor 11c,
It is preferable that 11b is configured with the same polarity and is configured with an N channel, and the transistors 11a and 11d are configured with a P channel. Generally, the P-channel transistor has features such as higher reliability and less kink current than the N-channel transistor, and the EL element 1 that obtains a desired light emission intensity by controlling the current
5, the effect of making the transistor 11a P-channel is large. Optimally, all the TFTs 11 constituting the pixel are formed by P channels, and the built-in gate driver 12
Is also preferably formed by a P channel. By forming the array with TFTs of only P-channel in this way, the number of masks becomes 5, and it is possible to realize low cost and high yield.

In order to facilitate the understanding of the present invention, the EL element structure of the present invention will be described below with reference to FIG. The EL element structure of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. By turning on the transistors 11b and 11c at this timing, an equivalent circuit shown in FIG. 3A is obtained. Here, a predetermined current Iw is written from the signal line. As a result, the gate and drain of the transistor 11a are connected to each other, and the current Iw flows through the transistor 11a and the transistor 11c. Therefore, the gate-source voltage of the transistor 11a becomes the voltage V1 at which I1 flows.

The second timing is the timing when the transistors 11a and 11c are closed and the transistor 11d is opened, and the equivalent circuit at that time is shown in FIG. 3 (b). The source-gate voltage of the transistor 11a remains held. In this case, the transistor 11a
Always operates in the saturation region, the current of Iw is constant.

When operated in this way, it becomes as shown in FIG. That is, 51a in FIG.
0 shows a pixel (row) (current writing pixel row) in which the current is programmed at a certain time. The pixel (row) 51a is not illuminated (non-display pixel (row)) as illustrated in FIG. The other pixels (rows) are display pixels (rows) 53 (current flows through the EL elements 15 of the non-pixels 53, and the EL elements 15 emit light).

In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing through Iw is retained. At this time, the transistor 11d is in an open state (off state).

Next, during the period in which a current is passed through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d operates as shown in FIG. 3B. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, the gate signal line 1
The on-voltage (Vgl) is applied to 7b, and the transistor 1
1d turns on.

This timing chart is shown in FIG. Note that, in FIG. 4 and the like, subscripts in parentheses (for example, (1) and the like) indicate pixel row numbers. That is, the gate signal line 17a (1) indicates the gate signal line 17a of the pixel row (1). In addition, * in the upper part of FIG.
H indicates a horizontal scanning period. That is, 1H is the first horizontal scanning period. The above items are
For ease of explanation, the limitation (1H number, 1
H period, order of pixel row numbers, etc.).

As can be seen from FIG. 4, in each selected pixel row (the selection period is 1H), when the ON voltage is applied to the gate signal line 17a, the OFF voltage is applied to the gate signal line 17b. Is being applied. During this period, no current flows in the EL element 15 (non-lighting state). In the unselected pixel rows, an off voltage is applied to the gate signal line 17a and an on voltage is applied to the gate signal line 17b. Also, during this period, EL
A current is flowing through the element 15 (lighting state).

The gate of the transistor 11a and the gate of the transistor 11c are connected to the same gate signal line 11a. However, the gate of the transistor 11a and the gate of the transistor 11c have different gate signal lines 1
1 may be connected (see FIG. 32). The number of gate signal lines for one pixel is three (the configuration of FIG. 1 is two). By individually controlling the ON / OFF timing of the gate of the transistor 11b and the ON / OFF timing of the gate of the transistor 11c, the transistor 1
It is possible to further reduce the variation in the current value of the EL element 15 due to the variation of 1a.

Gate signal line 17a and gate signal line 17b
If the transistors 11c and 11d have different conductivity types (N channel and P channel) in common, the driving circuit can be simplified and the aperture ratio of the pixel can be improved.

With this structure, the write path from the signal line is turned off in the operation timing of the present invention.
That is, when a predetermined current is stored, an accurate current value is not stored in the source (S) -gate (G) capacitance (capacitor) of the transistor 11a if there is a branch in the current flow path. Transistor 11c and transistor 11d
It is possible to turn on the transistor 11d after the transistor 11c is turned off at the timing of switching the scanning lines by controlling the thresholds of the transistors by making the transistors different in conductivity type.

However, in this case, it is necessary to control the threshold values of each other accurately, and therefore the process needs to be careful. Although the circuit described above can be realized with at least four transistors, the transistor 11e is cascade-connected as shown in FIG. 2 for more accurate timing control or for reducing the Miller effect, as will be described later. The operating principle is the same even if the total number of transistors is four or more. With the configuration including the transistor 11e in this manner, the programmed current can be made to flow through the EL element 15 with higher accuracy through the transistor 11c.

In the configuration of FIG. 1, it is more preferable that the current value Ids in the saturation region of the first transistor 11a satisfies the condition of the following equation. In the equation below, the value of λ is 0.06 or less between adjacent pixels 0.0
Satisfy one or more conditions.

Ids = k × (Vgs−Vth) ² (1 + Vds × λ) In the present invention, the operating range of the transistor 11a is limited to the saturation region. Generally, the transistor characteristic in the saturation region is lower than the ideal characteristic. It comes off and is affected by the voltage between source and drain. This effect is called the mirror effect.

Consider a case where a threshold shift of ΔVt occurs in each transistor 11a in adjacent pixels. In this case, the stored current values are the same. If the shift of the threshold value is ΔL, about ΔV × λ is about 1
This corresponds to the deviation of the current value of the EL element 15 due to the change in the threshold value of 1a. Therefore, the deviation of the current is x
In order to suppress the threshold value to less than or equal to (%), y is set to 0.
It can be seen that it must be 01 × x / y or less.

This tolerance depends on the brightness of the application.
Change. Brightness is 100 cd / m ²To 1000 cd
/ M²In the luminance range up to, the fluctuation amount is 2% or more.
Then, the human recognizes the changed boundary line. Therefore, shining
It is necessary that the fluctuation amount of the degree (current amount) is within 2%
It Brightness is 100 cd / cm²Adjacent if higher
The amount of change in luminance of the pixel is 2% or more. EL display of the present invention
When using the device as a display for mobile terminals,
Required brightness is 100 cd / m²It is a degree. In fact
Prototype the pixel configuration and measure the threshold variation
The maximum value of the fluctuation of the threshold in the transistor 11a of the pixel
Was found to be 0.3V. Therefore, the brightness change
In order to keep the movement within 2%, λ must be 0.06 or less.
I have to. However, it is not necessary to set it below 0.01
Yes. This is because humans cannot recognize the change.
In addition, in order to achieve this threshold variation, the transition
It is necessary to make the star size large enough,
It

It is preferable that the current value Ids in the saturation region of the first transistor 11a satisfies the following equation. The variation of λ is 5% or less and 1% or more between adjacent pixels.

Ids = k × (Vgs−Vth) ² (1 + Vds × λ) Even if there is no change in the threshold value between adjacent pixels, if λ in the above formula changes, the current value flowing through the EL changes. To do. To keep the fluctuation within ± 2%,
The variation of λ must be suppressed to ± 5%. However, however, it does not have to be 1% or less. This is because humans cannot recognize the change. Further, in order to achieve 1% or less, the transistor size needs to be considerably increased, which is unrealistic.

Further, according to experiments, array trial manufacture and examination, the channel length of the first transistor 11a is 10 μm.
It is preferable that the thickness is 200 μm or less. More preferably, the channel length of the first transistor 11a is 1
The thickness is preferably 5 μm or more and 150 μm or less. This is considered to be because when the channel length L is lengthened, the grain boundaries included in the channel increase, and the electric field is relaxed, and the kink effect is suppressed to a low level.

Further, the transistor 11 forming the pixel
Is preferably a polysilicon transistor formed by a laser recrystallization method (laser anneal), and the channel directions in all transistors are preferably the same as the laser irradiation direction. Further, it is preferable that the laser scans the same portion twice or more to form a semiconductor film.

The object of the invention of this patent is to propose a circuit configuration in which variations in transistor characteristics do not affect the display, and therefore four or more transistors are required. When the circuit constant is determined based on these transistor characteristics, it is difficult to obtain an appropriate circuit constant unless the four transistors have the same characteristics. When the channel direction is horizontal or vertical with respect to the long-axis direction of laser irradiation, the threshold and mobility of transistor characteristics are different. The degree of variation is the same in both cases. The mobility and the average value of the thresholds are different between the horizontal direction and the vertical direction. Therefore, it is desirable that the channel directions of all the transistors forming the pixel are the same.

The capacitance value of the storage capacitor 19 is set to Cs, the second
When the off-state current value of the transistor 11b is Ioff, it is preferable to satisfy the following equation.

3 <Cs / Ioff <24 More preferably, it is preferable to satisfy the following formula.

6 <Cs / Ioff <18 By setting the off current of the transistor 11b to 5 pA or less, it is possible to suppress the change in the current value flowing through the EL to 2% or less. This is because when the leak current increases, the charge stored between the gate and the source (both ends of the capacitor) cannot be retained for one field in the voltage non-writing state. Therefore, the larger the storage capacity of the capacitor 19, the larger the allowable amount of off-current. By satisfying the above equation, the fluctuation of the current value between adjacent pixels can be reduced by 2
% Or less.

Further, it is preferable that the transistors forming the active matrix are formed of p-ch polysilicon thin film transistors, and the transistor 11b has a multi-gate structure having at least dual gates. Since the transistor 11b acts as a switch between the source and drain of the transistor 11a, it is turned on / off as much as possible.
High OFF ratio characteristics are required. Transistor 11b
A high ON / OFF ratio characteristic can be realized by adopting a multi-gate structure having a dual gate structure or more as the gate structure.

It is preferable that the transistors forming the active matrix are polysilicon thin film transistors, and the (channel width W) × (channel length L) of each transistor is 54 μm ² or less. There is a correlation between (channel width W) × (channel length L) and variations in transistor characteristics. The cause of the variation in transistor characteristics is largely due to the variation in energy due to laser irradiation. Therefore, in order to absorb this, the laser irradiation pitch (generally 10 and several μm) should be set as much as possible within the channel. A structure containing many is desirable. By setting (channel width W) × (channel length L) of each transistor to 54 μm ² or less, there can be obtained a thin film transistor having uniform characteristics without variations due to laser irradiation. It should be noted that if the transistor size becomes too small, the characteristics will vary depending on the area. Therefore, the (channel width W) × (channel length L) of each transistor should be 9 μm ² or more. It is more preferable that the (channel width W) × (channel length L) of each transistor be 16 μm ² or more and 45 μm ² or less.

Further, it is preferable that the mobility fluctuation of the first transistor 11a in the adjacent unit pixel is 20% or less. Due to the lack of mobility, the charging capacity of the switching transistor deteriorates, and the gate-source capacitance of M1 cannot be charged by the time the necessary current value is passed. Therefore, by suppressing the variation in movement within 20%, it is possible to reduce the variation in luminance between pixels to the recognition limit or less.

Although the above description has been made assuming that the pixel configuration is that of FIG. 1, the above items can also be applied to other pixel configurations. The configuration and operation of the pixel configuration shown in FIG. 38 will be described below as an example.

When the current flowing through the EL element 15 is set, the signal current flowing through the transistor 11a is Iw, and as a result, the gate-source voltage generated in the transistor 11a is Vgs.
And At the time of writing, since the gate and drain of the transistor 11a are short-circuited by the transistor 11d, the transistor 11a operates in the saturation region. Therefore, Iw is given by the following formula.

Iw = μ1 · Cox1 · (W1 / L1) / 2 (Vgs−Vth1) ² (1) Here, Cox is a gate capacitance per unit area,
It is given by Cox = ε0 · εr / d. Vth is the threshold of the transistor, μ is the carrier mobility, W is the channel width, L is the channel length, ε0 is the vacuum mobility, εr is the relative dielectric constant of the gate insulating film, and d is the thickness of the gate insulating film. is there.

When the current flowing through the EL element 15 is Idd, the current level of Idd is controlled by the transistor 1b connected in series with the EL element 15. In the present invention, since the gate-source voltage thereof matches Vgs of the equation (1), the following equation is established assuming that the transistor 1b operates in the saturation region.

Idrv = μ2 · Cox2 · (W2 / L2) / 2 (Vgs−Vth2) ² (2) The condition for the insulated gate field effect thin film transistor (transistor) to operate in the saturation region is to drain Vds -The voltage between sources is generally given by the following formula.

| Vds |> | Vgs−Vth | (3) Here, the transistors 11a and 11b are
Since it is formed close to the inside of a small pixel, approximately μ1 =
μ2 and Cox1 = Cox2, and it is considered that Vth1 = Vth2 unless special measures are taken. Then,
At this time, the following equations are easily derived from the equations (1) and (2).

Idrv / Iw = (W2 / L2) / (W1 / L1) (4) The point to be noted here is that the values of μ, Cox, and Vth in equations (1) and (2) are , Per pixel, per product,
Or it is usually different for each production lot,
Since Equation (4) does not include these parameters, Idr
This means that the value of v / Iw does not depend on these variations.

If W1 = W2 and L1 = L2 are designed, Idrv / Iw = 1, that is, Iw and Idrv have the same value. That is, the drive current Idd flowing through the EL element 15 is exactly the same as the signal current Iw regardless of variations in transistor characteristics, and as a result, the emission brightness of the EL element 15 can be accurately controlled.

As described above, since Vth1 of the driving transistor 11a and Vth2 of the driving transistor 11b are basically the same, the cut-off level signal voltage is applied to the gates at the common potential of both transistors. When applied, transistor 11a and transistor 11
Both b should be in a non-conducting state. However, in reality, due to factors such as parameter variations within the pixel,
Vth2 may be lower than Vth1. At this time, since a sub-threshold level leak current flows through the driving transistor 11b, the EL element 1
5 exhibits weak light emission. This slight light emission lowers the contrast of the screen and impairs the display characteristics.

Particularly in the present invention, the driving transistor 11 is used.
The threshold voltage Vth2 of b is set so as not to be lower than the threshold voltage Vth1 of the corresponding driving transistor 11a in the pixel. For example, the gate length L2 of the transistor 11b
Is longer than the gate length L1 of the transistor 11a,
Even if the process parameters of these thin film transistors change, Vth2 does not become lower than Vth1. This makes it possible to suppress a minute current leak. The above items also apply to the relationship between the transistor 11a and the transistor 11d in FIG.

As shown in FIG. 38, the driving transistor 1a for controlling the driving current flowing through the light emitting element including the driving transistor 11a through which the signal current flows, the EL element 15 and the like.
1b, a gate transistor 11c for connecting or disconnecting the pixel circuit and the data line data by controlling the gate signal line 17a1, and a switch for short-circuiting the gate and drain of the transistor 11a during the writing period by controlling the gate signal line 17a2. Transistor 11d, a capacitor C19 for holding the gate-source voltage of the transistor 11a after writing is completed, and an EL element 15 as a light emitting element.

In FIG. 38, the transistors 11c and 11d are N
Channel MOS (NMOS) and other transistors are P channel MOS (PMOS),
This is an example, and it does not necessarily have to be the same. Although one terminal of the capacitor C is connected to the gate of the transistor 11a and the other terminal is connected to Vdd (power supply potential), the capacitance C is not limited to Vdd and may be any constant potential. The cathode (cathode) of the EL element 15 is connected to the ground potential. Therefore, it goes without saying that the above items also apply to FIG.

The terminal voltage of the EL element 15 also changes with temperature. Usually, it is high when the temperature is low, and becomes low when the temperature is high. This tendency has a linear relationship. Therefore, the Vdd voltage depends on the external temperature (to be exact, E
It is preferable to adjust (by the temperature of the L element 15).
The temperature sensor detects the external temperature, and the Vdd voltage or the Vk voltage is changed by feeding back the Vdd voltage generator or the Vk voltage generator. It is preferable that the Vdd voltage and the like change by 2% or more and 8% or less with a change of 10 ° C. Above all, it is preferably 3% or more and 6% or less.

The Vdd voltage in FIG. 1 is the off voltage of the transistor 11b (when the transistor is a P channel).
It is preferable to lower it. Specifically, Vgh
(Gate off voltage) is at least Vdd-0.5
It should be higher than (V). If it is lower than this, off-leakage of the transistor occurs, and shot unevenness of the laser anneal becomes conspicuous. Also, Vdd + 4
Should be lower than (V). If it is too high, on the contrary, the amount of off leak increases.

Therefore, the off-voltage of the gate (Vgh in FIG. 1, that is, the voltage side close to the power supply voltage), the power supply voltage (Vdd in FIG. 1) is -0.5 (V) or more +4.
(V) Should be below. More preferably, the power supply voltage (Vdd in FIG. 1) is 0 (V) or more and +2.
(V) Should be below. That is, the off voltage of the transistor applied to the gate signal line is set to be sufficiently off. When the transistor is N channel, Vgl
Is the off voltage. Therefore, Vgl is set within the range of -4 (V) or more and 0.5 (V) or less with respect to the GND voltage. More preferably, the range is −2 (V) or more and 0 (V) or less.

Although the above description has been made with respect to the pixel configuration of the current program shown in FIG. 1, it is needless to say that the present invention is not limited to this and can be applied to the pixel configuration of the voltage program. The Vt offset cancellation of the voltage program is preferably individually compensated for each of R, G, and B.

The driving transistor 11b receives the voltage level held in the capacitor 19 at its gate and supplies a driving current having a current level corresponding to the voltage level to the EL element 15 through the channel. Transistor transistor 11a
Is directly connected to the gate of the transistor transistor 11b to form a current mirror circuit, and the current level of the signal current Iw and the current level of the drive current are in a proportional relationship.

The transistor 11b operates in the saturation region,
A drive current according to the difference between the voltage level applied to the gate and the threshold voltage is passed through the EL element 15.

The transistor 11b is set so that its threshold voltage does not become lower than the threshold voltage of the corresponding transistor 11a in the pixel. Specifically, the transistor 11
b is set so that its gate length is not shorter than the gate length of the transistor 11a. Alternatively, the transistor 11b may be set such that its gate insulating film is not thinner than the gate insulating film of the corresponding transistor 11a in the pixel.

Alternatively, the transistor 11b may be set by adjusting the concentration of impurities implanted into its channel so that the threshold voltage does not become lower than the threshold voltage of the corresponding transistor 11a in the pixel. For example, the transistor 11a
When the threshold voltage of the transistor 11b and the threshold voltage of the transistor 11b are set to be the same, when the cutoff level signal voltage is applied to the gates of the commonly connected transistors, the transistor 1
Both 1a and transistor 11b should be off. However, in reality, there are slight variations in the process parameters even within the pixel, and the transistor 11
The threshold voltage of the transistor 11b may be lower than the threshold voltage of a.

At this time, a weak current of sub-threshold level flows through the driving transistor 11b even if the signal voltage is below the cutoff level, so that the EL element 15 slightly emits light and the contrast of the screen deteriorates. Therefore, the gate length of the transistor 11b is made longer than that of the transistor 11a. This prevents the threshold voltage of the transistor 11b from becoming lower than the threshold voltage of the transistor 11a even if the process parameter of the transistor 11 varies within the pixel.

In the short channel effect region A having a relatively short gate length L, Vth rises as the gate length L increases.
On the other hand, in the suppression region B having a relatively large gate length L, Vth is almost constant regardless of the gate length L. By utilizing this characteristic, the gate length of the transistor 11b is made longer than that of the transistor 11a. For example, when the gate length of the transistor 11a is 7 μm, the gate length of the transistor 11b is about 10 μm.

The gate length of the transistor 11a may belong to the short channel effect region A, while the gate length of the transistor 11b may belong to the suppression region B. Accordingly, the short channel effect in the transistor 11b can be suppressed, and the threshold voltage reduction due to the change of the process parameter can be suppressed. As described above, it is possible to suppress the sub-threshold level leak current flowing in the transistor 11b, suppress the slight light emission of the EL element 15, and contribute to the improvement of contrast.

FIGS. 1, 2 and 3 produced in this way
A direct current voltage was applied to the EL display element 15 described in 8, etc., and it was continuously driven at a constant current density of 10 mA / cm ² . In the EL structure, light emission of 7.0 V and 200 cd / cm 2 in green color (maximum emission wavelength λmax = 460 nm) was confirmed. The brightness of the blue light emitting portion is 100 cd / cm ^2.
, The color coordinate is x = 0.129, y = 0.105, the green light emitting portion has a luminance of 200 cd / cm ² , and the color coordinate is x =
0.340, y = 0.625, the red light emitting portion has a brightness of 10
At 0 cd / cm ² , the color coordinates are x = 0.649, y =
An emission color of 0.338 was obtained. For full-color organic EL display panels, improving the aperture ratio is an important development issue.
This is because if the aperture ratio is increased, the light utilization efficiency is increased, which leads to higher brightness and longer life. In order to increase the aperture ratio, the area of the transistor that blocks light from the organic EL layer may be reduced. The low-temperature polycrystalline Si-transistor has a performance 10 to 100 times higher than that of amorphous silicon and has a high current supply capability, so that the size of the transistor can be made extremely small. Therefore, in the organic EL display panel, it is preferable to manufacture the pixel transistor and the peripheral drive circuit by the low temperature polysilicon technique. Of course, it may be formed by the amorphous silicon technique, but the pixel aperture ratio becomes considerably small.

By forming a driving circuit such as the gate driver circuit 12 or the source driver circuit 14 on the glass substrate 71, it is possible to reduce the resistance which is a particular problem in the current driven organic EL display panel. In addition to eliminating the connection resistance of TCP, the lead wire from the electrode is shortened by 2 to 3 mm and the wiring resistance is reduced as compared with the case of TCP connection. Furthermore, the process for TCP connection is eliminated,
Suppose there is an advantage that the material cost is reduced.

Next, the EL display panel or E of the present invention is used.
The L display device will be described. FIG. 6 is an explanatory diagram centering on the circuit of the EL display device. The pixels 16 are arranged or formed in a matrix. A source driver circuit 14 that outputs a current for performing a current program of each pixel is connected to each pixel 16. Source driver circuit 14
A current mirror circuit corresponding to the number of bits of the video signal is formed in the output stage of (described later). For example,
In the case of 64 gradations, 63 current mirror circuits are formed in each source signal line, and a desired current is supplied to the source signal line 1 by selecting the number of these current mirror circuits.
It is configured so that it can be applied to eight.

The minimum output current of one current mirror circuit is 10 nA or more and 50 nA. In particular, the minimum output current of the current mirror circuit should be 15 nA or more and 35 nA. This is to ensure the accuracy of the transistors forming the current mirror circuit in the driver IC 14.

Further, a built-in precharge or discharge circuit for forcibly releasing or charging the electric charge of the source signal line 18 is incorporated. It is preferable that the voltage (current) output value of the precharge or discharge circuit for forcibly discharging or charging the charge of the source signal line 18 can be set independently by R, G, and B. EL element 15
This is because the threshold value of is different for RGB.

It goes without saying that the pixel configuration, array configuration, panel configuration and the like described above are applied to the configurations, methods and devices described below. Further, it goes without saying that the pixel configuration, array configuration, panel configuration, etc. already described are applied to the configurations, methods, and devices described below. It is known that the organic EL element has a large temperature-dependent characteristic (temperature characteristic). In order to adjust the change in emission brightness due to this temperature characteristic, a non-linear element such as a thermistor or posistor that changes the output current is added to the current mirror circuit, and the change due to the temperature characteristic is adjusted with the thermistor etc. Create an electric current.

In this case, since it is uniquely determined by the EL material to be selected, it is often unnecessary to perform software control of a microcomputer or the like. That is, the liquid crystal material may be fixed at a fixed shift amount or the like. What is important is that the temperature characteristics differ depending on the luminescent color material, and the luminescent color (R,
That is, it is necessary to perform optimum temperature compensation for each of G and B).

The temperature characteristics of the R, G and B EL elements must be within a certain range. It goes without saying that it is preferable that the R, G and B EL elements 15 have no temperature characteristics. At least the R, G, and B temperature characteristic directions are the same direction or do not change. Also, the change is a change of 10 degrees Celsius for each color,
It is preferable to change it by 2% or more and 8% or less.
Above all, it is preferably 3% or more and 6% or less. Also,
The temperature compensation may be performed by a microcomputer. The temperature of the EL display panel is measured by the temperature sensor, and the temperature is changed by a microcomputer (not shown) or the like. Further, at the time of switching, the reference current or the like may be automatically switched by microcomputer control or the like, or may be controlled so that a specific menu display can be displayed. In addition, it can be configured to switch using a mouse or the like. Further, the display screen of the EL display device may be a touch panel, and a menu may be displayed to switch the display screen by pressing a specific portion.

In the present invention, the source driver is formed of a semiconductor silicon chip and is connected to the terminal of the source signal line 18 of the substrate 71 by the glass on chip (COG) technique.
Wiring for signal lines such as the source signal line 18 is made of metal such as chromium, aluminum, and silver. This is because a low resistance wiring can be obtained with a narrow wiring width. When the pixel is of a reflective type, the wiring is a material forming a reflective film of the pixel, and is preferably formed at the same time as the reflective film. This is because the process can be simplified.

The present invention is not limited to the COG technique, and the above-mentioned source driver IC 14 or the like may be mounted on the chip-on-film (COF) technique and connected to the signal line of the display panel. Further, the drive IC may have a three-chip configuration by separately producing the power supply IC 82.

Also, TCF tape may be used. TC
Films for F tape are polyimide film and copper (C
u) The foil can be thermocompressed without the use of adhesives.
Attach Cu to polyimide film without using adhesive T
In addition to the above, the CP tape film includes a method in which molten polyimide is superposed on a Cu foil and cast molding, and a method in which Cu is plated or deposited on a metal film formed by sputtering on the polyimide film. Although any of these may be used, the method of using a TCP tape in which Cu is attached to a polyimide film without using an adhesive is most preferable. For a lead pitch of 30 μm or less, a Cu beam laminated plate that does not use an adhesive is used. Among the Cu beam laminates that do not use an adhesive, the method of forming the Cu layer by plating or vapor deposition is suitable for thinning the Cu layer, and is therefore advantageous for miniaturizing the lead pitch.

On the other hand, the gate driver circuit 12 is formed by the low temperature polysilicon technique. That is, it is formed in the same process as the pixel transistor. This is because the internal structure is easier and the operating frequency is lower than that of the source driver circuit 14. Therefore, it can be easily formed even if it is formed by the low-temperature poly-silicon technique, and a narrow frame can be realized. Of course, the gate driver 12 is formed of a silicon chip, and the substrate 7 is formed using COG technology or the like.
It goes without saying that it may be mounted on one. Further, switching elements such as pixel transistors, gate drivers, etc. may be formed by a high temperature polysilicon technique or may be formed by an organic material (organic transistor).

The gate driver 12 has a gate signal line 17a.
Shift register circuit 61a and gate signal line 17b
And a shift register circuit 61b for. Each shift register circuit 61 has positive and negative phase clock signals (CLK
xP, CLKxN), and start pulse (STx). In addition, it is preferable to add an enable (ENABL) signal that controls output and non-output of the gate signal line and an up-down (UPDWM) signal that vertically reverses the shift direction. In addition, it is preferable to provide an output terminal for confirming that the start pulse is shifted to the shift register and then output. The shift timing of the shift register is controlled by a control signal from the control IC 81. In addition, it has a built-in level shift circuit that shifts the level of external data. It also has a built-in inspection circuit.

Since the buffer capacity of the shift register circuit 61 is small, the gate signal line 17 cannot be directly driven. Therefore, at least two or more inverter circuits 62 are formed between the output of the shift register circuit 61 and the output gate 63 that drives the gate signal line 17.

The same applies to the case where the source driver 14 is directly formed on the substrate 71 by a polysilicon technique such as low temperature polysilicon, and the gate of an analog switch such as a transfer gate for driving the source signal line 18 and the shift register of the source driver circuit 14 are formed. A plurality of inverter circuits are formed between them. The following items (the output of the shift register and the output stage that drives the signal line (the items related to the inverter circuit placed between the output stages such as the output gate or the transfer gate) are common to the source drive and gate drive circuits. is there.

For example, in FIG. 6, the output of the source driver 14 is shown as being directly connected to the source signal line 18, but in reality, the output of the shift register of the source driver is connected to a multistage inverter circuit. The output of the inverter is connected to the gate of an analog switch such as a transfer gate.

The inverter circuit 62 is a P-channel MO
It is composed of an S-transistor and an N-channel MOS transistor. As described above, the inverter circuit 62 is connected to the output end of the shift register circuit 61 of the gate driver circuit 12 in multiple stages, and the final output thereof is connected to the output gate circuit 63. The inverter circuit 62 may be composed of only P channels. However, in this case, it may be configured as a simple gate circuit instead of the inverter.

FIG. 8 is a configuration diagram of signal and voltage supply of the display device of the present invention or a configuration diagram of the display device. Signals (power supply wiring, data wiring, etc.) supplied from the control and roll IC 81 to the source driver circuit 14a are supplied via the flexible substrate 84.

In FIG. 8, the control signal of the gate driver 12 is generated by the control IC, the source driver 14 once level shifts it, and then the gate driver 12 is controlled.
Is being applied to. The drive voltage of the source driver 14 is 4 to
Since it is 8 (V), the gate driver 1 outputs the control signal of 3.3 (V) amplitude output from the control IC 81.
It can be converted to a 5 (V) amplitude that 2 can receive.

It is preferable that the source driver 14 has an image memory. The image data in the image memory may be data after the error diffusion process or the dither process. By performing error diffusion processing, dither processing, etc., the 260,000-color display data can be converted into 4096 colors and the like, and the capacity of the image memory can be reduced. The error diffusion processing can be performed by the error diffusion controller 81. Further, the error diffusion process may be further performed after the dither process is performed. The above items also apply to the inverse error diffusion processing.

Although reference numeral 14 is shown as a source driver in FIG. 8 and the like, not only a driver but also a power supply circuit, a buffer circuit (including a circuit such as a shift register), a data conversion circuit, a latch circuit, a command decoder, and a shift circuit. A circuit, an address conversion circuit, an image memory, etc. may be incorporated. It is needless to say that the configuration described with reference to FIG. 8 and the like can also be applied to the three-side free configuration or the configuration and drive method described with reference to FIG.

When the display panel is used for an information display device such as a mobile phone, the source driver IC (circuit) 14 and the gate driver Ic (circuit) 12 are mounted (formed) on one side of the display panel as shown in FIG. It is preferable that the driver IC (circuit) is mounted (formed) on one side in this way is called a three-side free configuration (structure). Conventionally, the gate driver IC 12 is mounted on the X side of the display area. , The source driver IC 14 was mounted on the Y side). This is because it is easy to design so that the center line of the screen 50 becomes the center of the display device, and it is easy to mount the driver IC. It should be noted that the gate driver circuit may be manufactured by a high-temperature polysilicon technique or a low-temperature polysilicon technique in a three-side free configuration (that is, at least one of the source driver circuit 14 and the gate driver circuit 12 in FIG. 9 is polysilicon). Formed directly on the substrate 71 by a technique).

The three-side free structure is not limited to the structure in which the ICs are directly mounted or formed on the substrate 71, but also the film (TCP, TCP) to which the source driver IC (circuit) 14 and the gate driver IC (circuit) 12 are attached. A configuration in which TAB technology or the like is attached to one side (or almost one side) of the substrate 71 is also included. That is, it means a configuration, an arrangement or the like in which ICs are not mounted or attached on two sides.

When the gate driver circuit 12 is arranged beside the source driver circuit 14 as shown in FIG. 9, the gate signal line 17 needs to be formed along the side C and up to the screen display area 50.

The thick solid line in FIG. 9 and the like indicates the portion where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of scanning signal lines are formed in parallel in the portion b (the lower portion of the screen),
One gate signal line 17 is formed in the portion a (upper part of the screen).

The pitch of the gate signal lines 17 formed on the C side is set to 5 μm or more and 12 μm or less. When the thickness is less than 5 μm, noise is added to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the effect of the parasitic capacitance remarkably occurs at 7 μm or less. Further, if it is less than 5 μm, image noise such as beats is intensely generated on the display screen. In particular, the generation of noise differs between the left and right of the screen, and it is difficult to reduce this image noise such as beats. Further, when the reduction exceeds 12 μm, the frame width D of the display panel becomes too large, which is not practical.

In order to reduce the above-mentioned image noise, in the lower layer or the upper layer where the gate signal line 17 is formed,
This can be reduced by arranging a grant pattern (a conductive pattern in which the voltage is fixed to a constant voltage or is set to a stable potential as a whole). Further, a separately provided shield plate (shield foil (conducting pattern in which voltage is fixed to a constant voltage or set to a stable potential as a whole)) may be arranged on the gate signal line 17.

The gate signal line 17 on the C side in FIG. 9 may be formed of an ITO electrode, but it is preferable to form it by laminating ITO and a metal thin film in order to reduce the resistance. In addition, it is preferable to form a metal film. In the case of stacking with ITO, a titanium film is formed on ITO, and aluminum or an aluminum-molybdenum alloy thin film is formed thereon. Alternatively, a chrome film is formed on ITO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film.
The above matters also apply to other embodiments of the present invention.

In FIG. 9 and the like, the gate signal line 1
Although 7 and the like are arranged on one side of the display area, the invention is not limited to this and may be arranged on both sides. For example,
The gate signal line 17a may be arranged (formed) on the right side of the display region 50, and the gate signal line 17b may be arranged (formed) on the left side of the display region 50. The above matters are the same in other embodiments.

Further, the source driver IC 14 and the gate driver IC 12 may be integrated into one chip. If integrated into one chip, only one IC chip needs to be mounted on the display panel. Therefore, the mounting cost can be reduced. Further, various voltages used in the one-chip driver IC can be generated at the same time.

The source driver IC 14 and the gate driver IC 12 are made of a semiconductor wafer such as silicon and are mounted on the display panel. However, the present invention is not limited to this, and the display panel 82 is manufactured by the low temperature polysilicon technology or the high temperature polysilicon technology. It goes without saying that it may be formed directly on the.

In the configuration shown in FIG. 1 etc., the EL element 15
Is connected to the Vdd potential via the transistor 11a. However, there is a problem in that the driving voltage of the organic EL that constitutes each color is different. For example, when a current of 0.01 (A) per square centimeter is applied, the terminal voltage of the EL element is 5 (V) in blue (B), but is 9 (V) in green (G) and red (R). ). That is, the terminal voltage differs between B, G, and R. Therefore, B, G, R
, The source-drain voltage (SD voltage) of the held transistor 11a is different. Therefore, the off-leakage current between the source-drain voltage (SD voltage) of the transistor is different for each color. When an off-leakage current is generated and the off-leakage characteristics are different for each color, flicker occurs in a state where the color balance is deviated, and the gamma characteristic shifts in correlation with the emission color, resulting in a complicated display state.

In order to meet this problem, at least R,
Among the G and B colors, the potential of one cathode electrode is different from the potential of the cathode electrodes of the other colors. Alternatively, one of the R, G, and B colors is configured so that the potential of one Vdd is different from the potential of the Vdd of another color.

It goes without saying that it is preferable to make the terminal voltages of the R, G, and B EL elements 15 coincide with each other as much as possible. At least the white peak brightness is displayed and the color temperature is 60
EL of R, G, B in the range from 00K to 9000K
It is necessary to select the material or structure so that the terminal voltage of the device is 10 (V) or less. Further, among R, G, and B, the difference between the maximum terminal voltage and the minimum terminal voltage of the EL element needs to be within 2.5 (V). More preferably, it should be 1.5 (V) or less. Although the colors are RGB in the above embodiments, the colors are not limited to these. This will be explained later.

It is also necessary to correct color unevenness. This is caused by variations in film thickness and characteristics because EL materials of different colors are applied separately. In order to correct this, white raster display is performed at a luminance of 30% or 70%, and the in-plane distribution of each color in the display area 50 is measured. The in-plane distribution is measured at least every 30 pixels. The measurement data is stored in a table including a memory, and the stored data is used to correct the input image data and display it on the display screen 50.

Although the pixel has three primary colors of R, G, and B, it is not limited to this, and three colors of cyan, yellow, and magenta may be used. Also, two colors of B and yellow may be used. Of course, it may be a single color. Further, six colors of R, G, B, cyan, yellow and magenta may be used. R, G,
Five colors of B, cyan and magenta may be used. These are natural colors with a wide color reproduction range and good display. In addition, four colors of R, G, B, and white may be used. R,
Seven colors of G, B, cyan, yellow, magenta, black, and white may be used. Alternatively, white emission pixels may be formed (produced) in the entire display region 50, and three primary colors may be displayed by a color filter such as RGB. In this case, light emitting materials of respective colors may be stacked on the EL layer. Alternatively, one pixel may be painted separately such as B and yellow. As described above, the E of the present invention
The L display device is not limited to one that performs color display with the three primary colors of RGB.

There are mainly three methods for colorizing the organic EL display panel, and the color conversion method is one of them.
It is only necessary to form a single layer of blue as the light emitting layer, and the remaining green and red required for full colorization are created by color conversion from blue light. Therefore, there are advantages that it is not necessary to separately paint each layer of RGB, and it is not necessary to prepare organic EL materials of each color of RGB. The color conversion method does not reduce the yield unlike the color-coding method. The EL display panel and the like of the present invention can be applied in any of these systems.

In addition to the three primary colors, white light emitting pixels may be formed. A white light emitting pixel can be realized by manufacturing (forming or configuring) by stacking R, G, and B light emitting structures. One set of pixels has three primary colors of RGB,
It is composed of white light emitting pixels 16W. By forming the pixels that emit white light, the white peak luminance can be easily expressed. Therefore, it is possible to realize a bright image display.

Even when one set of three primary colors such as RGB is used, it is preferable that the area of the pixel electrode for each color be different as shown in FIG. Of course, the same area may be used as long as the luminous efficiency of each color is well balanced and the color purity is well balanced. However, if the balance of one or more colors is poor, it is preferable to adjust the pixel electrode (light emitting area). The electrode area for each color may be determined based on the current density. In other words, the color temperature is 6000K
When the white balance is adjusted in the range of (Kelvin) or more and 9000K or less, the difference between the current densities of the respective colors should be within ± 30%. It is more preferably within ± 15%. For example, if the current density is 100 A / square meter, all three primary colors should be 70 A / square meter or more and 130 A / square meter or less. More preferably, all three primary colors are set to 85 A / square meter or more and 115 A / square meter or less.

Further, it is preferable that adjacent pixel rows are arranged such that the arrangement of the three primary colors is different. For example, if the even-numbered row has the arrangement of R, G, and B from the left, the odd-numbered row has the arrangement of B, G, and R. By arranging in this way, the resolution in the diagonal direction of the image is improved even with a small number of pixels. Furthermore, the first line from the left is R, G, B, R, G,
B arrangement, 3 rows or more so that the second row is G, B, R, G, B, R arrangement and the third row is B, R, G, B, R, G arrangement. Therefore, the pixel arrangement may be different.
Of course, the R, G, and B pixel arrangements or the color arrangements such as cyan, yellow, and magenta are delta arrangements (1/2
It goes without saying that the arrangement may be such that the pixels are shifted.

The organic EL 15 is a self-luminous element. When the light generated by this light emission enters a transistor as a switching element, a photoconductor phenomenon occurs. The photocon refers to a phenomenon in which a leak (off leak) when a switching element such as a transistor is turned off is increased by photoexcitation.

In order to cope with this problem, in the present invention, the gate driver 12 (source driver 14 in some cases) is used.
The lower layer and the lower layer of the pixel transistor 11 form a light-shielding film. The light-shielding film is formed of a metal thin film such as chromium and has a film thickness of 50 nm or more and 150 nm or less. If the film thickness is thin, the light-shielding effect is poor, and if it is thick, irregularities occur and patterning of the upper transistor 11A1 becomes difficult.

A smoothing film made of an inorganic material having a thickness of 20 to 100 nm is formed on the light shielding film. One of the electrodes of the storage capacitor 19 may be formed using the layer of the light shielding film. In this case, it is preferable to make the smoothing film as thin as possible to increase the capacitance value of the storage capacitor. Alternatively, the light-shielding film may be formed of aluminum, a silicon oxide film may be formed on the surface of the light-shielding film by using an anodic oxidation technique, and this silicon oxide film may be used as the dielectric film of the storage capacitor 19. A pixel electrode having a high aperture (HA) structure is formed on the smoothing film.

The driver circuit 12 and the like should prevent light from entering not only from the back surface but also from the front surface. This is because a malfunction occurs due to the influence of photo control. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the driver 12 or the like, and this electrode is used as a light shielding film.

However, if the cathode electrode is formed on the driver 12, there is a possibility that the electric field from the cathode electrode may cause the driver to malfunction or the cathode electrode and the driver circuit to make electrical contact. In order to solve this problem, in the present invention, at least one layer, preferably a plurality of layers of organic EL films are formed on the driver circuit 12 and the like at the same time when the organic EL films are formed on the pixel electrodes.

Since the organic EL film is basically an insulator,
By forming the organic EL film on the driver, the cathode and the driver are isolated from each other. Therefore, the above-mentioned problem can be solved.

When the terminals of one or more transistors 11 of the pixel or the transistor 11 and the signal line are short-circuited,
The EL element 15 may be a bright spot that is always lit.
Since these bright spots are visually unnoticeable, it is necessary to turn them into black dots (not lit). For the bright spot, the corresponding pixel 16 is detected, and the condenser 19 is irradiated with laser light to short-circuit the terminals of the condenser. Therefore, the electric charge cannot be retained in the capacitor 19, so that the transistor 11a can stop the flow of current.

It should be noted that it corresponds to the position where the laser beam is emitted. It is desirable to remove the cathode film. This is to prevent a short circuit between the terminal electrode of the capacitor 19 and the cathode film due to laser irradiation.

The defect of the transistor 11 of the pixel 16 affects the driver IC 14 and the like. For example, in FIG.
In FIG. 8, the source-drain (S
D) When the short circuit 582 occurs, Vdd of the panel
The voltage is applied to the source driver IC 14. Therefore, it is preferable that the power supply voltage of the source driver IC 14 is equal to or higher than the power supply voltage Vdd of the panel. It is preferable that the reference current used in the source driver IC can be adjusted by the electronic volume 581.

SD short 582 to transistor 11a
Occurs, an excessive current flows through the EL element 15. That is, the EL element 15 is always in a lighting state (bright spot). Bright spots are easily noticeable as defects. For example, FIG.
, The source-drain (S
D) When a short circuit occurs, current always flows from the Vdd voltage to the EL element 15 regardless of the gate (G) terminal potential of the transistor 11a (transistor 11a).
d is on). Therefore, it becomes a bright spot.

On the other hand, if the SD short circuit occurs in the transistor 11a, the Vdd voltage is applied to the source signal line 18 and the Vdd voltage is applied to the source driver 14 when the transistor 11c is in the ON state. If the power supply voltage of the source driver 14 is Vdd or lower, the withstand voltage may be exceeded and the source driver 14 may be destroyed. Therefore, it is preferable that the power supply voltage of the source driver 14 be equal to or higher than the Vdd voltage (the higher voltage of the panel).

The SD short-circuit of the transistor 11a is not limited to point defects, and may damage the source driver circuit of the panel, and the bright spots are conspicuous, resulting in a defective panel. Therefore, it is necessary to disconnect the wiring connecting the transistor 11a and the EL element 15 in FIG. 58 to make the bright spot a black spot defect. This disconnection
It is preferable to cut using an optical means such as laser light. The optical means is not limited to the laser, and may be a method of condensing light generated from a xenon lamp or the like and cutting the wiring with the condensed light. Further, a method of cutting (cutting by spraying fine particle sand) on the cut portion by a sandblast method may be adopted. That is,
Any cutting means may be used. However, a method using an optical means such as a laser is preferable because it allows the cut portion to be processed without contact.

It is preferable to use pulsed laser light using a Q switch, rather than continuous laser light. In addition, a plurality of laser pulses are applied to the cut portion. The laser pulse interval is preferably 0.1 msec or more and 100 msec or less. Particularly, it is preferably set to 1 msec or more and 10 msec or less. This is because at this interval, the melted state of the processed portion due to the previously irradiated laser light continues, and good cutting or processing can be performed. The wavelength of the laser light is preferably around 1 μm. A YAG laser is illustrated as a laser of this wavelength. Of course, other lasers may be used. For example, a carbon dioxide gas laser, an excimer laser, a neon helium laser, etc. are exemplified.

In the above embodiment, the wiring is cut, but it is not limited to this for displaying black. For example, as can be seen from FIG. 1, the power supply Vdd of the transistor 11a may be modified so that it is always applied to the gate (G) terminal of the transistor 11a. For example, if the two electrodes of the capacitor 19 are short-circuited, the Vdd voltage will be the gate (G) of the transistor 11a.
It will be applied to the terminals. Therefore, the transistor 11a is completely turned off, and the EL element 15 can be prevented from passing a current. This is the condenser 19
Since the capacitor electrodes can be short-circuited by irradiating the laser beam on the, it can be easily realized. In addition, in reality, since the Vdd wiring is arranged under the pixel electrode, the display state of the pixel can be controlled (corrected) by irradiating the Vdd wiring and the pixel electrode with laser light.

Alternatively, it can be realized by opening the SD (channel) of the transistor 11a. Simply, the transistor 11a is irradiated with laser light to open the channel of the transistor 11a. Similarly,
The channel of the transistor 11d may be opened. Of course, even if the channel of the transistor 11b is opened, the corresponding pixel 16 is not selected, so that black display is performed.

In order to display the pixel 16 in black, the EL element 15 may be deteriorated. For example, the laser light is EL
The layer 15 is irradiated to physically or chemically deteriorate the EL layer 15 so that it does not emit light (always black display). The EL layer 15 can be heated and easily deteriorated by irradiation with laser light. Further, if an excimer laser is used, the EL film 15 can be easily chemically changed.

Although the above embodiment has illustrated the pixel configuration shown in FIG. 1, the present invention is not limited to this. It is needless to say that opening or short-circuiting a wiring or an electrode using laser light can be applied to other current-driven pixel configurations such as a current mirror or voltage-driven pixel configurations illustrated in FIGS. 62 and 51. Yes.

When the cathode (or anode) electrode is a transparent electrode, the pixel electrode is of a reflection type and the common electrode is a transparent electrode (ITO, IZO, etc.). Bottom take-out, E
In the case of taking out light from the L film deposition surface), the sheet resistance value of the transparent electrode becomes a problem. Although the transparent electrode has a high resistance, it is necessary to pass a current with a high current density to the cathode of the organic EL. Therefore, if the cathode electrode is formed of a single layer of the ITO film, heat is generated due to heat generation, or an extreme brightness gradient occurs on the display screen.

To meet this problem, a low resistance wiring made of a metal thin film may be formed on the surface of the cathode electrode. The low resistance wiring has the same structure as the black matrix (BM) of the liquid crystal display panel (film thickness of 50 nm to 200 nm made of chrome or aluminum material) and at the same position (between the pixel electrodes, on the driver 12, etc.). . But,
In the organic EL, it is not necessary to form the BM, so the function is completely different. The low resistance wiring is not limited to the front surface of the transparent electrode, but may be formed on the back surface (the surface in contact with the organic EL film). In addition, as a metal film formed in a BM shape, M
Alloys such as g.Ag, Mg.Li, and Al.Li or laminated structures such as aluminum, magnesium, indium, copper, or alloys thereof may be used. In addition, B
To prevent corrosion on M, ITO, IZ
An O film is laminated, and an inorganic thin film such as SiNx or SiO 2 or an organic thin film such as polyimide is formed.

When light is to be extracted from the vapor deposition surface of the EL film (upper extraction), Mg-on the organic EL film 15 is to be used.
It is preferable to form an Al film and then form an ITO or IZO film thereon. In addition, Mg-Al on the organic EL film 15
It is preferable to form a film and form a black matrix (black matrix such as a liquid crystal display panel) on the film. This black matrix is chrome, A
l, Ag, Au, Cu, etc., and SiO
₂ , it is preferable to form a protective film made of an inorganic insulating film such as SiN _x or an organic insulating film such as polyester or acrylic. Further, an antireflection film (AIR coat) is formed on this protective film.

The AIR coat has a three-layer structure or a two-layer structure. Aluminum oxide (Al ₂
O ₃ ) has an optical film thickness of nd = λ / 4, zirconium (Z
rO ₂ nd1 = λ / 2, magnesium fluoride (Mg
F ₂ ) is formed by stacking nd1 = λ / 4. Usually, a thin film is formed with λ of 520 nm or a value in the vicinity thereof.

In the case of a two-layer structure, silicon monoxide (Si
O) is an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF ₂ ) is nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride (MgF ₂ ) are n.
d1 = λ / 4 stacked layers are formed.

In the case of one layer, magnesium fluoride (Mg
F ₂ ) is formed by stacking nd1 = λ / 2.

Even in the case of the bottom extraction, it is effective to increase the transmittance of the metal film of the cathode electrode 106. This is because even if the display image is viewed from the substrate 71 side, the reflection is reduced because the transmittance of the metal film is high. Circularly polarizing plate (phase plate) if the reflection is reduced
108 is unnecessary. Therefore, the light extraction efficiency may be improved as compared with the upper extraction. The transmittance of the metal film is preferably 60% or more and 90% or less. In particular, it is preferably 70% or more and 90% or less. If it is 60% or less, the sheet resistance value of the cathode electrode becomes low. However, the reflection becomes large. On the contrary, when it is 90% or more, the sheet resistance value of the cathode electrode becomes high. Therefore, the brightness gradient of the display image becomes large.

To increase the transmittance of the metal film, the Al film is formed thin. The thickness is 20 nm or more and 100 nm or less. It is preferable to form an ITO or IZO film on it. Further, it is preferable to form a black matrix on the Al film. This black matrix is made of chromium, Al, Ag, Au, Cu, etc., and on top of this,
It is preferable to form a protective film made of an inorganic insulating film such as SiO ₂ or SiN _x , or an organic insulating film such as polyester or acrylic. Furthermore, an antireflection film (A
It is preferable to form an IR coat).

Incidentally, the EL film 15 or the pixel electrode 105.
Is not limited to a circular arc shape, but may be a triangular pyramid shape, a conical shape, a sine curve shape, or a structure in which these are combined. Further, one pixel may have a fine arc shape, a triangular pyramid shape, a conical shape, a sine curve shape, a combination thereof, or a structure in which random unevenness is formed.

The semiconductor film forming the transistor 11 of the pixel 16 is generally formed by laser annealing in the low temperature polysilicon technique. The variation in the conditions of this laser annealing causes the variation in the characteristics of the transistor 11. However, the transistor 1 in one pixel 16
If the characteristics of 1 are the same, the current programming method shown in FIG. 1 or the like can drive the EL element 15 so that a predetermined current flows. This is an advantage over voltage programming. An excimer laser is preferably used as the laser.

In the present invention, the formation of the semiconductor film is not limited to the laser annealing method, but may be a thermal annealing method or a solid phase (CGS) growth method. Besides, it is needless to say that the high temperature polysilicon technique is not limited to the low temperature polysilicon technique.

To solve this problem, in the present invention, as shown in FIG. 7, a laser irradiation spot (laser irradiation range) 72 at the time of annealing is irradiated in parallel to the source signal line 18. Further, the laser irradiation spot 72 is moved so as to coincide with one pixel column. Of course, the number of pixels is not limited to one pixel row, and for example, RGB of FIG.
You may irradiate the laser in units of (in this case,
It means 3 pixel columns). Further, a plurality of pixels may be simultaneously irradiated. Needless to say, the movements of the laser irradiation areas may overlap (usually, the movement areas of the moving laser light generally overlap).

The pixel is made up of three RGB pixels and has a square shape. Therefore, each of the R, G, and B pixels has a vertically long pixel shape. Therefore, by making the laser irradiation spot 72 vertically long and annealing it,
It is possible to prevent characteristic variations of the transistor 11 from occurring within one pixel. Further, the characteristics (mobility, Vt, S value, etc.) of the transistors 11 connected to one source signal line 18 can be made uniform (that is, when the characteristics are different from those of the transistors 11 of the adjacent source signal lines 18). However, the characteristics of the transistor 11 connected to one source signal line can be made almost equal).

Generally, the length of the laser irradiation spot 72 is a fixed value such as 10 inches. Since this laser irradiation spot 72 is moved, it is necessary to arrange the panel so that one laser irradiation spot 72 is placed within the movable range (that is, the laser irradiation spot 72 is located at the center of the display area 50 of the panel). Do not overlap).

In the configuration of FIG. 7, the laser irradiation spot 7
The three panels are formed to be vertically arranged within the range of the length of 2. The annealing device for irradiating the laser irradiation spot 72 is a positioning marker 7 on the glass substrate 74.
The laser irradiation spot 72 is moved by recognizing 3a and 73b (automatic positioning by pattern recognition). The recognition of the positioning marker 73 is performed by a pattern recognition device. An anneal device (not shown) recognizes the positioning marker 73 and finds the position of the pixel column (so that the laser irradiation range 72 is parallel to the source signal line 18). The laser irradiation spot 72 is irradiated so as to overlap the pixel row position, and annealing is sequentially performed.

The laser annealing method (method of irradiating a linear laser spot parallel to the source signal line 18) described with reference to FIG. 7 is preferably adopted especially in the current programming method of the organic EL display panel. This is because the characteristics of the transistor 11 match in the direction parallel to the source signal line (the characteristics of pixel transistors adjacent in the vertical direction are similar). Therefore, the change in the voltage level of the source signal line is small during current driving, and insufficient current writing is less likely to occur.

For example, in the case of white raster display, since the currents flowing through the transistors 11a of adjacent pixels are almost the same, the change in current amplitude output from the source driver IC 14 is small. If the characteristics of the transistor 11a in FIG. 1 are the same and the current value for current programming in each pixel is the same in the pixel column, the potential of the source signal line 18 during current programming is constant. Therefore, the potential fluctuation of the source signal line 18 does not occur. If the characteristics of the transistors 11a connected to one source signal line 18 are almost the same, the potential fluctuation of the source signal line 18 is small. This is the same in other current programming pixel configurations such as FIG. 38 (that is, it is preferable to apply the manufacturing method in FIG. 7).

Further, it is possible to realize uniform image display (because display unevenness is not likely to occur mainly due to variations in transistor characteristics) by the method of simultaneously writing a plurality of pixel rows described with reference to FIGS. 27 and 30. . Since a plurality of pixel rows are selected at the same time in FIG. 27 and the like, the driver circuit 14 can absorb the transistor characteristic unevenness in the vertical direction if the transistors in the adjacent pixel rows are uniform.

In FIG. 7, the source driver circuit 14
Although the IC chip is illustrated as being stacked, it is not limited to this, and it goes without saying that the source driver circuit 14 may be formed in the same process as the pixel 16.

The driving method of the pixel configuration shown in FIG. 1 will be described below. As shown in FIG. 1, the gate signal line 17a becomes conductive during the row selection period (because the transistor 11 of FIG. 1 is a p-channel transistor here, it becomes conductive at a low level), and the gate signal line 17b becomes non-selection period. Sometimes it becomes conductive.

The source signal line 18 has a parasitic capacitance (not shown). The parasitic capacitance is the capacitance of the cross portion between the source signal line 18 and the gate signal line 17, the transistor 11
It is caused by the channel capacity of b and 11c.

The time t required for changing the current value of the source signal line 18 is t = C · V, where C is the size of the stray capacitance, V is the voltage of the source signal line, and I is the current flowing through the source signal line.
Since / I, the current value can be increased ten times, and the time required to change the current value can be shortened to nearly one tenth.
Alternatively, it indicates that the current value can be changed to a predetermined current value even if the source capacitance is increased 10 times. Therefore, it is effective to increase the current value in order to write a predetermined current value within a short horizontal scanning period.

If the input current is multiplied by 10, the output current is also increased by 10.
Since the brightness of EL becomes 10 times, the conductive period of the transistor 17d in FIG. 1 is set to 1/10 and the light emission period is set to 1/10 of the conventional one in order to obtain a predetermined brightness. Displayed the brightness.

That is, in order to sufficiently charge and discharge the parasitic capacitance of the source signal line 18 and program a predetermined current value in the transistor 11a of the pixel 16, it is necessary to output a relatively large current from the source driver 14. There is. However, when such a large current is supplied to the source signal line 18, this current value is programmed in the pixel, and a large current flows to the EL element 15 with respect to a predetermined current. For example, if programming is performed with a current of 10 times, naturally, a current of 10 times flows into the EL element 15, and the EL element 15 emits light with a brightness of 10 times. In order to obtain a predetermined light emission brightness, the time for flowing through the EL element 15 may be set to 1/10. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.

A ten-fold current value is written in the pixel transistor 11a (more precisely, the terminal voltage of the capacitor 19 is set), and the ON time of the EL element 15 is 1/1.
It is set to 0, but this is an example. In some cases,
A ten times larger current value may be written in the pixel transistor 11a, and the ON time of the EL element 15 may be reduced to ⅕. On the contrary, there may be a case where a 10-fold current value is written in the pixel transistor 11a to halve the ON time of the EL element 15.

The present invention is characterized in that the write current to the pixel is set to a value other than the predetermined value and the current flowing in the EL element 15 is driven in an intermittent state. In this specification, in order to facilitate the description, a current value N times larger than that of the pixel transistor 11 is used.
, And the ON time of the EL element 15 is multiplied by 1 / N. However, the present invention is not limited to this, and the current value of N1 times is written in the transistor 11 of the pixel, and the ON time of the EL element 15 is 1 / N2 times (N1 and N2 times).
Needless to say, it may be different). The intermittent intervals are not limited to equal intervals. For example, it may be random (as a whole, the display period or the non-display period has a predetermined value (constant rate)). Further, it may be different for RGB. That is, the R, G, and B display periods or the non-display period may be adjusted (set) to a predetermined value (constant ratio) so that the white balance is optimized. For,
It is assumed that 1 / N is based on 1F (1 field or 1 frame) and 1F is set to 1 / N. However, there is a time (usually one horizontal scanning period (1H)) when one pixel row is selected and a current value is programmed, and
An error may occur depending on the scanning state. Therefore, the above description is merely a matter of convenience for facilitating the description, and the present invention is not limited to this.

The organic (inorganic) EL display device also has a problem in that the display method is basically different from that of a display that displays an image as a group of line displays with an electron gun, such as a CRT. That is, the EL display device holds the current (voltage) written in the pixel for a period of 1F (one field or one frame). Therefore, when a moving image is displayed, the problem occurs that the outline of the displayed image is blurred.

In the present invention, E only during the period of 1 F / N
A current is passed through the L element 15 for another period (1F (N-1) /
N) does not carry current. Consider the case where this driving method is implemented and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is, the image data display state becomes a temporally intermittent display (intermittent display) state. When the moving image data display is viewed in this intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, it is possible to realize moving image display close to that of a CRT. Although the intermittent display is realized, the main clock of the circuit is the same as the conventional one. Therefore, the power consumption of the circuit does not increase.

In the case of a liquid crystal display panel, image data (voltage) for light modulation is held in the liquid crystal layer. Therefore,
In order to perform black insertion display, it is necessary to rewrite the data applied to the liquid crystal layer. Therefore, it is necessary to increase the operation clock of the source driver IC 14 and apply the image data and the black display data to the source signal line 18 alternately. Therefore, black insertion (intermittent display such as black display)
In order to realize, it is necessary to raise the main clock of the circuit. Also, an image memory for performing the time axis expansion is required.

E of the present invention shown in FIGS. 1, 2, 38, etc.
In the pixel configuration of the L display panel, the image data is held in the capacitor 19. A current corresponding to the terminal voltage of the capacitor 19 is passed through the EL element 15. Therefore, the image data is not held in the light modulation layer like the liquid crystal display panel.

The present invention is a switching transistor 11
The current flowing through the EL element 15 is controlled only by turning on or off the transistor d or the transistor 11e. That is, E
Even if the current Iw flowing through the L element 15 is turned off, the image data is still held in the capacitor 19. Therefore, when the switching element 11d and the like are turned on at the next timing and a current is passed through the EL element 15, the current flowing is the same as the current value that was flowing before. In the present invention, when black insertion (intermittent display such as black display) is to be realized, it is not necessary to raise the main clock of the circuit. Moreover, an image memory is not necessary because it is not necessary to perform time-axis expansion. In addition, the organic EL element 15 has a short time from applying a current to emitting light and has a high-speed response. Therefore, it is suitable for displaying moving images, and by implementing intermittent display, it is possible to solve the problem of displaying moving images, which is a problem of conventional data-retention display panels (such as liquid crystal display panels and EL display panels).

Further, in the case of a large display device having a large source capacitance, the source current may be increased by a factor of 10 or more. Generally, when the source current value is multiplied by N, the conduction period of the gate signal line 17b (transistor 11d) is set to 1 F / N.
And it is sufficient. As a result, it can be applied to display devices for televisions and monitors.

Hereinafter, the driving method of the present invention will be described in more detail with reference to the drawings. Source signal line 1
The parasitic capacitance of 8 is generated by the coupling capacitance between the adjacent source signal lines 18, the buffer output capacitance of the source drive IC (circuit) 14, the cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This parasitic capacitance is usually 10 pF or more. In the case of voltage driving, since a voltage is applied from the driver IC 14 to the source signal line 18 with low impedance, there is no problem in driving even if the parasitic capacitance is somewhat large.

However, in the current driving, particularly in the image display of the black level, the pixel capacitor 19 is supplied with a minute current of 5 nA or less.
Need to be programmed. Therefore, when the parasitic capacitance is generated with a magnitude equal to or larger than a predetermined value, the programming time for one pixel row (usually within 1H, but two pixel rows may be written at the same time is not limited to within 1H). It is not possible to charge and discharge the parasitic capacitance inside the parentheses.
If charging / discharging cannot be performed in the 1H period, writing into the pixel becomes insufficient, resulting in poor resolution.

In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing through Iw is retained. At this time, the transistor 11d is in an open state (off state).

Next, during a period in which a current is passed through the EL element 15, as shown in FIG. 3B, the transistors 11c and 11b are turned off and the transistor 11d operates. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, the gate signal line 1
The on-voltage (Vgl) is applied to 7b, and the transistor 1
1d turns on.

Now, assuming that the current I1 is N times the current (predetermined value) originally flowing, the current flowing through the EL element 15 in FIG. 3B is also Iw. Therefore, the EL element 15 emits light with a brightness 10 times the predetermined value. That is, as shown in FIG. 12, the higher the magnification N, the higher the display brightness B of the display panel. Therefore, the magnification and the luminance have a proportional relationship. On the contrary, by driving with 1 / N, the luminance and the magnification have an inversely proportional relationship.

Therefore, if the transistor 11d is turned on for a period of 1 / N of the time it is originally turned on (about 1F) and turned off for the other period (N-1) / N periods, the average luminance of the entire 1F is predetermined. It becomes the brightness of. This display state is similar to that of a CRT scanning the screen with an electron gun. The difference is that
The range where the image is displayed is the point where 1 / N of the entire screen is illuminated (the entire screen is 1) (In the CRT, the illuminated range is 1 pixel row (strictly 1 pixel is is there).

In the present invention, the 1F / N image display area 53 moves from the top to the bottom of the screen 50 as shown in FIG. 13B. In the present invention, the EL is used only for the period of 1F / N.
A current flows through the element 15 and the other period (1F · (N−1) /
N) does not carry current. Therefore, each pixel is displayed intermittently. However, since the image is held by the afterimage in human eyes, the entire screen appears to be displayed uniformly.

As shown in FIG. 13, the writing pixel row 51a is the non-illuminated display 52a. However, this is the case with the pixel configurations shown in FIGS. In the pixel configuration of the current mirror illustrated in FIG. 38 and the like, the writing pixel row 51a may be in a lighting state. However, in this specification, in order to facilitate the description, the pixel configuration of FIG. 1 is mainly illustrated and described. Also, programming with a current larger than the predetermined drive current Iw shown in FIGS. 13 and 16,
The driving method of intermittent driving is called N times pulse driving.

In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is,
The image data display state becomes a temporally intermittent display (intermittent display) state. In the liquid crystal display panel (EL display panel other than the present invention), data is held in the pixel for the period of 1F, and therefore, in the case of moving image display, even if the image data changes, the change cannot be followed, The image was blurred (outlined image). However, in the present invention, since the image is displayed intermittently, the outline of the image is not blurred and a good display state can be realized. That is, it is possible to realize moving image display close to that of a CRT.

This timing chart is shown in FIG. Note that, in the present invention and the like, the pixel configuration is as shown in FIG. 1 unless otherwise specified. As can be seen from FIG. 14, in each selected pixel row (the selection period is set to 1H), when the ON voltage (Vgl) is applied to the gate signal line 17a (see FIG. 14A). The OFF voltage (Vgh) is applied to the gate signal line 17b (see FIG. 14B). Also, during this period, the EL element 15
Current is not flowing through (non-lighting state). In the unselected pixel rows, the off voltage (Vgh) is applied to the gate signal line 17a, and the on voltage (Vgl) is applied to the gate signal line 17b. Also, during this period,
A current is flowing through the L element 15 (lighting state). Further, in the lighted state, the EL element 15 has a predetermined N-fold luminance (N ·
It is lit in B), and its lighting period is 1 F / N. Therefore, the display brightness of the display panel obtained by averaging 1F is (N.
B) × (1 / N) = B (predetermined brightness).

FIG. 15 shows an embodiment in which the operation of FIG. 14 is applied to each pixel row. The waveform of the voltage applied to the gate signal line 17 is shown. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level).
Subscripts such as (1) and (2) indicate the selected pixel row number.

In FIG. 15, gate signal line 17a
(1) is selected (Vgl voltage), and the program current flows from the transistor 11a of the selected pixel row toward the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for ease of explanation, N
= 10 will be described. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Therefore, the capacitor 19 is programmed so that 10 times as much current flows through the transistor 11a. When the pixel row (1) is selected, the gate signal line 17b is used in the pixel configuration of FIG.
In (1), the off voltage (Vgh) is applied, and the EL element 15
No current flows through.

After 1H, the gate signal line 17a (2) is selected (Vgl voltage), and the program current flows from the transistor 11a in the selected pixel row to the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for ease of explanation, N = 10 will be described). Therefore, the capacitor 19 is programmed so that 10 times as much current flows through the transistor 11a. When the pixel row (2) is selected,
In the pixel configuration of FIG. 1, the gate signal line 17b (2) is applied with the off voltage (Vgh), and no current flows through the EL element 15. However, the gate signal line 17a of the previous pixel row (1)
Since the off voltage (Vgh) is applied to (1) and the on voltage (Vgl) is applied to the gate signal line 17b (1), it is in a lighting state.

After the next 1H, the gate signal line 17a
(3) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (3), and the EL element 15 of the pixel row (3) is selected.
No current flows through. However, the previous pixel row (1) (2)
To the gate signal lines 17a (1) (2) of the off voltage (Vg
h) is applied and the on-voltage (Vgl) is applied to the gate signal lines 17b (1) (2), so that the gate signal lines 17b (1) (17) are in a lighting state.

An image is displayed in synchronism with the above operation in synchronization with the 1H synchronization signal. However, in the driving method of FIG.
A 10 times larger current flows through the L element 15. Therefore, the display screen 50 is displayed with a brightness of about 10 times. of course,
It is needless to say that the program current may be set to 1/10 in order to display a predetermined brightness in this state. However, if the current is 1/10, writing shortage will occur due to parasitic capacitance and the like. Therefore, programming with a high current to obtain a predetermined brightness by inserting the black screen 52 is the basic gist of the present invention.

In the driving method of the present invention, the concept is that a current higher than a predetermined current is made to flow in the EL element 15 to sufficiently charge and discharge the parasitic capacitance of the source signal line 18. That is, it is not necessary to pass N times the current through the EL element 15. For example, a current path is formed in parallel with the EL element 15 (a dummy EL element is formed, and this EL element is formed with a light-shielding film so as not to emit light), and the current is divided into the dummy EL element and the EL element 15. You can wash it. For example, when the signal current is 0.2 μA, the program current is 2.2 μA, and the transistor 11a has 2.2 μA.
Shed. Among these currents, a method is exemplified in which a signal current of 0.2 μA is passed through the EL element 15 and 2 μA is passed through a dummy EL element.

With the above configuration, the current flowing through the source signal line 18 is increased N times,
It is possible to program the driving transistor 11a so that N times as much current flows, and the current EL element 15 can be supplied with a current sufficiently smaller than N times. With the above method, as shown in FIG. 5, the entire display area 50 can be used as the image display area 53 without providing the non-lighted area 52.

FIG. 13A shows a writing state in the display image 50. In FIG. 13A, 51a is a writing pixel row. A program current is supplied from the source driver IC 14 to each source signal line 18. Note that, in FIG. 13 and the like, one pixel row is written in the 1H period. However, it is not limited to 1H at all,
The period may be 0.5H or 2H. Further, although the programming current is written in the source signal line 18, the present invention is not limited to the current programming method, and a voltage programming method in which the voltage is written in the source signal line 18 may be used.

In FIG. 13A, the gate signal line 17
When a is selected, the current flowing through the source signal line 18 is programmed in the transistor 11a. At this time, an off voltage is applied to the gate signal line 17b, and no current flows in the EL element 15. This is the transistor 1 on the EL element 15 side.
This is because when 1d is in the on state, the capacitance component of the EL element 15 can be seen from the source signal line 18, and the capacitance 19 affects the capacitance component, which makes it impossible to perform accurate current programming in the capacitor 19. Therefore, taking the configuration of FIG. 1 as an example, the pixel row in which the current is written becomes the non-lighting area 52 as shown in FIG. 13B.

Now, N (here, as described above, N =
If programmed with 10 times the current, the brightness of the screen will be 10 times. Therefore, 9 of the display area 50
The 0% range may be set as the non-lighting area 52. Therefore, if the horizontal scanning lines in the image display area are 220 lines (S = 220) of QCIF, 22 lines and the display region 53 are obtained.
220-22 = 198 may be used as the non-display area 52. Generally speaking, if the horizontal scanning line (the number of pixel rows) is S, the S / N area is the display area 53, and the display area 53 is made to emit light with N times the brightness. Then, the display area 53 is scanned in the vertical direction of the screen. Therefore, S
The (N-1) / N area is a non-lighting area 52. This non-lighting area is black display (non-light emission). Further, the non-light emitting portion 52 is realized by turning off the transistor 11d. It is to be noted that the light is turned on with the brightness of N times, but it goes without saying that the brightness and the gamma adjustment are adjusted to the value of N times.

Further, in the previous embodiment, if programming is performed with a current of 10 times, the brightness of the screen will be 10 times, and 90% of the display area 50 should be the non-lighted area 52. . However, this is not limited to the common use of the RGB pixels as the non-lighting area 52. For example,
The R pixel has 1/8 the non-lighting area 52, the G pixel has 1/6 the non-lighting area 52, and the B pixel has the 1/1
0 may be changed depending on the non-illuminated area 52 and each color. Further, the non-lighting area 52 (or the lighting area 53) may be individually adjusted with RGB colors.
In order to realize these, separate gate signal lines 17b are required for R, G, and B. However, by enabling the individual RGB adjustments described above, it is possible to adjust the white balance, which facilitates color balance adjustment at each gradation (see FIG. 41).

As shown in FIG. 13B, the pixel row including the writing pixel row 51a is the non-lighting area 52, and the S / N of the screen above the writing pixel row 51a (temporarily 1
The range of (F / N) is set as the display area 53 (when writing scanning is from the top to the bottom of the screen, and vice versa when scanning the screen from the bottom to the top). The image display state is the display area 5
3 becomes a band and moves from the top to the bottom of the screen.

In the display of FIG. 13, one display area 53 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the display area 53 moves.
In particular, it becomes easy to be recognized when the eyelids are closed or when the face is moved up and down.

To solve this problem, the display area 53 may be divided into a plurality as shown in FIG. If the total of the divided areas is the area of S (N-1) / N,
It is equivalent to the brightness of. The divided display area 53
Do not have to be equal (equal). Further, it is not necessary to make the divided non-display areas 52 equal.

As described above, the flicker on the screen is reduced by dividing the display area 53 into a plurality of areas. Therefore, flicker does not occur and good image display can be realized. The division may be finer. However, the more divided it is, the lower the moving image display performance becomes.

FIG. 17 shows the voltage waveform of the gate signal line 17 and the EL emission brightness. As is clear from FIG. 17, the period (1 F /
N) is divided into a plurality (the number of divisions K). That is, Vg
The period of 1 is performed 1F / (K / N) times K times. By controlling in this way, it is possible to suppress the occurrence of flicker and realize image display at a low frame rate. Also,
It is preferable that the number of divided images is variable. For example, the user may press the brightness adjustment switch or turn the brightness adjustment volume to detect the change and change the value of K.
Alternatively, the user may adjust the brightness. It may be configured to change manually or automatically depending on the content and data of the image to be displayed.

In FIG. 17 and the like, the period (1F / N) in which the gate signal line 17b is set to Vgl is divided into a plurality (the number of divisions K), and the period in which Vgl is set is 1F / (K / N).
It is assumed that the period is performed K times, but the period is not limited to this. The period of 1F / (K / N) may be performed L (L ≠ K) times. That is, the present invention displays the image 50 by controlling the period (time) of flowing into the EL element 15. Therefore, the period of 1F / (K / N) is L (L
≠ K) times is included in the technical idea of the present invention. Further, by changing the value of L, the brightness of the image 50 can be changed digitally. For example,
When L = 2 and L = 3, the luminance (contrast) change is 50%. Further, when the image display area 53 is divided, the period in which the gate signal line 17b is set to Vgl is not limited to the same period.

In the above-described embodiment, the display screen 50 is turned on / off (lit or unlit) by cutting off the current flowing through the EL element 15 and connecting the current flowing through the EL element. That is, the substantially same current is caused to flow through the transistor 11a a plurality of times by the electric charge held in the capacitor 19. The present invention is not limited to this. For example, by charging / discharging the charge held in the capacitor 19, the display screen 50 is turned on / off (lighted,
The method of non-lighting) may be used.

FIG. 18 shows a voltage waveform applied to the gate signal line 17 for realizing the image display state of FIG.
The difference between FIG. 18 and FIG. 15 is the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off (Vgl and Vgh) by the number corresponding to the number of divided screens. Since the other points are the same as those in FIG. 15, description thereof will be omitted.

In the EL display device, the black display is completely non-illuminated, and therefore, the contrast is not lowered unlike the case where the liquid crystal display panel is intermittently displayed. Further, in the configuration of FIG. 1, by simply turning on and off the transistor 11d,
In the configuration of FIG. 38, intermittent display can be realized by simply turning on and off the transistor element 11e. This is because the image data is stored in the condenser 19 (the number of gradations is infinite because it is an analog value). That is, the image data is held in each pixel 16 during the period of 1F. Whether or not a current corresponding to the held image data is passed through the EL element 15 is realized by controlling the transistors 11d and 11e.

It is important to maintain the terminal voltage of the capacitor 19. This is because if the terminal voltage of the capacitor 19 changes (charges and discharges) in one field (frame) period, the screen brightness changes and flicker (such as flicker) occurs when the frame rate decreases. Transistor 11
It is necessary that the current flowing through the EL element 15 in a period of one frame (one field) does not drop to at least 65% or less. The 65% means that when the current of writing to the pixel 16 and flowing to the EL element 15 is 100% at first, the current flowing to the EL element 15 immediately before writing to the pixel 16 in the next frame (field) is 65% or more. Is to

In the pixel configuration of FIG. 1, the number of transistors 11 forming one pixel does not change between the case where the intermittent display is realized and the case where the intermittent display is not realized. In other words, the effect of the parasitic capacitance of the source signal line 18 is eliminated and the good current programming is realized while keeping the pixel configuration. In addition, a moving image display similar to a CRT is realized.

Since the operating clock of the gate driver circuit 12 is sufficiently slower than the operating clock of the source driver circuit 14, the main clock of the circuit does not become high. Moreover, the value of N can be easily changed.

Note that the image display direction (image writing direction)
May be from the top to the bottom of the screen in the first field (one frame), and may be from the bottom to the top of the screen in the next second field (frame). That is, the direction from top to bottom and the direction from bottom to top are alternately repeated.

Further, in the first field (one frame), the screen is directed downward from the top of the screen, and once the entire screen is displayed in black (not displayed), the second field (frame) is displayed from the bottom of the screen. It may be upward. Alternatively, the entire screen may be temporarily displayed in black (non-display).

In the above description of the driving method, the screen writing method is described as top to bottom or bottom to top of the screen, but the present invention is not limited to this. The writing direction of the screen is constantly fixed from top to bottom or bottom to top of the screen,
The operation direction of the non-display area 52 may be from the top to the bottom of the screen in the first field, and may be from the bottom to the top of the screen in the next second field. The above matters also apply to other embodiments of the present invention. The non-display area 52 does not need to be completely unlit. There is no problem in practice even if there is faint light emission or faint image display. That is, it should be interpreted as an area having a lower display brightness than the image display area 53. The non-display area 52 also includes the case where only one or two colors of the R, G, and B image displays are in the non-display state.

Basically, the brightness (brightness) of the display area 53
Is maintained at a predetermined value, the larger the area of the display region 53, the higher the brightness of the screen 50. For example, when the brightness of the display area 53 is 100 (nt), the display area 53
If the ratio of occupying the entire screen 50 is changed from 10% to 20%, the screen brightness is doubled. Therefore, the full screen 50
By changing the area of the display area 53 occupied by
The display brightness of the screen can be changed.

The area of the display area 53 is the same as that of the shift register 61.
It can be arbitrarily set by controlling the data pulse (ST2) to the. Further, the display state of FIG. 16 and the display state of FIG. 13 can be switched by changing the input timing and the cycle of the data pulse. If the number of data pulses in the 1F cycle is increased, the screen 50 becomes bright, and if it is decreased, the screen 50 becomes dark. If the data pulses are applied continuously, the display state shown in FIG. 13 is obtained, and if the data pulses are intermittently input, the display state shown in FIG. 16 is obtained.

FIG. 19A shows the display area 5 as shown in FIG.
This is a brightness adjustment method when 3 is continuous. FIG. 19
The display brightness of the screen 50 of (a1) is the brightest. FIG. 19
The display brightness of the screen 50 of (a2) is the next highest, and
The display brightness of the screen 50 of (a3) is the darkest. FIG. 19 (a
Change from 1) to Figure 19 (a3) (or vice versa)
Can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. At this time, it is not necessary to change the Vdd voltage in FIG. That is, the brightness of the display screen 50 can be changed without changing the power supply voltage. 19 (a1) to FIG.
When changing to (a3), the gamma characteristic of the screen does not change at all. Therefore, the contrast and gradation characteristics of the display image are maintained regardless of the brightness of the screen 50. This is an effective feature of the present invention. With conventional screen brightness adjustment,
When the brightness of the screen 50 is low, the gradation performance deteriorates. That is, in most cases, 64 gradations can be displayed in the high brightness display, but only half or less gradations can be displayed in the low brightness display. On the other hand, the driving method of the present invention can realize the maximum 64 gradation display without depending on the display brightness of the screen.

FIG. 19B shows the display area 5 as shown in FIG.
This is a brightness adjustment method when 3 is dispersed. FIG. 19
The display brightness of the screen 50 of (b1) is the brightest. FIG. 19
The display brightness of the screen 50 of (b2) is next brighter, and
The display brightness of the screen 50 of (b3) is the darkest. FIG. 19 (b)
Change from 1) to Figure 19 (b3) (or vice versa)
Can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. If the display areas 53 are dispersed as shown in FIG. 19B, flicker does not occur even at a low frame rate.

To prevent flicker even at a lower frame rate, the display areas 53 may be finely dispersed as shown in FIG. 19C. However, the display performance of moving images is degraded. So to display a video,
The driving method shown in FIG. 19A is suitable. When displaying a still image and demanding low power consumption, the driving method of FIG. 19C is suitable. The switching of the driving method shown in FIGS. 19A to 19C can be easily realized by controlling the shift register 61.

FIG. 20 is an explanatory diagram of another embodiment for increasing the current flowing through the source signal line 18. Basically, this is a method in which a plurality of pixel rows are selected at the same time, and the parasitic capacitance of the source signal line 18 is charged / discharged by a current combined with the plurality of pixel rows to significantly reduce the insufficient current writing. However, since a plurality of pixel rows are selected at the same time, the driving current per pixel can be reduced. Therefore, the EL element 1
The current flowing through 5 can be reduced. Here, in order to facilitate the description, N = 10 will be described as an example (the current flowing through the source signal line 18 is multiplied by 10).
In the present invention described with reference to FIG. 20, the pixel rows simultaneously select K pixel rows. From the source driver IC 14, a predetermined current of N
A double current is applied to the source signal line 18. EL for each pixel
A current N / K times the current passed through the element 15 is programmed. In order to make the EL element 15 have a predetermined emission brightness, the time to flow to the EL element 15 is set to K for one frame (one field).
/ N hours. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and good resolution and predetermined light emission luminance can be obtained.

That is, K of one frame (one field)
The current flows through the EL element 15 only during the period / N, and the current does not flow during the other period (1F (N-1) K / N). In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is, the image data display state becomes a temporally intermittent display (intermittent display) state. Therefore, the outline of the image is not blurred and a good moving image can be displayed. Further, since the source signal line 18 is driven by a current N times larger, it is not affected by parasitic capacitance and can be applied to a high-definition display panel.

FIG. 21 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. The signal waveform has an off voltage of V
gh (H level) and ON voltage is Vgl (L level)
I am trying. The suffix of each signal line is the pixel row number ((1)
(2) (3) etc. are described. The number of rows is QC
The IF display panel has 220 lines, and the VGA panel has 480 lines.

In FIG. 21, the gate signal line 17a
(1) is selected (Vgl voltage), and the program current flows from the transistor 11a of the selected pixel row toward the source driver 14 in the source signal line 18. Here, in order to facilitate the description, first, it is assumed that the write pixel row 51a is the pixel row (1) th.

Also, the program current flowing through the source signal line 18 is N times the predetermined value (for the sake of simplicity, N = 1.
It will be described as 0. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Also, description will be made assuming that five pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel is doubled (N / K = 1
0/5 = 2) is programmed so that current flows through transistor 11a.

When the writing pixel row is the (1) th pixel row, (1), (2), (3), (4) and (5) are selected as the gate signal lines 17a as shown in FIG. . That is, the switching transistors 11b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Further, the gate signal line 17b has a phase opposite to that of the gate signal line 17a. Therefore, the switching transistors 11d of the pixel rows (1), (2), (3), (4), and (5) are in the off state, and the EL of the corresponding pixel row is
No current is flowing through the element 15. That is, the non-lighting state 52.

Ideally, the transistor 11a of 5 pixels
However, a current of Iw × 2 is applied to the source signal line 18 (that is, Iw × 2 × N = Iw × is applied to the source signal line 18).
2 × 5 = Iw × 10. Therefore, assuming that the N times pulse driving of the present invention is not performed and the predetermined current is Iw, a current 10 times as large as Iw flows through the source signal line 18.

By the above operation (driving method), each pixel 1
The 6th capacitor 19 is programmed with double the current. Here, for ease of understanding, the description will be made assuming that the characteristics (Vt, S value) of each transistor 11a match.

The pixel rows selected at the same time are five pixel rows (K =
Since it is 5), the five drive transistors 11a operate. That is, a current of 10/5 = 2 times per pixel flows through the transistor 11a. In the source signal line 18,
A current obtained by adding the program currents of the five transistors 11a flows. For example, the current Iw originally written in the write pixel row 51a is set to I and the source signal line 18 is set to Iw.
A current of w × 10 is passed. A write pixel row 51b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18. However, since normal image data is written in the writing pixel row 51b later, there is no problem.

Therefore, in the 4-pixel row 51b, 1
During the H period, the same display as 51a is displayed. Therefore, at least the write pixel row 51a and the pixel row 51b selected for increasing the current are set to the non-display state 52. However, in the current mirror pixel configuration as shown in FIG. 38 and other voltage programming type pixel configurations, the display state may be set in some cases.

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (6) is selected (Vgl voltage), and the program current flows from the transistor 11a of the selected pixel row (6) to the source driver 14 in the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

After the next 1H, the gate signal line 17a
(2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (7) is selected (Vgl voltage), and the program current flows from the transistor 11a of the selected pixel row (7) to the source driver 14 in the source signal line 18. By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by the above operation and scanning while shifting by one pixel row.

In the driving method of FIG. 20, each pixel is programmed with a double current (voltage), so that the emission brightness of the EL element 15 of each pixel is ideally doubled. Therefore, the brightness of the display screen is twice the predetermined value. In order to make this a predetermined brightness, as shown in FIG.
1/2 of the display area 50 including the writing pixel row 51
The range may be set as the non-display area 52.

Similar to FIG. 13, when one display area 53 moves downward from the top of the screen as shown in FIG. 20, it is visually recognized that the display area 53 moves when the frame rate is low. . In particular, it becomes easy to be recognized when the eyelids are closed or when the face is moved up and down.

To solve this problem, the display area 53 may be divided into a plurality as shown in FIG. If the area to which the divided non-display area 52 is added has an area of S (N-1) / N, it is the same as the case without division.

FIG. 23 shows a voltage waveform applied to the gate signal line 17. The difference between FIG. 21 and FIG. 23 is basically the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off (Vgl and Vgh) by the number corresponding to the number of divided screens. Other points are almost the same as or can be inferred from FIG.

As described above, the flicker on the screen is reduced by dividing the display area 53 into a plurality of areas. Therefore, flicker does not occur and good image display can be realized. The division may be finer. However, the more divided it is, the more the flicker is reduced. Especially EL element 1
Since the response of No. 5 is fast, the display luminance does not decrease even if it is turned on / off in a time shorter than 5 μsec.

In the driving method of the present invention, the EL element 15
ON / OFF can be controlled by turning on / off a signal applied to the gate signal line 17b. Therefore, the clock frequency is KH
It can be controlled at a low frequency of z order. Moreover, an image memory or the like is not required to realize the black screen insertion (the non-display area 52 insertion). Therefore, the drive circuit or method of the present invention can be realized at low cost.

FIG. 24 shows a case where the pixel rows selected at the same time are two pixel rows. According to the examination result, in the display panel formed by the low temperature polysilicon technology, the display uniformity was practical in the method of simultaneously selecting two pixel rows. It is presumed that this is because the characteristics of the driving transistors 11a of the adjacent pixels are extremely matched. Also, laser animation
Good results were obtained by irradiating the source in which the stripe-shaped laser was irradiated in parallel with the source signal line 18.

This is because the semiconductor films in the range of being annealed at the same time have uniform characteristics. That is, the semiconductor film is uniformly formed within the stripe-shaped laser irradiation range, and the Vt and the mobility of the TFT using this semiconductor film are substantially equal. Therefore, by irradiating a stripe-shaped laser shot parallel to the formation direction of the source signal line 18 and moving this irradiation position, the pixels (pixel rows, pixels in the vertical direction of the screen) along the source signal line 18 The characteristics are made almost equal. Therefore, when a plurality of pixel rows are turned on at the same time and a current program is performed, the program current is selected at the same time and the current obtained by dividing the program current by the number of selected pixels is substantially the same. To be done. Therefore, a current program close to the target value can be executed, and uniform display can be realized. Therefore, there is a synergistic effect between the laser shot direction and the driving method described with reference to FIG.

As described above, by making the direction of the laser shot substantially coincide with the forming direction of the source signal line 18, the characteristics of the TFT 11a in the vertical direction of the pixel become substantially the same, and good current programming can be carried out. It is possible (even if the characteristics of the TFT 11a in the horizontal direction of the pixel do not match). The above operation is performed in synchronization with 1H (1 horizontal scanning period) by shifting the position of the selected pixel row by one pixel row or by a plurality of pixel rows. In the present invention, the direction of the laser shot is parallel to the source signal line 18, but
It does not have to be parallel. This is because the characteristics of the TFTs 11a in the vertical direction of the pixels along one source signal line 18 are formed to be substantially the same even if the source signal line 18 is irradiated with a laser shot in an oblique direction. Therefore, the meaning of irradiating the laser shot in parallel with the source signal line means that adjacent pixels above or below any pixel along the source signal line 18 are formed so as to be within one laser irradiation range. Is. Further, the source signal line 18 is generally a wiring for transmitting a program current or a voltage which becomes a video signal.

In the embodiment of the present invention, the writing pixel row position is shifted every 1H, but the invention is not limited to this, and it may be shifted every 2H. You may shift by one. Also,
You may shift by arbitrary time units. Further, the shift time may be changed according to the screen position. For example, the shift time at the center of the screen may be shortened and the shift time at the top and bottom of the screen may be increased. Also, the shift time may be changed for each frame. Further, it is not limited to selecting a plurality of consecutive pixel rows. For example, a pixel row extended to one pixel row may be selected. That is, in the first horizontal scanning period, the first pixel row and the third pixel row
The second pixel row is selected and the second pixel is selected in the second horizontal scanning period.
The fourth pixel row and the fourth pixel row are selected, the third pixel row and the fifth pixel row are selected in the third horizontal scanning period, and the fourth pixel row is selected in the fourth horizontal scanning period. This is a driving method for selecting the sixth pixel row and the sixth pixel row. Of course, in the first horizontal scanning period, the first pixel row and the third pixel row
The driving method of selecting the fifth pixel row and the fifth pixel row is also in the technical category.

The combination of selecting the laser shot direction and a plurality of pixel rows at the same time is not limited to the pixel configurations shown in FIGS. 1, 2 and 32, but the pixel configuration of the current mirror. 38 and FIG.
It goes without saying that the present invention can be applied to other current-driven pixel configurations such as those shown in FIG. Also, FIG. 43, FIG.
It can also be applied to voltage-driven pixel configurations shown in FIGS. That is, if the TFTs above and below the pixel have the same characteristics, the voltage program can be satisfactorily executed by the voltage value applied to the same source signal line 18.

In FIG. 24, the writing pixel row is (1)
When in the pixel row, the gate signal line 17a is (1) (2)
Has been selected (see Figure 25). That is, the switching transistors 11b in the pixel rows (1) and (2),
The transistor 11c is on. Further, the gate signal line 17b has a phase opposite to that of the gate signal line 17a. Therefore, at least the switching transistors 11d of the pixel rows (1) and (2) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 52. Note that in FIG. 24, the display area 53 is divided into five in order to reduce the occurrence of flicker.

Ideally, the transistors 11a of two pixels (rows) each have Iw × 5 (N = 10. That is, K = 2. Therefore, the current flowing through the source signal line 18 is Iw × K ×. 5 = Iw × 10) is applied to the source signal line 18. Then, the capacitor 19 of each pixel 16
Is programmed with 5 times the current.

The pixel rows selected at the same time are two pixel rows (K =
Since it is 2), the two drive transistors 11a operate. That is, a current of 10/2 = 5 times per pixel flows through the transistor 11a. In the source signal line 18,
A current obtained by adding the program currents of the two transistors 11a flows.

For example, the current Id originally written in the write pixel row 51a is set to I in the source signal line 18.
A current of w × 10 is passed. There is no problem because the writing pixel row 51b is written with regular image data later. The pixel row 51b has the same display as 51a during the 1H period. Therefore, at least the write pixel row 51a and the pixel row 51b selected to increase the current are in the non-display state 52.
And

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (3) is selected (Vgl voltage), and the program current flows from the transistor 11a of the selected pixel row (3) to the source driver 14 in the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

After the next 1H, the gate signal line 17a
(2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (4) is selected (Vgl voltage), and the program current flows from the transistor 11a of the selected pixel row (4) to the source driver 14 in the source signal line 18. By operating in this way, regular image data is held in the pixel row (2). The above operation and shifting by one pixel row (of course, shifting may be performed by a plurality of pixel rows. For example, in the case of pseudo interlace driving, 2
Will shift line by line. Further, from the viewpoint of image display, the same image may be written in a plurality of pixel rows in some cases.) While scanning, one screen is rewritten.

Although it is similar to FIG. 16, in the driving method of FIG. 24, since programming is performed with a current (voltage) of 5 times for each pixel, the light emission luminance of the EL element 15 of each pixel is ideally 5 Doubled. Therefore, the brightness of the display area 53 is five times higher than the predetermined value. To make this a predetermined brightness,
As shown in FIG. 16 and the like, the non-display area 52 may include a writing pixel row 51 and a range of 1/5 of the display screen 1.

As shown in FIG. 27, two write pixel rows 51 (51a, 51b) are selected and sequentially selected from the upper side to the lower side of the screen 50 (see also FIG. 26. In FIG. 26). Pixel rows 16a and 16b are selected). However, as shown in FIG. 27B, when the writing pixel row 51a exists at the bottom of the screen, 51b disappears. That is, only one pixel row is selected.
Therefore, all the current applied to the source signal line 18 is written in the pixel row 51a. Therefore, pixel row 5
Twice as much current is programmed into the pixel as compared to 1a.

To solve this problem, the present invention is shown in FIG.
As shown in (b), a dummy pixel row 281 is formed (arranged) on the lower side of the screen 50. Therefore, when the selected pixel row is selected up to the lower side of the screen 50, the final pixel row and the dummy pixel row 281 of the screen 50 are selected. Therefore, a prescribed current is written in the write pixel row of FIG.

FIG. 28 shows the state of FIG. 27 (b). As is clear from FIG. 28, when the selected pixel row is selected up to the pixel 16c row on the lower side of the screen 50, the final pixel row 281 of the screen 50 is selected. The dummy pixel row 281 is arranged outside the display area 50. That is, the dummy pixel row 28
1 is not turned on, or is not turned on, or is configured not to be displayed as a display even when turned on. For example,
For example, the contact hole between the pixel electrode and the TFT 11 is eliminated, or the EL film is not formed in the dummy pixel row.

In FIG. 27, dummy pixels (rows) 281 are provided (formed or arranged) on the lower side of the screen 50, but the invention is not limited to this. For example, in FIG.
When scanning is performed from the bottom side to the top side of the screen as shown in (a) (upside down scanning), dummy pixel rows 281 should be formed also on the top side of the screen 50 as shown in FIG. 29 (b). Is. That is, the dummy pixel rows 281 are formed (arranged) on the upper side and the lower side of the screen 50, respectively. With the above configuration, it is possible to support upside down scanning of the screen. In the above-described embodiment, two pixel rows are simultaneously selected.

The present invention is not limited to this, and for example, a method of simultaneously selecting 5 pixel rows (see FIG. 23) may be used. In other words, in the case of 5 pixel row simultaneous drive,
Four dummy pixel rows 281 may be formed. The dummy pixel row configuration or the dummy pixel row driving of the present invention is a method using at least one dummy pixel row. Of course, it is preferable to use the dummy pixel row driving method and the N times pulse driving in combination.

In the driving method in which a plurality of pixel rows are selected at the same time, it becomes more difficult to absorb the characteristic variation of the transistor 11a as the number of pixel rows selected at the same time increases. However, if the number of selected pixels decreases, the current programmed for one pixel increases, and a large current flows through the EL element 15. If the current flowing through the EL element 15 is large, E
The L element 15 is likely to deteriorate.

FIG. 30 solves this problem.
The basic concept of FIG. 30 is 1 / 2H (1 / H of the horizontal scanning period).
2) is a method of simultaneously selecting a plurality of pixel rows, as described with reference to FIGS. 22 and 29. The subsequent 1 / 2H (1/2 of the horizontal scanning period) is a combination of the methods for selecting one pixel row, as described with reference to FIGS. By combining in this way, it is possible to absorb the characteristic variation of the transistor 11a and to improve the in-plane uniformity at high speed.

In FIG. 30, for ease of explanation,
It is assumed that 5 pixel rows are simultaneously selected in the first period and 1 pixel row is selected in the second period. First, in the first period (1 / 2H in the first half), as shown in FIG. 30 (a1), five pixel rows are simultaneously selected. This operation has been described with reference to FIG. 22 and will not be described. As an example, the current passed through the source signal line 18 is 25 times the predetermined value. Therefore, the transistor 11a of each pixel 16 (in the case of the pixel configuration of FIG. 1) is programmed with a 5 times larger current (25/5 pixel rows = 5). Since the current is 25 times, the parasitic capacitance generated in the source signal line 18 and the like is charged and discharged in a very short time. Therefore, the potential of the source signal line 18 becomes a target potential in a short time, and the terminal voltage of the capacitor 19 of each pixel 16 is also programmed so as to flow a five times larger current. The application time of the 25-fold current is set to 1 / 2H of the first half (1/2 of one horizontal scanning period).

As a matter of course, since the same image data is written in the writing pixel row of the 5 pixel rows, the transistor 11d of the 5 pixel row is turned off so as not to display. Therefore, the display state is as shown in FIG.

During the subsequent 1 / 2H period, one pixel row is selected and current (voltage) programming is performed. This state is shown in Figure 3.
It is illustrated in 0 (b1). The write pixel row 51a is current-programmed (voltage) so as to flow five times as much current as before. 30 (a1) and 30 (b1) are made to have the same current to each pixel so that a change in the programmed terminal voltage of the capacitor 19 can be reduced so that the target current can be made to flow faster. This is because

That is, in FIG. 30 (a1), a current is caused to flow through a plurality of pixels, and the values are approximated to a value at which a rough current flows at high speed. In the first stage, since programming is performed by a plurality of transistors 11a, an error occurs due to variations in the transistors with respect to the target value. In the next second step, only the pixel row in which data is written and held is selected, and complete programming is performed from a rough target value to a predetermined target value.

The non-lighting area 52 is scanned downward from the top of the screen, and the write pixel row 51a is also scanned downward from the top of the screen, which is the same as the embodiment shown in FIG. 13 and the like. Is omitted.

FIG. 31 shows drive waveforms for realizing the drive method of FIG. As can be seen from FIG. 31, 1H (1 horizontal scanning period) is composed of two phases. These two phases are switched by the ISEL signal. ISEL
The signal is illustrated in FIG.

First, the ISEL signal will be described. The driver circuit 14 that implements FIG. 30 includes a current output circuit A and a current output circuit B. Each current output circuit is composed of a DA circuit that performs DA conversion of 8-bit grayscale data, an open amplifier, and the like. In the embodiment of FIG. 30, the current output circuit A is configured to output 25 times the current. On the other hand, the current output circuit B is configured to output 5 times the current. Current output circuit A
The output of the current output circuit B is applied to the source signal line 18 by controlling the switch circuit formed (arranged) in the current output section by the ISEL signal. This current output circuit is arranged on each source signal line.

When the ISEL signal is at the L level, the current output circuit A that outputs 25 times the current is selected and the current from the source signal line 18 is absorbed by the source driver IC 14 (more appropriately, the source driver circuit 14). It is absorbed by the current output circuit A formed therein). It is easy to adjust the magnitude of the current output circuit current such as 25 times or 5 times. This is because it can be easily configured with a plurality of resistors and analog switches.

When the writing pixel row is the (1) th pixel row as shown in FIG. 30 (see the column 1H in FIG. 30),
The gate signal line 17a is (1) (2) (3) (4) (5)
Is selected (in the case of the pixel configuration of FIG. 1). That is,
The switching transistors 11b and the transistors 11c of the pixel rows (1), (2), (3), (4), and (5) are in the ON state. Since ISEL is at L level, the current output circuit A that outputs 25 times the current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, the switching transistors 11d of the pixel rows (1), (2), (3), (4), and (5) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is,
The non-lighting state 52.

Ideally, the transistor 11a of 5 pixels
Respectively, a current of Iw × 2 is passed through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with five times the current. Here, for ease of understanding, the description will be made assuming that the characteristics (Vt, S value) of each transistor 11a match.

The pixel rows selected at the same time are five pixel rows (K =
Since it is 5), the five drive transistors 11a operate. That is, a current of 25/5 = 5 times per pixel flows through the transistor 11a. In the source signal line 18,
A current obtained by adding the program currents of the five transistors 11a flows. For example, when the current Iw to be written in the pixel by the conventional driving method is applied to the write pixel row 51a, a current of Iw × 25 is applied to the source signal line 18. A write pixel row 51b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18. However, since normal image data is written in the writing pixel row 51b later, there is no problem.

Therefore, the pixel row 51b displays the same as 51a during the 1H period. Therefore, the writing pixel row 51a and the pixel row 51 selected to increase the current are written.
b and at least the non-display state 52.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 51a is selected. That is,
(1) Only the pixel row is selected. As is apparent from FIG. 31, only the gate signal line 17a (1) is turned on (Vg
l) is applied to the gate signal lines 17a (2) (3)
In (4) and (5), off (Vgh) is applied. Therefore, although the transistor 11a in the pixel row (1) is in an operating state (a state in which current is supplied to the source signal line 18), the switching transistor 11b in the pixel rows (2), (3), (4), and (5) is The transistor 11c is off. That is, it is in a non-selected state. Further, since ISEL is at the H level, the current output circuit B that outputs 5 times the current is selected, and the current output circuit B and the source signal line 18 are connected. The state of the gate signal line 17b does not change from the previous 1 / 2H state, and the off voltage (Vgh) is applied. Therefore, pixel row (1) (2)
(3) (4) (5) switching transistor 11d
Is in an off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 52.

From the above, the transistors 11a in the pixel row (1) each supply a current of Iw × 5 to the source signal line 18. Then, the capacitors 19 of each pixel row (1)
Is programmed with 5 times the current.

In the next horizontal scanning period, one pixel row and the writing pixel row are shifted. That is, the write pixel row is (2) this time. In the first 1 / 2H period, when the writing pixel row is the (2) th pixel row as shown in FIG. 31, the gate signal lines 17a are (2) (3) (4) (5) (6). It is selected. That is, pixel rows (2) (3) (4)
(5) The switching transistor 11b and the transistor 11c of (6) are on. Also, ISEL is L
Because of the level, the current output circuit A that outputs 25 times the current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, pixel rows (2) (3) (4)
(5) The switching transistor 11d of (6) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 52. on the other hand,
Since the Vgl voltage is applied to the gate signal line 17b (1) of the pixel row (1), the transistor 11d is in the ON state and the EL element 15 of the pixel row (1) is turned on.

The pixel rows selected at the same time are five pixel rows (K =
Since it is 5), the five drive transistors 11a operate. That is, a current of 25/5 = 5 times per pixel flows through the transistor 11a. In the source signal line 18,
A current obtained by adding the program currents of the five transistors 11a flows.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 51a is selected. That is,
(2) Only the pixel row is selected. As is apparent from FIG. 31, only the gate signal line 17a (2) is turned on (Vg
l) is applied to the gate signal lines 17a (3) (4)
In (5) and (6), off (Vgh) is applied. Therefore, the transistors 11a in the pixel rows (1) and (2) are in an operating state (the pixel row (1) supplies a current to the EL element 15 and the pixel row (2) supplies a current to the source signal line 18). However, the switching transistors 11b and the transistors 11c in the pixel rows (3), (4), (5), and (6) are in the off state. That is, it is in a non-selected state. Also, IS
Since EL is at the H level, the current output circuit B that outputs 5 times the current is selected, and the current output circuit 1222b and the source signal line 18 are connected. The state of the gate signal line 17b does not change from the previous 1 / 2H state, and the off voltage (Vgh) is applied. Therefore, the switching transistors 11d of the pixel rows (2), (3), (4), (5), and (6) are in the off state, and E of the corresponding pixel row is
No current is flowing through the L element 15. That is, the non-lighting state 52.

From the above, the transistors 11a in the pixel row (2) cause a current of Iw × 5 to flow in the source signal line 18. Then, the capacitors 19 of each pixel row (2)
Is programmed with 5 times the current. One screen can be displayed by sequentially performing the above operation.

In the driving method described with reference to FIG. 30, G pixel rows (G is 2 or more) are selected in the first period, and programming is performed so that N times the current is passed through each pixel row. In the second period after the first period, B pixel rows (B is smaller than G and is 1 or more)
Is selected, and programming is performed so that N times the current flows through the pixel.

However, there are other measures. G in the first period
Pixel rows (G is 2 or more) are selected and programmed so that the total current of each pixel row is N times the current. In the second period after the first period, B pixel rows (B is smaller than G and is 1 or more) are selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, This is a method of programming so that the current of one pixel row) becomes N times. For example, in FIG.
In 0 (a1), 5 pixel rows are selected at the same time, and a double current is applied to the transistor 11a of each pixel. Therefore, 5 × 2 times = 10 times the current flows through the source signal line 18. In the next second period, 1 in FIG. 30 (b1).
Select a pixel row. A ten times larger current is passed through the transistor 11a of this one pixel.

In FIG. 31, the period for simultaneously selecting a plurality of pixel rows is 1 / 2H and the period for selecting one pixel row is 1 / 2H, but the invention is not limited to this.
The period for simultaneously selecting a plurality of pixel rows is set to 1 / 4H, and 1
The period for selecting a pixel row may be set to 3 / 4H. Also,
The period including the period of simultaneously selecting a plurality of pixel rows and the period of selecting one pixel row is set to 1H, but is not limited to this. For example, it may be a 2H period or a 1.5H period.

Further, in FIG. 30, the period for simultaneously selecting five pixel rows may be set to 1 / 2H, and two pixel rows may be simultaneously selected in the next second period. Even in this case, it is possible to realize image display without any trouble in practical use.

Further, in FIG. 30, the first period for simultaneously selecting 5 pixel rows is set to 1 / 2H, and the second period for selecting 1 pixel row is set to 1 / 2H. However, the present invention is not limited to this. Not something to do. For example, in the first stage, 5 pixel rows are simultaneously selected, and in the second period, among the 5 pixel rows,
There may be three stages of selecting two pixel rows and finally selecting one pixel row. That is, the image data may be written in the pixel rows in a plurality of stages.

In the above N-fold pulse driving method of the present invention,
In each pixel row, the waveform of the gate signal line 17b should be the same and 1
The voltage is shifted and applied at intervals of H. By scanning in this way, the time during which the EL element 15 is lit is set to 1
The pixel rows to be turned on can be sequentially shifted while defining the F / N. In this way, it is easy to realize that the gate signal lines 17b have the same waveform and are shifted in each pixel row. Data ST1 and ST applied to the shift register circuits 61a and 61b of FIG.
This is because it is only necessary to control 2. For example, input ST2
Is at L level, Vgl is output to the gate signal line 17b, and when input ST2 is at H level, Vgh is output to the gate signal line 17b. Input at L level only for a period and set to H level for other periods. This input ST2
Is only shifted by the clock CLK2 synchronized with 1H.

The cycle for turning on / off the EL element 15 must be 0.5 msec or more. When this cycle is short, the image is not completely displayed in black due to the afterimage characteristic of human eyes, and the image becomes blurry and the resolution is lowered. Further, the display state of the data holding type display panel is set. However, the on / off cycle is 100 msec.
When it is above, it looks like blinking. Therefore, the ON / OFF cycle of the EL element is 0.5 μsec or more and 100 msec.
Should be: More preferably, the on / off period should be 2 msec or more and 30 msec or less. More preferably, the on / off cycle is 3 msec or more and 20 m
It should be less than sec.

If the number of divisions of the black screen 152 is set to one, a good moving image display can be realized, but the flicker on the screen is easily visible. Therefore, it is preferable to divide the black insertion part into a plurality of parts. However, if the number of divisions is too large, moving image blur occurs. The number of divisions should be 1 or more and 8 or less. More preferably, it is 1 or more and 5 or less.

It is preferable that the number of divisions of the black screen can be changed between a still image and a moving image. What is the number of divisions?
When N = 4, 75% is a black screen and 25% is an image display. At this time, the number of divisions 1 is to scan 75% of the black display portion in the vertical direction of the screen with the black band state of 75%. Two
The number of divisions is 3 when scanning is performed with 3 blocks of a 5% black screen and a 25/3% display screen. For still images, increase the number of divisions. For movies, reduce the number of divisions. The switching may be performed automatically (moving image detection or the like) according to the input image, or may be performed manually by the user. Further, it may be configured such that the image of the display device or the like can be switched according to the input outlet.

For example, in a mobile phone or the like, the number of divisions is set to 10 or more in the wallpaper display and the input screen (extremely, it may be turned on and off every 1H). When displaying an NTSC video, the number of divisions should be 1 or more and 5 or less. It is preferable that the number of divisions can be switched in multiple stages of 3 or more. For example, there are no division numbers, such as 2, 4, 8 and the like.

The ratio of the black screen to the total display screen is 0.2 or more and 0.9 or less (1.2 or more and 9 or less when displayed by N) when the area of the entire screen is 1. preferable. In addition, it is particularly preferably 0.25 or more and 0.6 or less (when displayed by N, 1.25 or more and 6 or less). 0.
If it is 20 or less, the effect of improving the moving image display is low. 0.9
If it is above, the brightness of a display part will become high and it will become easy to be visually recognized that a display part moves up and down.

Further, the number of frames per second is preferably 10 or more and 100 or less (10 Hz or more and 100 Hz or less). Furthermore, 12 or more and 65 or less (12 Hz or more and 65 Hz
The following) are preferable. If the number of frames is small, the flickering of the screen becomes noticeable, and if the number of frames is too large, writing from the driver circuit 14 becomes difficult and the resolution deteriorates.

In any case, in the present invention, the brightness of the image can be changed by controlling the gate signal line 17. However, it goes without saying that the brightness of the image may be changed by changing the current (voltage) applied to the source signal line 18. In addition, the control of the gate signal line 17 and the source signal line 18 described above (using FIG. 33, FIG. 35, etc.)
It goes without saying that changing the current (voltage) to be applied may be performed in combination.

It goes without saying that the above items can be applied to the pixel configuration of the current program shown in FIG. 38 and the like and the pixel configuration of the voltage program shown in FIGS. 43, 51 and 54. 38, the transistor 11d is shown in FIG. 43, the transistor 11d is shown in FIG.
It suffices to control e on / off. In this way, the EL element 1
By turning on and off the wiring through which the current flows through 5, the N-fold pulse driving of the present invention can be easily realized.

Further, the time to set Vgl only for the period of 1F / N of the gate signal line 17b may be any time within the period of 1F (not limited to 1F; it may be a unit period). EL element 1 for a predetermined period of time per unit time
This is because a predetermined average luminance is obtained by turning on 5. However, current program period (1H)
Immediately after that, it is better to set the gate signal line 17b to Vgl to cause the EL element 15 to emit light. This is because the capacitor 19 in FIG. 1 is less likely to be affected by the holding ratio characteristic.

Further, it is preferable that the number of divisions of this image is variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the value of K is changed. It may be configured to change manually or automatically depending on the content and data of the image to be displayed.

Thus, the value of K (the number of divisions of the image display unit 53) can be easily changed. In FIG. 6, the timing of data applied to ST (when L on 1F
This is because it may be configured so that the level can be adjusted or changed.

In FIG. 16 and the like, the gate signal line 17
Although the period (1F / N) in which b is Vgl is divided into a plurality (division number K) and the period in which Vgl is 1F / (K / N) is performed K times, the period is not limited to this. 1
The period of F / (K / N) may be performed L (L ≠ K) times. That is, the present invention displays the image 50 by controlling the period (time) of flowing into the EL element 15. Therefore, the period of 1F / (K / N) is L (L ≠
Performing K) times is included in the technical idea of the present invention.
Further, by changing the value of L, the brightness of the image 50 can be changed digitally. For example, L =
With 2 and L = 3, there is a 50% change in brightness (contrast). It goes without saying that these controls can also be applied to other embodiments of the present invention (of course, they can also be applied to the present invention described below). These are also N-times pulse driving according to the present invention. In the above embodiment, the transistor 11d as a switching element is arranged (formed) between the EL element 15 and the driving transistor 11a.
The screen 50 is displayed on / off by controlling 1d. By this driving method, insufficient current writing in the black display state of the current program method is eliminated and good resolution or black display is realized. That is, it is important to realize good black display in the current programming method. The driving method described below is to reset the driving transistor 11a to realize good black display. The embodiment will be described below with reference to FIG.

32 basically shows the pixel configuration of FIG. In the pixel configuration of FIG. 32, the programmed Iw current flows through the EL element 15, and the EL element 15 emits light. That is, the drive transistor 11a is programmed to retain the ability to pass a current. A method of resetting the transistor 11a (off state) by utilizing this ability to flow the current is the driving method of FIG. Hereinafter, this driving method is referred to as reset driving.

In order to realize the reset drive with the pixel configuration of FIG. 1, it is necessary to configure the transistors 11b and 11c so that they can be controlled on and off independently. That is, as shown in FIG.
The gate signal line 11a (gate signal line WR) for ON / OFF control of b and the gate signal line 11c (gate signal line EL) for ON / OFF control of the transistor 11c can be controlled independently. Control of the gate signal line 11a and the gate signal line 11c may be performed by two independent shift registers 61 as shown in FIG.

The drive voltage of the gate signal line WR and the gate signal line EL may be changed. The amplitude value of the gate signal line WR (difference between ON voltage and OFF voltage) is made smaller than the amplitude value of the gate signal line EL. Basically, when the amplitude value of the gate signal line is large, the punch-through voltage between the gate signal line and the pixel becomes large, and black floating occurs. The amplitude of the gate signal line WR may be controlled so that the potential of the source signal line 18 is not applied (applied (selected)) to the pixel 16.
Since the potential fluctuation of the source signal line 18 is small, the amplitude value of the gate signal line WR can be reduced. On the other hand, for the gate signal line EL, it is necessary to control ON / OFF of EL. Therefore, the amplitude value becomes large. To deal with this, the output voltages of the shift registers 61a and 61b are changed. When the pixel is formed by a P-channel TFT, the Vgh (off voltage) of the shift registers 61a and 61b is set to be substantially the same, and the Vgl of the shift register 61a is set to the same value.
(ON voltage) is made lower than Vgl (ON voltage) of the shift register 61b.

The reset drive method will be described below with reference to FIG. FIG. 33 is a diagram illustrating the principle of reset driving. First, as illustrated in FIG. 33A, the transistors 11c and 11d are turned off and the transistor 11b is turned on. Then, the drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and the Ib current flows. In general, the transistor 11a is current-programmed in the previous field (frame) and has a capability of flowing current. In this state, if the transistor 11d is turned off and the transistor 11b is turned on, the drive current Ib flows to the gate (G) terminal of the transistor 11a. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (state in which no current flows).

The reset state (state in which no current flows) of the transistor 11a is equivalent to the state in which the offset voltage of the voltage offset canceller system described in FIG. 51 and the like is held. That is, in the state of FIG.
The offset voltage is held between the terminals of the capacitor 19. This offset voltage has a different voltage value depending on the characteristics of the transistor 11a. Therefore, by carrying out the operation of FIG. 33 (a), the capacitor 19 of each pixel holds the current which the transistor 11a does not flow (that is, the black display current (which is almost equal to 0)). is there.

Before the operation of FIG. 33 (a), it is preferable to carry out the operation of turning off the transistors 11b and 11c, turning on the transistor 11d, and passing a current through the driving transistor 11a. This operation is preferably made as short as possible. E
This is because a current may flow through the L element 15 to turn on the EL element 15 and reduce the display contrast. This operation time is 0.1% or more of 1H (1 horizontal scanning period) 1
It is preferably 0% or less. More preferably 0.
It is preferable to set it to 2% or more and 2% or less. Alternatively, it is preferably set to 0.2 μsec or more and 5 μsec or less. In addition, the above-described operation (operation performed before FIG. 33A) may be collectively performed on the pixels 16 of the entire screen. By performing the above operation, the drain (D) terminal voltage of the driving transistor 11a decreases,
In the state of FIG. 33 (a), a smooth Ib current can be passed. The above items also apply to other reset driving methods of the present invention.

As the execution time of FIG. 33 (a) is lengthened,
The Ib current flows, and the terminal voltage of the capacitor 19 tends to decrease. Therefore, the implementation time of FIG. 33A needs to be a fixed value. According to experiments and studies, the implementation time of FIG. 33 (a) is preferably 1H or more and 5H or less. Note that this period is preferably different for the R, G, and B pixels. This is because the EL material is different for each color pixel, and there is a difference in the rising voltage of the EL material. For each pixel of RGB, the most suitable period is set according to the EL material. In the examples,
This period is set to 1H or more and 5H or less, but it goes without saying that it may be 5H or more in a driving method mainly for black insertion (writing a black screen). Note that the longer this period, the better the black display state of the pixel.

After carrying out FIG. 33 (a), the state shown in FIG. 33 (b) is obtained in a period of 1H or more and 5H or less. FIG. 33
(B) shows a state in which the transistors 11c and 11b are turned on and the transistor 11d is turned off.
The state of FIG. 33B is a state in which current programming is being performed, as described above. That is, the source driver circuit 14 outputs (or absorbs) the program current Iw, and the program current Iw is supplied to the driving transistor 11a. The potential of the gate (G) terminal of the driving transistor 11a is set so that the program current Iw flows (the set potential is held in the capacitor 19).

If the program current Iw is 0 (A), the transistor 11a remains in the state in which no current flows as shown in FIG. 33 (a), so that good black display can be realized. Further, even when the current program for white display is performed in FIG. 33B, even if the characteristic variation of the driving transistor of each pixel occurs, the current program is performed from the offset voltage in the completely black display state. . Therefore, the time to be programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a, and good image display can be realized.

After the current programming of FIG. 33 (b), as shown in FIG. 33 (c), the transistors 11b and 11c are turned off and the transistor 11d is turned on, so that the program current Iw ( = Ie) is passed through the EL element 15,
Light up. 33 (c) has also been described above with reference to FIG.

That is, the driving method (reset driving) described with reference to FIG. 33 uses the driving transistor 11a and the EL element 1.
5 is cut (state in which no current flows), and the drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal of the driving transistor are expressed more generally. For example, the first operation of short-circuiting between the two terminals including the gate (G) terminal of the driving transistor, and a current (voltage) to the driving transistor after the above operation.
And a second operation of programming.
Then, at least the second operation is performed after the first operation. In order to carry out the reset drive, the transistors 11b and 11c must be configured to be independently controllable as in the configuration of FIG.

In the image display state (if an instantaneous change can be observed), first, the pixel row for which the current program is performed is in the reset state (black display state) for 1H.
After that, current programming is performed (the black display state is also present at this time, because the transistor 11d is off). Next, a current is supplied to the EL element 15, and the pixel row emits light with a predetermined brightness (programmed current). That is, the pixel row for black display should move from the top to the bottom of the screen, and the image should be rewritten at the position where the pixel row has passed. Although the current program is performed 1H after the reset, this period may be within 5H. This is because it takes a relatively long time to completely perform the reset of FIG. If this period is set to 5H, 5 pixel rows should be displayed in black (6 pixel rows including the pixel row for current programming).

The reset state is not limited to one pixel row at a time, but a plurality of pixel rows may be simultaneously reset. Alternatively, a plurality of pixel rows may be reset simultaneously and scanning may be performed while overlapping. For example, if four pixel rows are reset at the same time, the pixel rows (1), (2), (3), and (4) are reset in the first horizontal scanning period (1 unit), and the next second horizontal scanning is performed. In the scanning period, pixel rows (3) (4) (5) (6)
To the reset state, and during the next third horizontal scanning period, the pixel rows (5), (6), (7) and (8) are reset. Further, in the next fourth horizontal scanning period, the pixel row (7)
A driving state in which (8), (9) and (10) are reset is illustrated. Incidentally, as a matter of course, FIG.
The drive state of (c) is also performed in synchronization with the drive state of FIG. 33 (a).

Further, after all the pixels of one screen are reset at the same time or in the scanning state, FIG.
It goes without saying that the driving of (c) may be performed.
Needless to say, the interlace drive state (interlaced scanning of one pixel row or a plurality of pixel rows) may be set to the reset state (interlaced one pixel row or a plurality of pixel rows). Also, a random reset state may be implemented. Further, the explanation of the reset driving of the present invention is a method of operating a pixel row (that is, controlling the vertical direction of the screen). However, the concept of reset driving is not limited to the control of the pixel row. For example, it goes without saying that reset driving may be performed in the pixel column direction.

The reset drive shown in FIG. 33 can be combined with the N-times pulse drive of the present invention or the like, or can be combined with the interlace drive to realize better image display. In particular, the configuration of FIG. 22 is an intermittent N / K times pulse drive (a drive method in which a plurality of lighting regions are provided in one screen. This drive method is easy by controlling the gate signal line 17b and turning on / off the transistor 11d. This can be easily realized, and thus good image display can be realized without the occurrence of flicker. This is an excellent feature of FIG. 22 or its modified configuration. Further, it goes without saying that a more excellent image display can be realized by combining with another driving method, for example, a reverse bias driving method, a precharge driving method, a punch-through voltage driving method which will be described later. As described above, it goes without saying that the reset driving can be performed in combination with the other embodiments of the present specification as in the present invention.

FIG. 34 is a block diagram of a display device which realizes reset driving. The gate driver circuit 12a is shown in FIG.
Signal line 17a and gate signal line 17b in
To control. The transistor 11b is on / off controlled by applying an on / off voltage to the gate signal line 17a. Further, the transistor 11d is on / off controlled by applying an on / off voltage to the gate signal line 17b. The gate driver circuit 12b controls the gate signal line 17c in FIG. The transistor 11c is on / off controlled by applying an on / off voltage to the gate signal line 17c.

Therefore, the gate signal line 17a is operated by the gate driver circuit 12a, and the gate signal line 17c is operated by the gate driver circuit 12b. Therefore, the timing of turning on the transistor 11b to reset the driving transistor 11a and the timing of turning on the transistor 111c to perform current programming in the driving transistor 11a can be freely set. Other configurations are the same as or similar to those described above, and thus description thereof will be omitted.

FIG. 35 is a timing chart of reset driving. An on voltage is applied to the gate signal line 17a to turn on the transistor 11b, and the driving transistor 11
When a is being reset, an off voltage is applied to the gate signal line 17b to turn off the transistor 11d. Therefore, the state is as shown in FIG. Ib current flows during this period.

In the timing chart of FIG. 35, the reset time is 2H (the ON voltage is applied to the gate signal line 17a and the transistor 11b is turned ON), but the reset time is not limited to this. It may be 2H or more. Also,
If the reset can be performed very quickly, the reset time may be less than 1H. Further, the DAT input to the gate driver circuit 12 determines which H period the reset period is set to.
It can be easily changed in the A (ST) pulse period. For example,
If DATA input to the ST terminal is set to the H level for the 2H period, the reset period output from each gate signal line 17a becomes the 2H period. Similarly, D input to the ST terminal
If ATA is set to the H level for the 5H period, the reset period output from each gate signal line 17a becomes the 5H period.

After the reset for the 1H period, the ON voltage is applied to the gate signal line 17c (1) of the pixel row (1). When the transistor 11c is turned on, the program current Iw applied to the source signal line 18 is applied to the transistor 1
It is written in the driving transistor 11a via 1c.

After the current programming, the off voltage is applied to the gate signal line 17c of the pixel (1), and the transistor 11c
Turns off and the pixel is disconnected from the source signal line. At the same time, an off voltage is applied to the gate signal line 17a as well, and the reset state of the driving transistor 11a is canceled (note that during this period, it is more appropriate to describe the current programming state than the reset state. is there). Further, an ON voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and the current programmed in the driving transistor 11a flows through the EL element 15. The pixel rows (2) and thereafter are the same as the pixel rows (1),
Further, since the operation is clear from FIG. 35, the description will be omitted.

In FIG. 35, the reset period was the 1H period. FIG. 36 shows an example in which the reset period is 5H. The H period of the reset period can be easily changed by the DATA (ST) pulse period input to the gate driver circuit 12. In FIG. 36, the gate driver circuit 12a
In this embodiment, DATA input to the ST1 terminal is set to the H level for the 5H period, and the reset period output from each gate signal line 17a is set to the 5H period. The longer the reset period, the more completely the reset is performed, and good black display can be realized. However, the display brightness is reduced for the proportion of the reset period.

FIG. 36 shows an embodiment in which the reset period is 5H. Moreover, this reset state was a continuous state. However, the reset state is not limited to continuous operation. For example, the signal output from each gate signal line 17a may be turned on / off every 1H. Such on / off operation can be easily realized by operating an enable circuit (not shown) formed in the output stage of the shift register. Further, it can be easily realized by controlling the DATA (ST) pulse input to the gate driver circuit 12.

In the circuit configuration of FIG. 34, the gate driver circuit 12a requires at least two shift register circuits (one for controlling the gate signal line 17a and the other for controlling the gate signal line 17b). Therefore, there is a problem that the circuit scale of the gate driver circuit 12a becomes large. FIG. 37 shows an embodiment in which the gate driver circuit 12a has only one shift register. The timing chart of the output signal when the circuit of FIG. 37 is operated is as shown in FIG. Note that FIG. 35 and FIG. 37 show the gate driver circuit 12
Note that the symbols of the gate signal lines 17 output from a and 12b are different.

As is apparent from the addition of the OR circuit 371 of FIG. 37, the output of each gate signal line 17a is ORed with the output of the preceding stage of the shift register circuit 61a. That is, during the 2H period, the gate signal line 17
An on-voltage is output from a. On the other hand, the gate signal line 1
7c outputs the output of the shift register circuit 61a as it is. Therefore, the ON voltage is applied during the 1H period.

For example, 2 of the shift register circuit 61a.
When the H-level signal is output next, the pixel 16
The ON voltage is output to the gate signal line 17c of (1), and the pixel 16 (1) is in a current (voltage) program state.
At the same time, the ON voltage is output to the gate signal line 17a of the pixel 16 (2), and the transistor 11b of the pixel 16 (2) is output.
Is turned on, and the driving transistor 11a of the pixel 16 (2) is reset.

Similarly, when the H level signal is output to the third of the shift register circuit 61a, the pixel 16 (2)
The ON voltage is output to the gate signal line 17c of the pixel 16
(2) is the state of current (voltage) programming. At the same time, the ON voltage is also output to the gate signal line 17a of the pixel 16 (3), the transistor 16b of the pixel 16 (3) is turned on, and the transistor 11a for driving the pixel 16 (3) is reset. Gate signal line 17
ON voltage is output from a, and 1 is applied to the gate signal line 17c.
During the H period, the ON voltage is output.

In the programmed state, the transistor 11
b and the transistor 11c are turned on at the same time (see FIG. 3).
3 (b)) to the non-programmed state (FIG. 33 (c)), if the transistor 11c is turned off prior to the transistor 11b, the reset state shown in FIG. 33 (b) will result. To prevent this, the transistor 11c needs to be turned off later than the transistor 11b. For that purpose, the gate signal line 17
It is necessary to control so that the ON voltage is applied to the a before the gate signal line 17c.

The above examples are examples relating to the pixel configuration of FIG. 32 (basically FIG. 1). However, the present invention is not limited to this. For example, in FIG.
The present invention can be implemented even with a current mirror pixel configuration as shown in FIG. Note that in FIG. 38, the transistor 11
By controlling on / off of e, the N-fold pulse driving shown in FIGS. 13 and 15 can be realized. FIG. 39 shows FIG.
It is explanatory drawing of the Example in the pixel structure of the current mirror of FIG. Hereinafter, the reset driving method in the pixel configuration of the current mirror will be described with reference to FIG.

As shown in FIG. 39A, the transistors 11c and 11e are turned off and the transistor 11d is turned on. Then, the drain (D) terminal and the gate (G) terminal of the current programming transistor 11b are short-circuited, and as shown in FIG.
b current flows. In general, the transistor 11b is current-programmed in the previous field (frame) and has a capability of flowing current (the gate potential is 1 in the capacitor 19).
This is natural because it is held for F period and an image is displayed. However, current does not flow when displaying completely black). If the transistor 11e is turned off and the transistor 11d is turned on in this state, the drive current Ib flows in the direction of the gate (G) terminal of the transistor 11a (the gate (G) terminal and the drain (D) terminal are short-circuited). ). Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (state in which no current flows). Further, since the gate (G) terminal of the driving transistor 11b is common with the gate (G) terminal of the current programming transistor 11a, the driving transistor 11b is also in the reset state.

This transistor 11a and transistor 1
The reset state of 1b (state in which no current flows) is shown in FIG.
This is equivalent to the state of holding the offset voltage of the voltage offset canceller method described in the above. That is, FIG.
In the state of (a), an offset voltage (starting voltage at which a current starts to flow between the terminals of the capacitor 19. By applying a voltage equal to or higher than the absolute value of this voltage, the transistor 1
Current flows through 1). This offset voltage is applied to the transistors 11a and 1
The voltage value varies depending on the characteristics of 1b. Therefore,
By performing the operation of FIG. 39 (a), the transistors 19a and 1
Therefore, the state in which 1b does not flow current (that is, the black display current (which is almost equal to 0)) is maintained (reset to the starting voltage at which the current starts flowing).

Note that in FIG. 39 (a) as well, FIG.
As in (a), the longer the reset time is,
The Ib current flows, and the terminal voltage of the capacitor 19 tends to decrease. Therefore, the implementation time of FIG. 39 (a) needs to be a fixed value. According to experiments and studies, it is preferable that the execution time of FIG. 39 (a) is 1H or more and 10H (10 horizontal scanning periods) or less. Furthermore, it is preferable to set it to 1H or more and 5H or less. Alternatively, 20 μse
It is preferable to be c or more and 2 msec or less. This also applies to the drive system shown in FIG.

The same applies to FIG. 33 (a), but FIG.
When the reset state of (a) and the current program state of FIG. 39 (b) are synchronized, the period from the reset state of FIG. 39 (a) to the current program state of FIG. 39 (b) is There is no problem because it is a fixed value (constant value) (fixed value). That is, the period from the reset state of FIG. 33 (a) or 39 (a) to the current program state of FIG. 33 (b) or 39 (b) is 1H.
It is preferable to be 10H (10 horizontal scanning periods) or less. Furthermore, it is preferable to set it to 1H or more and 5H or less. Alternatively, it is preferably 20 μsec or more and 2 msec or less. If this period is short, the driving transistor 11 is not completely reset. Also,
If it is too long, the driving transistor 11 is completely turned off, and it takes a long time to program the current. Further, the brightness of the screen 50 also decreases.

After performing FIG. 39 (a), the state shown in FIG. 39 (b) is obtained. FIG. 39B shows a state in which the transistors 11c and 11d are turned on and the transistor 11e is turned off. The state of FIG. 39 (b) is a state in which current programming is being performed. That is, the source driver circuit 14 outputs (or absorbs) the program current Iw.
Then, the programming current Iw is passed through the current programming transistor 11a. The potential of the gate (G) terminal of the driving transistor 11b is set in the capacitor 19 so that the program current Iw flows.

If the program current Iw is 0 (A) (black display), the transistor 11b outputs the current as shown in FIG.
Since the state in which the current of (a) does not flow is maintained, a good black display can be realized. In the case of performing the current program for white display in FIG. 39B, even if the characteristic variation of the driving transistor of each pixel occurs, the offset voltage in the completely black display state (the characteristic of each driving transistor is The current program is performed from the starting voltage at which the set current flows). Therefore, the time to be programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a or the transistor 11b, and good image display can be realized.

After the current programming of FIG. 39 (b), as shown in FIG. 39 (c), the transistor 11c and the transistor 11d are turned off, the transistor 11e is turned on, and the program current Iw (from the driving transistor 11b ( = Ie) is passed through the EL element 15,
Light up. 39 (c) has also been described above, and the details thereof will be omitted.

In the driving method (reset driving) described with reference to FIGS. 33 and 39, the driving transistor 11a or transistor 11b and the EL element 15 are disconnected (no current flows. Transistor 11e or transistor 11).
d) and the drain (D) terminal and gate (G) terminal (or source (S)) of the driving transistor.
A first operation for short-circuiting between the terminal and the gate (G) terminal, or more generally, two terminals including the gate (G) terminal of the driving transistor), and a current ( And a second operation for programming a voltage). Then, at least the second operation is performed after the first operation. Note that the operation of disconnecting the EL element 15 from the driving transistor 11a or the transistor 11b in the first operation is not always an essential condition. If the driving transistor 11a or the transistor 11b in the first operation
Even if the first operation of short-circuiting the drain (D) terminal and the gate (G) terminal of the driving transistor without disconnecting between the EL element 15 and the EL element 15 is performed, the reset state may be slightly varied. This is because there are cases. this is,
The transistor characteristics of the fabricated array are examined and determined.

The pixel configuration of the current mirror of FIG. 39 is a driving method in which the current program transistor 11a is reset, and as a result, the driving transistor 11b is reset.

In the pixel configuration of the current mirror of FIG. 39,
In the reset state, the driving transistor 11b is not always required.
It is not necessary to disconnect between the EL element 15 and the EL element 15. Therefore,
The drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal of the current programming transistor a, or more generally, the gate (G) terminal of the current programming transistor is included. 2 terminals or 2 including the gate (G) terminal of the driving transistor
The first operation of shorting the terminals) and after the above operation,
A second operation of performing current (voltage) programming on the current programming transistor is performed. And
At least the second operation is performed after the first operation.

In the image display state (if an instantaneous change can be observed), first, the pixel row for which the current program is performed is in the reset state (black display state), and the current program is performed after a predetermined H. Be seen. The pixel row for black display should move from the top to the bottom of the screen, and the image should be rewritten at the position where this pixel row has passed.

Although the above embodiments have been described centering on the pixel configuration of the current program, the reset driving of the present invention can be applied to the pixel configuration of the voltage program.
FIG. 43 is an explanatory diagram of a pixel configuration (panel configuration) of the present invention for implementing reset driving in the voltage programmed pixel configuration.

In the pixel configuration of FIG. 43, the transistor 11 for resetting the driving transistor 11a is used.
e is formed. By applying an on-voltage to the gate signal line 17e, the transistor 11e is turned on,
The gate (G) terminal and the drain (D) terminal of the driving transistor 11a are short-circuited. In addition, the EL element 15
And a transistor 11d for disconnecting the current path between the drive transistor 11a and the drive transistor 11a. Hereinafter, the reset driving method of the present invention in the pixel configuration of voltage programming will be described with reference to FIG.

As shown in FIG. 44A, the transistors 11b and 11d are turned off and the transistor 11e is turned on. The drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and an Ib current flows as shown in the figure. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the driving transistor 11a is reset (state in which no current flows). Before resetting the transistor 11a, as described with reference to FIG. 33 or FIG. 39, the transistor 11d is first turned on and the transistor 11e is turned off in synchronization with the HD sync signal, so that a current flows through the transistor 11a. Keep it. Then, the operation of FIG. 44 (a) is performed.

This transistor 11a and transistor 1
The reset state of 1b (state in which no current flows) is shown in FIG.
This is equivalent to the state in which the offset voltage of the voltage offset canceller method described above is held. That is, FIG.
In the state of (a), the offset voltage (reset voltage) is held between the terminals of the capacitor 19. This reset voltage has a different voltage value depending on the characteristics of the driving transistor 11a. That is, FIG. 44 (a)
By carrying out the operation of
Therefore, the state in which the driving transistor 11a does not flow current (that is, the black display current (which is almost equal to 0)) is maintained (reset to the start voltage at which the current starts to flow).

Also in the pixel configuration of the voltage program, as in the pixel configuration of the current program, FIG.
The longer the reset execution time is, the more the Ib current flows, and the terminal voltage of the capacitor 19 tends to decrease. Therefore, the implementation time of FIG. 44 (a) needs to be a fixed value. The execution time is preferably 0.2H or more and 5H (5 horizontal scanning periods) or less. Furthermore 0.5
It is preferable that it is H or more and 4H or less. Or 2μ
It is preferable that the time is not less than sec and not more than 400 μsec.

Further, it is preferable that the gate signal line 17e is shared with the gate signal line 17a of the preceding pixel row. That is, the gate signal line 17e and the gate signal line 17a in the preceding pixel row are formed in a short-circuited state. This configuration is called the pre-stage gate control method. The pre-gate control method uses a gate signal line waveform of a pixel row selected at least 1H before the pixel row of interest. Therefore, it is not limited to one pixel row before. For example, the driving transistor 11a of the target pixel may be reset by using the signal waveform of the gate signal line two rows before.

The pre-stage gate control method will be described in more detail below. The pixel row of interest is the (N) pixel row, and its gate signal line is the gate signal line 17e.
(N) and the gate signal line 17a (N). In the previous pixel row selected 1H before, the pixel row is the (N-1) pixel row, and its gate signal line is the gate signal line 17e (N-
1) and the gate signal line 17a (N-1). Further, the pixel row selected 1H after the target pixel row is (N + 1)
The pixel signal line is a gate signal line 17e.
(N + 1) and the gate signal line 17a (N + 1).

During the (N-1) Hth period, when the ON voltage is applied to the gate signal line 17a (N-1) of the (N-1) th pixel row, the gate signal line of the (N) th pixel row is applied. 17e (N)
Is also applied with an on-voltage. Gate signal line 17e (N)
This is because the gate signal line 17a (N-1) of the preceding pixel row is formed in a short-circuited state. Therefore,
The transistor 11b (N-
1) is turned on, and the voltage of the source signal line 18 is written in the gate (G) terminal of the driving transistor 11a (N-1). At the same time, the transistor 1 of the pixel in the (N) th pixel row
1e (N) turns on, driving transistor 11a (N)
The gate (G) terminal and the drain (D) terminal are short-circuited, and the driving transistor 11a (N) is reset.

In the (N) th period subsequent to the (N-1) Hth period, when the ON voltage is applied to the gate signal line 17a (N) of the (N) th pixel row, the (N + 1) th pixel row The on-voltage is also applied to the gate signal line 17e (N + 1). Therefore, the transistor 11b of the pixel in the (N) th pixel row is
(N) is turned on, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N). At the same time, the transistor 11e (N + 1) of the pixel in the (N + 1) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N + 1) are short-circuited, and the driving transistor 1
1a (N + 1) is reset.

[0425] Similarly, the (N) th period next to the (Nth)
In the (+1) period, the gate signal line 1 of the (N + 1) th pixel row
When the ON voltage is applied to 7a (N + 1), the (N +
2) The ON voltage is also applied to the gate signal line 17e (N + 2) of the pixel row. Therefore, the transistor 11b (N + 1) of the pixel in the (N + 1) th pixel row is turned on, and the voltage applied to the source signal line 18 is applied to the driving transistor 1
It is written in the gate (G) terminal of 1a (N + 1). At the same time, the transistor 11e of the pixel in the (N + 2) th pixel row
(N + 2) is turned on, and the driving transistor 11a (N +
The gate (G) terminal and the drain (D) terminal of 2) are short-circuited, and the driving transistor 11a (N + 2) is reset.

In the preceding stage gate control system of the present invention,
During the 1H period, the driving transistor 11a is reset,
Then, the voltage (current) program is executed.

The same applies to FIG. 33 (a), but FIG.
When the reset state of (a) and the voltage programmed state of FIG. 44 (b) are synchronized, the period from the reset state of FIG. 44 (a) to the current programmed state of FIG. 44 (b) is There is no problem because it is a fixed value (constant value) (fixed value). If this period is short, the driving transistor 11 is not completely reset. If it is too long, the driving transistor 11a is completely turned off, and it takes a long time to program the current. Also, the brightness of the screen 12 is reduced.

After carrying out FIG. 44 (a), the state shown in FIG. 44 (b) is obtained. FIG. 44B shows a state in which the transistor 11b is turned on and the transistors 11e and 11d are turned off. The state of FIG. 44 (b) is a state in which voltage programming is being performed. That is, the source driver circuit 14 outputs a program voltage, and the program voltage is written to the gate (G) terminal of the driving transistor 11a (the potential of the gate (G) terminal of the driving transistor 11a is set in the capacitor 19). In the case of the voltage programming method, it is not always necessary to turn off the transistor 11d during voltage programming. Also, FIG.
3, N-times pulse driving as shown in FIG. 15 or the like, or intermittent N / K-times pulse driving as described above (a driving method in which a plurality of lighting regions are provided in one screen. This driving method uses the transistor 11e. The transistor 11e is not necessary unless it is necessary to implement (on-off operation). Since this has been described before, the description is omitted.

When the voltage display for white display is performed by the configuration of FIG. 43 or the driving method of FIG. 44, even if the characteristic variation of the driving transistor of each pixel occurs, the offset voltage of each black display state (each The voltage program is performed from the starting voltage at which the current is set according to the characteristics of the driving transistor). Therefore, the time to be programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a, and good image display can be realized.

After the current programming of FIG. 44 (b), as shown in FIG. 44 (c), the transistor 11b is turned off, the transistor 11d is turned on, and the program current from the driving transistor 11a is supplied to the EL element 15. Then, the EL element 15 is caused to emit light.

As described above, in the reset drive of the present invention in the voltage program of FIG. 43, first, the transistor 11d is first turned on and the transistor 11e is turned off in synchronism with the HD synchronizing signal, so that the current is supplied to the transistor 11a. The first operation of flowing the current, disconnecting between the transistor 11a and the EL element 15, and drain (D) terminal and gate (G) terminal (or source (S) terminal and gate (G) terminal) of the driving transistor 11a. More generally, a second operation of short-circuiting between two terminals including the gate (G) terminal of the driving transistor, and a third operation of performing voltage programming on the driving transistor 11a after the operation. And are to be carried out.

In the above embodiments, the transistor 11d is turned on / off to control the current flowing from the drive transistor element 11a (in the case of the pixel configuration of FIG. 1) to the EL element 15. In order to turn on / off the transistor 11d, it is necessary to scan the gate signal line 17b, and the scanning requires the shift register 61 (gate circuit 12). However, the shift register 61 has a large scale, and if the shift register 61 is used to control the gate signal line 17b, the frame cannot be narrowed. The method described in FIG. 40 solves this problem. The present invention is
The pixel configuration of the current program illustrated in FIG. 1 and the like will be mainly described below, but the present invention is not limited to this, and the current programming pixel configuration (current mirror pixel configuration) described in FIG. It goes without saying that it is also applicable. Further, it goes without saying that the technical concept of turning on and off in blocks can be applied to the pixel configuration of voltage programming such as FIG. 41. Further, since the present invention is a method of intermittently flowing the current flowing through the EL element 15, it goes without saying that it can be combined with the method of applying a reverse bias voltage described in FIG. 50 and the like. As described above, the present invention can be implemented in combination with other embodiments. FIG. 40 shows an example of a block drive system. First, for ease of explanation, it is assumed that the gate driver circuit 12 is directly formed on the substrate 71 or that the gate driver IC 12 of a silicon chip is mounted on the substrate 71. The source driver 14 and the source signal line 18 are omitted because the drawing is complicated. In FIG. 40, the gate signal line 17a is connected to the gate driver circuit 12. On the other hand, the gate signal line 17b of each pixel is connected to the lighting control line 401. In FIG. 40, the four gate signal lines 17b are connected to one lighting control line 401. The four gate signal lines 1
It is needless to say that the block at 7b is not limited to this and may be more.
Generally, the display area 50 is preferably divided into at least 5 or more. More preferably, it is preferably divided into 10 or more. Furthermore, it is preferable to divide into 20 or more. If the number of divisions is small, flicker is easy to see.
If the number of divisions is too large, the number of lighting control lines 401 will increase and the layout of the control lines 401 will be difficult. Therefore, in the case of the QCIF display panel, since the number of vertical scanning lines is 220, at least 220/5 =
It is necessary to block 44 or more, and preferably,
It is necessary to form blocks at 220/10 = 11 or more.
However, when two blocks are formed in the odd-numbered row and the even-numbered row, flicker is relatively small even at a low frame rate, and thus the two blocks may be sufficient. Figure 4
In the example of No. 0, the lighting control lines 401a, 401b, 40
ON voltage (Vg
1) is applied or an off voltage (Vgh) is applied to turn on / off the current flowing through the EL element 15 for each block. In the embodiment of FIG. 40, the gate signal line 1
7b and the lighting control line 401 do not cross each other. Therefore, a short defect between the gate signal line 17b and the lighting control line 401 does not occur. Also, the gate signal line 17b
And the lighting control line 401 are not capacitively coupled,
When the gate signal line 17b side is viewed from the lighting control line 401, the capacity addition is extremely small. Therefore, the lighting control line 40
1 is easy to drive. A gate signal line 17a is connected to the gate driver 12. By applying an ON voltage to the gate signal line 17a, a pixel row is selected, and the transistors 11b and 11c of each selected pixel are turned on,
The current (voltage) applied to the source signal line 18 is programmed in the capacitor 19 of each pixel. On the other hand, the gate signal line 17b is connected to the gate (G) terminal of the transistor 11d of each pixel. Therefore, when the ON voltage (Vgl) is applied to the lighting control line 401, a current path is formed between the drive transistor 11a and the EL element 15, and conversely, when the OFF voltage (Vgh) is applied, the EL element 15 is turned on. Open the anode terminal of. The lighting control line 401
It is preferable that the control timing of the on / off voltage applied to the gate driver circuit 12 and the timing of the pixel row selection voltage (Vgl) output to the gate signal line 17a by the gate driver circuit 12 are synchronized with one horizontal scanning clock (1H). However, the present invention is not limited to this. The signal applied to the lighting control line 401 simply turns on / off the current to the EL element 15. Further, it does not need to be synchronized with the image data output by the source driver 14. Lighting control line 401
This is because the signal applied to the pixel controls the current programmed in the capacitor 19 of each pixel 16. Therefore, it does not necessarily have to be synchronized with the selection signal of the pixel row. Further, the clock is not limited to the 1H signal even in the case of synchronization, and even if it is 1 / 2H, the clock is 1H.
It may be / 4H. Even in the case of the current mirror pixel configuration illustrated in FIG. 38, the transistor 11e can be on / off controlled by connecting the gate signal line 17b to the lighting control line 401. Therefore, block driving can be realized. Note that in FIG. 32, if the gate signal line 17a is connected to the lighting control line 401 and a reset is performed, block driving can be realized. That is, the block drive of the present invention is a drive method in which a plurality of pixel rows are simultaneously turned off (or displayed in black) with one control line.

In the above-mentioned embodiments, one selected pixel row is arranged (formed) for each pixel row. The present invention is
The present invention is not limited to this, and one selection gate signal line may be arranged (formed) in a plurality of pixel rows.

FIG. 41 shows an example thereof. For ease of explanation, the pixel configuration will be described mainly by exemplifying the case of FIG. In FIG. 41, the selection gate signal line 17a in the pixel row simultaneously selects three pixels (16R, 16G, 16B). The symbol R means the pixel relation of red, and G
The symbol of means a green pixel relation, and the symbol of B means a blue pixel relation.

Therefore, the pixel 16R, the pixel 16G and the pixel 16B are simultaneously selected by the selection of the gate signal line 17a to be in the data writing state. The pixel 16R writes data from the source signal line 18R to the capacitor 19R, and the pixel 16G writes data from the source signal line 18G to the capacitor 19G. The pixel 16B writes data from the source signal line 18B to the capacitor 19B.

The transistor 11d of the pixel 16R is connected to the gate signal line 17bR. The transistor 11d of the pixel 16G is connected to the gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to the gate signal line 1b.
It is connected to 7bB. Therefore, E of the pixel 16R
L element 15R, pixel 16G EL element 15G, pixel 16
The B EL element 15B can be individually turned on and off. That is, the EL element 15R, the EL element 15G, the EL element
The element 15B has respective gate signal lines 17bR and 17b.
By controlling G and 17bB, the lighting time and the lighting cycle can be individually controlled.

To realize this operation, in the configuration of FIG. 6, a shift register circuit 61 for scanning the gate signal line 17a, a shift register circuit 61 for scanning the gate signal line 17bR, and a gate signal line 17bG are scanned. It is appropriate to form (arrange) four shift register circuits 61 that perform scanning and the shift register circuits 61 that scan the gate signal line 17bB. Note that the source signal line 18 is supplied with a current N times the predetermined current and the EL element 15 is supplied with a current N times the predetermined current for a period of 1 / N, but this cannot be realized in practice. This is because the signal pulse applied to the gate signal line 17 actually penetrates into the capacitor 19 and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set in the capacitor 19. For example, 10
Even if driving is performed so as to set a double current value, only about five times the current is set in the capacitor 19. For example, N
= 10, the current actually flowing in the EL element 15 is N =
It becomes the same as the case of 5. Therefore, the present invention is a method of setting a current value of N times and driving such that a current proportional to or corresponding to N times flows through the EL element 15. Alternatively, it is a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape. In addition, a current higher than a desired value (a current that becomes higher than a desired brightness when a current is continuously applied to the EL element 15 as it is) is applied to the drive transistor 1.
A current (voltage) program is performed on 1a (in the case of exemplifying FIG. 1) to intermittently make the current flowing through the EL element 15 to obtain a desired emission brightness of the EL element. The compensating circuit for punching through the capacitor 19 is introduced in the source driver circuit 14. This matter will be described later.

The switching transistors 11b and 11c shown in FIG. 1 and the like are preferably formed by N-channel. This is because the penetration voltage to the capacitor 19 is reduced. Further, since the off-leakage of the condenser 19 is also reduced, it can be applied to a low frame rate of 10 Hz or less.

Depending on the pixel configuration, when the punch-through voltage acts in the direction of increasing the current flowing through the EL element 15, the white peak current increases and the contrast feeling of image display increases. Therefore, good image display can be realized.

On the contrary, the switching transistor 1 of FIG.
It is also effective to make Pb channels 1b and 11c more punch-through to improve black display. When the P-channel transistor 11b turns off, the voltage becomes Vgh voltage. Therefore, the terminal voltage of the capacitor 19 slightly shifts to the Vdd side. Therefore, the gate (G) terminal voltage of the transistor 11a rises, resulting in a more black display. In addition, since the current value for the first gradation display can be increased (a constant base current can be flown up to gradation 1), the shortage of the write current can be reduced by the current program method.

In addition, the capacitor 1 is positively connected between the gate signal line 17a and the gate (G) terminal of the transistor 11a.
It is also effective to form 9b to increase the punch-through voltage (see FIG. 42 (a)). The capacity of this capacitor 19b is 1/50 or more of the capacity of the regular capacitor 19a 1
It is preferably / 10 or less. Furthermore, it is preferable to set it to 1/40 or more and 1/15 or less. Alternatively, the source-gate (source-drain (S
G) or the gate-drain (GD) capacity is 1 to 10 times. More preferably, the SG capacity is 2
It is preferable that the number of times is 6 times or more. The formation position of the capacitor 19b may be formed or arranged between one terminal of the capacitor 19a (the gate (G) terminal of the transistor 11a) and the source (S) terminal of the transistor 11d. Also in this case, the capacity and the like are the same as the values described above.

The capacitance of the capacitor 19b for generating punch-through voltage (capacitance is Cb (pF)) is the capacitance of the capacitor 19a for charge retention (capacitance and Ca (pF)).
Then, the gate (G) terminal voltage Vw of the transistor 11a at the time of the white peak current (at the time of the white raster of the maximum brightness displayed in the image display) is made to flow the current in the black display (basically the current is 0. The gate (G) terminal voltage Vb at the time of black display in the image display is related. These relationships are as follows: Ca / (200Cb) ≤ | Vw-Vb | ≤ Ca
It is preferable to satisfy the condition of / (8Cb). Note that | Vw-V
b | is the absolute value of the difference between the terminal voltage of the driving transistor when displaying white and the terminal voltage when displaying black (that is, the varying voltage width).

More preferably, Ca / (100Cb) ≤ | Vw-Vb | ≤ Ca
It is preferable to satisfy the condition of / (10Cb).

The transistor 11b is a P channel,
This P channel should be at least a double gate or more. This is preferably triple gate or higher. More preferably, the number of gates is 4 or more. Then, it is preferable to form or dispose capacitors in parallel with the source-gate (SG or gate-drain (GD)) capacitance (capacitance when the transistor is on) of the transistor 11b that is 1 to 10 times.

The above matters are effective not only in the pixel configuration of FIG. 1 but also in other pixel configurations. For example, in FIG.
In the pixel configuration of the current mirror as shown in FIG. 2 (b), a capacitor that causes punch-through is arranged or formed between the gate signal line 17a or 17b and the gate (G) terminal of the transistor 11a. The N channel of the switching transistor 11c has a double gate or more. Alternatively, the switching transistors 11c and 11d
Is a P-channel and has a triple gate or more.

In the configuration of the voltage program of 41,
A capacitor 19 for generating a punch-through voltage between the gate signal line 17c and the gate (G) terminal of the driving transistor 11a.
Form or place c. The switching transistor 11c has a triple gate or more. The capacitor 19c for generating the punch-through voltage may be arranged between the drain (D) terminal (on the capacitor 19b side) of the transistor 11c and the gate signal line 17a. Further, the punch-through voltage generating capacitor 19c may be arranged between the gate (G) terminal of the transistor 11a and the gate signal line 17a. Further, the capacitor 19c for generating the punch-through voltage is the drain (D) terminal (capacitor 1c of the transistor 11c.
9b side) and the gate signal line 17c.

Further, the capacitance of the charge holding capacitor 19a is Ca, and the source-gate capacitance Cc of the switching transistor 11c or 11d (if there is a punch-through capacitor, its capacitance is added). , When a high voltage signal (Vgh) is applied to the gate signal line and a low voltage signal (Vgl) is applied to the gate signal line, a good black display is achieved by configuring the following conditions. Can be realized.

0.05 (V) ≤ (Vgh-Vgl)
X (Cc / Ca) ≤ 0.8 (V) More preferably, the following conditions are satisfied.

0.1 (V) ≦ (Vgh-Vgl) ×
(Cc / Ca) ≤ 0.5 (V) The above items are also effective for the pixel configuration shown in FIG. In the pixel configuration of the voltage program of FIG. 43, the transistor 1
A capacitor 19b for generating punch-through voltage is formed or placed between the gate (G) terminal of 1a and the gate signal line 17a.

The capacitor 19b for generating the punch-through voltage is formed by the source wiring and the gate wiring of the transistor. However, since the source width of the transistor 11 is widened so as to overlap the gate signal line 17, the transistor 11 may not be clearly separated from the transistor in practical use.

Further, the switching transistor 11b,
A method of apparently forming the capacitor 19b for punch-through voltage by forming 11c (in the case of the configuration of FIG. 1) larger than necessary is also within the scope of the present invention. The switching transistors 11b and 11c are often formed with a channel width W / channel length L = 6/6 μm. It is also possible to increase this to W so that the capacitor for punch-through voltage 1
9b will be configured. For example, a W: L ratio of 2:
A configuration in which the ratio is 1 or more and 20: 1 or less is exemplified. Preferably, the W: L ratio is 3: 1 or more and 10: 1 or less.

Further, the capacitor 19b for punch-through voltage
It is preferable to change the size (capacity) of R, G, and B modulated by the pixel. This is because the drive currents of the R, G, and B EL elements 15 are different. This is also because the cutoff voltage of the EL element 15 is different. Therefore, the voltage (current) programmed in the gate (G) terminal of the driving transistor 11a of the EL element 15 is different. For example, when the capacitor 11bR for the R pixel is 0.02 pF, the capacitors 11b for other colors (pixels for G and B) are
G and 11bB are set to 0.025 pF. Further, when the capacitor 11bR of the R pixel is 0.02 pF, the capacitors 11bG and G of the G pixel are 0.03 pF, and the capacitor 11bB of the B pixel is 0.025 pF. In this way, by changing the capacitance of the capacitor 11b for each of the R, G, and B pixels, the offset drive current can be adjusted for each RGB. Therefore, the black display level of each RGB can be set to the optimum value.

In the above, the capacity of the capacitor 19b for generating the punch-through voltage is changed, but the punch-through voltage is
This is a relative capacitance of the holding capacitor 19a and the punch-through voltage generating capacitor 19b. Therefore, the capacitor 19b is not limited to being changed for the R, G, and B pixels. That is, the capacitance of the holding capacitor 19a may be changed. For example, when the capacitor 11aR of the R pixel is 1.0 pF, the capacitors 11aG and G of the G pixel are 1.2 pF, and the capacitor 11aB of the B pixel is 0.9 pF. At this time, the capacitance of the punch-through capacitor 19b is R, G,
B has a common value. Therefore, according to the present invention, the capacitor 19a for holding and the capacitor 1 for generating the punch-through voltage are provided.
9B, at least one of the R, G, and B pixels has a different capacity ratio from the others. Note that both the capacitance of the holding capacitor 19a and the capacitance of the punch-through voltage generating capacitor 19b may be changed for the R, G, and B pixels.

Further, the capacitance of the capacitor 19b for punch-through voltage may be changed between the left and right sides of the screen 50. Since the pixel 16 located near the gate driver 12 is arranged on the signal supply side, the gate signal rises quickly (because the slew rate is high), and thus the punch-through voltage becomes large. Pixels arranged (formed) at the end of the gate signal line 17 have a dull signal waveform (because the gate signal line 17 has a capacitance). This is because the gate signal rises slowly (the slew rate is slow), and the punch-through voltage becomes small. Therefore, the punch-through voltage capacitor 1 of the pixel 16 near the connection side with the gate driver 12
9b is reduced. Further, the end of the gate signal line 17 enlarges the capacitor 19b. For example, the capacitance of the capacitor is changed on the left and right of the screen by about 10%.

The punch-through voltage generated is determined by the capacitance ratio between the holding capacitor 19a and the punch-through voltage generating capacitor 19b. Therefore, although the size of the capacitor 19b for generating the punch-through voltage is changed on the left and right of the screen, the present invention is not limited to this. The punch-through voltage generating capacitor 19b may be constant on the left and right sides of the screen, and the capacitance of the charge holding capacitor 19a may be changed on the left and right sides of the screen. Also, a capacitor 1 for generating punch-through voltage
It goes without saying that both 9b and the capacitance of the charge holding capacitor 19a may be changed on the left and right of the screen.

The problem of the N-fold pulse driving of the present invention is that the current applied to the EL element 15 is instantaneous, but there is a problem that it is N-fold larger than the conventional one. If the current is large, the life of the EL element may be shortened. In order to solve this problem, it is effective to apply the reverse bias voltage Vm to the EL element 15.

In the EL element 15, electrons are injected from the cathode (cathode) into the electron transport layer, and at the same time holes are also injected from the anode (anode) into the hole transport layer. The injected electrons and holes move to the counter electrode due to the applied electric field. that time,
They may be trapped in the organic layer or carriers may be accumulated due to the difference in energy level at the light emitting layer interface.

When space charges are accumulated in the organic layer, the molecules are oxidized or reduced, and the generated radical anion molecules or radical cation molecules are unstable, so that the film quality is deteriorated and the brightness is lowered and the brightness is reduced. It is known that driving voltage during current driving increases. In order to prevent this, as an example, the device structure is changed and a reverse voltage is applied.

When a reverse bias voltage is applied, a reverse current is applied, so the injected electrons and holes are extracted to the cathode and anode, respectively. This eliminates the formation of space charges in the organic layer and suppresses the electrochemical deterioration of the molecules, which makes it possible to prolong the life.

FIG. 45 shows changes in the reverse bias voltage Vm and the terminal voltage of the EL element 15. The terminal voltage is when the rated current is applied to the EL element 15. Figure 4
No. 5 is a case where the current passed through the EL element 15 has a current density of 100 A / square meter, the tendency of FIG.
There was almost no difference from the case of 0 to 100 A / square meter. Therefore, it is estimated that it can be applied in a wide range of current density.

The vertical axis represents the ratio of the initial terminal voltage of the EL element 15 to the terminal voltage after 2500 hours. For example, when the elapsed time is 0 hours, the terminal voltage is 8 (V) when a current density of 100 A / square meter is applied, and the elapsed time is 2500 hours, the current density is 100 A.
/ Terminal voltage when current of square meter is applied is 10
If it is (V), the terminal voltage ratio is 10/8 = 1.25.

The horizontal axis represents the ratio of the rated terminal voltage V0 to the product of the reverse bias voltage Vm and the time t1 when the reverse bias voltage is applied in one cycle. For example, 60Hz (especially 60
However, if the time when the reverse bias voltage Vm is applied is 1/2 (half), t1 = 0.5. Further, at the elapsed time of 0 hours, the current density is 100 A
/ The terminal voltage (rated terminal voltage) when a current of square meter is applied is 8 (V), and the reverse bias voltage Vm is 8
If (V), then | reverse bias voltage × t1 | / (rated terminal voltage × t2) = | −8 (V) × 0.5 | / (8 (V)
× 0.5) = 1.0.

According to FIG. 45, | reverse bias voltage × t1
When | / (rated terminal voltage × t2) is 1.0 or more, the terminal voltage ratio does not change (it does not change from the initial rated terminal voltage). The effect of applying the reverse bias voltage Vm is well exhibited. However, when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 or more, the terminal voltage ratio tends to increase. Therefore, | reverse bias voltage × t1
The magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio of t1 and t2) may be determined so that | / (rated terminal voltage × t2) is 1.0 or more. Further, preferably, | reverse bias voltage × t1 |
The magnitude of the reverse bias voltage Vm and the application time ratio t are set so that / (rated terminal voltage × t2) becomes 1.75 or less.
You may decide 1 or the like.

However, when the bias driving is performed, it is necessary to alternately apply the reverse bias Vm and the rated current.
When it is attempted to equalize the average brightness per unit time of the samples A and B as shown in FIG. 46, when a reverse bias voltage is applied, it is necessary to instantaneously flow a high current as compared with the case where no reverse bias voltage is applied. . Therefore, the reverse bias voltage Vm
EL element 15 when applying a voltage (Sample A in FIG. 46)
The terminal voltage of is also high.

However, in FIG. 45, even in the driving method in which the reverse bias voltage is applied, the rated terminal voltage V0 is the terminal voltage satisfying the average luminance (that is, the terminal voltage for lighting the EL element 15) (this specification). According to the specific example of the book, the terminal voltage when a current having a current density of 200 A / square meter is applied, but since the duty is 1/2, the average luminance of one cycle is 200 A / square meter. Brightness).

The above items assume that the EL element 15 is a white raster display (when the maximum current is applied to the EL elements on the entire screen). However, when displaying an image on the EL display device, it is a natural image, and gradation display is performed. Therefore, the white peak current of the EL element 15 (current flowing at maximum white display; in the specific example of the present specification, average current density of 100 A / square meter of current) does not always flow.

Generally, when displaying images, each EL is
The current applied to the element 15 (current flowing) is about 0.2 times the white peak current (current flowing at the rated terminal voltage. According to the specific example of the present specification, current density is 100 A / square meter current). is there.

Therefore, in the embodiment of FIG. 45, it is necessary to multiply the value on the horizontal axis by 0.2 when displaying an image. Therefore, | reverse bias voltage × t1 | /
The magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio between t1 and t2) may be determined so that (rated terminal voltage × t2) is 0.2 or more. Further, preferably, | reverse bias voltage × t1 |
/ (Rated terminal voltage x t2) is 1.75 x 0.2 = 0.3
The magnitude of the reverse bias voltage Vm, the application time ratio t1 and the like may be determined so as to be 5 or less.

That is, on the horizontal axis of FIG. 45 (| reverse bias voltage × t1 | / (rated terminal voltage × t2)), 1.0
The value of must be 0.2. Therefore, when displaying an image on the display panel (this usage state is normal, the white raster will not always be displayed),
The reverse bias voltage Vm is applied for a predetermined time t1 so that the reverse bias voltage × t1 | / (rated terminal voltage × t2) becomes larger than 0.2. Further, even if the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) becomes large, the increase in the terminal voltage ratio is not large as shown in FIG. Therefore, considering the white raster display as the upper limit, | reverse bias voltage × t1 | /
The value of (rated terminal voltage × t2) may be set to satisfy 1.75 or less.

The reverse bias method of the present invention will be described below with reference to the drawings. In the present invention, the reverse bias voltage Vm
It is basically applied (current). However, the present invention is not limited to this. For example, the reverse bias voltage Vm may be forcibly applied while a current is flowing through the EL element 15. In this case, as a result, no current will flow through the EL element 15, and the EL element 15 will be in a non-lighting state (black display state). Further, although the present invention is mainly described by applying the reverse bias voltage Vm in the pixel configuration of the current program, the present invention is not limited to this.

In the pixel structure of the reverse bias drive, as shown in FIG. 47, the transistor 11g is an N channel. Of course, the P channel may be used.

In FIG. 47, by making the voltage applied to the gate potential control line 473 higher than the voltage applied to the reverse bias line 471, the transistor 11g (N) is turned on and the anode electrode of the EL element 15 is turned on. Reverse bias voltage Vm is applied.

Further, in the pixel structure of FIG. 47 or the like, the gate potential control line 473 may always be fixed in potential and operated. For example, in FIG. 47, the Vk voltage is 0 (V).
In that case, the potential of the gate potential control line 473 is set to 0 (V) or higher (preferably 2 (V) or higher). Note that this potential is Vsg. In this state, the potential of the reverse bias line 471 is set to the reverse bias voltage Vm (0 (V) or less, preferably V
When the voltage is smaller than k by −5 (V) or more), the transistor 11g (N) is turned on, and the reverse bias voltage Vm is applied to the anode of the EL element 15. Reverse bias line 4
71 is the voltage of the gate potential control line 473 (that is,
When the voltage is higher than the gate (G) terminal voltage of the transistor 11g), the transistor 11g is in the off state,
The reverse bias voltage Vm is not applied to the EL element 15.
Needless to say, the reverse bias line 471 may be in a high impedance state (open state or the like) in this state.

Further, as shown in FIG. 48, the gate driver circuit 12c for controlling the reverse bias line 471 may be separately formed or arranged. Gate driver circuit 12c
Shift sequentially in the same manner as the gate driver circuit 12a, and the position to which the reverse bias voltage is applied is shifted in synchronization with the shift operation.

In the above driving method, the transistor 11g
The gate (G) terminal of the
The reverse bias voltage Vm can be applied to the EL element 15 only by changing the potential of the. Therefore, it is easy to control the application of the reverse bias voltage Vm. Further, the voltage applied between the gate (G) terminal and the source (S) terminal of the transistor 11g can be reduced. This is the same when the transistor 11g is a P channel.

The reverse bias voltage Vm is applied by EL
This is done when no current is flowing through the element 15. Therefore, when the transistor 11d is not turned on,
This may be done by turning on the transistor 11g. That is, the reverse of the on / off logic of the transistor 11d may be applied to the gate potential control line 473. For example, in FIG. 47, the transistor 1 is connected to the gate signal line 17b.
1d and the gate (G) terminal of the transistor 11g may be connected. Since the transistor 11d is a P channel and the transistor 11g is an N channel, the on / off operation is opposite.

FIG. 49 is a timing chart of reverse bias drive. In the chart, subscripts such as (1) and (2) indicate pixel rows. For ease of description, (1) will be described as the first pixel row and (2) will be described as the second pixel row, but the present invention is not limited to this. (1) shows the Nth pixel row, and (2) shows N pixel rows.
It may be considered to indicate the + 1st pixel row. The above is the same in other embodiments except for special cases. Further, in the embodiment shown in FIG. 49 and the like, the pixel configuration shown in FIG. 1 and the like will be described as an example, but the present invention is not limited to this. For example, in FIG.
The present invention can also be applied to the pixel configurations shown in FIG.

The gate signal line 17a (1) of the first pixel row
When the ON voltage (Vgl) is applied to the gate signal line 17b (1) of the first pixel row, the OFF voltage (Vg
h) is applied. That is, the transistor 11d is off, and no current flows in the EL element 15.

The reverse bias line 471 (1) is applied with the Vsl voltage (voltage at which the transistor 11g turns on). Therefore, the transistor 11g is turned on, and the reverse bias voltage is applied to the EL element 15. The reverse bias voltage is applied after a predetermined period (1/200 or more of 1H or 0.5 μsec) after the off voltage (Vgh) is applied to the gate signal line 17b. Also, the on-voltage (V
The reverse bias voltage is turned off before a predetermined period (1/200 or more of 1H or 0.5 μsec) in which gl) is applied. This is to prevent the transistors 11d and 11g from turning on at the same time.

In the next horizontal scanning period (1H), the off voltage (Vgh) is applied to the gate signal line 17a, and the second pixel row is selected. That is, the gate signal line 17b (2)
ON voltage is applied to the. On the other hand, an on-voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d
Is turned on, current flows from the transistor 11a to the EL element 15, and the EL element 15 emits light. Further, the off voltage (Vsh) is applied to the reverse bias line 471 (1), and the reverse bias voltage is not applied to the EL element 15 of the first pixel row (1). Reverse bias line 47 of the second pixel row
The Vsl voltage (reverse bias voltage) is applied to 1 (2).

By repeating the above operation in sequence,
The image on one screen is rewritten. In the above embodiments, the reverse bias voltage is applied during the period programmed in each pixel. However, the circuit configuration of FIG. 48 is not limited to this. It is obvious that the reverse bias voltage can be continuously applied to a plurality of pixel rows. Also, block drive (see FIG. 40) and N
It is obvious that the double pulse driving, the reset driving, and the dummy pixel driving can be combined.

Although the above-described embodiment has been applied to the pixel configuration shown in FIG. 1, it is needless to say that the present invention can be applied to other configurations such as those shown in FIGS. 38 and 41 for applying a reverse bias voltage. For example, FIG. 50 shows a pixel configuration of a current programming method.

FIG. 50 shows the pixel configuration of the current mirror. The transistor 11c is a pixel selection element. The transistor 11c is turned on by applying an on-voltage to the gate signal line 17a1. The transistor 11d is a switch element having a reset function and a function of short-circuiting (GD short-circuiting) the drain (D) -gate (G) terminals of the driving transistor 11a. The transistor 11d is turned on by applying an on voltage to the gate signal line 17a2.

The transistor 11d is turned on at least 1H (one horizontal scanning period, that is, one pixel row) before the corresponding pixel is selected. Preferably, it is turned on before 3H. If it is 3H before, the transistor 11d is turned on before 3H, and the gate (G) terminal and the drain (D) terminal of the transistor 11a are short-circuited. Therefore, the transistor 11a is turned off. Therefore, no current flows through the transistor 11b, and the EL element 15 is turned off.

When the EL element 15 is in a non-lighting state, the transistor 11g is turned on and a reverse bias voltage is applied to the EL element 15. Therefore, the reverse bias voltage is applied while the transistor 11d is on. Therefore, in terms of logic, the transistor 11d and the transistor 11g are turned on at the same time.

The gate (G) terminal of the transistor 11g is fixed by applying the Vsg voltage. By applying a reverse bias voltage that is sufficiently smaller than the Vsg voltage to the reverse bias line 471, the transistor 11g is turned on.

Thereafter, when a horizontal scanning period in which a video signal is applied (written) to the corresponding pixel comes, an ON voltage is applied to the gate signal line 17a1 and the transistor 1 is applied.
1c turns on. Therefore, the source driver circuit 14
The video signal voltage output from the source signal line 18 to the source signal line 18 is applied to the capacitor 19 (the transistor 11d is kept in the ON state).

When the transistor 11d is turned on, black display is performed. The longer the ON period of the transistor 11d in one field (one frame) period, the longer the ratio of the black display period. Therefore, in order to set the average luminance of one field (one frame) to a desired value even if there is a black display period, it is necessary to increase the luminance of the display period. That is, it is necessary to increase the current supplied to the EL element 15 during the display period. This operation is the N-fold pulse driving of the present invention. Therefore, N times pulse driving and the transistor 11 are performed.
One of the characteristic operations of the present invention is to combine the driving for turning on d to display black. Further, it is a characteristic configuration (method) of the present invention that a reverse bias voltage is applied to the EL element 15 when the EL element 15 is in a non-lighting state.

In the above embodiment, when displaying an image,
Although the method of applying the reverse bias voltage when the pixel is not illuminated is not limited to this, the configuration of applying the reverse bias voltage. If the reverse bias voltage is applied without displaying the image, it is not necessary to form the reverse bias TFT 11g in each pixel. The non-lighting state is a configuration in which the reverse bias voltage is applied after the use of the display panel is finished or before the use.

For example, in the pixel configuration of FIG.
6 is selected (TFT 11b and TFT 11c are turned on), the source driver IC (circuit) 14 outputs a low voltage V0 (for example, GND) that the source driver IC can output.
Voltage is output and applied to the drain terminal (D) of the driving TFT 11a. If the TFT 11d is also turned on in this state, the V0 voltage is applied to the anode terminal of the EL. At the same time, with respect to the V0 voltage at the cathode Vk of the EL element 15, −
A reverse bias voltage is applied to the EL element 15 by applying a voltage Vm which is lower by 5 to -15 (V). Further, the Vdd voltage is also applied a voltage that is 0 to −5 (V) lower than the V0 voltage, so that the TFT 11a is also turned off. By outputting the voltage from the source driver circuit 14 and controlling the gate signal line 17 as described above, the reverse bias voltage is changed to EL.
It can be applied to the element 15.

In the N-fold pulse driving, even if black display is performed once within one field (one frame) period, the
A predetermined current (a programmed current (depending on the voltage held in the capacitor 19)) can be passed through the L element 15. However, in the configuration of FIG. 50, once the transistor 11d is turned on, the electric charge of the capacitor 19 is discharged (including reduction), so that a predetermined current (a programmed current cannot flow in the EL element 15). The circuit operation is easy.

In the above embodiments, the pixel has a pixel configuration of current programming. However, the present invention is not limited to this, and pixel configurations of other current methods as shown in FIGS. 38 and 50 are also possible. Can be applied. Also, FIG. 51 and FIG.
4, it is also applicable to the pixel configuration of the voltage program as shown in FIG.

FIG. 51 is generally the simplest pixel configuration for voltage programming. The transistor 11b is the selection switching element, and the transistor 11a is the EL element 15
It is a driving transistor for applying a current to the. With this configuration, a transistor (switching element) 11g for applying a reverse bias voltage is arranged (formed) on the anode of the EL element 15.

In the pixel configuration of FIG. 51, the current flowing through the EL element 15 is applied to the source signal line 18 and selected by the transistor 11b, so that it is applied to the gate (G) terminal of the transistor 11a.

First, in order to explain the configuration of FIG. 51, the basic operation will be described with reference to FIG. The pixel configuration of FIG. 51 is a configuration called a voltage offset canceller,
It operates in four stages: initialization operation, reset operation, program operation, and light emission operation.

After the horizontal synchronizing signal (HD), the initialization operation is carried out. ON voltage is applied to the gate signal line 17b,
The transistor 11g turns on. Also, the gate signal line 1
The on-voltage is also applied to 7a, and the transistor 11c is turned on. At this time, the Vdd voltage is applied to the source signal line 18. Therefore, the Vdd voltage is applied to the a terminal of the capacitor 19b. In this state, the driving transistor 11a is turned on, and a slight current flows through the EL element 15. This current causes the driving transistor 11
The drain (D) terminal of a is at least the transistor 11
The absolute voltage value is larger than the operating point of a.

Next, the reset operation is carried out. The off voltage is applied to the gate signal line 17b, and the transistor 11e
Turns off. On the other hand, during the period of T1 on the gate signal line 17c,
The on voltage is applied, and the transistor 11b is turned on.
This T1 period is a reset period. The ON voltage is continuously applied to the gate signal line 17a for the period of 1H. Note that T1 is preferably a period of 20% or more and 90% or less of the 1H period. Alternatively, the time is preferably 20 μsec or more and 160 μsec or less. In addition, the capacitor 19b (Cb) and the capacitor 19a (C
The capacity ratio of a) is preferably Cb: Ca = 6: 1 or more and 1: 2 or less.

In the reset period, the gate (G) of the driving transistor 11a is turned on by turning on the transistor 11b.
The terminal and the drain (D) terminal are short-circuited. Therefore, the gate (G) terminal voltage and the drain (D) terminal voltage of the transistor 11a become equal,
a is in an offset state (reset state: state in which no current flows). This reset state means the transistor 11a
The gate (G) terminal of is close to the starting voltage at which the current starts to flow. The gate voltage for maintaining this reset state is held at the b terminal of the capacitor 19b. Therefore, the capacitor 19 holds the offset voltage (reset voltage).

In the next programmed state, the gate signal line 1
An off voltage is applied to 7c to turn off the transistor 11b. On the other hand, the source signal line 18 has DAT for the period of Td.
A voltage is applied. Therefore, to the gate (G) terminal of the driving transistor 11a, the one to which the DATA voltage + the offset voltage (reset voltage) is added is applied. Therefore, the driving transistor 11a can flow the programmed current.

After the programming period, an off voltage is applied to the gate signal line 17a, the transistor 11c is turned off, and the driving transistor 11a is turned on by the source signal line 18.
Separated from. Further, an off voltage is applied to the gate signal line 17c, the transistor 11b is turned off, and this off state is maintained for a period of 1F. On the other hand, the gate signal line 1
An on-voltage and an off-voltage are periodically applied to 7b as needed. That is, even better image display can be realized by combining with N times pulse driving as shown in FIGS. 13 and 15 or by combining with interlace driving.

In the drive system of FIG. 52, the capacitor 19 holds the starting current voltage (offset voltage, reset voltage) of the transistor 11a in the reset state. Therefore, the darkest black display state is when the reset voltage is applied to the gate (G) terminal of the transistor 11a. However, due to the coupling between the source signal line 18 and the pixel 16, the punch-through voltage to the capacitor 19 or the punch-through of the transistor, black floating (decrease in contrast) occurs. Therefore, the driving method described with reference to FIG. 53 cannot increase the display contrast.

In order to apply the reverse bias voltage Vm to the EL element 15, it is necessary to turn off the transistor 11a. In order to turn off the transistor 11a, the Vdd terminal and the gate (G) terminal of the transistor 11a may be short-circuited. This configuration will be described later with reference to FIG.

Further, the Vdd voltage or the voltage for turning off the transistor 11a may be applied to the source signal line 18, and the transistor 11b may be turned on to apply it to the gate (G) terminal of the transistor 11a. This voltage turns off the transistor 11a (or puts it in a state in which almost no current flows (substantially off state: the transistor 11a is in a high impedance state)). Then, the transistor 11g is turned on to apply a reverse bias voltage to the EL element 15. The reverse bias voltage Vm may be applied to all pixels at the same time. That is, a voltage that substantially turns off the transistor 11a is applied to the source signal line 18 to turn on the transistors 11b in all (a plurality of) pixel rows. Therefore, the transistor 11a is turned off. Then, the transistor 11g is turned on, and a reverse bias voltage is applied to the EL element 15. After that, a video signal is sequentially applied to each pixel row to display an image on the display device.

Next, reset driving in the pixel configuration of FIG. 51 will be described. FIG. 53 is an example thereof.
As shown in FIG. 53, the gate signal line 17a connected to the gate (G) terminal of the transistor 11c of the pixel 16a is also connected to the gate (G) terminal of the reset transistor 11b of the next-stage pixel 16b. Similarly, the gate signal line 17a connected to the gate (G) terminal of the transistor 11c of the pixel 16b is connected to the gate (G) terminal of the reset transistor 11b of the next-stage pixel 16c.

Therefore, the transistor 1 of the pixel 16a is
Gate signal line 17 connected to the gate (G) terminal of 1c
When the ON voltage is applied to a, the pixel 16a enters the voltage program state, the reset transistor 11b of the next-stage pixel 16b turns on, and the driving transistor 11a of the pixel 16b enters the reset state. Similarly, pixel 16
When an on-voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c of FIG.
6b is in the current program state and the next-stage pixel 1
The resetting transistor 11b of 6c is turned on, and the pixel 1
The driving transistor 11a of 6c is reset. Therefore, it is possible to easily realize the reset drive by the front gate control method. Further, the number of gate signal lines drawn out for each pixel can be reduced.

This will be described in more detail. It is assumed that a voltage is applied to the gate signal line 17 as shown in FIG.
That is, it is assumed that the ON voltage is applied to the gate signal line 17a of the pixel 16a and the OFF voltage is applied to the gate signal line 17a of the other pixel 16. Also, the gate signal line 17b
Is applied with an off voltage to the pixels 16a and 16b,
It is assumed that an on-voltage is applied to 6c and 16d.

In this state, the pixel 16a is not illuminated in the voltage program state, and the pixel 16b is not illuminated in the reset state.
Pixel 16c lights up while holding the program current, pixel 1
6d is a lighting state in which the program current is held.

After 1H, the data in the shift register circuit 61 of the control gate driver circuit 12 is shifted by 1 bit, and the state shown in FIG. 53 (b) is obtained. In the state of FIG. 53B, the pixel 16a is lit in the program current holding state, the pixel 16b is not lit in the current program state, the pixel 16c is unlit in the reset state, and the pixel 16d is lit in the program holding state.

From the above, in each pixel, the driving transistor 11a of the pixel of the next stage is reset by the voltage of the gate signal line 17a applied to the previous stage, and the voltage program is sequentially performed in the next horizontal scanning period. I understand.

The pre-stage gate control can also be realized by the pixel configuration of the voltage program shown in FIG. FIG. 54 shows an embodiment in which the pixel configuration of FIG. 43 is connected by the pre-gate control method.

As shown in FIG. 54, the gate signal line 17a connected to the gate (G) terminal of the transistor 11b of the pixel 16a is the reset transistor 1 of the next-stage pixel 16b.
It is connected to the gate (G) terminal of 1e. Similarly, the gate signal line 17a connected to the gate (G) terminal of the transistor 11b of the pixel 16b is connected to the gate (G) terminal of the resetting transistor 11e of the next-stage pixel 16c.

Therefore, the transistor 1 of the pixel 16a is
Gate signal line 17 connected to the gate (G) terminal of 1b
When the ON voltage is applied to a, the pixel 16a enters the voltage program state, the reset transistor 11e of the next-stage pixel 16b turns on, and the driving transistor 11a of the pixel 16b enters the reset state. Similarly, pixel 16
When the on-voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b of the pixel b, the pixel 1
6b is in the current program state and the next-stage pixel 1
The resetting transistor 11e of 6c is turned on, and the pixel 1
The driving transistor 11a of 6c is reset. Therefore, it is possible to easily realize the reset drive by the front gate control method.

This will be described in more detail. It is assumed that a voltage is applied to the gate signal line 17 as shown in FIG. 55 (a).
That is, it is assumed that the ON voltage is applied to the gate signal line 17a of the pixel 16a and the OFF voltage is applied to the gate signal line 17a of the other pixel 16. Further, it is assumed that all reverse bias transistors 11g are in the off state.

In this state, the pixel 16a is in the voltage program state, the pixel 16b is in the reset state, the pixel 16c is in the program current holding state, and the pixel 16d is in the program current holding state.

After 1H, the data in the shift register circuit 61 of the control gate driver circuit 12 is shifted by 1 bit, and the state shown in FIG. 55 (b) is obtained. In the state of FIG. 55B, the pixel 16a is in the program current holding state, and the pixel 16b is
Indicates a current program state, the pixel 16c is in a reset state, and the pixel 16d is in a program holding state.

From the above, in each pixel, the driving transistor 11a of the pixel of the next stage is reset by the voltage of the gate signal line 17a applied to the previous stage, and the voltage program is sequentially performed in the next horizontal scanning period. I understand.

The source driver circuit (IC) 14 of the present invention will be described below with reference to the drawings. The source driver circuit 14 is not only an IC formed of a semiconductor silicon chip, but also a polysilicon technology such as low-temperature polysilicon or high-temperature polysilicon.
Also included are those formed directly on the.

A first object of the source driver 14 of the present invention relates to a circuit configuration of a driver IC for driving a display device, which mainly realizes low power consumption and shortens the blanking period. It is intended to realize high display quality. The second purpose is to realize a good current drive system for the EL display panel and to achieve both high contrast display and high resolution.

The first aspect of the present invention will now be described with reference to the drawings.
A driver configuration and a driving method thereof that achieve the above object will be described.

A display panel such as a liquid crystal display panel or an organic EL display panel is composed of display elements in which a plurality of scanning lines (gate signal lines 17) and a plurality of video signal lines (source signal lines 18) are arranged in a matrix. ing. In order to drive the display panel, the gate signal line 17 side uses a gate driver circuit 14 incorporated by a technique such as low temperature polysilicon,
On the source signal line 18 side, a method in which the source driver IC 14 made of single crystal silicon is mounted by COG (chip on glass) is becoming mainstream. As a configuration of the source driver IC 14 made of single crystal silicon for driving the source signal line 18, a mobile phone display panel such as a mobile phone or a PDA having a display memory built-in is the mainstream. In addition,
The display panel of monitors and TVs does not have a built-in display memory.

FIG. 102 shows a general structure of the source driver IC 14 having no built-in display memory. Figure 10
2, 1021 is a shift register with clock stop, 1022 is an input stage latch, 1023 is a first stage latch, 1024 is a second stage latch, 1025 is a D / A converter, and 1026 is an output buffer.

Display data DR0-DR5 of 6-bit RGB, DG0-DG5, DB0-DB5, which are serially sent from the controller in synchronization with the original clock, are
After being latched in the input stage latch once, it is sequentially latched in the first stage latch according to the latch signal output from the shift register. After one horizontal period, the output signals of the first-stage latches are simultaneously latched by the second-stage latches by the latch signal LD synchronized with the horizontal synchronizing pulse. The output signal of the second stage latch is converted into an analog voltage by the D / A converter, and the display element is turned on through the output buffer.
Generally, the signal line driving driver IC having no built-in display memory is composed of a shift register with a clock stop, as described above.

FIG. 103 shows the configuration of a general shift register with clock stop. In FIG. 103, 103
Reference numeral 1 represents a D-type flip-flop that constitutes a shift register, and 1032 represents a clock stop circuit.

As the operating principle of the shift register with clock stop shown in FIG. 103, while the start pulse signal is input from the shift register of the previous stage or the shift register of its own stage is outputting the start pulse signal, Since the start pulse signal is passing through the shift register of the own stage, the clock signal FY is supplied to the clock terminal of the shift register of the own stage. Otherwise, clock signal F
By cutting off the input of Y, unnecessary operation of the shift register is eliminated and low power consumption is realized.

The circuit that realizes this function is the clock stop circuit 1032 in FIG. That is, as indicated by 1032, the logical sum of the output signal of the shift register of the previous stage and the output signal of the shift register of the own stage and the clock signal F
By inputting the logical product with Y to the clock terminal of the D-type flip-flop, the shift register of the own stage operates only when the start pulse signal is passing through the shift register of the own stage, and other than that, the shift register of the own stage is operated. The shift register does not work. With such a configuration, the power consumption of the shift register can be reduced from several mW to several 100 μW, and low power consumption can be realized.

However, in such a shift register with a clock stop, it takes several clocks until the first display data is latched by the first stage latch after the start pulse is input, and the blanking period is set longer by that amount. It is indispensable and causes the deterioration of display quality such as occurrence of flicker.

FIG. 104 shows a timing chart of the shift register with clock stop. As shown in FIG. 104, the start pulse S is generated at the rising of the original oscillation clock FY.
If T is input, the reset signal RST is generated, the divided clock FYS is oscillated, and the shift register is operated based on the start pulse STS internally adjusted to 2 clocks, the first stage, Second stage, third stage ...
.. The output waveforms of the shift registers are G1, G2, G
3, ...

After the start pulse ST is input, the first data is latched in the first-stage latch at the falling edge of the output signal G1 of the first-stage shift register. In order to latch with, the input data must be input 2.5 clocks after the start pulse is input. That is, it is necessary to set the blanking period longer, and the display quality such as occurrence of flicker is reduced.

FIG. 95 shows the source driver circuit 1 of the present invention.
4 shows a shift register unit of No. 4. In FIG. 95, 951
Is a D-type flip-flop forming a shift register, 9
Reference numeral 52 is a circuit for taking the logical product of the normal output signal of the shift register of its own stage and the inverted output signal of the latter stage shift register as the output signal of the shift register.

Note that the source driver circuit 14 is described as an example for ease of explanation, but the present invention is not limited to this, and it is needless to say that the present invention can be applied to the gate driver circuit 12.

[0531] Further, 953 is a dummy shift register added after the final stage shift register, and 954 is a self-stage based on the logical sum of the normal output signal of the previous shift register and the normal output signal of the own shift register. It is a circuit for cutting off the input of the clock signal of the shift register. The operation of the shift register with clock stop in the source driver circuit 14 of the present invention will be described below.

In FIG. 95, the output G1 of the first stage of the shift register is not the shift register output, but the start pulse S adjusted to the length of two clocks of the original oscillation clock.
Use TS. If the shift register output was used, as described above, the data immediately after the start pulse could not be latched in the first stage latch, and the 2.5
This is because there is no choice but to input data after the clock.

FIG. 96 shows a timing chart of the present invention. In FIG. 96, a start pulse STS adjusted to have a length of two clocks of the original oscillation clock is generated from the input start pulse ST. By using this STS as the output of the first stage of the shift register, the data after the input stage is latched is latched at the falling edge of STS.
Data can be latched earlier than when the shift register output as shown in 03 is used as the output of the first stage.

Further, in the present invention, the normal output signal Q of the D-type flip-flop is used as the output signal G of the shift register.
Is not output as it is, but the logical product of the normal output signal Q _n of the flip-flop of the current stage and the inverted output signal NQ _{n + 1} of the flip-flop of the subsequent stage is used as the output signal G _n of the shift register of the current stage. . With such a configuration, as shown in FIG. 97, the normal output signal Q of the flip-flop is output.
Since it falls 0.5 shift clock (FYS) earlier than _n , the data can be latched earlier accordingly.

A circuit that realizes this function is shown at 95 in FIG.
It is a dotted line portion shown in FIG. Regarding the output of the final stage, there is no output of the shift register of the subsequent stage, so this function cannot be realized. Therefore, as shown in FIG. 95, by adding a dummy shift register in the rear stage of the final stage, the output waveform of the shift register in the final stage can also fall 0.5 shift clock (FYS) earlier.

With the circuit configuration of the present invention described above, FIG.
As shown in FIG. 6, if data is input with a delay of one clock of the original clock after the start pulse is input, the data after the input stage latch can be latched in the first stage latch in the middle. In the conventional shift register with a clock stop, as described above, since the data must be input with a delay of 2.5 clocks of the original clock after the start pulse is input, the blanking period can be shortened by the present invention. Thus, it is possible to suppress the occurrence of flicker and the like, and it becomes possible to perform high-quality display.

As for the circuit configuration of the shift register with clock stop, as shown in FIG. 95, the own stage shift is performed by the logical sum of the normal output signal of the preceding shift register and the normal output signal of the own shift register. It is realized by cutting off the input of the clock signal of the register. Fig. 98
As shown in, the clock signal is input to the self-stage shift register to operate only during the period when the start pulse passes through the self-stage shift register, so that low power consumption can be realized.

FIG. 99 shows the second embodiment of the present invention. FIG. 99 shows a circuit for generating a reset signal RST having a length of one clock of the original clock, a shift clock signal FYS which is a divided clock of the original clock, and a start pulse signal STS having a length of two clocks of the original clock of the present invention. .

In FIG. 99, reference numeral 991 is a reset signal generator having one clock length of the original clock, 992 is a shift clock signal generator which is a divided clock of the original clock,
Reference numeral 993 is a start pulse signal generator having a length of 2 clocks of the original oscillation clock. FIG. 100 shows a timing chart of each part. Hereinafter, a method of generating various control signals will be described.

First, a method of generating a reset signal of one clock length of the original clock will be described. The present invention has a configuration of a reset circuit for generating a reset signal having a length of one clock of an original clock, and a normal output of a first D-type flip-flop that holds an input start pulse at the rising edge of the original clock, It is characterized in that it is constituted by an inverted logical product with the inverted output of the second D-type flip-flop that holds the non-inverted output at the rising edge of the original clock.

As shown in the timing chart of FIG. 100, the operation of the reset signal generator 991 of FIG. 99 is the normal signal of the D-type flip-flop which holds the input start pulse ST at the rising of the original clock FY. A
And the inverted logical product of the signal and the inverted signal B of the D-type flip-flop which is held with a delay of one source clock, thereby generating the reset signal RST having a length of one clock of the source clock. The reset signal resets the D-type flip-flop that forms the shift register and the D-type flip-flop that creates the shift clock by dividing the original clock.

Next, a method of generating a shift clock signal which is a divided clock of the original clock will be described. The present invention provides, as a shift clock for operating the shift register, a third D-type flip-flop that divides the original clock by a falling edge of the original clock, and resets the original clock with one clock length. It is characterized by being generated by a signal.

As shown in the timing chart of FIG. 100, the operation of the shift clock signal generation unit 992 of FIG. 99 is the inversion of the D-type flip-flop which holds the input original clock FY at the falling edge of the original clock. By using the signal as the input signal, the shift clock FYS divided at the falling edge of the original oscillation clock is generated. As a result, after the reset operation is released by the reset signal, it is possible to generate a shift clock that operates with a delay of 0.5 clock of the original clock.

Next, a method of generating a start pulse signal having a two clock length of the original clock will be described. The present invention is
As a configuration of a circuit that generates a start pulse adjusted to the two clock length of the original clock, an inverted signal of the reset signal having one clock length of the original clock and the inverted signal are held at the rising edge of the original clock. It is characterized in that it is constituted by a logical sum with the non-inverted output of the fourth D-type flip-flop.

As shown in the timing chart of FIG. 100, the operation of the start pulse signal generating section of FIG. 99 is the inversion signal C of the reset signal of one clock length of the original clock.
And the inversion signal thereof is ORed with the non-inverted output D of the fourth D-type flip-flop which holds the rising edge of the original clock, the start pulse STH adjusted to the two clock length of the original clock is obtained. Is generated.

The operation of various control signals for controlling the shift register with clock stop generated by the circuit configuration according to the present invention will be described with reference to FIG. Figure 10
At 0, when the start pulse ST is input, the reset signal RST is generated at the rising of the original oscillation clock, and the shift clock and the shift register of each stage are reset. The shift clock FYS is
It is generated in synchronization with the falling edge of the original oscillation clock with a delay of 0.5 original oscillation clock. On the other hand, the input start pulse S
From T, the start pulse STH adjusted to the two clock length of the original oscillation clock is generated.

The output Q1 of the first-stage shift register is the start pulse STH adjusted to this 2 clock length, and thereafter, in synchronization with the shift clock, the output Q2 of the second-stage shift register and the output of the third-stage shift register STH. Output Q of shift register
3, ... Is output. The outputs Q1, Q2, Q3, ... Of these shift registers are logically ANDed with the inversion outputs of the subsequent stages to generate G1, G2, G3, ...
It is transformed into the waveform of and becomes the latch signal of the first stage. When the display data is input with a delay of one clock of the original oscillation clock after the start pulse ST is input, the display data is latched in the first stage latch in the middle of the data after the input stage latch. That is,
The blanking period can be shortened and high quality display can be realized.

In order to realize low power consumption, the shift register with clock stop described above is operated by inputting the clock signal to the D-type flip-flop only while the start pulse is passing. The source driver circuit 14 described next is to realize low power consumption by stopping the shift clock during the blanking period.

In order to realize this, the present invention is characterized in that the shift clock is stopped during the blanking period. Then, as means for stopping the shift clock during the blanking period, the first D-type flip-flop for holding the output signal of the shift register at the final stage at the rising edge of the original clock causes normal rotation output of the first D-type flip-flop. The dividing operation of the D-type flip-flop is stopped, and the dividing operation of the first D-type flip-flop is started by resetting the fifth D-type flip-flop by a reset signal. .

FIG. 101 shows the blanking period of the present invention,
The circuit configuration for stopping the operation of the shift clock is shown. In FIG. 101, 71 is a first D-type flip-flop,
72 is a fifth D-type flip-flop. The operation of FIG. 101 will be described. The output signal G176 of the final-stage shift register is detected by the fifth D-type flip-flop.

That is, the output signal G176 of the final stage shift register (the output number of the QCIF panel is 176 × RGB).
Becomes high, the non-inverted output of the fifth D-type flip-flop always becomes HIGH. Then, since the HIGH signal is always input to the first D-type flip-flop that divides the original clock to generate the shift clock, its output is fixed at HIGH and the generation of the shift clock is stopped. The reset signal is input to the fifth D-type flip-flop and the first reset pulse when the start pulse is input.
When it is input to the D-type flip-flop, the shift clock is generated in the initial state.

With the above operation, the shift clock is not generated during the blanking period from the output of the final-stage shift register to the input of the start pulse, so that the power consumption on the clock line can be reduced and the low power consumption can be achieved. Electricity can be realized.

As described above, the source driver circuit (IC) 14 using the shift register with clock stop according to the present invention.
Then, when the start pulse does not pass, the shift register stops operating, and the shift clock stops operating during the blanking period, so low power consumption can be realized.
Moreover, since the display data can be input with a delay of one original oscillation clock after the input of the start pulse, the blanking period can be set short. Further, it is possible to realize high quality display by suppressing the occurrence of flicker and the like.

The current-driven source driver IC (circuit) 14 of the present invention will be described below. First, FIG.
Fig. 2 shows an example of a conventional current-driven driver circuit. However, such a current driver IC does not exist, but the current driver type source driver I of the present invention is used.
This is a principle for explaining C.

In FIG. 72, 721 is a D / A converter. An n-bit data signal is input to the D / A converter 721, and an analog signal is output from the D / A converter based on the input data. This analog signal is input to the operational amplifier 722. The operational amplifier 722 is input to the N-channel transistor 631a, and the current flowing through the transistor 631a flows through the resistor 691. The terminal voltage of the resistor R serves as the-input of the operational amplifier 722, and the voltage at this-terminal and the positive terminal of the operational amplifier 722 are the same voltage. Therefore, the output voltage of the D / A converter 721 is the resistance 6
It becomes the terminal voltage of 91.

Now, assume that the resistance value of the resistor 691 is 1 MΩ and D
If the output of the A / A converter 721 is 1 (V), the resistance 69
A current of 1 (V) / 1 MΩ = 1 (μA) flows through 1.
This becomes a constant current circuit. Therefore, the analog output of the D / A converter 721 changes according to the value of the data signal, and a predetermined current flows through the resistor 691 based on the value of this analog output.

The transistors 631p1 and 631p2 form a current mirror circuit. The transistor 631p is a P-channel transistor. On the other hand, 633n is an n-channel type transistor forming a current mirror. The same current flows through the source-drain (SD) of the driving transistor 631a,
Since the same current value also flows in the current mirror circuit configured by p1 and 631p2 and the same current value also flows in the current mirror circuit configured by each transistor 633n, the output terminals O1, O2, O3, O4, O5 ,.・ ・ Is a constant current output terminal through which the same current flows (when the current magnification is the same).

However, even if the IC is manufactured from the same mask based on the same process, the electrical characteristics of each element such as a transistor and a resistor formed on the semiconductor chip are different, and the output current of the driver IC is Even with the same IC, there are variations among the outputs between the constant current output terminals. In this case, if the output current value of each constant current output terminal varies, the light emission amount of the light emitting element also varies, and display unevenness occurs on the display panel. Therefore, using the driver IC 14,
When driving a light emitting element such as an organic EL display panel,
It is necessary to minimize variations between constant current output terminals.

The present invention has been made in view of the above points, and has a circuit configuration and a layout configuration for minimizing the output current variation between the constant current output terminals as much as possible. I will provide a.

FIG. 63 is a block diagram of the current-driving source driver IC (circuit) 14 of the present invention. In FIG. 1, as an example, a current source is configured in three stages (631, 632, 633).
Shows a multistage current mirror circuit in the case of.

In FIG. 63, the current value of the first stage current source 631 is copied to N (where N is an arbitrary integer) second stage current source 632 by the current mirror circuit.
Further, the current value of the second stage current source 632 is M (however,
The current mirror circuit copies M to an arbitrary integer 3rd stage current source 633. With this configuration, as a result, the current value of the first-stage current source 631 is copied to the N × M third-stage current sources 633.

For example, when one driver IC 14 drives the source signal line 18 of the QCIF format display panel, the output is 176 (because the source signal line requires 176 outputs for each RGB). In this case, N is 16,
Let M = 11. Therefore, 16 × 11 = 176, which corresponds to 176 outputs. Thus, by setting one of N and M to 8 or 16 or a multiple thereof, the layout design of the current source of the driver IC becomes easy.

Conventional current drive type source driver IC
In (virtually assumed), the current value of the first-stage current source 631 is directly copied to the N × M third-stage current sources by the current mirror circuit. If there is a difference between the characteristics and the transistor characteristics of the third-stage current source, the difference directly causes a variation in the current value, resulting in display unevenness on the display panel. In particular, the source driver IC 14 has a width of about 2 mm and a length of 20 mm.
Since it has a long and narrow shape, there is a large variation in transistor characteristics between the central portion and both ends, and it is considered that such a problem is remarkable.

To address this problem, a current-driving source driver IC using the multi-stage current mirror circuit of the present invention
In the (circuit) 14, as described above, the first stage current source 63
The current value of 1 is not directly copied to the N × M number of third-stage current sources 633 by the current mirror circuit, but the second-stage current source 632 is arranged in the middle, so that variations in transistor characteristics are absorbed. It is possible to

In particular, the present invention is characterized in that the current mirror circuit (current source 631) in the first stage and the current mirror circuit (current source 632) in the second stage are closely arranged. First-stage current source 631 to third-stage current source 633
(That is, the two-stage configuration of the current mirror circuit),
The number of second-stage current sources 633 connected to the first-stage current sources is large, and the first-stage current sources 631 and the third-stage current sources 63 are connected.
3 cannot be placed close together.

Like the source driver circuit 14 of the present invention, the current of the first-stage current mirror circuit (current source 631) is copied to the second-stage current mirror circuit (current source 632), and the second-stage current mirror circuit (current source 632) is copied. Mirror circuit (current source 632)
Current to the third stage in the current mirror circuit (current source 632)
It is a configuration to be copied to. In this configuration, the number of second-stage current mirror circuits (current sources 632) connected to the first-stage current mirror circuits (current sources 631) is small.
Therefore, the first stage current mirror circuit (current source 63
1) and the second stage current mirror circuit (current source 632) can be arranged in close contact with each other.

If the transistors forming the current mirror circuit can be arranged in close contact with each other, the variation of the transistors is naturally reduced, and the variation of the copied current value is also reduced. Also, the number of the third-stage current mirror circuits (current sources 633) connected to the second-stage current mirror circuits (current sources 632) is reduced. Therefore, the second stage current mirror circuit (current source 63
2) and the third stage current mirror circuit (current source 633) can be arranged in close contact with each other.

That is, as a whole, the current receiving section of the first-stage current mirror circuit (current source 631), the second-stage current mirror circuit (current source 632), and the third-stage current mirror circuit (current source 633). The transistors can be arranged closely. Therefore, since the transistors forming the current mirror circuit can be arranged in close contact with each other, variations in the transistors are reduced, and variations in current signals from the output terminals are extremely reduced (high accuracy).

In this example, the multi-stage current mirror circuit is described as a three-stage configuration for simplicity. However, the larger the number of stages, the smaller the current variation of the source driver IC 14 of the current-driven display panel. Needless to say. Therefore, the number of stages of the current mirror circuit is not limited to three and may be three or more.

In the present invention, the current sources 631, 632,
It is expressed as 633 or a current mirror circuit. These are used synonymously. That is, the current source is a basic configuration concept of the present invention, and when the current source is specifically configured, it becomes a current mirror circuit.
Therefore, the current source is not limited to the current mirror circuit, but the operational amplifier 7 as shown in FIG.
Alternatively, a current circuit including a combination of 22, a transistor 631, and a resistor R may be used.

FIG. 64 shows a more specific source driver I.
It is a structural diagram of C (circuit) 14. FIG. 64 shows a portion of the third current source 633. That is, it is an output unit connected to one source signal line 18. As the final stage current mirror configuration, a plurality of current mirror circuits of the same size (current source 634 (1 unit)) are configured, and the number thereof is bit-weighted corresponding to the bits of the image data.

As is apparent from FIG. 64, the case of 6-bit digital input is shown as an example of the present invention. In other words, since it is 2 to the 6th power, 64 gradations are displayed. By mounting the source driver IC 14 on the array substrate, each of red (R), green (G) and blue (B) is 64
Since there are gradations, 64 × 64 × 64 = about 260,000 colors can be displayed.

In FIG. 64, D0 indicates the LSB input, and D5 indicates the MSB input. When the D0 input terminal is at H level (in positive logic), the switch 641a (on / off means. Of course, a single transistor may be used, or an analog switch in which a P-channel transistor and an N-channel transistor are combined may be used. ) Turns on. Then, the current flows toward the current source (one unit) 634 that constitutes the current mirror. This current flows through the internal wiring 643 in the IC 14. Since the internal wiring 643 is connected to the source signal line 18 via the terminal electrode of the IC 14, the current flowing through the internal wiring 643 becomes the program current of the pixel 16.

When the D1 input terminal is at H level (in positive logic), the switch 641b is turned on. Then, the current flows toward the two current sources (one unit) 634 that form the current mirror. This current is the internal wiring 64 in the IC14.
Flow to 3. Since the internal wiring 643 is connected to the source signal line 18 via the terminal electrode of the IC 14, the current flowing through the internal wiring 643 becomes the program current of the pixel 16.

The same applies to the other switches 641. D2
When the input terminal is at H level (in positive logic), switch 64
1c turns on. Then, configure the current mirror 4
Current flows toward one current source (one unit) 634.
When the D5 input terminal is at H level (in positive logic), the switch 641f is turned on. Then, the current flows toward the 32 current sources (1 unit) 634 that configure the current mirror.

As described above, external data (D0 to D0
According to D5), a current flows toward the corresponding current source (1 unit). Therefore, depending on the data, 0
The current is configured to flow from one to 63 current sources (one unit). In the present invention, the number of current sources is 63, which is 6 bits, for ease of explanation, but the present invention is not limited to this. In the case of 8 bits, 255 unit current sources 634 may be formed (arranged). In the case of 4 bits, 15 unit current sources 634 are formed (arranged)
do it.

Further, the current sources 634 are not limited to all supplying the same current. For example, each current source 634 may be weighted. For example, the current output circuit may be configured by mixing one unit current source 634, two times the current source 634, and four times the current source 634. However, if the current sources 634 are configured by weighting, the weighted current sources do not have the weighted ratio, and variations may occur. Therefore, even in the case of weighting, it is preferable that each current source is formed by forming a plurality of transistors each serving as a unit of current source.

The configuration shown in FIG. 64 is the third stage current mirror section shown in FIG. Therefore, the first current source 6
31 and the second stage current source 632 are separately formed, and these are arranged densely (closely or adjacently). In addition, the transistor 633a of the currant mirror circuit that constitutes the second-stage current source 632 and the third-stage current source
Are also densely (closely or adjacently) arranged.

Note that the current sources (1 unit) 634 are densely arranged and a minute current flows. Therefore, the light emitted from the EL display panel (emitted light)
However, when the current source 634 (in addition, 631, 632, and 633 should be considered) is irradiated with light, a malfunction occurs due to a photoconductor phenomenon (photocon). To cope with this problem, a light shielding film is formed on the back surface of the chip. In addition, a light-shielding film is formed on the board where it is mounted and where the current source of the chip is formed (a light-absorbing film made of a metal thin film, an organic material or an inorganic material is formed on the surface of the panel substrate). . This light-shielding film guides the anode wiring and the cathode wiring that supply a current to the EL element 15 (I
If it is constructed, it can be easily formed and the cost can be reduced. This configuration is not limited to the IC chip. It is also applied to the source driver circuit 14 using low-temperature polysilicon, high-temperature polysilicon, or a semiconductor film (CGS) formed by solid phase growth. That is, a light shielding film is formed on the back surface of the source driver circuit 14.

The current flowing through the second-stage current mirror circuit 632 is copied to the transistor 633a which constitutes the third-stage current mirror circuit. When the current mirror magnification is 1, this current flows through the transistor 633b. This current is copied to the final stage transistor 634.

Since the portion corresponding to D0 is composed of one transistor 634, it is the current value flowing in the transistor 633 of the final stage current source. Since the portion corresponding to D1 is composed of two transistors 634,
The current value is twice that of the final stage current source. Since D2 is composed of four transistors 634, the current value is four times that of the final stage current source, and the portion corresponding to D5 is 3
Since it is composed of two transistors, the current value is 32 times that of the final stage current source. Therefore, the program current Iw is output to the source signal line (current is drawn) via the switches controlled by the 6-bit image data D0, D1, D2, ..., D5. Therefore, 6-bit image data D0, D1, D2, ..., D5 ON,
Depending on the OFF state, the output line has 1 of the final stage current source 633.
Double, double, quadruple, ..., 32-fold currents are added and output. That is, 6-bit image data D0, D
1, D2, ..., D5, a current value 0 to 63 times that of the final stage current source 633 is output from the output line (current is drawn from the source signal line 18).

As described above, with the configuration of an integral multiple of the final stage current source 633, compared with the conventional proportional distribution of W / L,
The current value can be controlled with higher accuracy (the output variation of each terminal is eliminated).

However, in this structure, the driving TFT 11a forming the pixel 16 is composed of the P channel, and
This is a case where the current source (1 unit) unit 634 forming the source driver IC 14 is formed of an N-channel transistor. In other cases (for example, the TFT for driving the pixel 16)
It is needless to say that the program current Iw can be a discharge current when 11a is composed of N-channel transistors. ).

It is assumed that the current of 0 to 63 times that of the final stage current source 633 is output.
This is when the current mirror magnification of is 1. When the current mirror magnification is 2 times, the final stage current source 633 0 to 126
When the current mirror magnification is 0.5 times, the current of 0 to 31.5 times that of the final stage current source 633 is output. As described above, the present invention provides the final stage current source 633.
Alternatively, the current value of the output can be easily changed by changing the current mirror magnification of the current source (631, 632, etc.) in the preceding stage. In addition, the above items are
It is also preferable to change (make different) the current mirror magnification for each of R, G, and B. For example, only for R, the current mirror magnification of any current source may be changed (different) with respect to other colors (with respect to current source circuits corresponding to other colors). In particular, the EL display panel has different luminous efficiency for each color (R, G, B or cyan, yellow, magenta). Therefore, the white balance can be improved by changing the current mirror magnification for each color.

The matter of changing (changing) the current mirror magnification of the current source with respect to other colors (with respect to current source circuits corresponding to other colors) is not limited to fixed ones. It also includes changing. The variable can be realized by forming a plurality of transistors forming a current mirror circuit in a current source and switching the number of the transistors through which a current flows by an external signal. The EL manufactured by the above configuration
It becomes possible to adjust to the optimum white balance while observing the light emission state of each color of the display panel. In particular, the present invention has a configuration in which current sources (current mirror circuits) are connected in multiple stages. Therefore, when the current mirror magnifications of the first-stage current source 631 and the second-stage current source 632 are changed, the output currents of a large number of outputs can be easily changed with a small number of connecting portions (current mirror circuit or the like). Of course, it is possible to easily change the output current of a large number of outputs with a small number of connecting portions (current mirror circuit, etc.) rather than changing the current mirror magnification of the second stage current source 632 and the third stage current source 633. Needless to say.

Note that the concept of changing the current mirror magnification means changing (adjusting) the current magnification.
Therefore, the present invention is not limited to the current mirror circuit. For example, it can be realized by a current output operational amplifier circuit, a current output D / A circuit, or the like.

It goes without saying that the matters described above are also applicable to other embodiments of the present invention.

FIG. 65 shows an example of a circuit diagram of 176 outputs (N × M = 176) by the three-stage current mirror circuit. In FIG. 65, the current source 631 based on the first-stage current mirror circuit is referred to as a parent current source, the current source 632 based on the second-stage current mirror circuit is referred to as a child current source, and the current source 633 based on the third-stage current mirror circuit is referred to as a grandchild current source. ing. With the configuration of the third stage current mirror circuit which is the final stage current mirror circuit, which is an integral multiple of the current source, it is possible to suppress variations in the 176 outputs as much as possible and to perform highly accurate current output. of course,
One must not forget the configuration in which the current sources 531, 632, 633 are densely arranged.

The dense arrangement means that the first current source 631 and the second current source 632 are arranged at a distance of at least 8 mm (current or voltage output side and current or voltage input side). Say that. Furthermore, 5 mm
It is preferable to place it within. This is because, if it is within this range, a difference in characteristics (Vt, mobility (μ)) of the transistors arranged in the silicon chip hardly occurs by study. Similarly, the second current source 632 and the third current source 633 (current output side and current input side) are also arranged at a distance of at least 8 mm. More preferably, it is preferably arranged at a position within 5 mm. It goes without saying that the above items also apply to other embodiments of the present invention.

The output side of the current or voltage and the input side of the current or voltage mean the following relationship. FIG. 66
In the case of voltage transfer, the transistor 631 (output side) of the (I) th stage current source and the transistor 632a (input side) of the (I + 1) th current source are closely arranged. In the case of current transfer in FIG. 67, the transistor 631a (output side) of the (I) th stage current source and the (I +) th stage
The relation is that the current source transistor 632b (input side) of 1) is densely arranged.

Here, a silicon chip is used, but this means a semiconductor chip. Therefore, the same applies to chips formed on a gallium substrate and other semiconductor chips formed on a germanium substrate or the like.

Furthermore, a low temperature polysilicon, a high temperature polysilicon or a semiconductor film (C
It is also applied to the source driver circuit using GS). However, in this case, the panel is often relatively large.
If the panel is large, it is difficult to be visually recognized even if there is some variation in the output from the source signal line 18. Therefore, in the display panel in which the source driver circuit 14 is formed simultaneously with the pixel TFTs on the glass substrate or the like, it means that the first current source 631 and the second current source 6 are densely arranged.
32 is arranged at a distance of at least 30 mm (current output side and current input side). Furthermore, 2
It is preferable to arrange it within 0 mm. This is because, within this range, a difference in characteristics (Vt, mobility (μ)) of the transistors arranged in this range hardly occurs as a result of examination. Similarly, the second current source 632 and the third current source 632
The current source 633 (current output side and current input side) is also arranged at a distance of at least 30 mm. More preferably, it is preferably arranged at a position within 20 mm.

In the above description, for ease of understanding or for ease of explanation, it is explained that signals are transferred between the current mirror circuits by voltage. However, with the current passing configuration. Driver circuit (IC) 14 for driving a current-driven display panel with less variation
Can be realized.

FIG. 67 shows an embodiment of the current transfer configuration. Note that FIG. 66 shows an example of a voltage transfer configuration.
66 and 67 are the same as the circuit diagram, but the layout configuration, that is, the way of wiring is different. FIG. 66
, 631 is a first-stage current source Nch transistor, 632a is a second-stage current source Nch transistor, 6
32b is a Pch transistor for the second stage current source.

In FIG. 67, 631a is a first-stage current source Nch transistor, and 632a is a second-stage current source Nc transistor.
The h transistor 632b is a Pch transistor for the second stage current source.

In FIG. 66, the variable resistor 651 (used to change the current) and the Nch transistor 6 are used.
Since the gate voltage of the first-stage current source composed of 31 is transferred to the gate of the Nch transistor 632a of the second-stage current source, the layout structure is a voltage transfer system.

On the other hand, in FIG. 67, the variable resistors 651 and Nc are
The gate voltage of the first-stage current source composed of the h-transistor 631a is applied to the gate of the Nch transistor 632a of the adjacent second-stage current source, and as a result, the current value flowing through the transistor is Pch of the second-stage current source. Since it is delivered to the transistor 632b, the layout configuration is a current delivery system.

In the embodiments of the present invention, the relationship between the first current source and the second current source is mainly described in order to facilitate the description or the understanding. It is needless to say that the present invention is not limited to this, and is applied (applicable) to the relationship between the second current source and the third current source or the relationship to other current sources.

In the layout configuration of the voltage mirroring type current mirror circuit of FIG. 66, the Nch transistor 631 of the current source of the first stage and the Nch transistor 632a of the current source of the second stage forming the current mirror circuit are separated from each other ( It should be said that they are easily separated from each other), so that a difference is likely to occur in the transistor characteristics of both. Therefore, the current value of the first-stage current source is not accurately transmitted to the second-stage current source, and variations easily occur.

On the other hand, in the layout configuration of the current transfer type current mirror circuit of FIG. 67, the Nch transistor 631a of the first stage current source and the Nch transistor 632 of the second stage current source forming the current mirror circuit.
Since a is adjacent (it is easy to arrange adjacent to each other), the transistor characteristics of the two are unlikely to differ, the current value of the first-stage current source is accurately transmitted to the second-stage current source, and variation is unlikely to occur. .

From the above, the circuit configuration of the multistage current mirror circuit of the present invention (source driver circuit (IC) 14 of the current drive system of the present invention) has a layout configuration of current transfer instead of voltage transfer. This is preferable because the variation can be further reduced. It goes without saying that the above embodiment can be applied to other embodiments of the present invention.

For convenience of explanation, the case where the first-stage current source to the second-stage current source is shown, but the second-stage current source to the third-stage current source and the third-stage current source to the fourth-stage current source. It goes without saying that the same applies to the case of source.

FIG. 68 shows an example in which the current mirror circuit of the three-stage configuration (current source of the three-stage configuration) of FIG. 65 is set to the current delivery system (thus, FIG. 65 is a circuit of the voltage delivery system). Configuration).

The transistors forming the source driver IC (circuit) 14 of the present invention are not limited to the MOS type, but may be the bipolar type. Further, it is not limited to a silicon semiconductor, and a gallium arsenide semiconductor may be used. Alternatively, a germanium semiconductor may be used.
Alternatively, it may be directly formed on the substrate by a low temperature polysilicon technique. The above matters also apply to the other embodiments.

In FIG. 68, first, the variable resistors 651 and Nc are connected.
A reference current is created by the h transistor 631a. Although the variable resistor 651 adjusts the reference current, the source voltage of the transistor 631a is actually set by the electronic volume circuit formed (or arranged) in the source driver IC (circuit) 14. Configured to be adjusted. Alternatively, the reference current is adjusted by directly supplying the current output from a current-type electronic volume composed of a large number of current sources (one unit) 634 as shown in FIG. 64 to the source terminal of the transistor 631. (See FIG. 69).

The gate voltage of the first stage current source formed by the transistor 631a is applied to the gate of the Nch transistor 632a of the adjacent second stage current source, and as a result, the current value flowing through the transistor is the Pch transistor of the second stage current source. It is delivered to 632b. Further, the gate voltage of the transistor 6312b of the second current source is applied to the gate of the Nch transistor 633a of the adjacent third stage current source, and as a result, the current value flowing through the transistor is the third value.
It is transferred to the Nch transistor 633b of the stage current source. A large number of current sources 634 shown in FIG. 64 are formed (disposed) at the gate of the Nch transistor 633b of the third stage current source according to the required number of bits.

The Vt variation (characteristic variation) of the transistor varies by about 100 mV within one wafer. However, the Vt variation of the transistors formed close to each other within 100 μ is at least 10 mV or less (actual measurement). That is, by forming the transistors close to each other to form the current mirror circuit, it is possible to reduce the output current variation of the current mirror circuit. Therefore, it is possible to reduce variations in the output current of each terminal of the source driver IC of the present invention.

FIG. 105 shows the measurement results of the transistor formation area (square millimeter) and the output current variation (3σ) of a single transistor. The output current variation is a current variation at the Vt voltage. Black dots are evaluation samples (10-200) produced within a predetermined formation area.
Variations in transistor output current. FIG. 105
The transistor formed in the area A (formed area within 0.5 mm 2) has almost no variation in output current (almost only output current variation within error range. That is, a constant output current is output). ). On the contrary, in the C region (forming area of 2.4 square millimeters or more), the variation of the output current with respect to the forming area tends to increase sharply. In the B region (forming area of 0.5 square millimeters or more and 2.4 square millimeters or less), the variation of the output current is substantially proportional to the forming area.

However, the absolute value of the output current is different for each wafer. However, this problem can be solved by adjusting the reference current or setting it to a predetermined value in the source driver circuit (IC) 14 of the present invention. In addition, it can be solved (solved) by devising a circuit such as a current mirror circuit.

According to the present invention, the amount of current flowing through the source signal line 18 is changed (controlled) by switching the number of currents flowing through the unit transistors 634 according to the input digital data (D). If the number of gradations is 64 or more, then 1/6
Since 4 = 0.015, theoretically it is necessary to keep the output current within 1 to 2%. 1%
It is difficult to visually discriminate the output variation within the range of 0.5% or less (almost uniform).

In order to keep the output current variation (%) within 1%, as shown in the result of FIG. 105, the formation area of the transistor group (transistor whose variation should be suppressed) is set within 2 square millimeters. There is a need. More preferably, the variation in the output current (that is, the Vt variation in the transistor) is preferably within 0.5%. As shown in the result of FIG. 105, the transistor group 681
The formation area of s should be 1.2 square millimeters or less. The formation area is an area of length × width.
For example, as an example, with 1.2 square millimeters,
It is 1 mm × 1.2 mm.

The above is especially the case of 8 bits (256 gradations) or more. In the case of 256 gradations or less, for example, in the case of 6 bits (64 gradations), the variation of the output current may be about 2% (there is no problem in image display in actuality). In this case, the transistor group 681 may be formed within 5 square millimeters. Both of the transistor groups 681 (two transistor groups 681a and 681b are illustrated in FIG. 68) do not need to satisfy this condition. The effect of the present invention is exerted if at least one of them (when there are three or more, one or more transistor groups 681) is configured to satisfy this condition. In particular, it is preferable to satisfy this condition with respect to the lower transistor group 681 (the relationship in which 681a is the upper layer and 681b is the lower layer). This is because problems in image display are less likely to occur.

The above items are also applicable to other embodiments of the present invention, and can be combined with the display panel, array, display device or the like of the present invention.

Source Driver Circuit (IC) 14 of the Present Invention
68, as shown in FIG. 68, at least a plurality of current sources such as a parent, a child, and a grandchild are connected in multiple stages, and each current source is densely arranged (of course, a two-stage connection of the parent and the child is also possible). . In addition, current is passed between the respective current sources (between the transistor groups 681). Specifically, a range (transistor group 681) surrounded by a dotted line in FIG. 68 is densely arranged.
The transistor group 681 has a voltage transfer relationship. Further, the parent current source 631 and the child current source 632a are formed or arranged in the substantially central portion of the source driver IC 14 chip. This is because the distance between the transistor 632a forming the child current source and the transistor 632b forming the child current source arranged on the left and right of the chip can be made relatively short. That is, the uppermost transistor group 681a is arranged substantially in the center of the IC chip. And
On the left and right of the IC chip 14, lower transistor groups 681
Place b. Preferably, the lower transistor groups 681b are arranged, formed or manufactured such that the numbers of the lower transistor groups 681b are substantially equal on the left and right sides of the IC chip. In addition,
The above items are not limited to the IC chip 14, and are also applied to the source driver circuit 14 directly formed on the substrate 71 by the low temperature or high temperature polysilicon technique. Other matters are also the same.

In the present invention, the transistor group 681a is I
One C-chip 14 is formed, arranged, formed or manufactured in the substantially central portion, and eight transistor groups 681b are formed on the left and right sides of the chip (N = 8 + 8,
See FIG. 63). The child transistor groups 681b are equal to each other on the left and right sides of the chip, or the difference between the number of transistor groups 681b formed or arranged on the left side of the chip and the number of transistor groups 681b formed or arranged on the right side of the chip. It is preferable that the number is 4 or less. Furthermore, the number of transistor groups 681b formed or arranged on the left side of the chip,
Transistor group 6 formed or arranged on the right side of the chip
It is preferable that the difference from the number of 81b is within one. The above items are the same for the grandchild transistor group (not shown in FIG. 68).

Voltage is transferred (voltage-connected) between the parent current source 631 and the child current source 632a. Therefore, it is easily affected by the Vt variation of the transistor. Therefore, the transistor group 681a is densely arranged. The formation area of the transistor group 681a is formed within an area of 2 mm 2 as shown in FIG.
More preferably, it is formed within 1.2 mm 2. Of course, when the number of gradations is 64 gradations or less, it may be within 5 square millimeters.

Data is transferred by current between the transistor group 681a and the child transistor 632b (current transfer).
Since it is doing, it does not matter if the distance flows a little. This distance range (for example, the upper transistor group 681a
From the output end of the second current source (child) to the input end of the lower transistor 681b), as described above.
632a and second current source (child) that configure the
And a transistor 632b forming the
Place it within a distance of mm. This is preferably placed or formed within 8 mm. Furthermore, it is preferable to arrange within 5 mm. This is because, if it is within this range, the difference in characteristics (Vt, mobility (μ)) of the transistors arranged in the silicon chip has almost no effect on the current transfer when examined. In particular, this relationship is preferably implemented in the lower transistor group. For example, the transistor group 681a is in the upper layer, and the transistor group 6 is in the lower layer.
81b, and if there is a transistor group 681c below it, there are transistor group 681b and transistor group 681.
The current passing of c satisfies this relationship. Therefore, the present invention is not limited to the case where all the transistor groups 681 satisfy this relationship. It suffices that at least one transistor group 681 satisfy this relationship. This is because the number of transistor groups 681 in the lower layer is particularly large.

[0618] The transistor 633a forming the third current source (grandchild) and the transistor 63 forming the third current source.
The same applies to 3b. In addition, even when passing voltage,
It goes without saying that it is almost applicable.

The transistor group 681b is formed, manufactured or arranged in the left-right direction of the chip (longitudinal direction, that is, at a position facing the output terminal 761). The transistor group 681b is formed, manufactured, or arranged in the left-right direction of the chip (longitudinal direction, that is, at a position facing the output terminal 761). This transistor group 681
In the present invention, the number M of b is 11 (see FIG. 63).

Voltage is transferred (voltage connected) between the child current source 632b and the grandchild current source 633a. Therefore, similarly to the transistor group 681a, the transistor group 681b is densely arranged. The formation area of the transistor group 681b is formed within an area of 2 mm 2 as shown in FIG. More preferably, it is formed within 1.2 mm 2. However, if the Vt of the transistor group 681b varies even a little, it is easily recognized as an image. Therefore, the formation area is preferably set to the area A in FIG. 105 (within 0.5 mm 2), so that almost no variation occurs.

[0621] Since the transistor group 681b transfers data by current (current transfer) between the grandchild transistor 633a and the transistor 633b, a slight distance may flow. The range of this distance is similar to the above description. The transistor 633a included in the third current source (grandchild) and the transistor 633b included in the second current source (grandchild) are arranged at a distance of at least 8 mm. Furthermore, it is preferable to arrange within 5 mm.

In FIG. 69, the first-stage current source 631 of the multistage current mirror circuit is provided with a current value adjusting element. With this configuration, the first
The output current can be controlled by changing the current value of the stage current source 631.

FIG. 69 shows, as the current value control element,
A case where the electronic volume is used is shown. The electronic volume is composed of a resistor 691 (current limit and each reference voltage are created. The resistor 691 is formed of polysilicon), a decoder 692, a level shifter 693, and the like. The electronic volume outputs a current. The transistor 641 functions as an analog switch circuit.

The electronic volume circuit is formed (or arranged) according to the number of colors of the EL display panel. For example, for the three primary colors of RGB, it is preferable to form (or arrange) three electronic volume circuits corresponding to the respective colors so that the respective colors can be adjusted independently. However, when one color is used as a reference (fixed), an electronic volume circuit for the number of colors minus 1 is formed (or arranged).

FIG. 76 shows a structure in which a resistance element 651 for independently controlling the reference currents of the three primary colors of RGB is formed (arranged). Needless to say, the resistance element 651 may be replaced with an electronic volume. Basic (root) such as parent current sources such as current source 631 and current source 632, child current sources
The current source becomes the current output circuit 7 in the area shown in FIG.
Place it densely on 04. By arranging them densely, the variation in the output from each source signal line 18 is reduced. By arranging the current output circuit 704 in the central portion of the IC chip (circuit) 14 as shown in FIG.
It becomes easy to distribute the current evenly from the current sources 631 and 632 to the left and right of the C chip (circuit) 14. Therefore, left and right output variations are unlikely to occur.

The current output circuit 704 is formed (arranged) for each of R, G and B, and the RGB current output circuit 70 is provided.
4R, 704G, and 704B are also arranged close to each other. Also,
The low-current region reference current INL shown in FIG. 73 is adjusted for each color (R, G, B), and the low-current region reference current INH shown in FIG. 74 is also adjusted (see also FIG. 79). thing). Therefore, the R current output circuit 704R has a volume (or voltage output or current output electronic volume) 65 for adjusting the reference current INL in the low current region.
1RL is arranged, and a volume (or a voltage output or current output electronic volume) 651RH for adjusting the reference current INH in the high current region is arranged. Similarly, the reference current INL in the low current region is applied to the G current output circuit 704G.
Is arranged (or a voltage output or current output electronic volume) 651GL, and a volume (or voltage output or current output electronic volume) 651GH is arranged to adjust the reference current INH in the high current region. Further, the B current output circuit 704B has a volume (or voltage output or current output electronic volume) 651 for adjusting the reference current INL in the low current region.
BL is arranged, and a volume (or electronic volume for voltage output or current output) 651BH for adjusting the reference current INH in the high current region is arranged. The volume 651 and the like are preferably configured to change with temperature so that the temperature characteristics of the EL element 15 can be compensated. Further, in the gamma characteristic of FIG. 79, when there are two or more bending points, it goes without saying that the number of electronic regulators or resistors for adjusting the reference current of each color may be three or more.

Output pad 7 is connected to the output terminal of the IC chip.
61 is formed or arranged. This output pad,
The source signal line 18 of the display panel is connected. The output pad 761 has bumps (projections) formed by a plating technique or a nail head bonder technique. The height of the protrusion is 10 μm or more and 40 μm or less.

The bumps and the source signal lines 18 are electrically connected to each other via a conductive bonding layer (not shown). The conductive bonding layer is mainly composed of epoxy-based or phenol-based adhesive as an adhesive, and is mixed with flakes of silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO ₂ ), etc. Or a UV curable resin. The conductive bonding layer is formed on the bump by a technique such as transfer. Further, the bump and the source signal line 18 are thermocompression-bonded with ACF resin. Note that bumps or output pads 761
The connection between the source signal line 18 and the source signal line 18 is not limited to the above method. Alternatively, the film carrier technique may be used without mounting the IC 14 on the array substrate. Alternatively, the source signal line 18 and the like may be connected using a polyimide film or the like.

In FIG. 69, the input 4-bit current value control data (DI) is the 4-bit decoder circuit 6
Decoded by 92 (or 6 if the number of divisions is 64)
Needless to say that it is a bit. Here, in order to facilitate the description, the description will be made with 4 bits). The output is boosted from the logic level voltage value to the analog level voltage value by the level shifter circuit 693, and is input to the analog switch 641.

The main constituent part of the electronic volume circuit is composed of a fixed resistor R0691a and 16 unit resistors r691b. The output of the decoder circuit 692 is connected to any of the 16 analog switches 641. The output of the decoder circuit 692 is configured to determine the resistance value of the electronic volume. That is, for example, when the output of the decoder circuit 692 is 4, the resistance value of the electronic volume is R0 + 5r. The resistance of this electronic volume serves as a load of the first stage current source 631.
Pulled up to Vdd. Therefore, when the resistance value of the electronic volume changes, the current value of the first stage current source 631 changes, and as a result, the current value of the second stage current source 632 changes, and as a result, the third stage current source 633. The current value of is also changed, and the output current of the driver IC is controlled.

For convenience of explanation, the current value control data is set to 4 bits, but it is not fixed to 4 bits. The larger the number of bits, the larger the variable number of current values. Needless to say. Further, the configuration of the multistage current mirror has been described as having three stages, but it is needless to say that this is not fixed to three stages and that any number of stages may be used.

Further, in order to solve the problem that the light emission luminance of the EL element changes due to the temperature change, the external resistor 6 whose resistance value changes depending on the temperature is constituted as the electronic volume circuit.
It is preferable to include 91a. Examples of the external resistor whose resistance value changes with temperature include a thermistor and a posistor. In general, a light emitting element whose brightness changes according to the current flowing through the element has a temperature characteristic, and even if the same current value is passed, the light emission brightness changes depending on the temperature.
Therefore, an external resistor 691 whose resistance value changes with temperature
By attaching a to the electronic regulator, the current value of the constant current output can be changed depending on the temperature, and the light emission luminance can be kept constant even if the temperature changes.

The multi-stage current mirror circuit is
It is preferable to separate into three systems for red (R), green (G), and blue (B). Generally, in a current drive type light emitting element such as an organic EL, the light emitting characteristics differ for R, G and B. Therefore,
In order to obtain the same brightness for R, G, and B, it is necessary to adjust the value of the current flowing through the light emitting element with R, G, and B, respectively. Further, in a current-driven light emitting element such as an organic EL display panel,
The temperature characteristics differ for R, G, and B. Therefore, the characteristics of the external auxiliary element such as the thermistor for correcting the temperature characteristics,
It is necessary to adjust R, G and B respectively.

In the present invention, since the multistage current mirror circuit is separated into three systems for R, G and B, the light emission characteristics and the temperature characteristics can be adjusted by R, G and B, respectively. It is possible to obtain the optimum white balance.

As described above, in the current driving method, the current written in the pixel is small during black display. Therefore, if the source signal line 18 or the like has a parasitic capacitance, there is a problem that a sufficient current cannot be written in the pixel 16 in one horizontal scanning period (1H). Generally, in a current-driven light-emitting element, the black level current value is as small as several nanoamperes, so it is difficult to drive the parasitic capacitance (wiring load capacitance) which is thought to be several tens of pF in terms of the signal value. . In order to solve this problem, a precharge voltage is applied before the image data is written to the source signal line 18, and the potential level of the source signal line 18 is set to the pixel TFT 11.
a black display current (a TFT 11a is basically off)
It is effective to In order to form (create) this precharge voltage, it is effective to output a constant voltage of black level by decoding the upper bits of the image data.

FIG. 70 shows an example of a current output type source driver circuit (IC) 14 having a precharge function of the present invention. FIG. 70 shows a case where a precharge function is provided in the output stage of a 6-bit constant current output circuit. In FIG. 70, the precharge control signal is decoded by the NOR circuit 702 when the upper 3 bits D3, D4, and D5 of the image data D0 to D5 are all 0, and the dot clock CLK having the reset function by the horizontal synchronizing signal HD. AND circuit 7 with the output of the counter circuit 701 of
03, and outputs the black level voltage Vp for a certain period. In other cases, the output current from the current output stage 704 described with reference to FIG. 68 and the like is applied to the source signal line 18 (from the source signal line 18 to the program current Iw).
Absorbs). With this configuration, when the image data has 0th to 7th gradations close to the black level, the voltage corresponding to the black level is written only for the first fixed period of one horizontal period, and the load of current driving is reduced. It becomes possible to make up for the insufficient writing. Note that the completely black display is the 0th gradation and the completely white display is the 63rd gradation (in the case of the 64 gradation display).

Note that the gradation for precharging should be limited to the black display area. That is, the write image data is determined, and the black region gradation (low luminance, that is, the write current is small (minute) in the current drive method) is selected and precharged (selective precharge). When all the grayscale data are precharged, the brightness is lowered (the target brightness is not reached) in the white display area. In addition, vertical stripes are displayed on the image.

[0638] It is preferable that the gradation data from gradation 0 to 1 /
Selective precharge is performed in the gradation of the area of 8 (for example, in the case of 64 gradations, in the case of image data of 0th gradation to 7th gradation, precharge is performed and then the image data is written. ). Further, it is preferable that the gradation of the gradation data is 0.
Selective precharge is performed in the gradation of the region from 1/16 to 1/16 (for example, in the case of 64 gradations, the image data from 0th gradation to 3rd gradation and Write the data).

Particularly in black display, a method of detecting only gradation 0 and precharging is also effective in order to increase the contrast. Very good black display. The problem is that when the entire screen has gradations 1 and 2, the screen appears black. Therefore, the selective precharge is performed within a certain range from the gradation 0 to 1/8 of the gradation data.

The precharge voltage and gradation range are
It is also effective to make R, G, and B different. This is because the EL display element 15 has different emission start voltages and emission brightness for R, G, and B. For example, R is a gradation in the region of gradation 0 to 1/8 of gradation data, and performs selective precharge (for example, in the case of 64 gradations, an image from gradation 01 to gradation 7). At the time of data, after precharging,
Write the image data). The other colors (G, B) are selectively precharged in the gradation range of 0 to 1/16 of the gradation data (for example, in the case of 64 gradations, 0th gradation to 3rd floor) When the image data up to the tone is reached, the image data is written after the precharge is performed). As for the precharge voltage, if R is 7 (V), the voltage of 7.5 (V) is applied to the source signal line 1 for the other colors (G, B).
Write to 8. The optimum precharge voltage is
It often differs depending on the manufacturing lot of the EL display panel. Therefore, it is preferable that the precharge voltage can be adjusted by an external regulator or the like. This adjusting circuit can also be easily realized by using an electronic volume circuit.

The 0th mode in which no precharge is performed at all, the first mode in which only gradation 0 is precharged, and gradation 0
Set the second mode that precharges in the range from 3 to 3 and the 3rd mode that precharges in the range from 0 to 7 and the 4th mode that precharges in the range of all gradations. It is preferable to be configured to switch by a command. These are source driver circuits (IC) 1
This can be easily realized by configuring (designing) a logic circuit within 4.

FIG. 75 is a specific block diagram of the selective precharge circuit section. PV is an input terminal for the precharge voltage. External input or electronic volume circuit, R,
Individual precharge voltages are set by G and B. In addition,
Although the individual precharge voltages are set for R, G, and B, the present invention is not limited to this. R, G, and B may be common. The precharge voltage is the driving TF of the pixel 16.
This is because it is related to Vt of T11a, and this pixel 16 is the same for R, G, and B pixels. Conversely, pixel 16
When the W / L ratio of the driving TFT 11a is different for R, G, and B (different designs), it is preferable to adjust the precharge voltage corresponding to the different designs. For example, if L becomes large, the TFT 11a
The diode characteristics of, and the source-drain (S
D) The voltage increases. Therefore, the precharge voltage needs to be set lower than the source potential (Vdd).

The precharge voltage PV is input to the analog switch 731. W of this analog switch
(Channel width) is 10μ in order to reduce ON resistance
It must be m or more. However, if W is too large, the parasitic capacitance also becomes large, so the value is set to 100 μm or less.
More preferably, the channel width W is 15 μm or more and 60
It is preferable that the thickness is less than μm. The above items also apply to the analog switch 731 of the switch 641b of FIG. 75 and the analog switch 731 of FIG.

The switch 641a has a precharge enable (PEN) signal and a selection precharge signal (PSL).
And the upper 3 bits (H5, H) of the logic signal of FIG.
4, H3). The meaning of the upper 3 bits (H5, H4, H3) of the logic signal as an example is that the selective precharge is executed when the upper 3 bits are “0”. That is, the configuration is such that when the lower 3 bits are "1" (gray scale 0 to gray scale 7), the precharge is performed.

This selective precharge may be fixed by precharging only gradation 0 or precharging in the range of gradation 0 to gradation 7, but it is fixed in the low gradation range (see FIG. 79). Gradation 0 to gradation R1 or gradation (R1-
1)) may be interlocked with the low gradation region such as selective precharge. In other words, the selective precharge is
When the low gradation region is from gradation 0 to gradation R1, it is performed in this range, and when the low gradation region is from gradation 0 to gradation R2, it is performed in this range. Note that this control method has a smaller hardware scale than other methods.

[0646] Depending on the applied state of the above signals, the switch 6
41a is on / off controlled, and when the switch 641a is on, the precharge voltage PV is applied to the source signal line 18. The time for applying the precharge voltage PV is
It is set by a counter (not shown) formed separately.
This counter is configured to be set by a command. Further, the application time of the precharge voltage is preferably set to a time of 1/100 or more and 1/5 or less of one horizontal scanning period (1H). For example, 1H is 100 μs
If ec, it is 1 μsec or more and 20 μsec. More preferably, it is set to 2 μsec or more and 10 μsec.

[0647] The precharge application time is R, G,
Good results can also be obtained by making B different. For example, the R precharge time is set longer than the G and B precharge times. This is because, in an organic EL or the like, the light emission start time is different for each of the RGB materials. Also, a good result can be obtained by changing the pre-charge voltage PV application time according to the image data applied to the source signal line 18 next. For example, the application time is set longer at the gradation 0 of the completely black display and shorter than that at the gradation 4. Also, it is possible to obtain a good result by setting the application time in consideration of the difference between the image data of 1H before and the image data of the next application. For example, when the current for writing the pixel in the white display is written to the source signal line 1H before and the current for writing the black display in the pixel is written in the next 1H, the precharge time is lengthened. This is because the black display current is very small. On the contrary, when the current for writing the pixel in black is written to the source signal line 1H before and the current for writing the black in white is written in the next 1H, the precharge time is shortened or the precharge is performed. Stop (do not do). This is because the write current for white display is large.

It is also effective to change the precharge voltage according to the image data to be applied. This is because the write current for black display is minute and the write current for white display is large. Therefore, the precharge voltage becomes higher (to Vdd, when the pixel TFT 11a is the P channel) in the lower gradation region, and becomes lower (in the pixel TFT 11a in the higher gradation region). Is for P channel).

[0649] Program current open terminal (PO terminal)
When is “0”, the switch 641b is turned off,
The IL terminal and the IH terminal are disconnected from the source signal line 18 (the Iout terminal is connected to the source signal line 18). Therefore, the program current Iw does not flow in the source signal line 18. Program current Iw at PO terminal
Is applied to the source signal line, it is set to "1", the switch 641b is turned on, and the program current Iw is supplied to the source signal line 18.

[0650] Apply "0" to the PO terminal and switch 64
When 1b is opened, no pixel row in the display area is selected. The current source 634 does not maintain the current based on the input data (D0 to D5) and draws it from the source signal line 18. This current is a current flowing from the Vdd terminal of the selected pixel 16 into the source signal line 18 via the TFT 11a. Therefore, when no pixel row is selected, there is no path for current to flow from the pixel 16 to the source signal line 18. The time when no pixel row is selected occurs until an arbitrary pixel row is selected and the next pixel row is selected. Note that a state in which no such pixel (pixel row) is selected and there is no path for flowing into (flowing out from) the source signal line 18 is referred to as a total non-selection period.

In this state, when the IOUT terminal is connected to the source signal line 18, the unit current source 63 which is turned on is turned on.
4 (currently turned on is the switch 641 controlled by the data of the D0 to D5 terminals). Therefore, the electric charge charged in the parasitic capacitance of the source signal line 18 is discharged, and the potential of the source signal line 18 drops sharply.

As described above, when the potential of the source signal line 18 drops, it takes time to recover the original potential due to the current originally written in the source signal line 18.

To solve this problem, in the present invention, "0" is applied to the PO terminal and the switch 641b in FIG. 75 is turned off to disconnect the IOUT terminal and the source signal line 18 during the entire non-selection period. By disconnecting, the current does not flow from the source signal line 18 to the current source 634, so that the potential change of the source signal line 18 does not occur during the entire non-selection period. As described above, by controlling the PO terminal and disconnecting the current source from the source signal line 18 during the entire non-selection period, excellent current writing can be performed.

Also, the area (white area) of the white display area (area having a constant brightness) and the area (black area) of the black display area (area of brightness below a predetermined level) are mixed on the screen, and the white area It is effective to add the function of stopping precharge when the ratio of black area is in a certain range (proper precharge). This is because vertical stripes are generated in the image within this fixed range. Of course, on the contrary, there are also cases where precharging is performed within a certain range. Moreover, when the image moves, the image becomes noise. The proper precharge can be easily realized by counting (calculating) the data of the pixels corresponding to the white area and the black area by the arithmetic circuit. It is also effective to make the proper precharge different for R, G, and B. The EL display element 15 includes R, G, B
This is because the light emission starting voltage and the light emission luminance are different.
For example, R indicates that the precharge is stopped or started when the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance is 1:20 or more, and G and B are the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance. Is configured to stop or start precharging at 1:16 or more. According to the results of experiments and examinations, in the case of an organic EL display panel, when the ratio of the white area of a predetermined brightness to the black area of a predetermined brightness is 1: 100 or more (that is, the black area is 100 times or more the white area), It is preferable to stop the charging. Furthermore, it is preferable to stop the precharge when the ratio of the white area of the predetermined brightness to the black area of the predetermined brightness is 1: 200 or more (that is, the black area is 200 times or more the white area).

When the driving TFT 11a of the pixel 16 is a P channel, the precharge voltage PV needs to be output from the source driver circuit (IC) 14 at a voltage close to Vdd (see FIG. 1). However, this precharge voltage P
As V becomes closer to Vdd, the driver circuit (IC) 14 needs to use a semiconductor having a high withstand voltage process (the high withstand voltage is 5 (V) to 10 (V), but
The problem is that if the withstand voltage exceeds 5 (V), the semiconductor process price increases. Therefore, it is possible to use a higher-definition, lower-priced process that adopts a 5 (V) withstand voltage process.

When the driving TFT 11a of the pixel 16 has a good diode characteristic and an on-state current for white display is secured, 5
If (V) or less, the source driver IC 14 is also 5
(V) Since the process can be used, no problem occurs. However, when the diode characteristic exceeds 5 (V), it becomes a problem. Particularly, the precharge cannot be output from the IC 14 because it is necessary to apply the precharge voltage PV close to the source voltage Vdd of the TFT 11a.

FIG. 92 shows a panel structure for solving this problem. In FIG. 92, the switch circuit 64 is provided on the array 71 side.
1 is formed. The source driver IC 14 outputs an ON / OFF signal for the switch 641. This on / off signal is applied to the level shift circuit 69 formed in the array 71.
The voltage is boosted at 3, and the switch 641 is turned on and off.
Note that the switch 641 and the level shift circuit 693 are formed simultaneously or sequentially in the process of forming the TFT of the pixel. Of course, it may be separately formed by an external circuit (IC) and mounted on the array 71.

The ON / OFF signal has been described above (FIG. 75, etc.).
The terminal 76 of the IC 14 is
It is output from 1a. Therefore, it goes without saying that the method of applying and driving the precharge voltage can be applied to the embodiment of FIG. The voltage (signal) output from the terminal 761a is as low as 5 (V) or less. This voltage (signal)
The level shifter circuit 693 increases the amplitude up to the on / off logic level of the switch 641.

With the above structure, the source driver circuit (IC) 14 has a sufficient power supply voltage within the operating voltage range capable of driving the program current Iw. The pre-charge voltage PV is no problem in the array substrate 71 having a high operating voltage. Therefore, the precharge can be sufficiently applied up to the Vdd voltage.

If the switch circuit 641 of FIG. 89 is also formed (arranged) in the source driver circuit (IC) 14, the breakdown voltage becomes a problem. For example, if the Vdd voltage of pixel 16 is
If it is higher than the power supply voltage of IC14, terminal 7 of IC14
This is because there is a risk that a voltage that destroys the IC 14 is applied to 61.

The embodiment shown in FIG. 91 solves this problem. A switch circuit 641 is formed (arranged) on the array substrate 71. The configuration and the like of the switch circuit 641 is the same as or similar to the configuration and specifications described in FIG.

The switch 641 is arranged before the output of the IC 14 and in the middle of the source signal line 18. When the switch 641 is turned on, the current Iw for programming the pixel 16 flows into the source driver circuit (IC) 14. When the switch 641 is turned off, the source driver circuit (IC) 14 is disconnected from the source signal line 18. By controlling this switch 641, it is possible to implement the drive system shown in FIG.

Similar to FIG. 92, the voltage (signal) output from the terminal 761a is as low as 5 (V) or less. The amplitude of this voltage (signal) is increased to the on / off logic level of the switch 641 by the level shifter circuit 693.

With the above configuration, the source driver circuit (IC) 14 has a sufficient power supply voltage within the operating voltage range capable of driving the program current Iw. Further, since the switch 641 also operates with the power supply voltage of the array 71,
Even if the Vdd voltage is applied to the source signal line 18 from the pixel 16, the switch 641 is not destroyed, and the source driver circuit (IC) 14 is not destroyed.

It goes without saying that both the switch 641 and the precharge voltage PV application switch 641 arranged (formed) in the middle of the source signal line 18 in FIG. 91 may be formed (arranged) on the array substrate 71. Yes (Fig. 91+
92 configuration).

As described above, as shown in FIG.
6 driving TFT 11a, selection TFT (11b, 11
When c) is a P-channel TFT, a penetration voltage is generated. This is because the potential variation of the gate signal line 17a is caused by the G-S capacitance (parasitic capacitance) of the selection TFT (11b, 11c).
This is because it penetrates through the terminal of the capacitor 19 via. When the P-channel transistor 11b turns off, the voltage becomes Vgh voltage. Therefore, the terminal voltage of the capacitor 19 slightly shifts to the Vdd side. Therefore, the gate (G) terminal voltage of the transistor 11a rises, resulting in a more black display.

On the other hand, although complete black display of the first gradation can be realized, it is difficult to display the second gradation.
Alternatively, a large gradation jump occurs from the first gradation to the second gradation, or blackout occurs in a specific gradation range.

A structure for solving this problem is the structure shown in FIG. It is characterized by having a function of raising the output current value. The main purpose of the padding circuit 711 is to compensate for punch-through voltage. Also, the image data is black level 0.
Even in such a case, the current can be made to flow to some extent (several tens nA) and can be used for adjusting the black level.

Basically, in FIG. 71, a padding circuit (a portion surrounded by a dotted line in FIG. 71) is added to the output stage of FIG. FIG. 71 shows 3 as the current value raising control signal.
Bits (K0, K1, K2) are assumed, and 0 to 3 of the current value of the grandchild current source are controlled by the control signal of 3 bits.
It is possible to add a sevenfold current value to the output current.

The above is the source driver circuit (I
C) A basic overview of 14. Hereinafter, the source driver circuit (IC) 14 of the present invention will be described in more detail.

There is a linear relationship between the current I (A) flowing through the EL element 15 and the light emission brightness B (nt). That is, the current I (A) flowing through the EL element 15 is proportional to the emission brightness B (nt). In the current drive method, 1 step (gradation step)
Current (current source 634 (1 unit)).

[0672] The visual sense of human brightness has a squared characteristic. That is, the brightness is perceived as changing linearly when it changes with a square curve. However, FIG.
The relationship between EL in both low and high brightness areas
The current I (A) flowing through the element 15 is proportional to the light emission brightness B (nt). Therefore, when the brightness is changed step by step, the luminance change with respect to one step is large in the low gradation part (black area) (black jump occurs). Since the high gradation part (white area) almost coincides with the linear area of the square curve,
It is perceived that the luminance changes for the steps are changing at equal intervals. From the above, in the current driving method (when one step is the current step) (in the current driving method source driver circuit (IC) 14), the black display region becomes a problem.

To address this problem, the present invention reduces the slope of the current output in the low gradation region (gradation 0 (complete black display) to gradation (R1)) as shown in FIG. The slope of the current output in the high gradation region (gradation (R1) to maximum gradation (R)) is increased. That is, in the low gradation region, the amount of current increases per gradation (1 step) and is small. In the high gradation region, the amount of current increases per gradation (one step), which is large. By making the amount of current changing per step different in the two gradation regions of FIG. 79, the gradation characteristics become close to a square curve, and blackening does not occur in the low gradation region. The gradation-current characteristic curve illustrated in FIG. 79 and the like above is called a gamma curve.

In the above embodiment, the current gradient has two levels, that is, the low gradation region and the high gradation region. However, the present invention is not limited to this. It goes without saying that the number of steps may be three or more. However, it goes without saying that the case of two stages is preferable because the circuit configuration becomes simple.

The technical idea of the present invention is a circuit in which a source driver circuit (IC) of a current drive system is used (basically, a gradation display is made by a current output. Therefore, the display panel is limited to an active matrix type. However, a simple matrix type is also included.) That is, a plurality of current increase amounts per one gradation step exist.

In a current-driven display panel such as EL, the display brightness changes in proportion to the amount of applied current. Therefore, in the source driver circuit (IC) 14 of the present invention,
The brightness of the display panel can be easily adjusted by adjusting the reference current that is a source of current flowing through one current source (one unit) 634.

In the EL display panel, R, G, and B have different luminous efficiencies, and the color purity with respect to the NTSC standard is deviated. Therefore, in order to optimize the white balance, it is necessary to properly adjust the RGB ratio. The adjustment is performed by adjusting the respective reference currents of RGB. For example, the reference current for R is 2 μA, the reference current for G is 1.5 μA, and the reference current for B is 3.5 μA. In the driver of the present invention, the reference current is as shown in FIG.
The current mirror 631 of the first stage current source 631 of No. 7 has a small current mirror magnification (for example, if the reference current is 1 μA, the current flowing through the transistor 632b is set to 1/100, 10 nA), and the reference current adjusted from the outside The adjustment accuracy can be made rough and the accuracy of the minute current in the chip can be adjusted efficiently.

In order to realize the gamma curve of FIG. 79, a reference current adjusting circuit in the low gradation region and a reference current adjusting circuit in the high gradation region are provided. Further, each RGB is provided with a reference current adjusting circuit for a low gradation region and a reference current adjusting circuit for a high gradation region so that RGB can be adjusted independently. Of course, when one color is fixed and the white balance is adjusted by adjusting the reference currents of the other colors, two colors (for example, when G is fixed, R,
It suffices to provide a reference current adjusting circuit in the low gradation region and a reference current adjusting circuit in the high gradation region for adjusting B).

In the current driving method, as shown in FIG. 83, the relationship between the current I flowing through the EL and the luminance has a linear relationship. Therefore, the adjustment of the white balance by mixing the RGB need only adjust the RGB reference current at one point of the predetermined brightness. That is, if the RGB reference currents are adjusted and the white balance is adjusted at one point of a predetermined brightness, the white balance is basically achieved over all the gradations.

However, in the case of the gamma curve of FIG. 79,
A little caution is required. First, in order to obtain the white balance of RGB, it is necessary to make the bending position (gradation R1) of the gamma curve the same for RGB (conversely, in the current drive method, the relative relationship of the gamma curve is It means that RGB can be the same). In addition, the ratio of the inclination of the low gradation area to the inclination of the high gradation area is RGB,
It is necessary to make them constant (that is, in the current drive method, the relative relationship of the gamma curves can be the same for RGB). For example, 10 nA increase per gradation in the low gradation area (gradient of gamma curve in the low gradation area)
Then, increase by 50 nA per gradation in the high gradation area (gradient of gamma curve in the high gradation area) (Note that the current increase amount per gradation in the high gradation area / current increase per gradation in the low gradation area) The quantity is referred to as the gamma current ratio, which in this example is 50 nA / 10 nA = 5). Then, the RGB gamma current ratios are made the same. That is,
In RGB, the current flowing through the EL element 15 is adjusted with the gamma current ratio kept the same.

FIG. 80 shows an example of the gamma curve.
In FIG. 80A, the current increase per gradation is large in both the low gradation part and the high gradation part. In FIG. 80 (b), the increase in current per gradation in both the low gradation part and the high gradation part is smaller than that in FIG. 80 (a). However, FIG. 80 (a) and FIG. 80 (b)
Both have the same gamma current ratio. In this way, adjusting the gamma current ratio while maintaining the same for RGB allows the constant current circuit that generates the reference current to be applied to the low gradation part and the reference current to be applied to the high gradation part for each color to be adjusted. This is because a constant current circuit to be generated may be manufactured, and a volume for adjusting a current flowing through these may be manufactured (arranged).

FIG. 77 shows that the gamma current ratio is maintained,
This is a circuit configuration that changes the output current. Current control circuit 77
2, while maintaining the gamma current ratio between the reference current source 771L in the low current region and the reference current source 771H in the high current region,
The currents flowing through the current sources 633L and 633H are changed.

Further, as shown in FIG. 78, it is preferable that the temperature detection circuit 781 formed in the IC chip (circuit) 14 detect the relative temperature of the display panel. This is because the organic EL element has different temperature characteristics depending on the materials forming RGB. This temperature detection utilizes that the state of the junction of the bipolar transistor changes with temperature and the output current changes with temperature. The detected temperature is fed back to the temperature control circuit 782 arranged (formed) for each color, and the current control circuit 772 performs temperature compensation.

Note that it is appropriate to set the gamma ratio to a relationship of 3 or more and 10 or less by study. More preferably, it is appropriate that the relationship is 4 or more and 8 or less. In particular, it is preferable that the gamma current ratio satisfies the relationship of 5 or more and 7 or less. This is called the first relationship.

Further, it is appropriate that the change point between the low gradation part and the high gradation part (gradation R1 in FIG. 79) is set to 1/32 or more and 1/4 or less of the maximum gradation number K ( For example, if the maximum gradation number K is 64 gradations of 6 bits, 64/32
= 2nd gray scale or more and 64/4 = 16 gray scale or less). More preferably, the change point between the low gradation part and the high gradation part (gradation R1 in FIG. 79) is 1 / the maximum gradation number K.
It is appropriate to set it to 16 or more and 1/4 or less (for example, if the maximum gradation number K is 6 bits, 64 gradations, 64
/ 16 = 4th gradation or more and 64/4 = 16th gradation or less). More preferably, it is 1/10 of the maximum gradation number K.
It is appropriate to set it to ⅕ or less (if a decimal point is generated by calculation, it is rounded down. For example, if the maximum gradation number K is 64 bits of 6 bits, 64
/ 10 = 6th gradation or more and 64/5 = 12th gradation or less). The above relationship is called the second relationship. Note that the above description relates to the gamma current ratio in the two current regions. However, the above second relationship is also applied when there are three or more current region gamma current ratios (that is, there are two or more bending points). That is, it is only necessary to apply the relationship to any two inclinations with respect to three or more inclinations.

By satisfying both the above first relationship and second relationship at the same time, it is possible to realize a good image display without blackout.

FIG. 82 shows an embodiment in which a plurality of current source type source driver circuits (ICs) 14 of the present invention are used in one display panel. Source driver IC 14 of the present invention
Is supposed to use multiple driver ICs 14,
It has a slave / master (S / M) terminal. S
It operates as a master chip by setting the / M terminal to the H level, and outputs the reference current from the reference current output terminal (not shown). This current is the slave IC14 (14
a, 14c), the current flows through the INL and INH terminals in FIGS. 73 and 74. By setting the S / M terminal to the L level, the IC 14 operates as a slave chip and receives the reference current of the master chip from the reference current input terminal (not shown). This current is INL, IN in FIGS. 73 and 74.
It becomes the current flowing through the H terminal.

The reference current transferred between the reference current input terminal and the reference current output terminal is of two systems, a low gradation area and a high gradation area of each color. Therefore, in the three colors of RGB, 3
X2 gives 6 lines. In the above embodiment, each color is 2
Although the system is used, the system is not limited to this, and three or more systems for each color may be used.

In the current driving system of the present invention, as shown in FIG. 81, the bending point (gradation R1 etc.) can be changed. In FIG. 81 (a), the low gradation part and the high gradation part are changed at gradation R1, and in FIG. 81 (b),
The low gradation portion and the high gradation portion are changed at the gradation R2. In this way, the bending position can be changed at a plurality of positions.

Specifically, the present invention can realize 64-gradation display. No bending point (R1), 2nd gradation,
The 4th gradation, the 8th gradation, and the 16th gradation are set. In addition, since the gradation is 0 for completely black display, the number of bending points is 2,
If the gradation of black display is completely set to gradation 1, the bending points are 3, 5,
It becomes 9, 17, 33. As described above, it is possible to simplify the circuit configuration by arranging the bending position at a position that is a multiple of 2 (or a position that is a multiple of 2 + 1 when perfect black display is gradation 1). The effect occurs.

FIG. 73 is a block diagram of a current source circuit section in the low current region. In addition, FIG. 74 is a configuration diagram of the current source unit and the padding current circuit unit in the high current region. As shown in FIG. 73, a reference current INL is applied to the low current source circuit section, and this current basically becomes a unit current, and the input data L0 to L
4, the required number of the current sources 634 operate, and the program current IwL of the low current portion flows as a total thereof.

As shown in FIG. 74, the reference current INH is applied to the high current source circuit section, and basically this current becomes a unit current, and the required number of current sources 634 operate according to the input data H0 to L5. However, the program current IwH of the low current portion flows as the sum thereof.

The same is true for the padding current circuit section, as shown in FIG.
A reference current INH is applied as shown in FIG. 2, and this current basically becomes a unit current, and the input data AK0 to AK
2, the required number of the current sources 634 operate, and the program current Iw flowing through the source signal line 18 in which the current IwK corresponding to the padding current flows as a total is Iw = IwH +
IwL + IwK. The ratio of IwH and IwL,
That is, the gamma current ratio is set to satisfy the first relationship described above.

As shown in FIGS. 73 and 74, the on / off switch 641 is composed of an inverter 732 and an analog switch 731 composed of a P-channel transistor and an N-channel transistor. By configuring the switch 641 with the inverter 732 and the analog switch 731 including the P-channel transistor and the N-channel transistor as described above, the on-resistance can be reduced, and the voltage drop between the current source 634 and the source signal line 18 can be reduced. It can be extremely small.

Operation of the low current circuit section of FIG. 73 and the high current circuit section of FIG. 74 will be described. The source driver circuit (IC) 14 of the present invention is configured by 5 bits of the low current circuit units L0 to L4 and 6 bits of the high current circuit units H0 to H5. The data input from the outside of the circuit is 6 bits D0 to D5 (64 gradations for each color). This 6
Bit data of 5 bits of L0 to L4, high current circuit section H
The program current Iw corresponding to the image data is applied to the source signal line after being converted into 6 bits of 0 to H5. That is,
The input 6-bit data is converted into 5 + 6 = 11-bit data. Therefore, a highly accurate gamma curve can be formed.

[0696] As described above, input 6-bit data is converted to 5
It is converted to + 6 = 11-bit data. In the present invention, the number of bits (H) of the circuit in the high current region is the same as the number of bits of the input data (D), and the number of bits (L) of the circuit in the low current region is the number of bits of the input data (D). -1. The bit number (L) of the circuit in the low current region may be the bit number-2 of the input data (D). With this configuration, the gamma curve in the low current region and
The gamma curve in the high current region is most suitable for image display on the EL display panel.

The circuit control data (L0
~ L4) and circuit control data of high current area (H0 to H4)
The control method for and will be described with reference to FIGS. 84 to 86.

The present invention is characterized by the operation of the current source 634a connected to the L4 terminal of FIG. 73 of FIG. This 63
4a is composed of one transistor which serves as a unit of current source. By turning on / off this transistor, control of the program current Iw (on / off control) becomes easy.

FIG. 84 shows applied signals to the low current side signal line (L) and the high current side signal line (H) when the low current region and the high current region are switched by gradation 4. 84 to 86, the gradations 0 to 18 are shown, but actually the gradations are up to the 63rd gradation. Therefore, gradations 18 and above are omitted in each drawing. The switch 641 is turned on when the value is “1” in the table, the corresponding current source 634 and the source signal line 18 are connected, and the switch 641 is selected when the value is “0” in the table.
It is said that 1 is off.

In FIG. 84, in the case of gradation 0 of completely black display, (L0 to L4) = (0,0,0,0,0), and (H0 to H5) = (0,0,0) , 0, 0).
Therefore, all the switches 641 are off, and the source signal line 18 has the program current Iw = 0.

At gradation 1, (L0 to L4) = (1, 0,
0, 0, 0), and (H0 to H5) = (0, 0, 0,
0, 0). Therefore, one unit current source 634 in the low current region is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

At gradation 2, (L0 to L4) = (0, 1,
0, 0, 0), and (H0 to H5) = (0, 0, 0,
0, 0). Therefore, the two unit current sources 634 in the low current region are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

At gradation 3, (L0 to L4) = (1, 1,
0, 0, 0), and (H0 to H5) = (0, 0, 0,
0, 0). Therefore, the two switches 641La and 641Lb in the low current region are turned on, and the three unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

At gradation 4, (L0 to L4) = (1, 1,
0, 0, 1), and (H0 to H5) = (0, 0, 0,
0, 0). Therefore, the three switches 641La, 641Lb, 641Le in the low current region are turned on, and
One unit current source 634 is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

At a gradation level of 5 or higher, the low current region (L0 to L
4) = (1,1,0,0,1) is unchanged. But,
In the high current region, at gradation 5, (H0 to H5) =
(1, 0, 0, 0, 0), the switch 641Ha is turned on, and one unit current source 641 in the high current region is connected to the source signal line 18. For gradation 6, (H0
~ H5) = (0, 1, 0, 0, 0) and switch 6
41Hb is turned on, and two unit current sources 64 in the high current region
1 is connected to the source signal line 18. Similarly, for gradation 7, (H0 to H5) = (1,1,0,0,0), and 2
One switch 641Ha switch 641Hb turns on,
The three unit current sources 641 in the high current region are the source signal lines 1
8 is connected. Furthermore, at gradation 8, (H0 to H5) =
(0, 0, 1, 0, 0) and one switch 641
Hc is turned on, and the four unit current sources 641 in the high current region are connected to the source signal line 18. Thereafter, the switch 641 is sequentially turned on and off as shown in FIG. 84, and the program current Iw
Is applied to the source signal line 18.

A characteristic feature of the above operation is a bending point (a switching point between a low current region and a high current region, more precisely, a low current IwL is added as the program current Iw in the case of a gradation in the high current region. Therefore, the expression "switching point" is not correct (and the padding current IwK is also added), that is, in the gradation of the high gradation part, it is added to the current of the low gradation part, The current corresponding to the step (gradation) is the program current Iw.Control of the low current region is performed with the gradation of one step (which should be called a point or point or position where the current changes) as a boundary. The bit (L) does not change, and at this time, the L4 terminal in FIG.
This is a point at which e is turned on and a current flows through the transistor 634a. Therefore, in gradation 4 in FIG. 84, four unit transistors (current sources) 634 in the low gradation part are operating. Then, at gradation 5, four unit transistors (current sources) 634 in the low gradation portion are operating and one transistor (current source) 634 in the high gradation portion is operating. Thereafter, similarly, in the gradation 6, four unit transistors (current sources) 634 in the low gradation part operate and two transistors (current source) 634 in the high gradation part operate. Therefore, when the gray level is 5 or more, which is the bending point, the current sources 634 in the low gray level region below the bending point are turned on for the gray level (4 in this case), and in addition to this, the current of the high gray level portion is sequentially added. The number of sources 634 sequentially turns on according to the gradation.

Therefore, it can be seen that one of the transistors 634a at the L4 terminal in FIG. 73 works effectively. If this transistor 634a is not provided, the operation is such that one transistor 634 in the high gradation part is turned on next to the gradation 3. Therefore, the switching points are 4, 8 and 16
It doesn't become a power of 2. The multiplier of 2 is a state in which only one signal is "1". Therefore, it is easy to determine the condition that the signal line with the weight of 2 becomes "1". Therefore, the hardware scale for condition determination can be reduced. That is, the logic circuit of the IC chip is simplified, and as a result, an IC having a small chip area can be designed (cost can be reduced).

FIG. 85 is an explanatory diagram of applied signals to the low current side signal line (L) and the high current side signal line (H) when switching the low current region and the high current region at the gradation 8.

In FIG. 85, in the case of gradation 0 of completely black display, it is the same as in FIG. 84, and (L0 to L4) = (0,
0, 0, 0, 0), and (H0 to H5) = (0, 0,
0, 0, 0). Therefore, all switches 6
41 is in the off state, and the source signal line 18 has the program current Iw = 0.

Similarly, for gradation 1, (L0 to L4) =
(1,0,0,0,0) and (H0-H5) =
(0, 0, 0, 0, 0). Therefore, one unit current source 634 in the low current region is connected to the source signal line 18. The unit current source in the high current region is the source signal line 1
8 is not connected.

For gradation 2, (L0 to L4) = (0, 1,
0, 0, 0), and (H0 to H5) = (0, 0, 0,
0, 0). Therefore, the two unit current sources 634 in the low current region are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

For gradation 3, (L0 to L4) = (1, 1,
0, 0, 0), and (H0 to H5) = (0, 0, 0,
0, 0). Therefore, the two switches 641La and 641Lb in the low current region are turned on, and the three unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

Similarly, for gradation 4, (L0 to L)
4) = (0,0,1,0,0), and (H0-H5)
= (0,0,0,0,0). Also, with gradation 5,
(L0 to L4) = (1, 0, 1, 0, 0), and (H
0 to H5) = (0,0,0,0,0). At gradation 6, (L0 to L4) = (0, 1, 1, 0, 0),
(H0 to H5) = (0,0,0,0,0). Further, in the gradation 7, (L0 to L4) = (1,1,1,0,
0), and (H0 to H5) = (0, 0, 0, 0, 0)
Is.

[0714] Gradation 8 is the switching point (bending position). At gradation 8, (L0 to L4) = (1,
1, 1, 0, 1), and (H0 to H5) = (0, 0,
0, 0, 0). Therefore, the four switches 641La, 641Lb, 641Lc, 641 in the low current region
Le is turned on, and eight unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

[0715] For gradations 8 and above, a low current region (L0 to L
4) = (1,1,1,0,1) is unchanged. But,
In the high current region, at gradation 9, (H0 to H5) =
(1, 0, 0, 0, 0), the switch 641Ha is turned on, and one unit current source 641 in the high current region is connected to the source signal line 18.

Similarly, the number of transistors 634 in the high current region is increased by one according to the gradation step. That is, at gradation 10, (H0 to H5) = (0, 1,
0, 0, 0), the switch 641Hb is turned on, and the two unit current sources 641 in the high current region are connected to the source signal line 18
Connected with. Similarly, for gradation 11, (H0 to H5) =
(1, 1, 0, 0, 0) and two switches 641
The Ha switch 641Hb is turned on, and the three unit current sources 641 in the high current region are connected to the source signal line 18. Further, in gradation 12, (H0 to H5) = (0, 0, 1,
0, 0), one switch 641Hc is turned on,
The four unit current sources 641 in the high current region are the source signal lines 1
8 is connected. After that, as shown in FIG.
41 is turned on and off, and the program current Iw is applied to the source signal line 18.

FIG. 86 is an explanatory diagram of applied signals to the low current side signal line (L) and the high current side signal line (H) when the low current region and the high current region are switched by the gradation 16. Also in this case, the basic operation is the same as in FIGS. 84 and 85.

That is to say, in FIG. 86, the case of gradation 0 of full black display is the same as in FIG. 85, and (L0 to L4) =
(0, 0, 0, 0, 0) and (H0-H5) =
(0, 0, 0, 0, 0). Therefore, all the switches 641 are off, and the source signal line 18 has the program current Iw = 0. Similarly, from the gradation 1 to the gradation 16, (H0 to H5) = (0,
0, 0, 0, 0). Therefore, in the low current region 1
One unit current source 634 is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18. That is, (L0 to L in the low gradation region)
Only 4) changes.

That is, for gradation 1, (L0 to L4) =
(1, 0, 0, 0, 0), and at gradation 2, (L0-
L4) = (0,1,0,0,0), and in gradation 3,
(L0 to L4) = (1,1,0,0,0), and at gradation 2, (L0 to L4) = (0,0,1,0,0). The gradation is counted up to 16 in sequence. That is, at gradation 15, (L0 to L4) = (1,1,1,1,0)
And in gradation 16, (L0 to L4) = (1, 1,
1, 1, 1). In gradation 16, D0 indicating gradation
Since only one of the fifth bit (D4) of D5 is turned on, it can be determined by the determination of one data signal line (D4) that the content represented by the data D0 to D5 is 16.
Therefore, the hardware scale of the logic circuit can be reduced.

The gradation 16 is the switching point (the bending position) (or the gradation 17 may be the switching point). At gradation 16,
(L0 to L4) = (1, 1, 1, 1, 1), and (H
0 to H5) = (0,0,0,0,0). Therefore, the four switches 641La and 641L in the low current region
b, 641Lc, 641d, 641Le turn on, 16
One unit current source 634 is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

At gradation levels 16 and above, a low current region (L0 to L
4) = (1,1,1,0,1) is unchanged. But,
In the high current region, at gradation 17, (H0 to H5) =
(1, 0, 0, 0, 0), the switch 641Ha is turned on, and one unit current source 641 in the high current region is connected to the source signal line 18. Hereinafter, similarly, the number of the transistors 634 in the high current region is increased by one according to the gradation step. That is, at gradation 18, (H0-H
5) = (0,1,0,0,0), and the switch 641
Hb is turned on, and the two unit current sources 641 in the high current region are connected to the source signal line 18. Similarly, in gradation 19, (H0 to H5) = (1,1,0,0,0), two switches 641Ha switch 641Hb are turned on, and three unit current sources 641 in the high current region are source signals. Line 18
Connected with. Furthermore, at gradation 20, (H0 to H5) =
(0, 0, 1, 0, 0) and one switch 641
Hc is turned on, and the four unit current sources 641 in the high current region are connected to the source signal line 18.

As described above, at the switching point (the bending position), the number of current sources (1 unit) of the number of powers of 2 is 6
The logic processing for configuring 34 to be turned on or connected to the source signal line 18 (conversely, a configuration in which it is turned off is also conceivable) becomes extremely easy. For example, as shown in FIG. 84, if the bending position is gradation 4 (4 is a multiplier of 2), four current sources (one unit) 634 are operated. And for higher tones,
The current source (1 unit) 634 in the high current region is configured to be added. Further, as shown in FIG. 85, if the bending position is gradation 8 (8 is a multiplier of 2), eight current sources (one unit) 634 are configured to operate. Then, for gradations higher than that, the current sources (1 unit) 634 in the high current region are configured to be added. If the configuration of the present invention is adopted, it is not limited to 64 gradations (16 gradations: 4
(096 colors, 256 gradations: 16.7 million colors, etc.), a gamma control circuit with a small hardware configuration can be configured with any gradation expression.

In the embodiments described with reference to FIGS. 84, 85 and 86, the gradation at the switching point is a multiplier of 2, but this is the case where the complete black gradation is gradation 0. . When the gradation 1 is to be displayed completely in black, it is necessary to add +1. However, these are matters of convenience. What is important in the present invention is to have a plurality of current regions (low current region, high current region, etc.), and to configure the switching point so that the signal input can be determined (processed) with a small amount of signal input.
As an example, if it is a multiplier of 2, it is a technical idea that the hardware scale becomes extremely small because only one signal line needs to be detected. Also, in order to facilitate the process,
A current source 634a is added.

Therefore, with negative logic, 2, 4, 8
.., but gradations 1, 3, 7, 15 ,. Further, although the gradation 0 is displayed completely in black, it is not limited to this. For example, 6
In case of 4 gradation display, gradation 63 is set to a completely black display state,
The gradation 0 may be the maximum white display. In this case, the switching points may be processed in consideration of the reverse direction.
Therefore, there may be a case where the processing is different from the multiplier of 2 in terms of processing.

The switching point (bending position) is not limited to one gamma curve.
The circuit of the present invention can be configured even if there are a plurality of bending positions. For example, the bending position can be set to gradation 4 and gradation 16. It is also possible to set three points or more such as gradation 4, gradation 16, and gradation 32.

In the above embodiment, the gradation is set to a power of 2, but the present invention is not limited to this. For example, the powers of 2 and 8 (2 + 8 =
The bending point may be set at the tenth gradation, that is, two signal lines required for the determination. 2 of 2 or more
The bending points may be set at 8 and 16 (2 + 8 + 16 = 26th gradation, that is, three signal lines are required for determination). In this case, although the hardware scale required for the determination or the processing becomes somewhat large, it is possible to sufficiently deal with it in terms of the circuit configuration. Needless to say, the matters described above are included in the technical scope of the present invention.

As shown in FIG. 87, the source driver circuit (IC) 14 of the present invention is composed of three parts of the current output circuit 704. A high current region current output circuit 704a which operates in a high gradation region and a low current region current output circuit 704b which operates in a low current region and a high gradation region.
The current raising current output circuit 704b outputs the raising current.

The high current region current output circuit 704a and the current raising current output circuit 704c operate with the reference current source 771a that outputs a high current as a reference current, and the low current region current output circuit 704b outputs a low current. 771b
Operates as a reference current.

As described above, the current output circuit 7
Reference numeral 04 denotes a high current region current output circuit 704a, a low current region current output circuit 704b, and a current raising current output circuit 704.
It is not limited to three of c, but may be two of a high current region current output circuit 704a and a low current region current output circuit 704b, or may be composed of three or more current output circuits 704. Further, the reference current source 771 may be arranged or formed corresponding to each current domain current output circuit 704, and all the current domain current output circuits 704 may be provided.
You may make it common to.

The above current output circuit 704 operates the internal transistor 634 in response to the grayscale data to absorb the current from the source signal line 18. And transistor 6
34 operates in synchronization with the signal for one horizontal scanning period (1H). That is, the current based on the corresponding grayscale data is input during the period of 1H (when the transistor 634 is an N channel).

On the other hand, the gate driver circuit 12 basically selects one gate signal line 17a sequentially in synchronization with the 1H signal. That is, in synchronization with the 1H signal, the gate signal line 17a (1) is selected in the first H period, the gate signal line 17a (2) is selected in the second H period, and the gate signal line 17a is selected in the third H period. (3) is selected, and the gate signal line 17a (4) is selected in the fourth H period.

However, from the selection of the first gate signal line 17a to the selection of the next second gate signal line 17a, a period in which no gate signal line 17a is selected (non-selection period, 88 t1). The non-selection period needs a rising period and a falling period of the gate signal line 17a, and is provided to secure an on / off control period of the TFT 11d.

If the ON voltage is applied to any of the gate signal lines 17a and the TFTs 11b and 11c of the pixel 16 are turned on, the source signal line 18 is programmed from the Vdd power source (anode voltage) through the driving TFT 11a. The current Iw flows. The program current Iw flows through the transistor 634 (period t2 in FIG. 88). A parasitic capacitance C is generated in the source signal line 18 (a parasitic capacitance is generated due to the capacitance at the cross point between the gate signal line and the source signal line).

However, when none of the gate signal lines 17a is selected (non-selected period, t1 period in FIG. 88), T is set.
There is no current path through the FT 11a. Transistor 63
Since 4 passes a current, it absorbs electric charges from the parasitic capacitance of the source signal line 18. Therefore, the potential of the source signal line 18 decreases (portion A in FIG. 88). When the potential of the source signal line 18 drops, it takes time to write a current corresponding to the next image data.

To solve this problem, as shown in FIG. 89, a switch 64 is provided at the output end of the source terminal 761.
1a is formed. Further, the padding current / current output circuit 704
The switch 641b is formed or placed in the output stage of c.

In the non-selection period t1, a control signal is applied to the control terminal S1 to turn off the switch 641a. In the selection period t2, the switch 641a is turned on (conduction state).
To Program current Iw = IwH in ON state
+ IwL + IwK flows. When the switch 641a is turned off, the Iw current does not flow. Therefore, as shown in FIG. 90, the potential as indicated by A in FIG. 88 decreases (no change). The analog switch 731 of the switch 641
The channel width W is set to 10 μm or more and 100 μm or less. The W (channel width) of this analog switch needs to be 10 μm or more in order to reduce the ON resistance. However, if W is too large, the parasitic capacitance also becomes large, so the value is set to 100 μm or less. More preferably, the channel width W is preferably 15 μm or more and 60 μm or less.

The switch 641b is a switch for controlling only low gradation display. During low gradation display (black display), the gate potential of the TFT 11a of the pixel 16 needs to be close to Vdd (thus, in black display, the source signal line 18).
Must be near Vdd). In black display, the program current Iw is small, and once the potential drops as shown in A of FIG. 88, it takes a long time to return to the normal potential.

Therefore, in the case of low gradation display, it is necessary to avoid the occurrence of the non-selection period t1. vice versa,
In high gradation display, since the program current Iw is large, there is often no problem even if the non-selection period t1 occurs. Therefore, in the present invention, when writing an image of high gradation display,
Even in the non-selection period, both the switch 641a and the switch 641b are turned on. It is also necessary to cut off the padding current IwK. This is to realize black display as much as possible. In the image writing for low gradation display, the switch 641a is turned on and the switch 641b is turned off during the non-selection period. The switch 641b is controlled by the terminal S2.

Of course, in both the low gradation display and the high gradation display, the switch 641a is turned off (non-conducting state) and the switch 641b is kept on (conducting) during the non-selection period t1. Good. Of course, in both the low gradation display and the high gradation display, driving may be performed with both the switches 641a and 641b turned off (non-conducting) during the non-selection period t1.

In any case, the switch 641 can be controlled by controlling the control terminals S1 and S2. The control terminal S
1, S2 is controlled by command control.

For example, the control terminal S2 is set in the non-selection period t1.
The period t3 is set to the "0" logic level so as to overlap with each other. By controlling in this way, FIG.
State A of 8 does not occur. Further, when the gradation is a black display level above a certain level, the control terminal S1 is set to the "0" logic level. Then, the padding current IwK is stopped, and more black display can be realized.

The above embodiments have been described on the assumption that one source driver IC 14 is mounted on the display panel. However, the present invention is not limited to this configuration. A plurality of source driver ICs 14 may be stacked on one display panel. For example, FIG.
It is an embodiment of a display panel on which one source driver IC 14 is loaded.

The source driver IC 14 of the present invention is shown in FIG.
As described in FIG. 3, FIG. 74, FIG. 76, FIG. 77, etc.,
At least two systems of a reference current in the low gradation region and a reference current in the high gradation region are provided. This is also explained in FIG. 82.

As described with reference to FIG. 82, the current driver type source driver circuit (IC) 14 of the present invention assumes that a plurality of driver ICs 14 are used.
It has a master (S / M) terminal. It operates as a master chip by setting the S / M terminal to H level, and outputs a reference current from a reference current output terminal (not shown). Of course, the logic of the S / M terminal may have opposite polarities. Alternatively, the source driver IC 14 may be switched by a command. The reference current is transmitted through the skate current connection line 931. By setting the S / M terminal to the L level, the IC 14 operates as a slave chip and receives the reference current of the master chip from the reference current input terminal (not shown). This current is INL, I in FIGS. 73 and 74.
It becomes the current flowing through the NH terminal.

The reference current is generated by the current output circuit 704 in the central portion (middle portion) of the IC chip 14. The reference current of the master chip is applied from the outside by adjusting the reference current by an external resistor or a current stepping type electronic volume arranged or configured inside the IC. In addition,
A control circuit (command decoder or the like) is also formed (arranged) in the central portion of the IC chip 14. The reference current source is formed in the center of the chip in order to minimize the distance between the reference current generating circuit and the program current output terminal 761.

In the configuration of FIG. 93, the master chip 14b
The slave chips (14a, 14
c). The slave chip receives a reference current and generates parent, child, and grandchild currents based on this reference current. The reference current delivered by the master chip 14b to the slave chip is provided by the current delivery of the current mirror circuit (see FIG. 67). By passing the current, the deviation of the reference current between the chips is eliminated, and the dividing line of the screen is not displayed.

FIG. 94 conceptually shows the positions of the reference current transfer terminals. The reference current signal line 932 is arranged at the center of the IC chip and connected to the signal input terminal 941i. The current applied to the reference current signal line 932 (which may be a voltage, see FIG. 76) is
The temperature characteristics of the EL material are compensated. In addition, compensation is made by the deterioration of the life of the EL material.

On the basis of the current (voltage) applied to the reference current signal line 932, each current source (631,
632, 633, 634). This reference current is output as a reference current to the slave chip via the current mirror circuit. The reference current to the slave chip is output from the terminal 941o. At least one terminal 941o is arranged (formed) on the left and right of the reference current generation circuit 704. In FIG. 94, two pieces are arranged (formed) on each side.
Has been done. This reference current is the cascade signal line 931.
It is transmitted to the slave chip 14 through a1, 931a2, 931b1, and 931b2. The slave chip 14a
The reference current applied to the master chip 14b may be fed back to the master chip 14b to correct the deviation amount.

An embodiment of the display device of the present invention which uses the display panel and display device of the present invention described above or which implements the drive system of the present invention will be described.

[0750] Fig. 57 is a plan view of a mobile phone as an example of the information terminal device. An antenna 571, a numeric keypad 572, and the like are attached to the housing 573. Reference numeral 572 and the like are display color switching keys or power on / off and frame rate switching keys.

When the key 572 is pressed once, the display color is changed to the 8-color mode, when the same key 572 is pressed, the display color is changed to the 256-color mode, and when the key 572 is pressed, the display color is changed to the 4096-color mode. May be assembled. The key is a toggle switch whose display color mode changes each time it is pressed. A change key for the display color may be separately provided. In this case, the number of keys 572 is three (or more).

The key 572 may be a push switch, another mechanical switch such as a slide switch, or may be switched by voice recognition or the like. For example, by voice inputting 4096 colors into the handset, for example, "high quality display", "256 color mode" or "low display color mode" is input to the handset and displayed on the display screen 50 of the display panel. It is configured so that the display color changes. This can be easily realized by adopting the existing voice recognition technology.

The display color can be switched by an electrically switching switch or a touch panel for selecting by touching a menu displayed on the display unit 21 of the display panel. Alternatively, the switch may be switched depending on the number of times the switch is pressed, or may be switched by rotation or direction like a click ball.

Although 572 is a display color switching key, it may be a key for switching the frame rate or the like. Also, it may be a key for switching between a moving image and a still image. Also, a plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be gradually (continuously) changed when the button is held down.
In this case, it can be realized by changing the resistance R of the capacitor C and the resistance R constituting the oscillator to a variable resistance or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, it may be realized by forming a plurality of capacitors on a semiconductor chip, selecting one or more capacitors, and connecting them in parallel in a circuit.

The technical idea of switching the frame rate according to the display color is not limited to the mobile phone, and is applicable to devices having a display screen such as a palmtop computer, a notebook computer, a desktop computer, and a mobile clock. It can be widely applied. Further, it is not limited to the liquid crystal display device (liquid crystal display panel),
It can also be applied to a liquid crystal display panel, an organic EL display panel, a transistor panel, a PLZT panel, and a CRT.

Although not shown in the mobile phone of the present invention described with reference to FIG. 19, a CCD camera is provided on the back side of the housing. The image taken by the CCD camera can be immediately displayed on the display screen 50 of the display panel. Data captured by the CCD camera can be displayed on the display screen 50. Image data of CCD camera is 24 bits (16.7 million colors), 18
Bit (260,000 colors), 16 bits (650,000 colors), 12
Bit 5 (4096 colors), 8-bit (256 colors) key 5
It can be switched with 72 inputs.

When the display data is 12 bits or more, the error diffusion processing is performed for display. That is, when the image data from the CCD camera exceeds the capacity of the built-in memory, error diffusion processing or the like is performed, and the image processing is performed so that the number of display colors becomes equal to or less than the capacity of the built-in image memory.

Now, the source driver IC 14 has 4096
A description will be given assuming that a built-in RAM for one screen is provided for each color (4 bits for each RGB). When the image data sent from outside the module is 4096 colors, it is directly stored in the built-in image RAM of the source driver IC 14, the image data is read from this built-in image RAM, and the image is displayed on the display screen 50.

Image data has 260,000 colors (G: 6 bits,
In the case of R and B: 5 bits in total (16 bits), the error diffusion or dither processing is performed by an operation circuit that is temporarily stored in the operation memory of the error diffusion controller and at the same time performs error diffusion or dither processing. 16-bit image data is stored in the built-in image RAM by this error diffusion process.
Is converted to 12 bits, which is the number of bits, and transferred to the source driver IC 14. Source driver IC14 is R
Output 4-bit (4096 color) image data for each GB
The image is displayed on the display screen 50.

Further, an embodiment adopting the EL display panel, the EL display device or the driving method of the present invention will be described with reference to the drawings.

FIG. 58 is a sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for ease of explanation. In addition, there are some areas that are enlarged or reduced, and some areas are omitted. For example, in FIG. 58, the eyepiece cover is omitted. The above also applies to other drawings.

The back surface of the body 573 is dark or black. This is an EL display panel (display device) 57.
This is to prevent the stray light emitted from No. 4 from being irregularly reflected on the inner surface of the body 573 and lowering the display contrast. Further, a phase plate (λ / 4 plate, etc.) 10 is provided on the light emitting side of the display panel.
8, a polarizing plate 109 and the like are arranged. This is also explained in FIGS. 10 and 11.

A magnifying lens 582 is attached to the eyepiece ring 581. The observer can change the insertion position of the eyepiece ring 581 in the body 573 to display the display panel 574.
The display image 50 is adjusted so that it is in focus.

If a positive lens 583 is arranged on the light emitting side of the display panel 574 as needed, the magnifying lens 58 can be provided.
The principal ray incident on 2 can be converged. Therefore, the lens diameter of the magnifying lens 582 can be reduced, and the viewfinder can be downsized.

FIG. 59 is a perspective view of a video camera. The video camera includes a photographing (imaging) lens unit 592 and a video or camera body 573, and the photographing lens unit 592 and the viewfinder unit 573 are back to back. Also,
An eyepiece cover is attached to the viewfinder (see also FIG. 58) 573. An observer (user) observes the image 50 on the display panel 574 through the eyepiece cover.

On the other hand, the EL display panel of the present invention is also used as a display monitor. Display unit 50 is fulcrum 591
You can freely adjust the angle with. When the display unit 50 is not used, it is stored in the storage unit 593.

Switch 594 is a changeover or control switch that performs the following functions. The switch 594 is a display mode switching switch. Switch 594
Is preferably attached to a mobile phone or the like. The display mode changeover switch 594 will be described.

One of the driving methods of the present invention is applied with N times the current E
There is a method of supplying the light to the L element 15 and turning on the light only for 1 / M of 1F. The brightness can be digitally changed by changing only the M value of 1 / M to be turned on. For example, assuming N = 4, a four times larger current is passed through the EL element 15. The lighting period is 1 / M, and M = 1,
By switching to 2, 3 and 4, it is possible to switch the brightness from 1 to 4 times. In addition, M = 1, 1.5, 2,
It may be configured so that it can be changed to 3, 4, 5, 6, and the like.

The above switching operation causes the display screen 50 to be displayed very bright when the power of the mobile phone is turned on.
It is used in a configuration in which the display brightness is lowered in order to save power after a certain time has elapsed. It can also be used as a function of setting the brightness desired by the user. For example, when outdoors, the screen is made very bright. This is because when you are outdoors, the surrounding area is bright and you cannot see the screen at all. However, if the display is continued at high brightness, the EL element 15 deteriorates rapidly. Therefore, when it is made extremely bright, it is configured to restore the normal brightness in a short time. Furthermore, when displaying with high brightness, the user can press the button to increase the display brightness.

[0770] Therefore, it is necessary to allow the user to switch using the button 594, to automatically change the setting mode, or to detect the brightness of external light and automatically switch. preferable. In addition, it is preferable that the display brightness can be set to 50%, 60%, and 80% by the user or the like.

The display screen 50 is preferably a Gaussian distribution display. The Gaussian distribution display is a method in which the brightness of the central part is bright and the peripheral part is relatively dark. Visually, if the central part is bright, it is perceived as bright even if the peripheral part is dark. According to the subjective evaluation, if the peripheral part maintains a luminance of 70% as compared with the central part, it is visually comparable. There is almost no problem even if the luminance is further reduced to 50%. In the self-emission type display panel of the present invention, the N-time pulse drive (the N-time current is passed through the EL element 15 described above,
A Gaussian distribution is generated from the top to the bottom of the screen by using a method of lighting only for 1 / M period of 1F).

Specifically, the value of M is increased in the upper and lower parts of the screen, and the value of M is decreased in the central part. This is realized by modulating the operation speed of the shift register of the gate driver 12. The brightness modulation on the left and right of the screen is generated by multiplying the table data and the video data. By the above operation, when the peripheral brightness (angle of view 0.9) is set to 50%, it is possible to reduce the power consumption by about 20% as compared with the case of 100% brightness. When the peripheral brightness (angle of view 0.9) is 70%, it is possible to reduce the power consumption by about 15% as compared with the case of 100% brightness.

Note that it is preferable to provide a changeover switch or the like so that the Gaussian distribution display can be turned on and off. This is because, for example, when a Gaussian display is made outdoors, the periphery of the screen becomes completely invisible. Therefore, it is preferable that the user can switch with a button, can be automatically changed in the setting mode, or can be automatically switched by detecting the brightness of external light. Further, it is preferable that the peripheral brightness can be set to 50%, 60%, 80% by the user or the like.

In the liquid crystal display panel, a fixed Gaussian distribution is generated by the backlight. Therefore, the Gaussian distribution cannot be turned on / off. The fact that the Gaussian distribution can be turned on and off is an effect peculiar to self-luminous display devices.

Also, when the frame rate is predetermined, there may be a case where flicker occurs by interfering with the lighting state of indoor fluorescent lamps. In other words, when the fluorescent lamp is lit with an alternating current of 60 Hz, the EL display element 15 has a frame rate of 60 Hz.
When you are operating in, slight interference may occur and you may feel that the screen is blinking slowly. To avoid this, change the frame rate. The present invention adds a frame rate changing function. Further, in N-fold pulse driving (a method in which a N-fold current is passed through the EL element 15 to turn on for 1 / M of 1F), the value of N or M can be changed.

The above function is realized by the switch 594. The switch 594 implements the function described above by holding down the switch 594 multiple times according to the menu on the display screen 50.

Needless to say, the above items are not limited to mobile phones, but can be applied to televisions, monitors and the like. Also, so that the user can immediately recognize what kind of display state,
It is preferable to display icons on the display screen. The above items also apply to the following items.

The EL display device of this embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The display device is used as the monitor 50 attached to the camera body 601. Camera body 60
In addition to the shutter 603, a switch 594 is attached to the apparatus 1.

The video camera of the present invention is equipped with a touch panel and has an Internet terminal function capable of operating Web browsing, E-mail and the like with a finger or a pen. Further, it is preferable to mount a compact flash card (with error correction function) of 256 Mbytes or more instead of the hard disk device. The capacity can be reduced by adopting only the basic function part of the Windows (registered trademark) OS. Since there is no HDD, you can secure robustness without worrying about disk crashes. Equipped with two PC card slots. Modem, ISDN, PIA
It is preferable to configure so that FS, LAN, wireless LAN, etc. can be used. Built-in antenna for wireless LAN. With the USB / RS232C interface, commercial peripherals such as bar code readers can also be connected. In addition to a keyboard-less space-saving design, it can withstand water and dust (conforms to JIS Drip-proof 2)
To configure. We have improved the operability by assuming the use of BtoBtoC for general users, such as the adoption of a touch panel, "one-touch keys" that can easily start applications, and the installation of handwritten E-mail functions (including handwritten memo functions). ing. The above functions and the like are also mounted on another display device, information terminal, and the like of the present invention.

The above is the case where the display area of the display panel is relatively small, but the display screen 50 is easily bent when the display area is large such as 30 inches or more. To prevent this, in the present invention, an outer frame 611 is attached to the display panel as shown in FIG. 61, and the outer frame 611 is attached by a fixing member 614 so that it can be suspended. Using this fixing member 614, it is attached to a wall or the like.

However, the larger the screen size of the display panel, the heavier the weight becomes. Therefore, the leg mounting portion 613 is arranged on the lower side of the display panel so that the weight of the display panel can be held by the plurality of legs 612.

The leg 612 is constructed so that it can move to the left and right as shown in A, and the leg 612 can contract as shown in B. Therefore, the display device can be easily installed even in a narrow place.

A plastic film-metal plate composite material (hereinafter referred to as a composite material) is used for the leg 612 or the housing (also in the present invention). The composite material is obtained by strongly adhering a metal and a plastic film via a special surface treatment layer (adhesive layer). The metal plate is preferably 0.2 mm or more and 0.8 mm or less, and the plastic film laminated on the metal plate via the special surface treatment layer has a thickness of 15 μm.
It is preferable that the thickness is not less than m and not more than 100 μm. The special adhesion method provides a strong adhesion between the plastic and the metal plate. By using this composite material, it is possible to color, dye, and print the plastic layer.
It is possible to eliminate the secondary processing steps (hand-attaching the film, plating coating) on the pressed parts. It is also suitable for deep drawing and DI molding, which has been impossible in the past.

In the television shown in FIG. 61, the surface of the screen is covered with a protective film (may be a protective plate). This is one purpose to prevent the surface of the display panel from being hit and damaged. A on the surface of the protective film
An IR coat is formed, and the surface is embossed to prevent external conditions (external light) from being reflected on the display panel.

A certain space is arranged by dispersing beads or the like between the protective film and the display panel. Further, a fine convex portion is formed on the back surface of the protective film, and the convex portion holds a space between the display panel and the protective film. By holding the space in this way, it is possible to prevent the impact from the protective film from being transmitted to the display panel.

Further, it is also effective to dispose or inject an optical binder such as alcohol or ethylene glycol liquid or gel acrylic resin or epoxy solid resin between the protective film and the display panel. This is because interface reflection can be prevented and the optical coupling agent functions as a buffer material.

As a protective film, a polycarbonate film (board), a polypropylene film (board), an acrylic film (board), a polyester film (board), P
An example is a VA film (plate). It goes without saying that other engineering resin films (ABS, etc.) can be used. It may also be made of an inorganic material such as tempered glass. The same effect can be obtained by coating the surface of the display panel with an epoxy resin, a phenol resin, or an acrylic resin in a thickness of 0.5 mm or more and 2.0 mm or less, instead of disposing the protective film. It is also effective to emboss the surface of these resins.

It is also effective to coat the surface of the protective film or the coating material with fluorine. This is because stains on the surface can be easily wiped off with a detergent or the like. In addition, the protective film may be formed thick to serve also as the front light.

The screen is not limited to 4: 3,
A wide display may be used. Resolution is 1280x
It is preferably 768 dots or more. With the wide type, you can enjoy full-screen titles and programs in landscape display such as DVD movies and TV broadcasts. The brightness of the display panel is preferably 300 cd / m ² (candela / square meter). More preferably, the brightness of the display panel is preferably 500 cd / m ² (candela / square meter). Also, the brightness (20
The changeover switch is installed so that it can be displayed at 0 cd / m ² ).

Therefore, the user can set the brightness of the screen to the optimum depending on the display content or the usage method. Furthermore, only the window displaying the video is 500
in the cd / m ^2, the other parts are also available settings to 200cd / m ^2. It is flexible enough to display TV programs in the corner of the display and check mail. The speaker has a tower shape and is designed to spread the sound not only in the front direction but also in the entire space.

[0791] The functions of reproducing and recording TV programs are improved. It makes it easy to schedule recordings from i-mode. Conventionally, it was necessary to make a reservation after checking the time and channel on a TV program guide such as a newspaper, but it is possible to make a reservation by checking the electronic program guide in i-mode. This way, you don't have to worry about not knowing the broadcast time. Also,
It also allows short playback of recorded programs. While judging the importance of the presence or absence of telops and voices in news programs and the like, you can skip the parts that you have decided to be unnecessary and see the outline of the program in a short time (1 to 10 minutes for a 30-minute program).

A hard disk having a disk capacity of 40 GB or more is mounted so that television recording can be performed. In addition to the main body, it is composed of an expansion box that combines the power supply and video input / output terminals. In addition to a personal computer and TV, two types of video equipment can be connected to the expansion box used to connect AV equipment such as video. In addition to the D1 terminal for the BS digital tuner, the video input also has an S terminal input, which can be selected according to the connected device. The terminals for AV are arranged on the front for convenient connection with game consoles.

[0793] Also, the display screen is bent forward 30 degrees or more and backward bent 1
90 degrees / 180/270 by setting it to 20 degrees or more
By being configured so that it can be rotated once, it can be installed freely according to the operating environment. For example, the browser screen can be displayed vertically by rotating it 90 degrees. In addition, the screen can be displayed toward the person who sits face-to-face by bending backward by 145 degrees.

The above protective film, housing, configuration, characteristics,
It goes without saying that matters relating to functions and the like also apply to other display devices or information display devices of the present invention.

In the above embodiments, the EL element 15 is R,
Although G and B have been described, the present invention is not limited to this.
For example, cyan, yellow, magenta, or any two colors may be used. Six colors of R, G, B, cyan, yellow, and magenta, or any four or more colors may be used.
Further, it may be a single white color, or white monochromatic light may be converted into RGB by a color filter. Further, it is not limited to the organic EL element, and may be an inorganic EL element.

The embodiment of the present invention has been described by exemplifying the active matrix type display panel, but the present invention is not limited to this. From the source driver IC 14 or the like, N times the predetermined current is applied to (source of) the source signal line 18. In addition, a plurality of pixel rows are simultaneously selected. The concept that a current is passed through the EL element only during a predetermined period and no current is passed during other periods can be applied to a simple matrix display panel.

The EL element 15 has a large characteristic change in the initial stage of lighting. Therefore, burning and the like are likely to occur. For this measure, after aging with white raster display for 20 hours to 150 hours after panel formation,
It is preferable to ship as a product. In this aging, it is preferable to display with a brightness which is about 2-10 times higher than the predetermined display brightness.

The display panel in the embodiment of the present invention is 3
It goes without saying that combining with the edge-free configuration is also effective. In particular, the three-side free structure is effective when the pixel is manufactured by using the amorphous silicon technology. Further, in a panel formed by the amorphous silicon technology, it is not possible to perform process control of the characteristic variation of the transistor element, so it is preferable to carry out the N-fold pulse driving, reset driving, dummy pixel driving, etc. of the present invention. That is, the transistors and the like in the present invention are not limited to those based on polysilicon technology, and may be based on amorphous silicon.

The N-fold pulse driving of the present invention (see FIG. 13,
16, FIG. 19, FIG. 20, FIG. 22, FIG. 24, FIG.
Is more effective for a display panel in which the transistor 11 is formed by the amorphous silicon technique than in the case where the transistor 11 is formed. This is because in the amorphous silicon transistor 11, the characteristics of adjacent transistors are substantially the same. Therefore, the drive current of each transistor is almost the target value even if it is driven by the added current (especially,
The N-fold pulse driving of FIGS. 22, 24, and 30 is effective in the pixel configuration of the transistor formed of amorphous silicon).

The pixel configuration or the driving method described in this specification is such that
The display panel is not limited to the L display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 may be replaced with a liquid crystal layer or a light modulation layer such as PLZT or LED. For example, in the case of liquid crystal,
TN (Twisted Nematic), IPS (I
n-Plane Switching), FLC (Fe
rroelectric Liquid Crystal
l), OCB (Optically Compensat)
ory Bend), STN (Super Twis)
ted Nematic), VA (Vertical all)
y Aligned), ECB (Electrical)
ly Controlled Birefringen
ce) and HAN (Hybrid Aligned)
Nematic mode, DSM mode (dynamic scattering mode), and the like. In particular, the DSM can be optically modulated by the applied current, so that it is well matched with the present invention.

The technical idea described in the embodiments of the present invention can be applied to video cameras, projectors, stereoscopic televisions, projection televisions, and the like. Further, it is also applicable to a viewfinder, a mobile phone monitor, a PHS, a personal digital assistant and its monitor, a digital camera and its monitor.

Also, the present invention can be applied to an electrophotographic system, head mounted display, direct view monitor display, notebook personal computer, video camera, electronic still camera. Also, monitors of cash drawers, payphones, videophones, personal computers,
It can also be applied to a wristwatch and its display device.

Further, it is needless to say that the present invention can be applied or expanded to a display monitor of home electric appliances, a pocket game machine and its monitor, a backlight for a display panel or a lighting device for home or business use. It is preferable that the lighting device is configured so that the color temperature can be changed. In this, the color temperature can be changed by forming RGB pixels in a stripe shape or a dot matrix shape and adjusting the current flowing through these. Further, the present invention can be applied to display devices for advertisements or posters, RGB traffic lights, alarm indicators, etc.

The organic EL display panel is also effective as the light source of the scanner. The object is irradiated with light using the RGB dot matrix as a light source to read an image. Of course, it is needless to say that it may be a single color. Further, the matrix is not limited to the active matrix, and a simple matrix may be used. If the color temperature can be adjusted, the image reading accuracy will be improved.

The organic EL display device is also effective as a backlight of a liquid crystal display device. It is possible to change the color temperature and easily adjust the brightness by forming the RGB pixels of the EL display device (backlight) in a stripe shape or a dot matrix shape and adjusting the current flowing through them. In addition, since it is a surface light source, a Gaussian distribution that brightens the central part of the screen and darkens the peripheral part can be easily configured. It is also effective as a backlight for a field-sequential liquid crystal display panel that alternately scans R, G, and B lights. Also, by inserting black even if the backlight blinks, it can be used as a backlight of a liquid crystal display panel for displaying moving images.

In the source driver circuit of the present invention, the shift register stops operating when the start pulse has not passed and the shift clock stops operating during the blanking period, so that low power consumption can be realized. Further, since the display data can be input with a delay of one original oscillation clock after the input of the start pulse, the blanking period can be set short, flicker and the like can be suppressed, and high quality display can be realized.

[0807]

EFFECTS OF THE INVENTION The display panel, display device, and the like of the present invention have high image quality, good moving image display performance, low power consumption, and low cost.
A characteristic effect is exhibited according to each structure such as high brightness.

By using the present invention, a low power consumption information display device or the like can be formed, so that power consumption is not performed.
In addition, since the size and weight can be reduced, resources are not consumed. Further, even a high-definition display panel can be sufficiently dealt with.
Therefore, it is friendly to the global environment and space environment.

[Brief description of drawings]

FIG. 1 is a pixel configuration diagram of a display panel of the present invention.

FIG. 2 is a pixel configuration diagram of a display panel of the present invention.

FIG. 3 is an explanatory diagram of the operation of the display panel of the present invention.

FIG. 4 is an explanatory diagram of the operation of the display panel of the present invention.

FIG. 5 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 6 is a configuration diagram of a display device of the present invention.

FIG. 7 is an explanatory view of the method for manufacturing the display panel of the present invention.

FIG. 8 is a configuration diagram of a display device of the present invention.

FIG. 9 is a configuration diagram of a display device of the present invention.

FIG. 10 is a cross-sectional view of a display panel of the present invention.

FIG. 11 is a cross-sectional view of a display panel of the present invention.

FIG. 12 is an explanatory diagram of a display panel of the present invention.

FIG. 13 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 14 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 15 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 16 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 17 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 18 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 19 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 20 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 21 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 22 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 23 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 24 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 25 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 26 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 27 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 28 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 29 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 30 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 31 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 32 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 33 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 34 is a configuration diagram of a display device of the present invention.

FIG. 35 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 36 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 37 is a configuration diagram of a display device of the present invention.

FIG. 38 is a configuration diagram of a display device of the present invention.

FIG. 39 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 40 is a configuration diagram of a display device of the present invention.

FIG. 41 is a configuration diagram of a display device of the present invention.

FIG. 42 is a pixel configuration diagram of a display panel of the present invention.

FIG. 43 is a pixel configuration diagram of a display panel of the present invention.

FIG. 44 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 45 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 46 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 47 is a pixel configuration diagram of a display panel of the present invention.

FIG. 48 is a configuration diagram of a display device of the present invention.

FIG. 49 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 50 is a pixel configuration diagram of a display panel of the present invention.

FIG. 51 is a pixel diagram of a display panel of the present invention.

FIG. 52 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 53 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 54 is a pixel configuration diagram of a display panel of the present invention.

FIG. 55 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 56 is an explanatory diagram of a driving method of the display device of the present invention.

FIG. 57 is an explanatory diagram of a mobile phone according to the present invention.

FIG. 58 is an explanatory diagram of a viewfinder of the present invention.

FIG. 59 is an explanatory diagram of a video camera of the present invention.

FIG. 60 is an explanatory diagram of a digital camera of the present invention.

FIG. 61 is an explanatory diagram of a television (monitor) according to the present invention.

FIG. 62 is a pixel configuration diagram of a conventional display panel.

FIG. 63 is a functional block diagram of a driver circuit of the present invention.

FIG. 64 is an explanatory diagram of a driver circuit of the present invention.

FIG. 65 is an explanatory diagram of a driver circuit of the present invention.

FIG. 66 is an explanatory diagram of a voltage transfer multistage current mirror circuit.

FIG. 67 is an explanatory diagram of a current transfer multistage current mirror circuit.

FIG. 68 is an explanatory diagram of a driver circuit according to another embodiment of the present invention.

FIG. 69 is an explanatory diagram of a driver circuit according to another embodiment of the present invention.

FIG. 70 is an explanatory diagram of a driver circuit according to another embodiment of the present invention.

FIG. 71 is an explanatory diagram of a driver circuit according to another embodiment of the present invention.

FIG. 72 is an explanatory diagram of a conventional driver circuit.

FIG. 73 is an explanatory diagram of a driver circuit according to the present invention.

FIG. 74 is an explanatory diagram of a driver circuit of the present invention.

FIG. 75 is an explanatory diagram of a driver circuit of the present invention.

FIG. 76 is an explanatory diagram of a driver circuit of the present invention.

FIG. 77 is an explanatory diagram of a control method of a driver circuit of the present invention.

FIG. 78 is an explanatory diagram of a driver circuit according to the present invention.

FIG. 79 is an explanatory diagram of a driver circuit of the present invention.

FIG. 80 is an explanatory diagram of a driver circuit of the present invention.

FIG. 81 is an explanatory diagram of a driver circuit of the present invention.

FIG. 82 is an explanatory diagram of a driver circuit of the present invention.

FIG. 83 is an explanatory diagram of a driver circuit according to the present invention.

FIG. 84 is an explanatory diagram of a driver circuit of the present invention.

FIG. 85 is an explanatory diagram of a driver circuit of the present invention.

FIG. 86 is an explanatory diagram of a driver circuit of the present invention.

FIG. 87 is an explanatory diagram of a driver circuit of the present invention.

FIG. 88 is an explanatory diagram of a driving method of the present invention.

FIG. 89 is an explanatory diagram of a driver circuit of the present invention.

FIG. 90 is an explanatory diagram of a driving method of the present invention.

FIG. 91 is a configuration diagram of an EL display device of the present invention.

FIG. 92 is a configuration diagram of an EL display device of the present invention.

FIG. 93 is an explanatory diagram of a driver circuit of the present invention.

FIG. 94 is an explanatory diagram of a driver circuit of the present invention.

FIG. 95 is a circuit diagram of a shift register of the present invention.

96 is a timing chart of the shift register of the present invention. FIG.

97 is a timing chart of the shift register of the invention. FIG.

98 is a timing chart of the clock stop circuit according to the present invention. FIG.

FIG. 99 is a configuration diagram of a control signal generation circuit of the present invention.

100 is a timing chart of the shift register section of the present invention. FIG.

101 is a configuration diagram of a shift register of the present invention. FIG.

FIG. 102 is an explanatory diagram of a conventional signal line driver driver IC.

103 is an explanatory diagram of a conventional shift register circuit. FIG.

FIG. 104 is a timing chart of a conventional shift register circuit.

FIG. 105 is an explanatory diagram of a driver circuit according to the present invention.

[Explanation of symbols]

11 TFT (thin film transistor) 12 Gate driver IC (circuit) 14 Source driver IC (circuit) 15 EL (element) (light emitting element) 16 pixels 17 Gate signal line 18 Source signal line 19 Storage capacity (additional capacitor, addition capacity) 50 display screen 51 write pixels (row) 52 Non-display pixel (non-display area, non-lighting area) 53 display pixels (display area, lighting area) 61 shift register 62 inverter 63 output buffer 71 Array substrate (display panel) 72 Laser irradiation range (laser spot) 73 Positioning marker 74 Glass substrate (array substrate) 81 Control IC (circuit) 82 Power supply IC (circuit) 83 Printed circuit board 84 Flexible substrate 85 sealing lid 86 cathode wiring 87 Anode wiring (Vdd) 88 data signal line 89 Gate control signal line 101 Bank (rib) 102 interlayer insulating film 104 contact connection part 105 pixel electrode 106 cathode electrode 107 desiccant 108 λ / 4 plate 109 Polarizer 111 Thin film sealing film 281 dummy pixels (row) 341 output stage circuit 371 OR circuit 401 lighting control line 471 reverse bias line 472 gate potential control line 561 Electronic volume circuit 562 TFT SD (source-drain) short circuit 571 antenna 572 key 573 housing 574 display panel 581 eyepiece ring 582 magnifying lens 583 convex lens 591 Support point (rotating part) 592 shooting lens 593 Storage 594 switch 601 body 602 shooting section 603 shutter switch 611 mounting frame 612 leg 613 mounting base 614 Fixed part 631 current source 632 current source 633 current source 641 switch (on / off means) 634 Current source (1 unit) 643 internal wiring 651 volume (current adjusting means) 681 transistor group 691 resistance (current limiting means, predetermined voltage generating means) 692 decoder circuit 693 level shifter circuit 701 counter (counting means) 702 NOR 703 AND 704 Current output circuit 711 padding circuit 721 D / A converter 722 operational amplifier 731 Analog switch (on / off means) 732 Inverter 761 Output pad (output signal terminal) 771 Reference current source 772 Current control circuit 781 Temperature detection circuit 782 Temperature control circuit 931 Cascade current connection line 932 Reference current signal line 941i current input terminal 941o current output terminal 951 Base anode line (anode voltage line) 952 Anode wiring 953 connection terminal 961 connection anode wire 962 common anode line 971 contact hole 991 Base cathode line 992 Input signal line 1001 Connection resin (conductive resin, anisotropic conductive resin) 1011 light absorption film 1012 resin beads 1013 sealing resin 1021 circuit forming unit 1051 Gate voltage line 1091 power supply circuit (IC) 1092 Power supply IC control signal 1093 Gate driver circuit control signal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642A G11C 19/00 G11C 19/00 J H05B 33/14 H05B 33/14 A (72) Inventor Hitoshi Tsuge 4-8 Konan, Minato-ku, Tokyo F-term within Toshiba Matsushita Display Technology Co., Ltd. (reference) 3K007 AB00 AB02 AB17 AB18 BA06 BB07 DB03 GA04 5C080 AA06 BB05 DD05 FF11 JJ02 JJ03 JJ04 JJ05 JJ06 KK43 KK47

Claims (10)

[Claims] 1. A driver circuit for driving a source signal line, comprising: a latch circuit for latching display data at a rising edge of an original clock; and a shift register with a clock stop, the shift register being a first-stage shift register. A driver circuit comprising an output and a circuit for outputting a start pulse adjusted to a length of two clocks of the original clock. 2. The driver circuit according to claim 1, wherein a logical product of a normal output signal of the shift register of its own stage and an inverted output signal of the latter shift register is used as an output signal of the shift register. 3. The driver circuit according to claim 1, further comprising a dummy shift register at a stage subsequent to the shift register at the final stage. 4. The driver circuit according to claim 1, wherein the input of the clock signal of the shift register of the self stage is interrupted by the logical sum of the normal output signal of the shift register and the normal output signal of the shift register of the self stage. 5. A normal output of a first D-type flip-flop that holds an input start pulse at the rising edge of the original clock in a reset circuit that generates a reset signal of one clock length of the original clock,
2. The driver circuit according to claim 1, wherein the driver circuit is configured by an inverted logical product with an inverted output of a second D-type flip-flop that holds the normal output at the rising edge of the original clock. 6. A third D-type flip-flop that divides an original clock by a falling edge of the original clock, and a reset signal having one clock length of the original clock. Driver circuit. 7. A logical sum of an inversion signal of a reset signal having a length of one clock of the original clock and a non-inverted output of a fourth D flip-flop which holds the inverted signal at the rising edge of the original clock. The driver circuit according to claim 1, further comprising: 8. The driver circuit according to claim 7, wherein the shift clock is stopped during the blanking period. 9. A fifth D which holds the output signal of the shift register at the final stage at the rising edge of the original clock as means for stopping the shift clock during the blanking period.
Of the first D-type flip-flop by stopping the frequency dividing operation of the first D-type flip-flop by the normal output of the first D-type flip-flop and resetting the fifth D-type flip-flop by the reset signal. 8. The driver circuit according to claim 7, which starts the frequency dividing operation of the driver. 10. The driver circuit according to claim 1, and ELs arranged in a matrix.
An EL display device including an element.