JP2003303965A - Semiconductor element and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor element exhibiting low ON voltage characteristics and a high switching performance simultaneously, especially a power semiconductor element which can be implemented even in a semiconductor element of low or intermediate breakdown voltage. <P>SOLUTION: A stripe base layer arranged alternately and repeatedly with an n-type base layer 21 and a p-type base layer 22 is formed on one surface of an n-type buffer layer 1 and a p-type well layer 3, an n-type emitter layer 4, an emitter electrode 10 and an insulating gate electrode 6 are formed on the base layer. A stripe shape arranged repeatedly with an n-type semiconductor layer 7 and a p-type collector layer 9 is formed on the other surface of the n-type buffer layer 1, an n-type collector short circuit layer 8 is formed on the surface of the n-type semiconductor layer 7, and a collector electrode 11 is formed on the n-type collector short circuit layer 8 and the p-type collector layer 9. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a power semiconductor device, and particularly to an insulated gate bipolar transistor (Insu) suitable as a power switching element.
gated Gate Bipolar Transi
store: IGBT).

[0002]

2. Description of the Related Art In response to the recent demand for miniaturization and high performance of power supply equipment in the field of power electronics,
In the power semiconductor device, performance improvement is being made for high breakdown voltage and large current, as well as low loss, high speed, and high breakdown resistance. In particular, in order to reduce the loss, it is necessary to reduce both the on-voltage (steady loss) and the turn-off loss, and various element structures have been studied.

Among these element structures, there is a collector short-circuit type insulated gate bipolar transistor (IGBT) which has a low on-voltage characteristic and at the same time has a reduced turn-off loss due to higher speed.

FIG. 25 shows a planar collector short-circuit type I.
It is sectional drawing which shows the structure of GBT. In this IGBT,
P is selectively formed on one surface of the high-resistance n-type base layer 102.
A type well layer 103 is formed, and an n type emitter layer 104 is selectively formed on the surface of the p type well layer 103.
Further, an insulated gate electrode 106 is provided on the surfaces of the n-type base layer 102 and the p-type well layer 103 between the adjacent n-type emitter layers 104 with a gate insulating film 105 interposed therebetween. These n-type emitter layer 104 and p-type well layer 10
3, the p-type well layer 103 immediately below the insulated gate electrode 106 by the n-type base layer 102 and the insulated gate electrode 106.
N-channel MOSFET (Me
tal Oxide Semiconductor F
field Effect Transistor). On the other hand, an n-type collector short-circuit layer 108 and a p-type collector layer 109 are selectively formed on the other surface of the n-type base layer 102. Then, the n-type emitter layer 1
04 and the p-type well layer 103, an emitter electrode 110 is provided so as to be in contact with both layers at the same time, and a collector electrode is provided on the n-type collector shorting layer 108 and the p-type collector layer 109 so as to be in contact with both layers at the same time. 111 is provided.

The collector shorted type IGBT shown in FIG.
In the on state, electrons are injected into the n-type base layer 102 through the n-type channel, and the p-type collector layer 109
The holes are injected from the holes to cause conductivity modulation, and a low on-voltage is obtained. At that time, due to the collector short-circuit structure, a part of the electron current does not flow into the p-type collector layer 109 and reaches the collector electrode 111 through the n-type collector short-circuit layer 108, so that the injection efficiency of the p-type collector layer 109 (Ih / I
c) is suppressed, the accumulated carriers are reduced, and the turn-off is speeded up.

[0006]

However, in the collector-shorted type IGBT shown in FIG. 25, the pn junction between the n-type base layer 102 and the p-type collector layer 109 is not forward biased at the time of initial energization. The electrons injected into the n-type base layer 102 through the n-type channel flow into the n-type collector short-circuit layer 108 to operate as a MOSFET, resulting in a high on-voltage (voltage drop). p of the n-type base layer 102 and the p-type collector layer 109
In order for the n-junction to be forward biased, the p-type collector layer 1
This can be achieved by causing an electron current to flow directly above 09 to raise the potential at the point A ′ of the n-type base layer 102 to a potential equivalent to the built-in voltage of the pn junction. For that purpose, the lateral width of the p-type collector layer 109 can be set. It needs to be designed long. As a result, the layer thickness of the n-type base layer 102 (Ln
In the case of a low-medium breakdown voltage element having a thin thickness of b), the collector short-circuit rate cannot be sufficiently obtained, and the speed cannot be increased. For this reason, the collector short-circuit IGBT has been conventionally effective only in a device having a high breakdown voltage.

Here, FIG. 26 is a diagram showing the electric field intensity in the cross section of the line segment DD 'in the collector short-circuited IGBT shown in FIG. As shown in FIG. 26, the depletion layer is expanded from the p-type well layer 103 to the n-type base layer 102 along the line segment D2-D3 to obtain the breakdown voltage. Electric field strength E and n-type base layer 10
Between the impurity concentration Nn of 2 and dE / dy = Nn / ε
(Ε represents the dielectric constant of the semiconductor material),
The breakdown voltage Vb is calculated as Vb = ∫E · dy. Therefore, the electric field intensity distribution between the line segments D2 and D3 has a slope proportional to the impurity concentration of the n-type base layer 102, and the integral of this electric field intensity distribution becomes the collector voltage. The breakdown voltage is the breakdown electric field of the semiconductor material whose peak electric field strength is Emax (for Si, Emax
= 2 × 10 ⁵ V / cm), the n-type base layer 10 can be used to increase the breakdown voltage.
Since it is necessary to increase the thickness of 2 and simultaneously reduce the impurity concentration, it is not possible to achieve low on-resistance during the above-described MOSFET operation and IGBT operation.

Therefore, an object of the present invention is to provide a power semiconductor element having a low on-voltage characteristic and a high-speed switching performance at the same time, particularly a power semiconductor element which can be realized even in a semiconductor element having a low and medium breakdown voltage.

[0009]

In order to solve the above problems, the present invention provides a first conductivity type base layer and a second conductivity type well selectively formed on one surface of the first conductivity type base layer. A layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type well layer, and a first main electrode formed on the first conductivity type emitter layer and the second conductivity type well layer, First
The insulated gate electrode formed on the conductive type base layer and the second conductive type well layer via the gate insulating film and between the adjacent first conductive type emitters, and the other of the first conductive type base layer. A first conductivity type semiconductor layer selectively formed on the surface and having an impurity concentration higher than that of the first conductivity type base layer, and a first conductivity type collector short-circuit layer formed on the surface of the first conductivity type semiconductor layer. A second conductivity type collector layer formed on the other surface of the first conductivity type base layer and between the adjacent first conductivity type semiconductor layer and first conductivity type collector short-circuit layer, and a second conductivity type. A semiconductor device having a collector layer and a second main electrode formed on the surface of a first-conductivity-type collector short-circuit layer.

By the above means, the aspect ratio of the second conductivity type collector layer in contact with the first conductivity type semiconductor layer can be increased, and the electron current flowing in the first conductivity type semiconductor layer in the vicinity of the second conductivity type collector layer. Thus, the potential in the vicinity of the second conductivity type collector layer can be increased. Therefore, the density of the second-conductivity-type collector layer and the first-conductivity-type collector short-circuit rate can be increased, and as a result, low on-voltage and high speed can be realized at the same time.

In order to solve the above-mentioned problems, the present invention provides a first conductivity type buffer layer and a plurality of first conductivity type base layers selectively formed on one surface of the first conductivity type buffer layer. A plurality of second conductivity type base layers formed on one surface of the first conductivity type buffer layer and between adjacent first conductivity type base layers, the second conductivity type base layer and the first conductivity type Second conductive type well layer selectively formed on the surface of the type base layer, first conductive type emitter layer selectively formed on the surface of the second conductive type well layer, first conductive type emitter layer and first conductive type emitter layer A first main electrode formed on the second conductivity type well layer, and a first conductivity type emitter layer formed on the first conductivity type base layer and the second conductivity type well layer via a gate insulating film and adjacent to each other. Between the insulated gate electrode and the other surface of the first conductivity type buffer layer. A plurality of first conductivity type semiconductor layers selectively formed thereon, a first conductivity type collector short-circuit layer formed on the surface of the first conductivity type semiconductor layer, and the other surface of the first conductivity type buffer layer A second conductive layer formed between the first conductive type semiconductor layer and the adjacent first conductive type collector short-circuit layer
There is provided a semiconductor device having a conductive type collector layer and a second main electrode formed on the surfaces of the second conductive type collector layer and the first conductive type collector short-circuit layer.

By the means for solving the above problems, the aspect ratio in which the second conductive type collector layer contacts the first conductive type semiconductor layer can be increased, and the electron current flowing in the first conductive type semiconductor layer near the second conductive type collector layer. Thus, the potential in the vicinity of the second conductivity type collector layer can be increased. Therefore, the density of the second-conductivity-type collector layer and the first-conductivity-type collector short-circuit rate can be increased, and as a result, low on-voltage and high speed can be realized at the same time. Moreover, since the impurity concentration of the first conductivity type base layer can be set to a high concentration, it is possible to further reduce the on-resistance while maintaining the high speed.

In order to solve the above-mentioned problems, the present invention provides a step of forming a plurality of second conductivity type collector layers on one of the first conductivity type semiconductor layers, and a step of forming the second conductivity type collector layers. Forming a first conductivity type buffer layer on the first conductivity type semiconductor layer; forming a first conductivity type base layer on the first conductivity type buffer layer; and selectively forming a first conductivity type base layer surface. Forming a second conductivity type well layer and selectively forming a first conductivity type emitter layer on the surface of the second conductivity type well layer; and forming a first conductivity type emitter layer and a second conductivity type well layer on the first conductivity type well layer. Forming a main electrode, and forming an insulated gate electrode on the first conductivity type base layer and the second conductivity type well layer between the adjacent first conductivity type emitter layers with a gate insulating film interposed therebetween. A step of thinning the first conductivity type semiconductor layer to a predetermined thickness; And a step of forming a first conductivity type collector short-circuit layer on the surface of the electric conductivity type semiconductor layer, and a step of forming a second main electrode on the surfaces of the first conductivity type collector short-circuit layer and the second conductivity type collector layer. A method of manufacturing a semiconductor device or a plurality of second conductive layers on one of the first conductive type semiconductor layers.
Forming a conductive type collector layer; forming a first conductive type buffer layer on the first conductive type semiconductor layer on which the second conductive type collector layer is formed; and forming a first conductive type buffer layer on the first conductive type buffer layer. A step of forming a conductive type base layer, a step of forming a plurality of trench grooves in the first conductive type base layer, a step of embedding a second conductive type base layer in the plurality of trench grooves, a second conductive type base layer, and A step of selectively forming a second conductivity type well layer on the surface of the first conductivity type base layer and selectively forming a first conductivity type emitter layer on the surface of the second conductivity type well layer;
A first conductive type emitter layer and a second conductive type well layer,
Forming a main electrode, and forming an insulated gate electrode on the first conductivity type base layer and the second conductivity type well layer between the adjacent first conductivity type emitter layers with a gate insulating film interposed therebetween. A step of thinning the first conductivity type semiconductor layer to a predetermined thickness, a step of forming a first conductivity type collector short circuit layer on the surface of the first conductivity type semiconductor layer, a first conductivity type collector short circuit layer and a second And a step of forming a second main electrode on the surface of the conductivity type collector layer.

By the means for solving the problems described above, it is possible to manufacture a semiconductor element having a large aspect ratio in which the second conductive type collector layer is in contact with the first conductive type semiconductor layer, that is, it is possible to simultaneously realize low on-voltage and high speed. it can.

[0015]

Embodiments of the present invention will be described with reference to the drawings. It should be noted that all of the present embodiments will be described using an n-type IGBT as the first conductivity type and a p-type IGBT as the second conductivity type. Therefore, in practicing the present invention, the first conductivity type is p-type and the second conductivity type is n-type.
Naturally, even GBT is possible.

[First Embodiment] FIG. 1 is a sectional view showing the structure of a vertical power semiconductor device according to the first embodiment of the present invention. This embodiment is a vertical collector short-circuit IG.
It is an embodiment in which the present invention is applied to BT.

As shown in FIG. 1, a high resistance n-type base layer 2 is formed on one surface of the n-type buffer layer 1. A p-type well layer 3 is selectively formed on the surface of the n-type base layer 2, and an n-type emitter layer 4 is selectively formed on the surface of the p-type well layer 3. Adjacent n-type emitter layer 4
An insulated gate electrode 6 is provided on the surfaces of the n-type base layer 2 and the p-type well layer 3 with a gate insulating film 5 interposed therebetween. The n-type emitter layer 4, the p-type well layer 3, the n-type base layer 2 and the insulated gate electrode 6 constitute an n-type channel MOSFET having the p-type well layer 3 immediately below the insulated gate electrode 6 as a channel region. . An emitter electrode 10 is provided on the surfaces of the n-type emitter layer 4 and the p-type well layer 3 so as to contact both layers at the same time.

On the other hand, the n-type semiconductor layer 7 and the p-type collector layer 9 are selectively formed on the other surface of the n-type buffer layer 1, and the n-type collector short circuit is formed on the surface of the n-type semiconductor layer 7. Layer 8 has been formed. Here, the layer thickness (Lns) of the n-type semiconductor layer 7 is half the lateral width (Wp) of the p-type collector layer 9.
The p-type collector layer 9 is formed thicker, and half of the lateral width (Wp) of the p-type collector layer 9 is formed sufficiently smaller than the layer thickness (Lnb) of the n-type base layer 2. A collector electrode 11 is provided on the surfaces of the n-type collector short-circuit layer 8 and the p-type collector layer 9 so as to contact both layers simultaneously.

Next, a method of manufacturing the structure of the vertical power semiconductor device shown in FIG. 1 will be described with reference to FIGS.

As shown in FIG. 2A, a trench groove 7a is formed in the low-concentration n-type semiconductor layer 7. Next, FIG. 2 (b)
As shown in, the trench groove 7a formed in (a)
P-type collector layer 9 is deposited so that
The collector layer of CMP (Chemical Mechanical)
Polishing and removing with a nickel polish) or the like. Next, as shown in FIG. 2C, the n-type buffer layer 1 is epitaxially grown on the surfaces of the n-type semiconductor layer 7 and the p-type collector layer 9, and then the n-type base layer 2 is epitaxially grown on the n-type buffer layer 1. .

Next, as shown in FIG. 3D, the p-type well layer 3 is selectively formed on the surface of the n-type base layer 2. Further, the n-type emitter layer 4 is selectively formed on the surface of the p-type well layer 3.
To form. An insulated gate electrode 6 is provided between the adjacent n-type emitter layers 4 on the surfaces of the n-type base layer 2 and the p-type well layer 3 with a gate insulating film 5 interposed therebetween. Further, an emitter electrode 10 is formed so as to contact both the n-type emitter layer 4 and the p-type well layer 3 at the same time. Further, the back surface of the n-type semiconductor layer 7 is polished and removed by CMP or the like until the selectively formed p-type collector layer 9 is exposed, so that the n-type semiconductor layer 7 and the p-type collector layer 9 have a predetermined layer thickness. To do.
Next, as shown in FIG. 3E, n-type impurity ions 12 are implanted into the entire surfaces of the n-type semiconductor layer 7 and the p-type collector layer 9. In this case, the impurity concentration of the p-type collector layer 9 is set to a relatively high concentration of about 5 × 10 ¹⁹ cm ^{−3 in} advance, and the concentration of the n-type impurity ions 12 to be implanted is lower than the impurity concentration of the p-type collector layer 9, for example, 2 × 10 ¹⁹ cm ⁻³ may be used. The n-type collector short-circuit layer 8 can also be formed by masking the p-type collector layer 9 with a resist and implanting the n-type impurity ions 12 only in the n-type semiconductor layer 7.

In the above manufacturing method, the n-type collector short-circuit layer 8 is formed after the n-type channel MOSFET is formed on the surface of the n-type base layer 2, but the formation of the n-type collector short-circuit layer 8 is not limited to the above method. Without, for example, the n-type buffer layer 1
May be before the epitaxial growth.

FIG. 4 shows the flow of electrons 13 at the initial stage of energization of the vertical power semiconductor device shown in FIG. 1 or at the time of energization with a low current, and FIG. 5 is a diagram showing the flow of carriers in the ON state. is there. When a predetermined voltage is applied to the insulated gate electrode 6, an electron current flows through the n-type semiconductor layer 7 as shown in FIG. An electric current flowing through the n-type semiconductor layer 7 in contact with the p-type collector layer 9 surely raises the potential at the point A shown in FIG. 4, and the pn junction is in a forward biased state. As shown in FIG. Holes 1 from layer 9 to n-type base layer 2
4 is injected. This does not depend on the half width (Wp) of the lateral width of the p-type collector layer 9, but by increasing the contact distance (Lns) between the p-type collector layer 9 and the n-type semiconductor layer 7, the point shown in FIG. It shows that the potential increase of A can be accelerated. Therefore, the p-type collector layer 9
Also, the n-type semiconductor layer 7 can be laterally miniaturized. That is, it is possible to increase both the density of the p-type collector layer 9 and the n-type collector short-circuit rate per area of the collector electrode 11, and it is possible to simultaneously realize low on-voltage and high speed.

The vertical collector short-circuit type IGBT described above has the n-type base layer 2, the p-type collector layer 9 and the n-type base layer 2.
Although the n-type buffer layer 1 is interposed between the n-type buffer layer 1 and the type semiconductor layer 7, the present invention can be implemented without the n-type buffer layer 1 interposed therebetween as shown in FIG.

Here, to show the relationship between the impurity concentration and the distance through which the electron current flows for carrying out the embodiment of the present invention, the impurity concentrations of the n-type buffer layer 1 and the n-type semiconductor layer 7 are Nn1 and Nn2, respectively. Put, Lns / Nn2
The relationship of> Wp / Nn1 is established. In the IGBT having no n-type buffer layer 1 as shown in FIG. 6, the invention can be implemented by replacing Nn1 in the above-mentioned relational expression with the impurity concentration of the n-type base layer 2. The relational expressions described above must hold in the embodiments of the present invention described below.

Further, the insulated gate electrode 6 is formed on the n-type base layer 2
Although not limited to this, a trench groove is formed in the n-type emitter layer 4, the p-type well layer 3 and the n-type base layer 2 and the gate insulating film 5 is formed in the trench groove. It is also possible to embed the insulated gate electrode 6 via the same, and the same applies to the embodiments of the present invention described below.

[Second Embodiment] FIG. 8 is a sectional view showing the structure of a vertical power semiconductor device according to a second embodiment of the present invention. This embodiment is also a vertical collector short-circuit IG
It is an embodiment in which the present invention is applied to BT.

As shown in FIG. 8, a striped base layer in which an n-type base layer 21 and a p-type base layer 22 are alternately and repeatedly arranged is formed on the n-type buffer layer 1. That is, the adjacent n-type base layer 21 and the p-type base layer 22
And the n-type base layer 21 is sandwiched between the adjacent p-type base layers 22. The relationship between the lateral width and the concentration of the n-type base layer 21 and the p-type base layer 22 is
For example, when the lateral width of each base layer is 5 μm and the impurity concentration is approximately 4 × 10 ¹⁵ cm ^−3, or when the lateral width is 1 μm, the impurity concentration may be set to 2 × 10 ¹⁶ cm ⁻³ .

The p-type well layer 3 is selectively formed on the surfaces of the p-type base layer 22 and the n-type base layer 21, and the n-type emitter layer 4 is selectively formed on the surface of the p-type well layer 3. There is. An insulated gate electrode 6 is provided between the adjacent n-type emitter layers 4 on the surfaces of the n-type base layer 21 and the p-type well layer 3 with a gate insulating film 5 interposed therebetween. With these n-type emitter layer 4, p-type well layer 3, n-type base layer 21, and insulated gate electrode 6, an n-type channel MOSFE having the p-type well layer 3 immediately below the insulated gate electrode 6 as a channel region is formed.
T is configured. An emitter electrode 10 is provided on the surfaces of the n-type emitter layer 4 and the p-type well layer 3 so as to contact both layers at the same time.

On the other hand, the n-type semiconductor layer 7 and the p-type collector layer 9 are selectively formed on the surface of the n-type buffer layer 1, and the n-type collector short-circuit layer 8 is formed on the surface of the n-type semiconductor layer 7. Has been formed. A collector electrode 11 is provided on the surfaces of the n-type collector short-circuit layer 8 and the p-type collector layer 9 so as to contact both layers simultaneously.

Next, a method of manufacturing the structure of the vertical power semiconductor device of FIG. 8 will be described with reference to FIGS.

As shown in FIG. 9A, a trench groove 7a is formed in the low concentration n-type semiconductor layer 7. Next, FIG. 9 (b)
As shown in, the trench groove 7a formed in (a)
P-type collector layer 9 is deposited so that
The mold collector layer is polished and removed by CMP or the like. Next in FIG.
As shown in (c), the n-type buffer layer 1 is formed on the surfaces of the n-type semiconductor layer 7 and the p-type collector layer 9, and the impurity concentration on the n-type buffer layer 1 is about 2 × 10 ¹⁵ cm ^−3. N
The mold base layer 21 is epitaxially grown.

Next, as shown in FIG.
A plurality of trench grooves 21a are formed in the n-type base layer 21 formed in (c) until the n-type buffer layer 1 is exposed. Next, as shown in FIG. 10E, the p-type base layer 22 is deposited so as to fill the trench groove 21a formed in (d), and the excess p-type base layer is removed by polishing by CMP or the like.

Next, as shown in FIG. 11F, the p-type well layer 3 is selectively formed on the surfaces of the p-type base layer 22 and the n-type base layer 21. Further, the n-type emitter layer 4 is selectively formed on the surface of the p-type well layer 3. A gate insulating film 5 is formed on the surfaces of the p-type well layer 4 and the n-type base layer 21 so as to be in contact with the adjacent n-type emitter layer 4 via the n-type base layer 21, and an insulated gate is formed on the gate insulating film 5. The electrode 6 is formed. Further, the emitter electrode 1 is formed so as to be in contact with both the n-type emitter layer 4 and the p-type well layer 3 at the same time.
Form 0. In addition, the back surface of the n-type semiconductor layer 7 is subjected to CMP until the selectively formed p-type collector layer 9 is exposed.
Etc. to remove by polishing. Next, as shown in FIG. 3E, n-type impurity ions 12 are implanted into the entire surfaces of the n-type semiconductor layer 7 and the p-type collector layer 9. In this case, the impurity concentration of the p-type collector layer 9 is set to a relatively high concentration of about 5 × 10 ¹⁹ cm ^{−3 in} advance, and the concentration of the n-type impurity ions 12 to be implanted is lower than the impurity concentration of the p-type collector layer 9, for example, 2 × 10 ¹⁹ cm ⁻³ may be used. Also, by masking the p-type collector layer 9 with a resist and implanting the n-type impurity ions 12 only in the n-type semiconductor layer 7,
The type collector short-circuit layer 8 can be formed.

In the above manufacturing method, the n-type base layer 21
And n-type channel MOSFE on the surface of the p-type base layer 22.
After forming T, the n-type collector shorting layer 8 was formed,
The formation of the n-type collector short-circuit layer 8 is not limited to the above method,
For example, it may be before the epitaxial growth of the n-type buffer layer 1.

FIG. 12 is a diagram showing the voltage applied between the collector and the emitter of the vertical power semiconductor device shown in FIG. 8 (Vce ≦ 50).
FIG. 5 is a diagram showing the initial spread of the depletion layer 15 in the case of (V). The depletion layer 15 begins to spread in the direction of the arrow in FIG. 8 with the boundary between the n-type base layer 21 and the p-type base layer 22 as the junction surface.

FIG. 13 is a diagram showing a potential distribution (equipotential lines) in the off state (blocking state) of the vertical power semiconductor device shown in FIG. Further, FIG. 14 shows an electric field strength distribution in an off state in a cross section taken along the line BB ′ of FIG.
5 shows the electric field strength distribution in the cross section of the line segment CC ′.

It can be seen from FIG. 15 that the electric field strengths in the n-type base layer 21 and the p-type base layer 22 between the p-type well layer 3 and the n-type buffer layer 1 are almost flat. This is because the n-type base layer 21 and p
Since the depletion layer spreads along the junction surface of the mold base layer 22,
This is a phenomenon caused by the electric field strength in the C1-C2 direction becoming substantially constant. Therefore, even if the impurity concentration of the n-type base layer 21 is set to a high concentration, both the n-type base layer 21 and the p-type base layer 22 are completely depleted before breakdown, so that a high breakdown voltage can be obtained. .

The collector-shorted IGBT shown in FIG. 8 is also the first
Similar to the first embodiment, it operates as a MOSFET in the initial stage of energization, but the potential at the point A of the n-type semiconductor layer 7 rises due to the electron current flowing in the n-type semiconductor layer 7 near the p-type collector layer 9 and the pn junction. The part is forward biased and holes are injected from the p-type collector layer 9 to the n-type base layer 21 to start the operation as an IGBT. The current required to be forward biased in the pn junction depends on the contact distance (Lns) between the p-type collector layer 9 and the n-type semiconductor layer 7. Therefore, by setting Lns to a predetermined length, The current required for bias can be adjusted. Therefore, the p-type collector layer 9 and the n-type semiconductor layer 7 can be miniaturized in the lateral direction, and the p-type collector layer 9 per area of the collector electrode 11 can be miniaturized.
It is possible to increase both the density and the short circuit ratio of the n-type collector, and it is possible to realize low ON voltage and high speed at the same time. In addition, the n-type base layer 21 of the IGBT in the present embodiment can be set to an impurity concentration that is several times higher than that of a normal IGBT by one digit or more.
The on-voltage during the ET operation can be significantly reduced.
Therefore, it is possible to further reduce the ON resistance while maintaining high speed.

Here, FIG. 16 shows the emitter / element of the semiconductor element.
It is a characteristic view showing collector voltage (on-voltage) -collector voltage current density characteristic (Vce-Jc characteristic). The dotted line is the conventional IGBT, and the alternate long and short dash line is the conventional SJ-MOSFET.
(Super Junction-MOSFE
T) and a thick solid line are collector short-circuit type I according to the second embodiment.
The GBT and the thin solid line show the characteristics of the collector short-circuited IGBT according to the first embodiment. The semiconductor element shown in FIG. 16 is a Si element having a breakdown voltage of 600V. From FIG. 16, a collector short-circuited IGBT according to the second embodiment
Shows a low on-resistance similar to that of the SJ-MOSFET in the low current density region. On the other hand, in the high current density region, S
It can be seen that the on-resistance is significantly lower than that of the J-MOSFET.

Further, in the conventional IGBT, when half the width (Wp) of the width of the p-type collector layer is narrowed, holes are not injected from the p-type collector layer and the same characteristics as those of the conventional MOSFET are shown. Conversely, when Wp is widened. In the relatively low current density region, holes are injected from the p-type collector layer, but the n-type collector short circuit rate becomes low, which impairs high speed. On the other hand, the IGBT according to the first embodiment is a conventional IGBT.
It can be seen that the ON resistance is remarkably reduced as compared with the conventional IGBT while maintaining the same high speed. Further, the IGBT according to the second embodiment has a conventional IGBT even in a low current density region operating as a MOSFET.
The on resistance is remarkably lower than that of

As described above, the present invention that enables a low on-voltage in a low current to high current density region is provided, for example, in a power supply device or the like in which a high load (high current) and a low load (low current) are repeated. It is effective for use in inverter devices.

[Third Embodiment] FIG. 17 shows a third embodiment of the present invention.
2 is a cross-sectional view showing the structure of a vertical power semiconductor device according to the embodiment of FIG. This embodiment is also a vertical collector short-circuit type I.
It is an embodiment in which the present invention is applied to GBT.

As shown in FIG. 17, on the n-type buffer layer 1, an n-type base layer 21 and a p-type base layer 22 having irregularities in the direction perpendicular to the surface of the n-type buffer layer 1 are alternately and repeatedly arranged. To form a striped base layer. That is, the adjacent n-type base layer 21 and the p-type base layer 22
And the n-type base layer 21 is sandwiched between the adjacent p-type base layers 22.

The p-type well layer 3 is selectively formed on the surfaces of the p-type base layer 22 and the n-type base layer 21, and the n-type emitter layer 4 is selectively formed on the surface of the p-type well layer 3. There is. The n-type base layer 2 is provided between adjacent n-type emitter layers 4.
An insulated gate electrode 6 is provided on the surfaces of the 1 and p-type well layers 3 with a gate insulating film 5 interposed therebetween. These n-type emitter layer 4, p-type well layer 3, n-type base layer 21, and insulated gate electrode 6 constitute an n-type channel MOSFET having the p-type well layer 3 immediately below the insulated gate electrode 6 as a channel region. . An emitter electrode 10 is provided on the surfaces of the n-type emitter layer 4 and the p-type well layer 3 so as to contact both layers at the same time.

On the other hand, the n-type semiconductor layer 7 and the p-type collector layer 9 are selectively formed on the surface of the n-type buffer layer 1, and the n-type collector short-circuit layer 8 is formed on the surface of the n-type semiconductor layer 7. Has been formed. A collector electrode 11 is provided on the surfaces of the n-type collector short-circuit layer 8 and the p-type collector layer 9 so as to contact both layers simultaneously.

Next, a method of manufacturing the structure of the vertical power semiconductor device of FIG. 17 will be described with reference to FIGS.

As shown in FIG. 18A, p-type impurities 16 such as boron are selectively ion-implanted into the surface of the n-type semiconductor layer 7. Next, as shown in FIG. 18B, the n-type buffer layer 1 and the n-type base layer 21 are successively epitaxially grown on the ion-implanted n-type semiconductor layer 7, and the surface of the n-type base layer 21 is selectively grown. Then, a p-type impurity 16 such as boron is ion-implanted. Next, as shown in FIG.
The type base layer 21a is epitaxially grown, and p-type impurities 16 such as boron are selectively ion-implanted into the surface of the newly epitaxially grown n-type base layer 21a. In the present embodiment, this step was repeated twice, but it is not limited to this and may be repeated three times or more. Next, these p-type impurities 16 are drive-in diffused by heat treatment to form the p-type collector layer 9 and the p-type base layer 22.

As described above, the n-type semiconductor layers 7 and n
After the p-type impurity 16 is continuously ion-implanted into the type base layer 21, the p-type impurity 16 is not thermally drive-diffused all at once, but the p-type impurity 16 is driven by the heat treatment each time the p-type impurity 16 is ion-implanted. The p-type collector layer 9 or the p-type base layer 22 may be formed by in-diffusion.

Next, as shown in FIG.
Of the p-type layer 22 and the n-type base layer 21a
The well layer 3 is formed. Furthermore, this p-type well layer 3 is selected.
Then, the n-type emitter layer 4 is formed. Adjacent n-type Emi
Between the n-type base layer 21a and the p-type well layer 3
An insulated gate electrode 6 is arranged on the surface through a gate insulating film 5.
It is set up. Further, the n-type emitter layer 4 and the p-type well layer 3
Of the emitter electrode 10 so as to simultaneously contact both layers of
To form. In addition, the n-type semiconductor layer 7 is selectively formed.
Until the p-type collector layer 9 is exposed by CMP or the like.
Remove by polishing. Next, as shown in FIG. 3 (e), an n-type semiconductor
N-type impurity on all surfaces of the body layer 7 and the p-type collector layer 9
Material ions 12 are implanted. In this case, the p-type collector layer 9
The impurity concentration of 5 × 10¹⁹cm^-3Relatively high concentration
And the concentration of implanted n-type impurity ions 12 is p-type.
Lower than the impurity concentration of the collector layer 9, for example, 2 × 10¹⁹c
m ^-3Can be used. In addition, the p-type collector layer 9 is
Masked with the n-type semiconductor layer 7
N-type collector shorting by implanting the product ions 12
The envelope layer 8 can be formed.

In the above manufacturing method, the n-type base layer 21
And n-type channel MOSFE on the surface of the p-type base layer 22.
After forming T, the n-type collector shorting layer 8 was formed,
The formation of the n-type collector short-circuit layer 8 is not limited to the above method,
For example, it may be before the epitaxial growth of the n-type buffer layer 1.

Similar to the second embodiment, the n-type base layer 2
1, 21a and the p-type base layer 22 form a striped base layer that is alternately and repeatedly arranged, so that the impurity concentration of the n-type base layers 21 and 21a can be increased and a high breakdown voltage can be obtained. Further, it is possible to obtain an element having a lower on-resistance while maintaining high speed.

[Fourth Embodiment] FIG. 20 shows a fourth embodiment of the present invention.
2 is a cross-sectional view showing the structure of a vertical power semiconductor device according to the embodiment of FIG. This embodiment is also a vertical collector short-circuit type I.
It is an embodiment in which the present invention is applied to GBT.

Vertical collector short-circuit IGB shown in FIG.
A method of manufacturing T will be described with reference to FIGS.

As shown in FIG. 21A, a trench groove 7a is formed in the low concentration n-type semiconductor layer 7. Next, FIG.
As shown in (b), the p-type collector layer 9 is deposited so as to fill the trench groove 7a formed in (a), and the excess p-type collector layer is polished and removed by CMP or the like. Next, as shown in FIG. 21C, the n-type buffer layer 1 is formed on the surfaces of the n-type semiconductor layer 7 and the p-type collector layer 9, and the impurity concentration of the n-type buffer layer 1 is about 2 × 10 ¹⁵ cm ^−. The n-type base layer 21 of about ³ is epitaxially grown.

Next, as shown in FIG.
A plurality of trench grooves 21b are formed to such an extent that the n-type buffer layer 1 is not exposed in the n-type base layer 21 formed in (c). If the n-type base layer is etched until the n-type buffer layer 1 is exposed as in the second embodiment, even the n-type buffer layer 1 that does not need to be etched may be damaged. Since the etching of the n-type base layer 21 is stopped before that, the n-type buffer layer 1 is not damaged, and a better semiconductor element can be formed. Next, as shown in FIG.
A p-type base layer 22 is deposited so as to fill the trench groove 21b formed in (d), and the excess p-type base layer is polished and removed by CMP or the like.

Next, as shown in FIG. 23 (f), a p-type base is
Of the p-type layer on the surfaces of the n-type base layer 21 and the n-type base layer 21.
The cell layer 3 is formed. Furthermore, on the surface of the p-type well layer 3,
The n-type emitter layer 4 is selectively formed. Adjacent n-type d
The n-type base layer 21a and the p-type well layer are provided between the mitter layers 4.
Insulated gate electrode 6 on the surface of 3 through gate insulating film 5
Is provided. Further, the n-type emitter layer 4 and the p-type well
Emitter electrode so that both layers of layer 3 are simultaneously contacted
Form 10. Further, the n-type semiconductor layer 7 is selectively formed.
CMP or the like until the exposed p-type collector layer 9 is exposed.
Therefore, it is removed by polishing. Next, as shown in FIG.
N with respect to all surfaces of the p-type semiconductor layer 7 and the p-type collector layer 9
Type impurity ions 12 are implanted. In this case, p-type collect
The impurity concentration of the layer 9 is 5 × 10 in advance.¹⁹cm^-3Comparison of degree
The concentration of the n-type impurity ions 12 to be injected is
Lower than the impurity concentration of the p-type collector layer 9, for example, 2 × 1
0 ¹⁹cm^-3Can be used. In addition, the p-type collector layer 9
Masking with a resist, only n-type semiconductor layer 7
N-type
The contactor short-circuit layer 8 can be formed.

In the above manufacturing method, the n-type base layer 21
And n-type channel MOSFE on the surface of the p-type base layer 22.
After forming T, the n-type collector shorting layer 8 was formed,
The formation of the n-type collector short-circuit layer 8 is not limited to the above method,
For example, it may be before the epitaxial growth of the n-type buffer layer 1.

Although the first to fourth embodiments of the present invention have been described with respect to the vertical collector short-circuit IGBT,
As shown in FIG. 24, SOI (Silicon On I)
The present invention can also be implemented by configuring a lateral element in which the short-circuited IGBT according to the present invention is formed on a substrate. FIG. 24 shows the lateral semiconductor element of the collector short-circuited IGBT of the second embodiment, but it is of course possible to configure the lateral semiconductor element using the collector short-circuited IGBT of the first, third and fourth embodiments. Is.

The embodiment described above is an example of the present invention, and the present invention is not limited to the embodiment, and various modifications and changes can be made within the scope of the claims.

[0061]

As described in detail above, according to the present invention,
It is possible to provide a power semiconductor device having low on-voltage characteristics and high-speed switching performance at the same time.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a vertical power semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view showing a method of manufacturing a vertical power semiconductor device according to the first embodiment of the present invention (No. 1).

FIG. 3 is a diagram showing a method for manufacturing a vertical power semiconductor device according to the first embodiment of the present invention (No. 2).

FIG. 4 is a diagram showing a flow of electrons in the vertical power semiconductor device shown in FIG. 1 at the beginning of energization or when a low current is energized.

5 is a diagram showing a flow of carriers in an ON state in the vertical power semiconductor device shown in FIG.

FIG. 6 is a cross-sectional view showing the structure of a modification of the vertical power semiconductor device according to the first embodiment of the invention.

FIG. 7 is a sectional view showing a structure of a modification of the vertical power semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing the structure of a vertical power semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a view showing a method of manufacturing a vertical power semiconductor device according to the second embodiment of the present invention (No. 1).

FIG. 10 is a view showing a method of manufacturing a vertical power semiconductor device according to the second embodiment of the present invention (No. 2).

FIG. 11 is a view (No. 3) showing the method of manufacturing the vertical power semiconductor device according to the second embodiment of the present invention.

12 is a diagram showing the spread of a depletion layer at the initial stage of applying a collector-emitter voltage in the vertical power semiconductor device shown in FIG.

13 is a diagram showing a potential distribution (equipotential lines) in the off state (blocking state) in the vertical power semiconductor device shown in FIG.

14 is a diagram showing an electric field intensity distribution between line segments BB ′ in the vertical power semiconductor device shown in FIG.

15 is a diagram showing an electric field intensity distribution between line segments CC ′ in the vertical power semiconductor device shown in FIG.

16 is a characteristic diagram showing emitter-collector voltage-collector current density characteristics of the vertical power semiconductor device shown in FIGS. 1 and 8, the conventional IGBT, and the conventional SJ-MOSFET.

FIG. 17 is a sectional view showing a structure of a vertical power semiconductor device according to a third embodiment of the present invention.

FIG. 18 is a diagram showing a method of manufacturing a vertical power semiconductor device according to the third embodiment of the present invention (No. 1).

FIG. 19 is a view showing a method of manufacturing a vertical power semiconductor device according to the third embodiment of the present invention (No. 2).

FIG. 20 is a sectional view showing a structure of a vertical power semiconductor device according to a fourth embodiment of the present invention.

FIG. 21 is a diagram showing a method of manufacturing a vertical power semiconductor device according to the fourth embodiment of the present invention (No. 1).

FIG. 22 is a diagram showing a manufacturing method for the vertical power semiconductor device according to the fourth embodiment of the present invention (No. 2).

FIG. 23 is a view (No. 3) showing the method of manufacturing the vertical power semiconductor device according to the fourth embodiment of the present invention.

FIG. 24 is a perspective view showing a configuration of a lateral semiconductor element in which the power semiconductor element of the present invention is formed on an SOI substrate.

FIG. 25 is a sectional view showing a structure of a vertical power semiconductor device according to a conventional technique.

FIG. 26 is a diagram showing an electric field strength distribution between line segments DD ′ of the vertical power semiconductor device shown in FIG. 25.

[Explanation of symbols]

1 ... N-type buffer layer, 2, 21 ... N-type base layer, 22 ...
p type base layer, 3 ... p type well layer, 4 ... n type emitter layer, 5 ... gate insulating film, 6 ... insulated gate electrode, 7 ... n type semiconductor layer, 8 ... n type collector shorting layer, 9 ... p type Collector layer, 10 ... Emitter electrode, 11 ... Collector electrode

Claims (22)

[Claims] 1. A first conductivity type base layer, a second conductivity type well layer selectively formed on one surface of the first conductivity type base layer, and a second conductivity type well layer surface selectively formed on the second conductivity type well layer. Formed on the first
A conductive type emitter layer, a first main electrode formed on the first conductive type emitter layer and the second conductive type well layer, and on the first conductive type base layer and the second conductive type well layer. An insulating gate electrode formed via a gate insulating film and formed between the adjacent first conductivity type emitters, and a plurality of selectively formed on the other surface of the first conductivity type base layer. A first conductivity type semiconductor layer, a first conductivity type collector short-circuit layer formed on the surfaces of the first conductivity type semiconductor layers, and the first conductivity type adjacent to the other surface of the first conductivity type base layer. A second conductivity type collector layer formed between the semiconductor layer and the first conductivity type collector short circuit layer; and a second conductivity type collector layer formed on the surface of the second conductivity type collector layer and the first conductivity type collector short circuit layer. Characterized by having two main electrodes Conductive element. 2. A first-conductivity-type buffer layer, formed on one surface of the first-conductivity-type buffer layer,
A first conductive type base layer having an impurity concentration lower than that of the first conductive type buffer layer; and a second selectively formed on the surface of the first conductive type base layer.
A conductive type well layer and a first conductive layer selectively formed on the surface of the second conductive type well layer.
A conductive type emitter layer, a first main electrode formed on the first conductive type emitter layer and the second conductive type well layer, and on the first conductive type base layer and the second conductive type well layer. An insulating gate electrode formed via a gate insulating film and formed between the adjacent first conductivity type emitter layers, and a plurality of selectively formed on the other surface of the first conductivity type buffer layer. A first conductive type semiconductor layer, a first conductive type collector short-circuit layer formed on the surfaces of the first conductive type semiconductor layers, and the first conductive layer adjacent to the other surface of the first conductive type buffer layer Second conductivity type collector layer formed between the second conductivity type collector layer and the first conductivity type collector short circuit layer, and formed on the surfaces of the second conductivity type collector layer and the first conductivity type collector short circuit layer. Characterized by having a second main electrode Semiconductor element. 3. A first conductivity type buffer layer, a plurality of first conductivity type base layers selectively formed on one surface of the first conductivity type buffer layer, and a plurality of first conductivity type buffer layers. A plurality of second conductivity type base layers formed on one surface and between the adjacent first conductivity type base layers, and selected to the second conductivity type base layer and the first conductivity type base layer surface. Second conductivity type well layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type well layer, the first conductivity type emitter layer and the second conductivity type A first main electrode formed on a well layer, and a first conductive type emitter layer formed on the first conductive type base layer and the second conductive type well layer via a gate insulating film, and adjacent to each other. And an insulated gate electrode formed between the first and second conductive type electrodes. A plurality of first conductivity type semiconductor layers selectively formed on the other surface of the first conductivity type layer, a first conductivity type collector short-circuit layer formed on the surfaces of these first conductivity type semiconductor layers, and the first conductivity type A second conductive type collector layer formed on the other surface of the positive type buffer layer and between the first conductive type semiconductor layer and the first conductive type collector short-circuit layer adjacent to each other, and the second conductive type collector layer. And a second main electrode formed on the surface of the first conductivity type collector short-circuit layer. 4. The product of the lateral width of the first conductivity type base layer and the impurity concentration of the first conductivity type base layer, the lateral width of the second conductivity type base layer and the impurity concentration of the second conductivity type base layer. 4. The semiconductor element according to claim 3, wherein the product of and is substantially equal. 5. A first conductivity type buffer layer, a first first conductivity type base layer formed on one surface of the first conductivity type buffer layer, and a first first conductivity type base layer. A plurality of second first-conductivity-type base layers selectively formed on the surface of the second first-conductivity-type base, and adjacent second first-conductivity-type bases on the surface of the first first-conductivity-type base layer A plurality of second conductivity type base layers formed between the layers, and second conductivity type wells selectively formed on the surfaces of the second conductivity type base layers and the second first conductivity type base layer Layer, and a first layer selectively formed on the surface of the second conductivity type well layer
A conductive type emitter layer, a first main electrode formed on the first conductive type emitter layer and the second conductive type well layer, the second first conductive type base layer and the second conductive type well An insulating gate electrode formed on a layer via a gate insulating film and formed between adjacent first conductivity type emitter layers, and selectively formed on the other surface of the first conductivity type buffer layer. A plurality of first conductive type semiconductor layers, a first conductive type collector short-circuit layer formed on the surfaces of these first conductive type semiconductor layers, and adjacent to the other surface of the first conductive type buffer layer. A second conductive type collector layer formed between the first conductive type semiconductor layer and the first conductive type collector short circuit layer; and a surface of the second conductive type collector layer and the first conductive type collector short circuit layer. And a second main electrode formed on the The semiconductor device characterized. 6. The product of the lateral width of the second first conductivity type base layer and the impurity concentration of the second first conductivity type base layer,
The semiconductor device according to claim 5, wherein a product of a lateral width of the second conductive type base layer and an impurity concentration of the second conductive type base layer is substantially equal to each other. 7. A longitudinal direction parallel to the second main electrode surface of the first conductive type semiconductor layer and the second conductive type collector layer, and parallel to the second main electrode surface of the insulated gate electrode. 7. The semiconductor device according to claim 1, wherein the longitudinal direction is orthogonal to each other. 8. A longitudinal direction of the first conductive type base layer and the second conductive type base layer parallel to the second main electrode surface, and a longitudinal direction parallel to the second main electrode surface of the insulated gate electrode. 7. The semiconductor device according to claim 3, wherein the longitudinal direction is orthogonal to each other. 9. The insulated gate electrode has both side surfaces in contact with the first conductive type emitter layer and the second conductive type well layer via the gate insulating film, and has a bottom surface via the gate insulating film. 9. The semiconductor device according to claim 1, which is in contact with the first conductivity type base layer. 10. The value obtained by dividing the layer thickness of the first conductive type semiconductor layer by the impurity concentration of the first conductive type semiconductor layer is half the lateral width of the second conductive type collector layer as the first conductive type base. 2. The semiconductor element according to claim 1, wherein the semiconductor element has a value larger than a value obtained by dividing the impurity concentration of the layer. 11. A value obtained by dividing the layer thickness of the first conductive type semiconductor layer by the impurity concentration of the first conductive type semiconductor layer is half the width of the second conductive type collector layer as the first conductive type buffer layer. 6. The semiconductor device according to claim 2, wherein the semiconductor device has a value larger than a value obtained by dividing the impurity concentration of the layer. 12. The semiconductor device according to claim 1, wherein the layer thickness of the first conductive type semiconductor layer is thicker than half the lateral width of the second conductive type collector layer. 13. A step of forming a plurality of second conductive type collector layers on one of the first conductive type semiconductor layers, and a first conductive layer on the first conductive type semiconductor layer on which the second conductive type collector layers are formed. Forming a type buffer layer, forming a first conductive type base layer on the first conductive type buffer layer, and selectively forming a second conductive type well layer on the surface of the first conductive type base layer And selectively forming a first conductivity type emitter layer on the surface of the second conductivity type well layer, and forming a first main electrode on the first conductivity type emitter layer and the second conductivity type well layer. And a step of forming an insulated gate electrode on the first conductive type base layer and the second conductive type well layer between the adjacent first conductive type emitter layers with a gate insulating film interposed therebetween. A step of thinning the one-conductivity-type semiconductor layer to a predetermined thickness; Forming a first conductivity type collector short circuit layer on the surface of the first conductivity type semiconductor layer, and forming a second main electrode on the first conductivity type collector short circuit layer and the second conductivity type collector layer surface. A method of manufacturing a semiconductor device, comprising: 14. A step of forming a plurality of second conductive type collector layers on one of the first conductive type semiconductor layers, and a first conductive layer on the first conductive type semiconductor layer on which the second conductive type collector layers are formed. Forming a base layer of the second conductivity type, selectively forming a well layer of the second conductivity type on the surface of the base layer of the first conductivity type, and selectively forming an emitter layer of the first conductivity type on the surface of the second well layer of the second conductivity type. A step of forming, a step of forming a first main electrode on the first conductive type emitter layer and the second conductive type well layer, and the first conductive type between adjacent first conductive type emitter layers. Forming an insulated gate electrode on the base layer and the second conductivity type well layer via a gate insulating film, thinning the first conductivity type semiconductor layer to a predetermined thickness, and the first conductivity type Forming a first conductivity type collector shorting layer on the surface of the semiconductor layer And a step of forming a second main electrode on the surfaces of the first conductive type collector short-circuit layer and the second conductive type collector layer. 15. A step of forming a plurality of second conductive type collector layers on one of the first conductive type semiconductor layers, and a first conductive layer on the first conductive type semiconductor layer on which the second conductive type collector layers are formed. A step of forming a type buffer layer, a step of forming a first conductivity type base layer on the first conductivity type buffer layer, a step of forming a plurality of trench grooves in the first conductivity type base layer, Embedding a second conductivity type base layer in the plurality of trench grooves, and selectively forming a second conductivity type well layer on the surfaces of the second conductivity type base layer and the first conductivity type base layer.
A step of selectively forming a first conductivity type emitter layer on a surface of the conductivity type well layer; a step of forming a first main electrode on the first conductivity type emitter layer and the second conductivity type well layer; Forming an insulated gate electrode on the first conductive type base layer and the second conductive type well layer between the adjacent first conductive type emitter layers via a gate insulating film; and the first conductive type semiconductor. Thinning the layer to a predetermined thickness, forming a first conductivity type collector short-circuit layer on the surface of the first conductivity type semiconductor layer, the first conductivity-type collector short-circuit layer and the second conductivity type And a step of forming a second main electrode on the surface of the collector layer. 16. A step of forming a plurality of second conductivity type collector layers on one of the first conductivity type semiconductor layers, and a step of forming a first conductivity type buffer layer on the first conductivity type semiconductor layers, A first base on which a first first-conductivity-type base layer is formed on a first-conductivity-type buffer layer, and a second-conductivity-type impurity is selectively ion-implanted into the surface of the first first-conductivity-type base layer. A layer forming step, and forming a second first conductivity type base layer on the first first conductivity type base layer, and selecting a second conductivity type impurity on the surface of the second first conductivity type base layer. A second base layer forming step of selectively ion-implanting, and the first conductivity type base layer and the second conductivity type impurity implanted in the second first conductivity type base layer are heat-treated to form the first base layer. First conductivity type base layer and the second first type
Drive-in diffusing into the conductive type base layer to form a first second conductive type base layer and a second second conductive type base layer, and the second second conductive type base layer and the second conductive type base layer. Selectively forming a second conductivity type well layer on the surface of the first conductivity type base layer, and selectively forming a first conductivity type emitter layer on the surface of the second conductivity type well layer, Forming a first main electrode on the first-conductivity-type emitter layer and the second-conductivity-type well layer; and forming the second first-conductivity-type base layer and the second main-conductivity-type base layer between the adjacent first-conductivity-type emitter layers Forming an insulated gate electrode on the second conductivity type well layer via a gate insulating film; thinning the first conductivity type semiconductor layer to a predetermined thickness; and a surface of the first conductivity type semiconductor layer. Forming a first conductivity type collector short-circuit layer on the first conductivity type The method of manufacturing a semiconductor device characterized by a step of forming a second main electrode to the collector shorting layer and the second conductivity type collector layer on the surface. 17. A step of forming a plurality of second conductivity type collector layers on one of the first conductivity type semiconductor layers, and a step of forming a first conductivity type buffer layer on the first conductivity type semiconductor layers, Forming a first first-conductivity-type base layer on the first-conductivity-type buffer layer, and selectively ion-implanting a second-conductivity-type impurity into the surface of the first first-conductivity-type base layer, A first conductive type drive layer is drive-in-diffused into the first first conductive type base layer by heat treatment to form a first second conductive type base layer.
And a step of forming a second first-conductivity-type base layer on the first first-conductivity-type base layer, and a step of forming a second conductor on the surface of the second first-conductivity-type base layer. A second impurity is selectively ion-implanted, and the second conductivity type impurity is drive-in-diffused into the second first conductivity type base layer by heat treatment to form a second second conductivity type base layer.
And a second conductive type well layer is selectively formed on the surfaces of the second second conductive type base layer and the second first conductive type base layer, and the second conductive type well is formed. Selectively forming a first conductivity type emitter layer on the surface of the layer, forming a first main electrode on the first conductivity type emitter layer and the second conductivity type well layer, and adjoining the first main electrode Forming an insulated gate electrode on the second first-conductivity-type base layer and the second-conductivity-type well layer between the first-conductivity-type emitter layers via a gate insulating film; and the first-conductivity-type semiconductor Thinning the layer to a predetermined thickness, forming a first conductivity type collector short-circuit layer on the surface of the first conductivity type semiconductor layer, the first conductivity-type collector short-circuit layer and the second conductivity type Forming a second main electrode on the surface of the collector layer The method of manufacturing a semiconductor device characterized by. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the base layer is formed by repeating the second base layer forming step twice or more. 19. The step of forming a plurality of second conductivity type collector layers on one of the first conductivity type semiconductor layers comprises forming a plurality of trench grooves on one of the first conductivity type semiconductor layers, and forming these trench grooves in these trench grooves. 19. The method of manufacturing a semiconductor device according to claim 13, which is a step of burying the second conductivity type collector layer. 20. The step of forming a plurality of second-conductivity-type collector layers on one of the first-conductivity-type semiconductor layers comprises selectively ion-implanting a second-conductivity-type impurity into the surface of the first-conductivity-type semiconductor layer, 19. The method of manufacturing a semiconductor device according to claim 13, which is a step of drive-in diffusing the second conductivity type impurities into the first conductivity type semiconductor layer by heat treatment. 21. In the step of forming the first conductivity type collector short-circuit layer, the second conductivity type collector layer is masked,
14. The step of ion-implanting a first conductivity type impurity into the first conductivity type semiconductor layer and drive-in diffusing the first conductivity type impurity into the first conductivity type semiconductor layer by heat treatment. 21. A method of manufacturing a semiconductor device according to any one of claims 20 to 20. 22. In the step of forming the first conductivity type collector short-circuit layer, the first conductivity type impurity is ion-implanted into the first conductivity type semiconductor layer and the second conductivity type collector layer, and the first conductivity type collector short circuit layer is formed. 21. The method of manufacturing a semiconductor device according to claim 13, which is a step of drive-in diffusing impurities into the first conductive type semiconductor layer by heat treatment.