JP2003347904A - Electric circuit, latch circuit, electric circuit apparatus, display apparatus, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit which is operable with low power consumption and at a high frequency and resistant to a variation in characteristic of thin film transistors (TFTs) by forming a data reading circuit operable with a low voltage signal. <P>SOLUTION: In order to perform operations securely, a high potential power supply is connected to a gate electrode of a P-type TFT to which data signals are inputted in such a manner that the TFT receiving data signals is turned off as much as possible during a non-operating period. Similarly, a low potential power supply is connected to a gate electrode of an N-type TFT. Switch TFTs are provided between the high potential power supply and the P-type TFT and between the low potential power supply and the N-type TFT so as to turn the TFT off as required. Similarly, switch TFTs are provided between a data signal input terminal and a P-type TFT and between a data signal input terminal and an N-type TFT such that a data signal can be inputted thereto as required. The switching is controlled by using a latch signal and an inverse latch signal. Therefore, a latch circuit without a level shifter can be produced which can operate with stability. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display device for displaying an image by inputting a digital image signal. In addition,
The display device includes a liquid crystal display device including a liquid crystal element in a pixel and a display device including a light-emitting element such as an electroluminescence (EL) element.

[0002] The present invention also relates to an electric circuit, and more particularly to a latch circuit for retaining data.

[0003]

2. Description of the Related Art In recent years, a display device in which a semiconductor thin film is formed on an insulator such as a glass substrate, particularly an LCD (liquid crystal display device) using a thin film transistor (hereinafter referred to as TFT).
And other active matrix display devices are used in many products and are widely used. An active matrix display device has hundreds of thousands to millions of pixels arranged on a matrix, and displays an image by controlling the luminance of each pixel by a TFT arranged at each pixel. .

[0004] As a more recent technology, polysilicon T
2. Description of the Related Art A technique for integrally forming a pixel and a peripheral circuit on the same substrate using FT has been developed, and has greatly contributed to miniaturization and low power consumption of a display device. Such a display device,
In recent years, it has become an indispensable device for a display unit of a mobile information terminal, whose application field is remarkably expanding.

FIG. 2 shows a conventional example (conventional data latch) of a circuit for sequentially capturing and holding video data in response to a pulse from a shift register. This circuit is a P-type TFT
1001 and 1002, N-type TFTs 1003 and 100
4, a first clocked inverter 1000 including four TFTs, an inverter 1010, and a second clocked inverter 1020. Although the second clocked inverter 1020 is shown in FIG. 2 by a generally used circuit symbol, the configuration is the same as that of the first clocked inverter 1000 shown in FIG. A latch signal (LAT) is applied to the gate electrode of the P-type TFT 1001.
Is input, a high potential power supply (VDD) is connected to the source electrode of the P-type TFT 1001, and the source electrode of the P-type TFT 1002 is connected to the drain electrode of the P-type TFT 1001. A data signal (DATA) is input to the gate electrode of the P-type TFT 1002,
02 is connected to the first clocked inverter 1
000 output terminals (OUTPUT) are connected.

On the other hand, an inverted latch signal (LATB) is input to the gate electrode of the N-type TFT 1004,
A low potential power supply (VSS) is connected to the source electrode of the N-type TFT 1004, and one of the source electrode and the drain electrode of the N-type TFT 1003 is connected to the other of the drain electrode of the N-type TFT 1004. Also, the N-type TFT 100
The data signal (DATA) is input to the gate electrode of No. 3 and the output terminal (OUTPUT) of the first clocked inverter 1000 is connected to the drain electrode of the N-type TFT 1003.
Is connected.

The input terminal of the inverter 1010 is connected to the output terminal (OUTPUT) of the first clocked inverter 1000, and the input terminal of the second clocked inverter 1020 is connected to the output terminal of the inverter 1010. The output terminal (OUTPUT) of the first clocked inverter 1000 is connected to the output terminal of the second clocked inverter 1020. The latch signal and its inverted signal (not shown) are connected to the second clocked inverter.

The operation of the circuit shown in FIG. 2 will be described in detail. Note that in this specification, since a digital circuit is handled, the input / output potential is represented by a binary value of HIGH or LOW. The data signal (DA) input to this circuit
TA), latch signal (LAT), inverted latch signal (LA
The signal potential such as TB) is usually the same as the power supply potential of this circuit (the HIGH potential of the input / output potential is VDD and the LOW potential is VSS), but the HIGH / LOW potential is not necessarily the power supply potential (VDD / VSS). Need not match, 2
It suffices if they match when viewed as a value. For example, a potential lower than VDD by a threshold value by an N-type transistor is also included in the HIGH potential. A potential that can be restored to VDD / VSS by an amplitude compensation circuit or the like is considered to be the same HIGH / LOW potential.

First, the operation when the latch signal (LAT) is LOW and the inverted latch signal (LATB) is HIGH will be described. At this time, the P-type TFT 1001 and N
The type TFT 1004 turns on. Therefore, the P-type TFT 10
VDD, N-type TFT 1004
VSS is output from the drain electrode of.

The data signal (DATA) is supplied to the P-type TFT 1
002 and the gate electrode of the N-type TFT 1003. Here, assuming that the input potential of the data signal (DATA) is HIGH, the P-type TFT 1002 and the N-type TFT
The N-type TFT 1003 of the FT 1003 is turned on. Therefore, VSS is output to the output terminal (OUTPUT).

On the other hand, if the input potential of the data signal (DATA) is LOW, the P-type TFT 1002 and the N-type TFT
The P-type TFT 1002 of the FT 1003 is turned on. Therefore, VDD is output to the output terminal (OUTPUT).

At this time, the second clocked inverter 10
20 is in a high impedance state when the latch signal (LAT) is LOW and the inverted latch signal (LATB) is HIGH, and does not compete with the output of the first clocked inverter 1000.

Subsequently, the latch signal (LAT) becomes HIGH,
The operation when the inverted latch signal (LATB) becomes LOW will be described. At this time, the P-type TFT 1001 and the N-type TFT 1004 are turned off, and the first clocked inverter 1000 enters a high impedance state. The second clocked inverter 1020 functions as an inverter, is in a state of forming a loop with the inverter 1010, and holds a video signal captured when the latch signal (LAT) is LOW.

[0014]

In the case of a TFT circuit, the power supply potential of the circuit usually needs to be about 10V. On the other hand, a controller IC for producing a data signal or the like outside the panel operates at a power supply potential lower than that of the TFT circuit, so that a signal of a 3.3 V voltage is usually produced. When trying to input a signal produced at this low voltage to a TFT circuit as shown in FIG. 2, the voltage must be raised to about 10 V by a level shift circuit inside or outside the panel, and then input to the circuit of FIG. Become. When the level is shifted outside the panel, the number of components such as the level shift IC and the power supply IC increases, and the power consumption increases. Further, when level shifting is performed within a panel, problems such as an increase in layout area, an increase in power consumption, and difficulty in high-frequency operation occur.

Therefore, it is conceivable that the 3.3 V signal is directly input to the circuit of FIG. 2 without level shifting.
In this case, the following problem occurs.

For example, when the potential of the circuit is set to VSS of 0 V, VD
D is 9V, LOW potential of data signal (DATA) is 3V, HI
It is assumed that the circuit shown in FIG. 2 is operated with the GH potential set to 6V. Further, the high potential of the latch signal (LAT) and the inverted latch signal (LATB) is 9 which is the same as the power supply potential.
The V and LOW potentials are set to 0V, the threshold values of all the N-type TFTs are set to 2V, and the threshold values of the P-type TFTs are set to -2V.

When the latch signal (LAT) is at the LOW potential and the inverted latch signal (LATB) is at the HIGH potential, the P-type TFT 1001 and the N-type TFT 1004 are completely turned on, and either the source electrode or the drain electrode of the P-type TFT 1001 is turned on. One potential becomes 9V, and the N-type TFT 100
The potential of one of the source electrode and the drain electrode of No. 4 is 0V. Here, when a HIGH potential (6 V) data signal (DATA) is input, the N-type TFT 1003 is turned on, but the P-type TFT 1002 is also turned on since the input voltage is low and the off-region operation is not performed. However, P at this time
The difference between the gate-source voltage of the type TFT 1002 and the threshold voltage of the N-type TFT 1003 is -1V and 4V, respectively. Usually obtained from the mobility and the size of the TFT,
Since the current capability of the P-type TFT and the current capability of the N-type TFT are designed to be substantially equal, the N-type TFT 1003 having a large absolute value of the difference between the gate-source voltage and the threshold value has a more effective resistance than the P-type TFT 1002. Is expected to decrease, and as a result, a value close to 0 V is output from the output terminal (OUTPUT). In this case, although the operation is logically correct, the P-type TFT 1002 to be turned off is on and a through current flows between the power supply VDD and VSS, which causes a problem that the consumption current increases.

Further, in the following case, there is a more serious problem that normal operation is not performed. This is the case, for example, when the threshold value of the N-type TFT is 5V and the threshold value of the P-type TFT is -1V. When the latch signal (LAT) is at the LOW potential and the inverted latch signal (LATB) is at the HIGH potential, the P-type TFT 1001 and the N-type TFT 1004 are completely turned on as described above, and the potential of the output electrode of the P-type TFT 1001 is 9V.
And the potential of the output electrode of the N-type TFT 1004 becomes 0V. Here, a HIGH potential (6 V) data signal (DAT
When A) is input, the difference between the gate-source voltage of the P-type TFT 1002 and the threshold value and the difference between the gate-source voltage and the threshold value of the N-type TFT 1003 are -2V and 1V, respectively. Here, assuming that β _P = β _N , a P-type TFT having a large absolute value of the difference between the gate-source voltage and the threshold value
The effective resistance of the transistor 1002 is lower than that of the N-type TFT 1003. As a result, VDD is output from the output with respect to the HIGH data input, and the device does not operate properly.

Since the threshold value of the TFT greatly varies depending on the manufacturing process of the TFT or the like, when a signal having a voltage lower than the power supply potential is directly input to the circuit of FIG. 2, the threshold of the opposing P-type TFT 1002 and N-type TFT 1003 is set. If the value deviates significantly from the expected value, the device may not operate properly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device including a TFT, which can operate at low power consumption and at a high frequency and is resistant to variation in TFT characteristics. Is the subject.

[0021]

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention takes the following measures.

In the initial state, the data signal (DAT)
A) TF for inputting a power supply potential to each of gate electrodes of a P-type TFT and an N-type TFT for determining HIGH and LOW
In the period of taking in the signal data (DATA) and T, a data signal (DATA) is input to the gate electrodes of the P-type TFT and the N-type TFT. With the use of the data reading circuit provided, a data signal (D) is applied to one of the gate electrodes of the P-type TFT and the N-type TFT.
ATA) and the gate electrode turns on, and the other gate electrode receives a potential that is more likely to turn off.

Conventionally, the P-type TFT and the N-type TFT
The data signal (DATA) was directly input to the gate electrode of the data read circuit.
The operating margin can be improved by making the potentials input to the gate electrodes of the type TFT and the N-type TFT different from each other in a direction in which the operation is performed more accurately. Further, it is possible to provide a data reading circuit which is resistant to variation in characteristics of transistors and can operate at high frequency with low power consumption.

FIG. 11 shows a schematic diagram of the arrangement. FIG.
Is composed of three circuits and three signal input sections.

The operation will be described. The first circuit selects the third signal or the first power supply according to the first signal and inputs the selected signal to the third circuit, and the second circuit selects the third signal or the first power supply according to the second signal.
A third signal or a second power supply is selected and input to the third circuit. When the first circuit and the second circuit select the third signal, the output of the third circuit is an output signal corresponding to the third signal (if the third signal is at the HIGH potential, the second signal is output). The first circuit selects the power supply 1 if the power supply potential is LOW, and the third circuit has the high impedance when the second circuit selects the power supply 2. Becomes

Here, the first circuit and the second circuit compensate for the output of the third circuit due to their existence, and are respectively called a first compensation circuit and a second compensation circuit.

The present invention is an electric circuit having an N-type transistor and a first P-type transistor connected in series, and a second P-type transistor, wherein the gate electrode of the N-type transistor and the gate electrode of the first P-type transistor are provided. Are connected to each other, a drain electrode of the N-type transistor and a drain electrode of the first P-type transistor are connected to a gate electrode of the second P-type transistor, and a source electrode of the first P-type transistor is electrically connected to a power supply. A signal is input to a source electrode of the N-type transistor.

Further, in the above configuration, the N-type transistor may be replaced with an analog switch.

The present invention also relates to the first N series connected in series.
An electric circuit comprising a type transistor, a P-type transistor, and a second N-type transistor, wherein a gate electrode of the first N-type transistor and a gate electrode of the P-type transistor are connected to each other, and a drain electrode of the first N-type transistor and A drain electrode of the P-type transistor is connected to a gate electrode of the second N-type transistor;
A source electrode of the first N-type transistor is electrically connected to a power supply, and a signal is input to a source electrode of the P-type transistor.

According to the present invention, in the above configuration, the P-type transistor may be replaced with an analog switch.

Further, the present invention is characterized in that, in the above configuration, the amplitude of the signal is smaller than a power supply voltage.

Further, the present invention is a latch circuit using an electric circuit having the above configuration.

According to the present invention, a first N-type transistor and a first P-type transistor connected in series, and a data signal input or a first power supply potential input are selected based on an input latch signal. A first compensating circuit for outputting the input to the gate electrode of the first P-type transistor, and selecting whether to input a data signal or a second power supply potential based on the input inverted latch signal. A second compensation circuit that outputs the selected input to a gate electrode, wherein the data signal is input from the same signal line, and the output of the latch circuit is the first N-type. It is characterized in that it is taken out from a connection between the transistor and the first P-type transistor.

The present invention also provides a circuit in which a first P-type transistor whose source electrode is connected to a first power supply and a first N-type transistor whose source electrode is connected to a second power supply are connected in series. And a first compensation circuit including a second N-type transistor and a second P-type transistor connected in series with each other, and the gate electrodes connected together and connected in series. A latch circuit having a third compensating circuit comprising a third N-type transistor and a third P-type transistor.
The source electrodes of the N-type transistor and the third P-type transistor are connected to the same data line, the source electrode of the second P-type transistor is connected to the first power supply, and the source electrode of the third N-type transistor is connected. Is connected to the second power supply, the drain electrodes of the second N-type transistor and the second P-type transistor are connected to the gate electrode of the first P-type transistor,
The drain electrodes of the third N-type transistor and the third P-type transistor are connected to the gate electrode of the first N-type transistor, and the output is taken out from the drain electrode of the first N-type transistor or the first P-type transistor. Features.

With such a configuration, a level shifter becomes unnecessary, and a circuit that can operate with low power consumption and high frequency and that is resistant to variation in TFT characteristics can be provided.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. Here, unless otherwise specified, VDD is 9 V, VSS is 0 V, and HIG of the data signal.
The H potential is 6 V, the LOW potential is 3 V, and the latch signal is HIGH.
The potential is 9 V, the LOW potential is 0 V, the output HIGH potential is 9 V, and the LOW potential is 0 V. Of course, the value is not limited to this value in an actual circuit. For convenience of explanation, the circuit of the present invention is hereinafter referred to as a data reading circuit. This data reading circuit corresponds to the first clocked inverter 1000 in the conventional example shown in FIG. Further, a TFT used in this specification may have any of a single gate, a double gate, and a multi-gate structure, and any of known structures can be used.

[Embodiment 1] FIG. 1 shows a configuration of a data reading circuit of this embodiment. The data reading circuit of the present embodiment includes first, second, and third P-type TFTs 101, 103,
106 and first, second, and third N-type TFTs 102, 10
It is composed of six transistors 4, 105. First
The gate electrode of the P-type TFT 101 is a second P-type TFT.
One of the drain electrode 103 and the source electrode and the drain electrode of the third N-type TFT 105 is connected,
A high potential power supply (VDD) is connected to the source electrode of the first P-type TFT 101. First N-type TFT 102
One of the drain electrode of the second N-type TFT 104 and the source electrode and the drain electrode of the third P-type TFT 106 is connected to the gate electrode of the first N-type TFT 1.
A low potential power supply (VSS) is connected to the source electrode 02.

A latch signal (LAT) is input to the gate electrode of the second P-type TFT 103 and the gate electrode of the third N-type TFT 105, and a high-potential power supply ( VDD) is connected.
Gate electrode of second N-type TFT 104 and third P-type TF
The inverted latch signal (LATB) is applied to the gate electrode of T106.
And a low-potential power supply (VSS) is connected to the source electrode of the second N-type TFT 104. Third N-type T
A data signal (DATA) is input to the other of the source electrode and the drain electrode of the FT 105 and the other of the source electrode and the drain electrode of the third P-type TFT 106.

An output terminal (OUTPUT) is connected to the drain electrode of the first P-type TFT 101 and the drain electrode of the first N-type TFT 102.

Next, the operation will be described. Data signal (D
ATA), a latch signal (LAT), and an inverted latch signal (LATB) are input according to a timing chart as shown in FIG. Here, the latch signal (LAT)
Is HIGH and the inverted latch signal (LATB) is LO
W is a period t1, and the latch signal (LAT) is LO.
W, and the period when the inverted latch signal (LATB) is HIGH is defined as a period t2. Data signal (DATA) is H
Both IGH and LOW can be taken (provided that the data signal does not change during the period t1). The operation in each period will be described below.

In a period t1, the HIGH level latch signal (LAT) and the LOW level inverted latch signal (LA)
TB) turns off the second P-type TFT 103 and the second N-type TFT 104. At this time, the data signal (DA
When TA) is HIGH, the third P-type TFT 106 and the first N-type TFT 102 are turned on. Also, the third N
When the absolute value of the threshold value of at least one of the TFT 105 and the first P-type TFT 101 exceeds 3 V, the first P-type TFT 101 is turned off, and the output (O
UTPUT) is at the VSS potential.

On the other hand, when the data signal (DATA) is LOW, the third N-type TFT 105 and the first P-type TFT 1
01 turns on. Further, the third P-type TFT 106 and the first
If the absolute value of the threshold value of at least one of the N-type TFTs 102 exceeds 3 V, the first N-type TFT 1
Since 02 is turned off, the output (OUTPUT) becomes the VDD potential. Therefore, low power consumption can be realized without a leak current.

When the absolute value of the threshold value does not exceed 3 V (for example, when the threshold value of the P-type TFT is -2 V, N
The operation of the TFT will be described.

When the data signal (DATA) is HIGH, the third P-type TFT 106 and the first N-type TFT 102
Turns on, but the third N-type TFT 105 and the first P-type TFT 101 also turn on without operating in the off-region. At this time, the first P-type TFT 101 and the first N-type TFT 10
The difference between the gate-source voltage and the threshold of
-1V and 4V. Usually, the current capability of the P-type TFT and the current capability of the N-type TFT, which are determined from the mobility and the size of the TFT, are designed to be substantially equal. N-type TFT
The effective resistance of the transistor 102 is lower than that of the P-type TFT 101, and a LOW potential is output from the output terminal (OUTPUT).

On the other hand, when the data signal (DATA) is LOW, the third N-type TFT 105 and the first P-type TFT 1
01 turns on, but the third P-type TFT 106 and the first N-type TFT 102 also turn on without operating in the off-region.
At this time, the first P-type TFT 101 and the first N-type TFT
The difference between the gate-source voltage and the threshold value of 102 is -4V and 1V, respectively. Therefore, the first P-type TFT 1
01 has a lower effective resistance than the first N-type TFT 102, and a HIGH potential is output to the output terminal (OUTPUT).

In a period t2, the third N-type TFT 105 is turned off, the second P-type TFT 103 is turned on, and the potential of the gate electrode of the first P-type TFT 101 is set to VDD by the LOW potential latch signal (LAT). Become the first
P-type TFT 101 is turned off. At the same time, the third P-type TFT 106 is turned off, the second N-type TFT 104 is turned on, and the potential of the gate electrode of the first N-type TFT 102 becomes V by the inverted latch signal (LATB) of the HIGH potential.
SS, the first N-type TFT 102 is also turned off, and the data reading circuit enters a high impedance state. Therefore, even if the data signal (DATA) changes during the period t2, the output of the output terminal (OUTPUT) is not affected.

Although the above operation is almost the same as that of the conventional example when the output result is viewed, the data reading circuit of the present invention has the following two features as compared with the conventional example.

First, it is possible to operate even if the threshold value does not operate in the conventional example. For example,
In FIG. 1, the threshold value of the N-type TFT is 5 V, and the P-type TFT is
Is -1V. As described above, the conventional example does not operate normally with this threshold value. At this time, the latch signal (LAT) is HIGH, and the inverted latch signal (LATB)
Is low, consider the data fetch operation. The second P-type TFT 103 is turned off by the HIGH potential latch signal (LAT), and the second N-type TFT 104 is similarly turned off by the LOW potential inverted latch signal (LATB). Also, as an initial state, the first P-type TF
The potential applied to the gate electrode of T101 is VDD (9
V), the potential applied to the gate electrode of the first N-type TFT 102 is VSS (0 V).

First, the data signal (DATA) is HIGH.
Consider the case of a potential (6 V). At this time, the third N-type TF
Since the threshold value of T105 is 5V, the third N-type TF
The absolute value of the gate-source voltage of T105 is N-type TFT
The third N-type TF because it is less than the absolute value of the threshold of 105
T105 turns off. On the other hand, the threshold value of the third P-type TFT 106 is −1 V, and the absolute value of the gate-source voltage of the third P-type TFT 106 is the third P-type TFT 106.
Exceeds the absolute value of the threshold value of the third P-type TFT 10
6 turns on. Therefore, the potential applied to the gate electrode of the first N-type TFT 102 is a HIGH data signal (DAT
A), and the first N-type TFT 102 is turned on. on the other hand,
The potential applied to the gate electrode of the first P-type TFT 101 is 9
Since it is V, it remains off. Therefore, a LOW potential is output from the output terminal (OUTPUT).

Next, consider the case where the data signal (DATA) is at the LOW potential (3 V). At this time, the third N-type TFT
105 turns on, the potential of the gate electrode of the first P-type TFT 101 matches the potential of the data signal (DATA), and the third
P-type TFT 106 is turned on and the first N-type TFT 102
Of the gate electrode coincides with the data signal (DATA). Here, the threshold value of the first N-type TFT 102 is 5 V
Therefore, the absolute value of the gate-source voltage of the first N-type TFT 102 falls below the absolute value of the threshold value, and the first N-type TFT 102 is turned off. On the other hand, the first P-type TFT 101
Turns on, so the output terminal (OUTPUT)
The H potential is output.

As described above, the present invention can be operated even with a threshold value that does not operate in the conventional example.

Another feature is an improvement in response speed.
In FIG. 1, the threshold value of the N-type TFT is 2 V, and the P-type TF
The threshold value of T is -2V. At this time, the data signal (D
ATA) is LOW and the latch signal (LAT) is H
Consider an output when IGH and the inverted latch signal (LATB) are LOW. At this time, the second P-type TFT 103 is turned off by the high potential latch signal (LAT),
Similarly, the second N-type TFT 104 is turned off by the inversion latch signal (LATB) of the LOW potential.

Data signal (DATA) at LOW potential
Is input to the input electrode of the third N-type TFT 105 and the gate electrode of the third P-type TFT 106, and is latched by a HIGH potential latch signal (LAT).
However, the third P-type TFT 106 is turned on by the inversion latch signal (LATB) of the LOW potential.

Since the second P-type TFT 103 was turned on by the LOW potential latch signal (LAT) until immediately before the third N-type TFT 105 was turned on, the third N-type TFT 103 was turned on.
The potential of the output electrode of the TFT 105 is VDD. Therefore, since the potential of the output electrode of the third N-type TFT 105 is equal to the potential of the gate electrode, the operation is in a saturation region,
The gate-source voltage of the third N-type TFT 105 and the third
Of the N-type TFT 105 is 4V.

On the other hand, the third P-type TFT 106 keeps the HIGH potential inverted latch signal (LAT) until immediately before it is turned on.
B), the potential of the output electrode of the third P-type TFT 106 becomes VSS.
It has become. Therefore, the difference between the gate-source voltage of the third P-type TFT 106 and the threshold value of the third P-type TFT 106 is -1V.

Normally, the current capacity of the P-type TFT and the current capacity of the N-type TFT, which are determined from the mobility and the size of the TFT, are designed to be substantially equal. Third N-type TFT 105 with large value
In this case, the effective resistance is lower than that of the third P-type TFT 106. Therefore, the data signal (DAT) having the LOW potential
A) is a first P-type TF more than the first N-type TFT 102.
It is first transmitted to the gate electrode of T101.

As a result, the first P-type TFT 101 is turned on earlier than the first N-type TFT 102, and HIGH
The potential can be output quickly. In the case where the input of the data signal (DATA) is HIGH, the first N-type TFT is used in the same principle.
102 is turned on first, and the output of the LOW potential can be performed faster.

To take advantage of these advantages, the period t1
It is preferable in terms of operation that the data signal (DATA) does not change during the period.

[Second Embodiment] FIG. 4 shows a configuration example of a data reading circuit according to a second embodiment, which is different from the first embodiment.
The data reading circuit of this embodiment is different from the first embodiment in that a fourth P-type TFT 201 and a fourth N-type TFT 202 are added.
Is added. The source electrode of the fourth P-type TFT 201 is connected to the drain electrode of the first P-type TFT 101, and the source electrode of the fourth N-type TFT 202 is the first electrode.
Is connected to the drain electrode of the fourth P-type TFT 201 and the fourth N-type TFT
An output terminal (OUTPUT) is connected to the drain electrode of 202. A data signal (DATA) is input to the gate electrode of the fourth P-type TFT 201 and the gate electrode of the fourth N-type TFT 202.

Next, the operation will be described. Data signal (D
ATA), a latch signal (LAT), and an inverted latch signal (LATB) are input according to a timing chart as shown in FIG. Here, the latch signal (LAT)
Is HIGH and the inverted latch signal (LATB) is LO
W is a period t1, and the latch signal (LAT) is LO.
W, and the period when the inverted latch signal (LATB) is HIGH is defined as a period t2. Data signal (DATA) is H
Both IGH and LOW can be taken (provided that the data signal does not change during the period t1). The operation in each period is described as follows.

In a period t1, the HIGH level latch signal (LAT) and the LOW level inverted latch signal (LA)
TB) turns off the second P-type TFT 103 and the second N-type TFT 104. At this time, the data signal (DA
When TA) is HIGH, the third P-type TFT 106,
The first N-type TFT 102 and the fourth N-type TFT 202 are turned on. When the absolute value of the threshold value of at least one of the third N-type TFT 105, the first P-type TFT 101, and the fourth P-type TFT 201 exceeds 3V,
VDD is not output to the output (OUTPUT), and the output (O
UTPUT) is at the VSS potential.

On the other hand, when the data signal (DATA) is LOW, the third N-type TFT 105 and the first P-type TFT 10
The first and fourth P-type TFTs 201 are turned on. Also, the third
If the absolute value of the threshold value of at least one of the P-type TFT 106, the first N-type TFT 102, and the fourth N-type TFT 202 exceeds 3 V, the output (OUTPUT)
Is not output to VDD, and the output (OUTPUT) is VDD.
Potential. Therefore, low power consumption can be realized without a leak current.

When the absolute value of the threshold value does not exceed 3 V (for example, the threshold value of the P-type TFT is -2 V, N
The operation of the TFT will be described.

When the data signal (DATA) is HIGH, the third P-type TFT 106, the first N-type TFT 102, and the fourth N-type TFT 202 are turned on, but the third N-type TFT
FT105, first P-type TFT 101 and fourth P-type TFT
The FT 201 also turns on without operating in the off-region. However, at this time, the difference between the gate-source voltage and the threshold value of the first P-type TFT 101 and the first N-type TFT 102 is -1V and 4V, respectively. Usually mobility and TFT
Since the current capability of the P-type TFT and the current capability of the N-type TFT, which are obtained from the size of
The first N-type TFT 102 and the fourth N-type TFT 202 having a large absolute value of the difference between the gate-source voltage and the threshold have a lower effective resistance than the first P-type TFT 101 and the fourth P-type TFT 201. , As a result, the output terminal (OUTP
UT) outputs a LOW potential.

On the other hand, when the data signal (DATA) is LOW, the third N-type TFT 105 and the first P-type TFT 10
The first and fourth P-type TFTs 201 are turned on, but the third P-type TFT 201 is turned on.
TFT 106, first N-type TFT 102 and fourth N-type TFT 102.
The type TFT 202 also turns on without operating in the off region. However, the first P-type TFT 101 and the first
The difference between the gate-source voltage and the threshold value of the N-type TFT 102 is -4V and 1V, respectively. Therefore, the first P-type TFT 101 and the fourth P-type TFT 201 having a large absolute value of the difference between the gate-source voltage and the threshold value are the first
The effective resistance is lower than that of the N-type TFT 102 and the fourth N-type TFT 202, and as a result, the output terminal (OUTP
UT) outputs a HIGH potential.

In the period t2, the third N-type TFT 105 is turned off by the LOW potential latch signal (LAT). Then, the second P-type TFT 103 is turned on,
The potential of the gate electrode of the first P-type TFT 101 becomes VDD, and the first P-type TFT 101 is turned off. At the same time, the third P-type TFT 106 is turned off by the HIGH level inverted latch signal (LATB). And the first
Of the first N-type TFT 1 are turned on.
02 becomes VSS, and the first N-type T
The FT 102 is also turned off, and the data reading circuit enters a high impedance state. Therefore, the data signal (DAT
Output terminal (OUTPUT) even if A) changes during the period
Does not affect the output of.

As a feature of this embodiment, the first embodiment
Similarly, the TFT operates even at the threshold value which does not operate in the conventional example, the response speed is improved, and the resistance ratio between the N-type TFT and the P-type TFT is increased by increasing the number of TFTs, so that the TFT operates more reliably. It is easy. Also in the present embodiment, similarly to the first embodiment, it is preferable in terms of operation that the data signal (DATA) does not change during the period t1.

[Third Embodiment] FIG. 5 shows a configuration example of a data reading circuit according to a third embodiment, which is different from the first and second embodiments. The data reading circuit of the present embodiment is the same as that of the first embodiment.
And a fourth N-type TFT 301 and a fourth P-type TFT 3
02 was added. In this embodiment, the latch signal (LAT) and the inverted latch signal (LATB) in the first embodiment are referred to as a first latch signal (LAT1) and a first inverted latch signal (LAT1B), and a second latch signal is newly added. Signal (LAT2) and a second inverted latch signal (LAT2).
B) was added.

The data signal (DAT) is applied to one of the source electrode and the drain electrode of the fourth N-type TFT 301.
A) is input, and one of the source electrode and the drain electrode of the third N-type TFT 105 is connected to the other. A data input signal (DATA) is applied to one of the source electrode and the drain electrode of the fourth P-type TFT 302.
, And one of the source electrode and the drain electrode of the third P-type TFT 106 is connected to the other.

The second P-type TFT 103 and the third N-type TF
A first latch signal (LAT) is applied to the gate electrode of T105.
1) The second N-type TFT 104 and the third P-type TFT
A first inverted latch signal (LAT1B), which is an inverted signal of the first latch signal, is input to the gate electrode of the FT. The second latch signal (LAT2) is supplied to the gate electrode of the fourth N-type TFT 301 by the fourth P-type TF.
A second inverted latch signal (LAT2B) which is an inverted signal of the second latch signal is input to the gate electrode of T302.

Next, the operation will be described. Data signal (D
ATA), a first latch signal (LAT1), a first inverted latch signal (LAT1B), and a second latch signal (LAT2) having the same cycle and a different phase as the first latch signal.
And the second inverted latch signal (LAT2B) in FIG.
Input is performed according to a timing chart as shown in FIG.
Here, the first latch signal (LAT1) is LOW, the second latch signal (LAT2) is LOW, the first inverted latch signal (LAT1B) is HIGH,
A period during which the second inverted latch signal (LAT2B) is HIGH is defined as a period t1. Subsequently, the first latch signal (LA
T1) is HIGH and the second latch signal (LAT)
2) is LOW, and the first inverted latch signal (LAT1)
B) is LOW, and the second inverted latch signal (LAT2)
A period during which B) is HIGH is defined as t2. Subsequently, the first latch signal (LAT1) is HIGH, the second latch signal (LAT2) is HIGH, the first inverted latch signal (LAT1B) is LOW, and the second inverted latch signal (LAT2B) ) Is LOW for a period t3. The first latch signal (LAT1) is LOW, the second latch signal (LAT2) is HIGH, the first inverted latch signal (LAT1B) is HIGH, and the second inverted latch signal (LAT2B) Is LOW for a period t4. The data signal (DATA) can be either HIGH or LOW (provided that the data signal does not change during the period t3). The operation in each period is described as follows.

In a period t1, the third latch signal (LAT1) of the LOW potential causes the third N-type TFT 10
5 goes off. Then, the second P-type TFT 103 is turned on. On the other hand, the first inverted latch signal (L
AT1B) turns off the third P-type TFT 106 and turns on the second N-type TFT 104. Therefore,
The potential of the gate electrode of the first P-type TFT 101 becomes VDD, and the first P-type TFT 101 is turned off. At the same time, the potential of the gate electrode of the first N-type TFT 102 becomes VSS, the first N-type TFT 102 is also turned off, and the data reading circuit enters a high impedance state. Therefore,
Even if the data signal (DATA) changes during the period t1, the output of the output terminal (OUTPUT) is not affected.

In the period t2, the third N-type TFT 10 is driven by the first latch signal (LAT1) of HIGH potential.
5 is turned on, and the third P-type TFT 106 is activated by (LAT1B) by the first inversion latch signal of the LOW potential.
Turns on. At the same time, the second P-type TFT 103 and the second
Is turned off, but the fourth N-type TFT 301 is turned off by the second latch signal (LAT2) of LOW potential.
Is turned off, and the fourth P-type TFT 302 is turned off by the second inversion latch signal (LAT2B) of the HIGH potential, so that the first P-type TF is still in the period t2.
The potential of the gate electrode of T101 is VDD, and the potential of the gate electrode of the first N-type TFT 102 is VSS. Therefore, both the first P-type TFT 101 and the first N-type TFT 102 are off. Therefore, the data reading circuit is in a high impedance state, and the data signal (DATA) is in the period t.
2 does not affect the output of the output terminal (OUTPUT).

In the period t3, the second P-type TFT 10 is driven by the first latch signal (LAT1) having the HIGH potential and the first inverted latch signal (LAT1B) having the LOW potential.
The third and second N-type TFTs 104 are turned off. At this time,
When the data signal (DATA) is HIGH, the fourth P
TFT 302, third P-type TFT 106, and first N
The type TFT 102 turns on. In addition, the fourth N-type TFT 3
01, third N-type TFT 105, first P-type TFT 10
When the absolute value of at least one of the threshold values of 1 exceeds 3 V, the first P-type TFT 101 is turned off, and the output (OUTPUT) becomes the VSS potential.

On the other hand, when the data signal (DATA) is LOW, the fourth N-type TFT 301 and the third N-type TFT 10
5 and the first P-type TFT 101 are turned on. Also, the fourth
P-type TFT 302, third P-type TFT 106 and first
If the absolute value of at least one of the thresholds of the N-type TFT 102 exceeds 3 V, the first N-type TFT 1
Since 02 is turned off, the output (OUTPUT) becomes the VDD potential. Therefore, low power consumption can be realized without a leak current.

When the absolute value of the threshold value does not exceed 3 V (for example, the threshold value of the P-type TFT is -2 V, N
The operation in the period t3 will be described.

When the data signal (DATA) is HIGH, the first N-type TFT 102 is turned on, but the first P-type TFT 102 is turned on.
The FT 101 is also turned on without performing the off-region operation. However, at this time, the difference between the gate-source voltage and the threshold value of the first P-type TFT 101 and the first N-type TFT 102 is -1V and 4V, respectively. Usually mobility and TFT
Since the current capability of the P-type TFT and the current capability of the N-type TFT, which are obtained from the size of
The first N-type TFT 102 having a large absolute value of the difference between the gate-source voltage and the threshold value has a lower effective resistance than the first P-type TFT 101, and as a result, the output terminal (OUTPU
T) outputs a LOW potential.

On the other hand, when the data signal (DATA) is LOW, the first P-type TFT 101 is turned on.
The type TFT 102 also turns on without operating in the off region. However, the first P-type TFT 101 and the first
The difference between the gate-source voltage and the threshold value of the N-type TFT 102 is -4V and 1V, respectively. Therefore, the first P-type TFT 101 having a large absolute value of the difference between the gate-source voltage and the threshold value has a lower effective resistance than the first N-type TFT 102, and as a result, the HIGH potential from the output terminal (OUTPUT). Is output.

In the period t4, the first latch signal (L
AT1) becomes LOW, the third N-type TFT 105 is turned off, the first inverted latch signal (LAT1B) becomes HIGH, and the third P-type TFT 106 is also turned off. On the other hand, since the second P-type TFT 103 and the second N-type TFT 104 are turned on, the first P-type TFT 101 is turned off when the potential of the gate electrode becomes VDD, and the first N-type TFT 102 is also turned on. The potential becomes VSS and turns off. Therefore, the data reading circuit enters a high impedance state. Therefore, even if the data signal (DATA) changes within the period t4, the output of the output terminal (OUTPUT) is not affected.

The above operation can be summarized as follows.
In this case, an active output corresponding to the input data signal (DATA) is performed, and the output becomes high impedance in other periods.

The second latch signal (LAT2) and the second inverted latch signal (LAT2B) may be newly generated by a pulse generator, or may be the first latch signal (LAT2).
1) and the first inverted latch signal (LAT1B) may be delayed by some means such as a delay circuit. In particular, the latter is preferable because it is not necessary to make a pulse generator and can be realized by easy means.

The first latch signal (LAT1) and the second latch signal (LAT2), the first inverted latch signal (LAT1B) and the second inverted latch signal (LAT2B)
Consider the case where the input is made according to the timing chart of FIG. In this case as well, an output corresponding to the data signal (DATA) is performed in the period t3, and otherwise, there is no influence on the output by the data signal (DATA). Therefore, the timing of the pulse may be either the first latch signal (LAT1) or the second latch signal (LAT2).

The feature of the present embodiment is that, similarly to the first embodiment, the TFT operates even at the threshold value which does not operate in the conventional example, and the response speed is improved. In the present embodiment, it is preferable in terms of operation that the data signal (DATA) does not change during the period t3.

[Fourth Embodiment] FIG. 6 shows a configuration example of a data reading circuit according to a fourth embodiment, which is different from the first to third embodiments. The data reading circuit of the present embodiment is the same as that of the first embodiment.
In this embodiment, a capacitance means 410 and an analog switch 420 are newly added. The analog switch 420 is connected to the third N-type TFT 105 and the third P-type TFT 105 for the data signal (DATA).
The input to the type TFT 106 is controlled. The latch signal (LAT) and the inverted latch signal (LATB) are input to the analog switch 420. An analog switch 420, one of a source electrode and a drain electrode of the third N-type TFT 105, and one of a source electrode and a drain electrode of the third P-type TFT 106 are connected to the capacitance means 410, and a data signal (DATA) The electric charge corresponding to the potential of (3) is stored.

Next, the operation will be described. Data signal (D
ATA), a latch signal (LAT), and an inverted latch signal (LATB) are input in accordance with a timing chart as shown in FIG. Here, the latch signal (LAT)
Is LOW, and the inverted latch signal (LATB) is HIG.
H is a period t1, and the latch signal (LAT) is HI.
GH, and a period during which the inverted latch signal (LATB) is LOW is defined as a period t2. Data signal (DATA) is H
Both IGH and LOW can be taken. The operation in each period is described as follows.

In the period t1, the latch signal (LAT) at the LOW potential and the inverted latch signal (LA) at the HIGH potential
By TB), the analog switch 420 is turned on, and charges corresponding to the data signal are stored in the capacitance means 410. Further, the third N-type TFT 105 is turned off by the latch signal (LAT) having the LOW potential. Then, the second P-type TFT 103 is turned on, and the first P-type TFT 103 is turned on.
The potential of the gate electrode 101 becomes VDD, and the first P-type TFT 101 is turned off. At the same time, the third P-type TFT 1 is activated by an inverted latch signal (LATB) having a HIGH potential.
06 turns off. Then, the second N-type TFT 104 is turned on, the potential of the gate electrode of the first N-type TFT 102 becomes VSS, the first N-type TFT 102 is also turned off, and the data reading circuit enters a high impedance state. Therefore, even if the data signal (DATA) changes during the period t1, the output of the output terminal (OUTPUT) is not affected.

In a period t2, a high potential latch signal (LAT) and a low potential inverted latch signal (LA)
TB), the analog switch 420, the second P-type T
The FT 103 and the second N-type TFT 104 are turned off, and the third
N-type TFT 105 and third P-type TFT 106 are turned on. The operation period of the capacitance means 410 is changed from the period t1 to the period t2.
Since the electric charge corresponding to the potential of the data signal (DATA) at the time when the first P-type TFT 1
The electric charge stored in the capacitor 410 is input to the gate electrode 01 and the gate electrode of the first N-type TFT 102. At this time, the first P-type TFT 10
The potential change due to the transfer of electric charge to the first gate electrode and the gate electrode of the first N-type TFT 102 (data signal (DAT
When A) is HIGH, the potential drops and the data signal (DAT)
When A) is LOW, the potential rise) occurs. However, since this potential change affects the ratio between the capacitance means 410 and the capacitance generated in the first P-type TFT 101 and the first N-type TFT 102, the capacitance means 410 If a sufficiently large capacitance can be obtained, the potential change can be suppressed. Therefore, the potential of the gate electrode of the first P-type TFT 101 and the first N-type TFT
The potential of the gate electrode of the FT102 is changed from the period t1 to the period t1.
The potential is almost the same as the potential of the data signal (DATA) when it changes to 2.

During this period, the potential of the data signal (DATA) is changed from HIGH to LOW (or from LOW to HIG).
H), the analog switch 420
Is off, so that the output of the output terminal (OUTPUT) is not affected.

The features of the present embodiment are that, similarly to the first embodiment, the TFT operates even at a threshold value which does not operate in the conventional example, and the response speed is improved. When the latch signal (LAT) is HIGH, the inverted latch signal (LAT)
B) When the potential of the data signal (DATA) is applied to the gate electrode of the first P-type TFT 101 and the gate electrode of the first N-type TFT 102 at LOW, since the data signal is cut off by the analog switch 420, Even if the data signal changes, the operation is not affected.

Further, the capacitance means 4 used in this embodiment
Reference numeral 10 denotes a material for forming a semiconductor layer, a material for forming a gate electrode, and a wiring material even when a capacitance means using a capacitance between a gate electrode and an input electrode of a TFT or between a gate electrode and an output electrode of a TFT is used. Any two of the above two materials
Capacitance means including an insulating film between materials may be used.

Further, in order to reduce the load on the entire data signal line, a capacitance means 4 such as a switch is provided between the input terminal of the analog switch 420 and the data signal (DATA) input section.
10 may be provided with a means for selecting a period for taking in a data signal (DATA).

[Fifth Embodiment] FIG. 7 shows a configuration example of a data reading circuit according to a fifth embodiment, which is different from the first to fourth embodiments. The data reading circuit of this embodiment is the same as that of the fourth embodiment.
A second P-type TFT 103, a second N-type TFT 104,
The positive and negative latch signals controlling the third N-type TFT 105, the third P-type TFT 106, and the analog switch 420 are further divided into those for TFT control (LAT1, LAT1B) and those for analog switch control (LAT2, LAT2B). Things. The analog switch 420 has a second latch signal (LAT2) and a second latch signal (LAT2).
Second inversion latch signal (LAT2B) which is an inversion signal of
Are input respectively.

Next, the operation will be described. Data signal (D
ATA), a first latch signal (LAT1), a first inverted latch signal (LAT1B), and a second latch signal (LAT2) having the same cycle and a different phase as the first latch signal.
And the second inverted latch signal (LAT2B) in FIG.
Input according to a timing chart as shown in FIG.
Here, the first latch signal (LAT1) is LOW, the second latch signal (LAT2) is HIGH,
A period in which the first inverted latch signal (LAT1B) is HIGH and the second inverted latch signal (LAT2B) is LOW is a period t1. Subsequently, the first latch signal (L
AT1) is LOW, and the second latch signal (LAT)
2) is LOW, and the first inverted latch signal (LAT1)
B) is HIGH, and the second inverted latch signal (LAT)
A period in which 2B) is HIGH is defined as a period t2. Subsequently, the first latch signal (LAT1) is HIGH and the second
LAT2 is HIGH, the first inverted latch signal (LAT1B) is LOW, and the second inverted latch signal (LAT2B) is LOW. Data signal (DATA) is HIGH, LO
W can take both. The operation in each period is described as follows.

In the period t1, the analog switch 42 is driven by the second latch signal (LAT2) having the HIGH potential and the second inverted latch signal (LAT2B) having the LOW potential.
0 is off. Further, the third N-type TFT 105 is turned off and the second P-type TFT 103 is turned on by the first latch signal (LAT1) having the LOW potential. Then, the potential of the gate electrode of the first P-type TFT 101 becomes VDD and the first P-type TFT 101 is turned off. At the same time, the third P-type TFT 106 is turned off by the first inverted latch signal (LAT1B) having the HIGH potential, and the second N-type TFT 106 is turned off.
The type TFT 104 is turned on. And the first N-type TFT
The potential of the gate electrode 102 becomes VSS, the first N-type TFT 102 is also turned off, and the data reading circuit enters a high impedance state. Therefore, the data signal (DA
TA) changes during the period t1, the output terminal (OUTP
UT) output is not affected.

In the period t2, the analog switch 42 is driven by the second latch signal (LAT2) having the LOW potential and the second inverted latch signal (LAT2B) having the HIGH potential.
0 turns on. As a result, charges corresponding to the potential of the data signal (DATA) are stored in the capacitance means 410. At this time, the second P-type TFT 103 is turned on by the first latch signal (LAT1) having the LOW potential, and the first P-type TF 103 is turned on.
The potential of the gate electrode of T101 becomes VDD, so that the first P-type TFT 101 is off. At the same time, the second N-type TFT 104 is also turned on by the first inverted latch signal (LAT1B) of the HIGH potential, and the first N-type TFT 104 is turned on.
The potential of the gate electrode of the type TFT 102 becomes VSS, so that the first N-type TFT 102 is also turned off. Therefore, the data reading circuit enters a high impedance state, and does not affect the output of the output terminal (OUTPUT) even if the data signal (DATA) changes during the period t2.

In the period t3, the analog switch 42 is driven by the second latch signal (LAT2) having the HIGH potential and the second inverted latch signal (LAT2B) having the LOW potential.
0 turns off. Further, the second P-type TFT 103 is turned off by the first latch signal (LAT1) at the HIGH potential, and the first inverted latch signal (LAT1) at the LOW potential.
B) turns off the second N-type TFT 104. Therefore, regardless of the change of the data signal (DATA) in the period t3, HIGH or LOW of the data signal (DATA) is determined based on the charge taken into the capacitor 410 in the period t2, and is output from the output terminal (OUTPUT). .

The feature of this embodiment is that the TFT operates even at a threshold value which does not operate in the conventional example.

[0098]

EXAMPLES Examples of the present invention will be described below.

(Embodiment 1) In this embodiment, a latch circuit using the data reading circuit used in the embodiment will be described.

FIG. 8 shows a circuit configuration of this embodiment. This circuit includes first, second, and third P-type TFTs 1301, 130
3, 1306 and first, second, and third N-type TFTs 130
It comprises a data read circuit 1300 comprising six transistors 2, 1304 and 1305, an inverter 1310 and a clocked inverter 1320. The gate electrode of the first P-type TFT 1301 has a second P-type TFT
Drain electrode 1303 and third N-type TFT 1305
One of the source electrode and the drain electrode of the first P-type TFT 1301 is connected to the source electrode of the first P-type TFT 1301, and a high potential power supply (VDD) is connected to the source electrode of the first P-type TFT 1301.
Is connected to the output terminal (OUTPUT) of the data reading circuit 1300. First N-type T
A second N-type TFT 130 is provided on the gate electrode of the FT 1302.
4 is connected to one of the drain electrode and the source electrode and the drain electrode of the third P-type TFT 1306. The source electrode of the first N-type TFT 1302 is connected to the low potential power supply (VSS). The output terminal (OUTPUT) of the data reading circuit 1300 is connected to the drain electrode of the type TFT 1302.

The latch signal (LAT) is input to the gate electrode of the second P-type TFT 1303 and the gate electrode of the third N-type TFT 1305, and the second P-type TFT 1303
3 is connected to a high potential power supply (VDD),
A data signal (DATA) is input to the other of the source electrode and the drain electrode of the third N-type TFT 1305. The gate electrode of the second N-type TFT 1304 and the third P
An inverted latch signal (L
ATB) is input, a low-potential power supply (VSS) is connected to the source electrode of the second N-type TFT 1304, and the third
A data signal (DATA) is input to the other of the source electrode and the drain electrode of the type TFT 1306.

The input terminal of the inverter 1310 is connected to the output terminal (OUTPUT) of the data reading circuit 1300, the input terminal of the clocked inverter 1320 is connected to the output terminal of the inverter 1310, and the output terminal of the clocked inverter 1320 is connected to the output terminal of the inverter 1310. Is a read circuit 1300
Output terminals are connected. The clocked inverter is controlled by a latch signal and an inverted latch signal (not shown).

For example, when the power supply potential of the circuit is VSS of 0 V,
VDD is 9 V, the LOW potential of the data signal (DATA) is 3 V,
It is assumed that the HIGH potential is 6 V and the circuit of FIG. 8 is to be operated. The latch signal (LAT) and the inverted latch signal (LATB) have a HIGH potential of 0 V and a LOW potential of 9 V, which are the same as the power supply potential, the threshold of all N-type TFTs is 2 V, and the threshold of P-type TFTs is 2 V. Is -2V. In the present embodiment, the read circuit 1300 uses the same circuit as that of the first embodiment. Therefore, the input of the data signal (DATA), the latch signal (LAT), and the inverted latch signal (LATB) is the same as that of the first embodiment. Perform according to 3 (A). Here, the period in which the latch signal (LAT) is HIGH and the inverted latch signal (LATB) is LOW is a period t1, the latch signal (LAT) is LOW, and the inverted latch signal (LAT) is
A period during which B) is HIGH is defined as a period t2. The data signal (DATA) can be either HIGH or LOW (provided that the data signal does not change during the period t1). The operation in each period is described as follows.

In the period t1, the data signal (DAT)
When A) is HIGH, the first N-type TFT 1302 turns on, but the first P-type TFT 1301 also turns on without operating in the off-region. However, at this time, the first P-type T
The gates of the FT 1301 and the first N-type TFT 1302
The difference between the source voltage and the threshold is -1V and 4V, respectively.
It becomes. Normally, the current capability of the P-type TFT and the current capability of the N-type TFT, which are determined from the mobility and the size of the TFT, are designed to be substantially equal, so that the absolute value of the difference between the gate-source voltage and the threshold value is large. First N-type TFT 13
02 has a lower effective resistance than the first P-type TFT 1301, and as a result, a LOW potential is output from the output terminal (OUTPUT).

On the other hand, when the data signal (DATA) is LOW, the first P-type TFT 1301 turns on, but the first N-type TFT 1302 also turns on without operating in the off region. However, the difference between the gate-source voltage and the threshold of the first P-type TFT 1301 and the first N-type TFT 1302 at this time is -4V and 1V, respectively. Therefore,
The first P-type TFT 1301 having a large absolute value of the difference between the gate-source voltage and the threshold value is replaced with the first N-type TFT 1302
The effective resistance is lower than that of the output terminal (OU
TPUT) outputs a HIGH potential.

At this time, clocked inverter 1320 is in a high impedance state and does not compete with the output of read circuit 1300.

In the period t2, the third N-type TFT 1305 is turned off and the second P-type TFT 1303 is turned on by the latch signal (LAT) of the LOW potential. Therefore, the potential of the gate electrode of the first P-type TFT 1301 becomes VD
As D, the first P-type TFT 1301 is turned off. At the same time, the third P-type TFT 1306 is turned off and the second N-type TFT 1304 is turned on by the inverted latch signal (LATB) having the HIGH potential. Therefore, the first N
The potential of the gate electrode of the TFT 1302 becomes VSS,
The first N-type TFT 1302 is also turned off, and the data reading circuit 1300 enters a high impedance state. The clocked inverter 1320 functions as an inverter, enters a state of forming a loop with the inverter 1310, and holds the video signal captured when the latch signal (LAT) is HIGH. Therefore, the data signal (DATA) is applied during the period t.
Even if it changes within the period of 2, the output of the output terminal (OUTPUT) is not affected.

The data reading circuit 1300 is not limited to this embodiment, and all the circuits described in the first to fifth embodiments can be used. In this embodiment, the inverter 1310 and the clocked inverter 1320 are used for holding data, but two inverters may be used instead.
A capacitance means or the like may be used.

(Embodiment 2) In this embodiment, an example in which the latch circuit used in Embodiment 1 is used as a source driver will be described. The source driver takes in an input data signal and outputs an analog-converted signal to a source line corresponding to a pixel to be driven.

FIG. 9 shows a configuration diagram of the source driver. The source driver includes a shift register 1200, a latch circuit 1201, and a DAC 1202. Normal,
In addition to the source driver, there is a level shifter required to amplify the data signal when operating the latch circuit. However, the present invention makes this unnecessary. Since the actual source driver requires source lines for the number of pixel rows,
In the source driver portion of the display device, the circuits in FIG. 9 are arranged for the number of rows.

The operation will be described. Shift register 1
The latch signal (LAT) and the inverted latch signal (LATB) sent from 200 are input to the latch circuit 1201. The latch circuit 1201 has a data signal (DATA),
The latch signal (LAT), the inverted latch signal (LAT), the sampling signal (SAMP) for controlling the clocked inverter in the latch circuit, and the inverted sampling signal (SA)
MPB), holds and outputs the input data signal (DATA) and sends it to the DAC. In the DAC, a plurality of power supply gradation lines (VO) are output in accordance with outputs from a plurality of latch circuits.
L), or select two power supply gradation lines, select a voltage within the voltage range, and select a source line (S
source).

As the latch circuit, the circuit used in Embodiment 1 may be used. The shift register includes a plurality of inverters and a clocked inverter, and shifts an input signal by one cycle or a half cycle and outputs the shifted signal. A known shift register can be used. The DAC converts a digital signal into an analog signal. There are various types of DACs depending on the structure, but a known signal may be used as in the case of the shift register. Further, an analog buffer may be provided after the DAC. Further, the sampling signal and the inverted sampling signal may use a latch signal and an inverted latch signal.

Further, in this embodiment, an example has been described in which a digitally input signal is output as an analog signal. However, it is of course possible to digitally output a digitally input signal.

(Embodiment 3) As an electronic apparatus using the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproducing apparatus (car audio, audio component, etc.), a notebook personal computer Computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), and image reproducing apparatuses equipped with recording media (specifically, Digital Versatile Discs)
(A device provided with a display capable of reproducing a recording medium such as (DVD) and displaying an image thereof). Specific examples of such electronic devices are shown in FIGS.

FIG. 10A shows a liquid crystal display or an OLED display.
402, a display unit 1403, and the like.
The invention can be applied to a driver circuit of a display device having the display portion 1403.

FIG. 10B shows a video camera, which includes a main body 1411, a display portion 1412, a voice input 1413, an operation switch 1414, an operation switch 1415, and a battery 1.
416, an image receiving unit 1417, and the like.
The invention can be applied to a driver circuit of a display device having the display portion 1417.

FIG. 10C shows a notebook personal computer, which includes a main body 1421, a housing 1422, a display portion 1423, a keyboard 1424, and the like. The invention can be applied to a driver circuit of a display device having the display portion 1423.

FIG. 10D shows a portable information terminal, which includes a main body 1431, a display portion 1432, operation buttons 1433, an external interface 1434, and the like. The invention can be applied to a driver circuit of a display device having the display portion 1432.

FIG. 10E shows a sound reproducing device, specifically, an audio device for a vehicle, which comprises a main body 1441, a display portion 1442, operation switches 1443 and 1444, and the like. The present invention can be applied to a driver circuit of a display device having the display portion 1442. Also, this time, an in-vehicle audio device has been described as an example, but it may be used for a portable or home audio device.

FIG. 10F shows a digital camera, which includes a main body 1451, a display portion (A) 1452, an eyepiece portion 1453,
The mobile phone includes an operation switch 1454, a display portion (B) 1455, a battery 1456, and the like. The present invention can be applied to a driver circuit of a display device including the display portion (A) 1452 and the display portion (B) 1455.

FIG. 10G shows a mobile phone, and the main body 14
61, audio output unit 1462, audio input unit 1463, display unit 1464, operation switch 1465, antenna 1466
It is constituted by such as. The present invention relates to a display unit 1464.
It can be applied to a driving circuit of a display device having

A display device used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate. Thereby, the weight can be further reduced.

It should be noted that the example shown in this embodiment is merely an example, and the present invention is not limited to these applications.

This embodiment is similar to the first to fifth embodiments and the first embodiment.
2 can be freely combined with each other.

According to the present invention, a level shifter becomes unnecessary, and the number of level shift ICs and power supply ICs outside the panel is reduced, so that the number of parts and power consumption can be reduced. In the panel, the layout area can be reduced, the yield can be improved by downsizing, the power consumption can be reduced, and operation at a high frequency is possible.

According to the present invention, a double-gate TFT (two TFTs connected in series) can be replaced with a single-gate TFT. As a result, it is not necessary to set the gate width of the TFT large, and the size of the TFT can be reduced, so that high integration can be achieved. Further, the load on an element having the gate (gate capacitance) as a load is reduced, and the load is reduced as a whole, so that high-frequency operation is possible. Further, the present invention is resistant to variations in the threshold value of the TFT, and can operate accurately using the signal as it is even if the amplitude of the signal is smaller than the power supply voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram of a latch circuit according to a conventional example.

FIG. 3 is a diagram showing a timing chart of an operation of a latch circuit.

FIG. 4 is a diagram showing an embodiment of the present invention.

FIG. 5 is a diagram showing an embodiment of the present invention.

FIG. 6 is a diagram showing an embodiment of the present invention.

FIG. 7 is a diagram showing an embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a latch circuit according to an embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a source driver according to an embodiment of the present invention.

FIG. 10 illustrates an example of an electronic device to which the present invention can be applied.

FIG. 11 is a diagram showing an outline of the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 H03K 3/037 B H03K 3/037 3/356 Z

Claims (23)

[Claims] 1. An electric circuit comprising an N-type transistor and a first P-type transistor and a second P-type transistor connected in series, wherein a gate electrode of the N-type transistor and a gate electrode of the first P-type transistor are mutually connected. A drain electrode of the N-type transistor and a drain electrode of the first P-type transistor are connected to a gate electrode of the second P-type transistor; a source electrode of the first P-type transistor is electrically connected to a power supply; An electric circuit, wherein a signal is input to a source electrode of an N-type transistor. 2. An electric circuit according to claim 1, further comprising an analog switch in place of said N-type transistor. 3. An electric circuit comprising a first N-type transistor and a P-type transistor and a second N-type transistor connected in series, wherein a gate electrode of the first N-type transistor and a gate electrode of the P-type transistor are mutually connected. A drain electrode of the first N-type transistor and a drain electrode of the P-type transistor are connected to a gate electrode of the second N-type transistor; a source electrode of the first N-type transistor is electrically connected to a power supply; An electric circuit, wherein a signal is input to a source electrode of a P-type transistor. 4. The electric circuit according to claim 3, further comprising an analog switch instead of said P-type transistor. 5. The electric circuit according to claim 1, wherein the amplitude of the signal is smaller than a power supply voltage. 6. A latch circuit using the electric circuit according to claim 1. 7. A first N-type transistor and a first P-type transistor connected in series, and an input of a data signal according to an input latch signal.
A first compensating circuit for selecting whether the power supply potential is input or not, and outputting the selected input to the gate electrode of the first P-type transistor; and a data signal input or a second power supply potential based on the input inverted latch signal. A second input for outputting the selected input to the gate electrode of the first N-type transistor.
A latch circuit having a compensation circuit, wherein the data signal is inputted from the same signal line, and an output of the latch circuit is taken out from a connection portion between the first N-type transistor and the first P-type transistor. A latch circuit characterized by the above-mentioned. 8. A circuit in which a first P-type transistor whose source electrode is connected to a first power supply and a first N-type transistor whose source electrode is connected to a second power supply are connected in series. A first compensating circuit including a second N-type transistor and a second P-type transistor connected to a gate electrode and connected in series; and a third N-type connected to the gate electrodes and connected in series to each other. A latch circuit including a transistor and a second compensation circuit including a third P-type transistor, wherein a source electrode of the second N-type transistor and a source electrode of the third P-type transistor are connected to a same data line; The source electrode of the third N-type transistor is connected to the second power source, and the source electrode of the third N-type transistor is connected to the second power source. The drain electrodes of the second N-type transistor and the second P-type transistor are connected to the gate electrode of the first P-type transistor, and the drain electrodes of the third N-type transistor and the third P-type transistor are connected to the first N-type transistor. A latch circuit connected to a gate electrode, wherein an output is taken from a drain electrode of the first N-type transistor or the first P-type transistor. 9. The latch circuit according to claim 6, wherein the transistor has a double gate structure. 10. The latch circuit according to claim 6, wherein the transistor has a multi-gate structure. 11. A display device using the latch circuit according to claim 6. 12. An electronic apparatus using the display device according to claim 11. 13. An electric circuit device comprising an N-type transistor and a first P-type transistor and a second P-type transistor connected in series, wherein a gate electrode of said N-type transistor and a gate electrode of said first P-type transistor are A drain electrode of the N-type transistor and a drain electrode of the first P-type transistor are connected to a gate electrode of the second P-type transistor; a source electrode of the first P-type transistor is electrically connected to a power supply; An electric circuit device, wherein a signal is input to a source electrode of the N-type transistor. 14. The electric circuit device according to claim 13, further comprising an analog switch instead of said N-type transistor. 15. An electric circuit device having a first N-type transistor and a P-type transistor connected in series and a second N-type transistor, wherein a gate electrode of the first N-type transistor and a gate electrode of the P-type transistor are A drain electrode of the first N-type transistor and a drain electrode of the P-type transistor are connected to a gate electrode of the second N-type transistor; a source electrode of the first N-type transistor is electrically connected to a power supply; An electric circuit device, wherein a signal is input to a source electrode of the P-type transistor. 16. An electric circuit device according to claim 15, further comprising an analog switch instead of said P-type transistor. 17. The electric circuit device according to claim 13, wherein the amplitude of the signal is smaller than a power supply voltage. 18. A first N-type transistor and a first P-type transistor connected in series, and whether a data signal is input or not according to an input latch signal.
A first compensating circuit for selecting whether the power supply potential is input or not, and outputting the selected input to the gate electrode of the first P-type transistor; and a data signal input or a second power supply potential based on the input inverted latch signal. A second input for outputting the selected input to the gate electrode of the first N-type transistor.
An electric circuit device having a compensation circuit, wherein the data signal is inputted from the same signal line, and an output of the latch circuit is the first N-type transistor and the first P-type transistor.
An electric circuit device, which is taken out from a connection portion of a type transistor. 19. A circuit in which a first P-type transistor whose source electrode is connected to a first power supply and a first N-type transistor whose source electrode is connected to a second power supply are connected in series. A first compensation circuit having a gate electrode connected thereto and comprising a second N-type transistor and a second P-type transistor connected in series; and a third N-type transistor having their gate electrodes connected and connected in series A device having a latch circuit having a transistor and a second compensation circuit including a third P-type transistor, wherein the source electrodes of the second N-type transistor and the third P-type transistor are connected to the same data line; A source electrode of the 2P-type transistor is connected to the first power supply, and a source electrode of the third N-type transistor is connected to the second power supply. The drain electrodes of the second N-type transistor and the second P-type transistor are connected to the gate electrode of the first P-type transistor, and the drain electrodes of the third N-type transistor and the third P-type transistor are connected to the second An electric circuit device which is connected to a gate electrode of a 1N-type transistor and whose output is taken out from a drain electrode of the first N-type transistor or the first P-type transistor. 20. The electric circuit device according to claim 17, wherein the transistor has a double gate structure. 21. The electric circuit device according to claim 17, wherein the transistor has a multi-gate structure. 22. A display device using the electric circuit device according to claim 13. 23. An electronic apparatus using the display device according to claim 22.