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JP2003347337A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JP2003347337A
JP2003347337A JP2002154236A JP2002154236A JP2003347337A JP 2003347337 A JP2003347337 A JP 2003347337A JP 2002154236 A JP2002154236 A JP 2002154236A JP 2002154236 A JP2002154236 A JP 2002154236A JP 2003347337 A JP2003347337 A JP 2003347337A
Authority
JP
Japan
Prior art keywords
electrode pad
gold layer
semiconductor device
bump
probe needle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002154236A
Other languages
Japanese (ja)
Inventor
Nobuaki Takahashi
信明 高橋
Naoharu Senba
直治 仙波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2002154236A priority Critical patent/JP2003347337A/en
Publication of JP2003347337A publication Critical patent/JP2003347337A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H01L2224/03921Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step by repairing the bonding area damaged by the probing step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To accurately measure electric characteristics of a semiconductor device by a probe needle and reliably form a bump electrode on the semiconductor device after measuring the electric characteristics. <P>SOLUTION: An electrode pad 2 is formed on a semiconductor substrate 1. The probe needle is contacted with a gold layer 5 formed on the electrode pad 2 to measure the electric characteristics of the semiconductor device. Thereafter, a bump electrode such as a gold stud bump 81 or the like is formed on the gold layer 5 to which the probe needle 6 is contacted. When a solder ball is used as a bump electrode, a barrier metal and a gold layer are sequentially formed on the electrode pad, and thereafter, the probe needle is contacted with the gold layer to measure the electric characteristics, and then, the solder ball is formed on the gold layer. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体基板の電極パ
ッド上に金属バンプを形成した半導体装置、いわゆる、
フリップチップに関し、更に詳しくは、フリップチップ
の構造及びその電気的特性の測定と金属バンプの形成方
法に関する。
The present invention relates to a semiconductor device having metal bumps formed on electrode pads of a semiconductor substrate, so-called
More particularly, the present invention relates to a flip chip structure, measurement of electrical characteristics thereof, and a method of forming metal bumps.

【0002】[0002]

【従来の技術】半導体装置は、半導体基板にトランジス
タや抵抗等の回路素子を金属配線層で接続し所望の回路
機能を実現したものである。その半導体装置へ電源電圧
及び各種信号を供給するため、半導体基板には電極パッ
ドが形成される。この電極パッド上に金属バンプを形成
した半導体装置は、一般的にフリップチップと呼ばれ
る。フリップチップにおける金属バンプは、フリップチ
ップとそれが実装されるプリント基板とを電気的、か
つ、機械的に接続するものである。
2. Description of the Related Art A semiconductor device realizes a desired circuit function by connecting circuit elements such as transistors and resistors to a semiconductor substrate through a metal wiring layer. In order to supply a power supply voltage and various signals to the semiconductor device, an electrode pad is formed on the semiconductor substrate. A semiconductor device in which metal bumps are formed on the electrode pads is generally called a flip chip. The metal bumps in the flip chip electrically and mechanically connect the flip chip and the printed circuit board on which the flip chip is mounted.

【0003】フリップチップをプリント基板に実装する
前には、当然のことながらその回路機能の電気的特性試
験を行う必要がある。係る試験は、金属バンプにプロー
ブ針を接触させて行われている。しかしながら、プロー
ブ針が接触した金属バンプの表面には、プローブ針の針
跡、すなわち、窪みが発生する。この金属バンプ表面の
窪みはフリップチップをプリント基板に実装する際、両
者の接続の信頼性を低下させる原因となる。
Before the flip chip is mounted on the printed circuit board, it is a matter of course that an electrical characteristic test of the circuit function must be performed. Such a test is performed by bringing a probe needle into contact with a metal bump. However, a needle mark of the probe needle, that is, a depression is generated on the surface of the metal bump contacted with the probe needle. When the flip chip is mounted on the printed board, the depression on the surface of the metal bump causes a reduction in the reliability of the connection between the two.

【0004】また、金属バンプに接触したプローブ針に
は金属バンプ屑が付着するため、プローブ針の洗浄が必
要となる。この金属バンプ屑のプローブ針への付着は、
金属バンプが半田ボールの場合特に顕著となる。
Further, since metal bump debris adheres to the probe needle in contact with the metal bump, it is necessary to clean the probe needle. The adhesion of this metal bump scrap to the probe needle
This is particularly noticeable when the metal bumps are solder balls.

【0005】そこで、電極パッドにプローブ針を接触さ
せて電気的特性試験を実施し、その後、金属バンプを形
成することが考えられる。この方法では、上述の電極バ
ンプ表面の窪みやプローブ針への金属バンプ屑付着とい
う問題が解消される。しかしながら、今度は電極パッド
にプローブ針の接触による針跡が発生し、この針跡が金
属バンプとバンプ電極との接続の信頼性を低下させてし
まう。
In view of this, it is conceivable that a probe needle is brought into contact with the electrode pad to conduct an electrical characteristic test, and then a metal bump is formed. In this method, the above-described problem of the depressions on the surface of the electrode bumps and adhesion of metal bump debris to the probe needle is solved. However, this time, a needle trace is generated on the electrode pad due to the contact of the probe needle, and this needle trace lowers the reliability of the connection between the metal bump and the bump electrode.

【0006】係る問題をも解決するための手法が特開2
001−93933号公報に開示されている。係る手法
は、半導体素子の電極パッドを導電ペーストで覆って当
該ペーストを硬化させ、かくして形成された導電ペース
トにプローブ針を接触させてテストを行い、しかる後
に、半田バンプを形成するものである。
A technique for solving such a problem is disclosed in JP-A-2
001-93933. According to such a technique, the electrode pad of the semiconductor element is covered with a conductive paste, the paste is cured, a probe needle is brought into contact with the conductive paste thus formed, a test is performed, and then solder bumps are formed.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この技
術にはいくつかの課題がある。まず第1は、導電ペース
トの導電率に起因するものである。電気的特性の試験の
際、プローブ針は導電ペーストを介してアルミパッドと
電気的に接続される。導電ペーストはその成分として樹
脂を含むため導電率が金属層に比べて小さく、この結
果、プローブ針とアルミパッドとの間には、電気的抵抗
が挿入された状態と等価である。この電気的抵抗が測定
値に誤差を発生させ、正確な特性評価を期待できない。
また、導電ペーストの電気的抵抗の問題は、半田バンプ
を形成してフリップチップとしてプリント基板に実装し
た後でも懸念される。
However, this technique has several problems. The first is due to the conductivity of the conductive paste. When testing the electrical characteristics, the probe needle is electrically connected to the aluminum pad via a conductive paste. Since the conductive paste contains a resin as its component, the conductivity is smaller than that of the metal layer. As a result, this is equivalent to a state in which an electrical resistance is inserted between the probe needle and the aluminum pad. This electrical resistance causes an error in the measured value, and accurate characteristic evaluation cannot be expected.
Further, the problem of electrical resistance of the conductive paste is a concern even after solder bumps are formed and mounted on a printed circuit board as a flip chip.

【0008】課題の第2は、導電ペーストの半田濡れ性
に関するものである。金属バンプとして半田ボールを採
用する場合、導電ペーストの半田濡れ性の問題から半田
バンプと導電ペースト間の接続の信頼性低下が問題とな
る。また、両者の電気的接続抵抗も増大してしまう。
The second problem relates to the solder wettability of the conductive paste. When solder balls are employed as the metal bumps, the reliability of the connection between the solder bumps and the conductive paste decreases due to the problem of solder wettability of the conductive paste. In addition, the electrical connection resistance between the two increases.

【0009】本発明の目的は、プローブ針によるテスト
の実行の際に起こり得る問題を解決し得るバンプ電極を
有する半導体装置の製造方法を提供することにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device having a bump electrode that can solve problems that may occur during the execution of a test with a probe needle.

【0010】[0010]

【発明を解決するための手段】本発明による製造方法
は、半導体基板に形成された電極パッド上に金層を形成
する工程と、その金層にプローブ針を接触させる工程
と、そのプローブ針を接触させた金層上に金属バンプを
形成する工程とを有することを特徴とする。
A manufacturing method according to the present invention comprises a step of forming a gold layer on an electrode pad formed on a semiconductor substrate, a step of bringing a probe needle into contact with the gold layer, And a step of forming metal bumps on the contacted gold layer.

【0011】すなわち、本発明は、半導体素子の電極パ
ッドを金層で覆い、前記金層にプローブ針を接触させて
テストを行い、しかる後にバンプ電極を形成することを
特徴としている。
That is, the present invention is characterized in that the electrode pad of the semiconductor element is covered with a gold layer, a probe needle is brought into contact with the gold layer, a test is performed, and then a bump electrode is formed.

【0012】金の電気抵抗は極めて小さく、しかも、バ
ンプ電極として専ら用いられている半田バンプや金バン
プとの接続性や濡れ性においても非常に優れている。さ
らには、金層の表面には実質的な自然酸化膜は形成され
ない。これは、プローブ針を金層に接触させる際にプロ
ーブ針に加える圧力を小さくしても、両者の接触抵抗を
十分に小さく保つことを意味している。従って、金層表
面に残るプローブ針跡が非常に小さくなり、バンプ電極
との接続性や濡れ性が優れていることからも、バンプ電
極との間には電気的、機械的に強固な接続が得られる。
勿論、テストは、バンプ電極への窪みを発生することな
く実行でき、また、プローブ針への加圧力を小さくでき
るので、プローブ針が金層を突き破って電極パッドに達
しこれを傷つけることもない。
The electrical resistance of gold is extremely small, and it is very excellent in the connectivity and wettability with solder bumps and gold bumps exclusively used as bump electrodes. Furthermore, a substantial natural oxide film is not formed on the surface of the gold layer. This means that even if the pressure applied to the probe needle when the probe needle is brought into contact with the gold layer is reduced, the contact resistance between the two is kept sufficiently small. Therefore, the probe needle trace remaining on the gold layer surface is very small, and the electrical connection and the wettability with the bump electrode are excellent. can get.
Of course, the test can be performed without generating a depression in the bump electrode, and the pressure applied to the probe needle can be reduced, so that the probe needle does not break through the gold layer and reach the electrode pad to damage it.

【0013】金属バンプとして半田バンプを形成する場
合、電極パッドと金層との間にバリアメタルを形成する
こと、すなわち、電極パッドをバリア層を介して金層で
覆うことが好ましい。このバリア層は半田バンプの半田
成分の電極パッドへの拡散を防止する。バリアメタルと
してニッケル又は銅を主成分とする金属層が好適であ
る。勿論、金のバンプ電極でも構わない。
When forming a solder bump as the metal bump, it is preferable to form a barrier metal between the electrode pad and the gold layer, that is, to cover the electrode pad with the gold layer via the barrier layer. This barrier layer prevents diffusion of solder components of the solder bumps to the electrode pads. A metal layer mainly composed of nickel or copper is suitable as the barrier metal. Of course, gold bump electrodes may be used.

【0014】電極パッドを金層で直接覆った場合は、金
属バンプとして金ワイヤーによるスタッドバンプを形成
することが好ましい。
When the electrode pad is directly covered with a gold layer, stud bumps made of gold wires are preferably formed as metal bumps.

【0015】さらに、金属バンプを形成する前に、平坦
な先端形状を有する押圧手段により金層表面を押圧する
工程を追加してもよい。
Further, a step of pressing the gold layer surface by pressing means having a flat tip shape may be added before forming the metal bumps.

【0016】[0016]

【発明の実施の形態】図1は、本発明の第1の実施形態
例に係わる金属バンプを有する半導体装置の製造工程を
示す。回路素子が形成された半導体基板1上にアルミニ
ウム、アルミニウムを主成分とする合金,銅,又は銅を
主成分とする合金からなる電極パッド2を形成する。そ
の後、半導体素子の表面にシリコン酸化膜等の絶縁膜か
らなる表面保護膜3を成膜し、電極パッド2を露出させ
る開口部4を表面保護膜3に形成する。この開口部4を
金層5で充填する。本実施形態例では、金層5を無電解
メッキ法で電極パッド2上に、その表面が表面保護膜3
の表面と略同一の高さとなるように形成した。ここまで
の製造工程を経て、図1(a)の断面形状を有する電極
パッド部が形成される。
FIG. 1 shows a manufacturing process of a semiconductor device having metal bumps according to a first embodiment of the present invention. An electrode pad 2 made of aluminum, an alloy containing aluminum as a main component, copper, or an alloy containing copper as a main component is formed on a semiconductor substrate 1 on which circuit elements are formed. Thereafter, a surface protective film 3 made of an insulating film such as a silicon oxide film is formed on the surface of the semiconductor element, and an opening 4 exposing the electrode pad 2 is formed in the surface protective film 3. The opening 4 is filled with a gold layer 5. In this embodiment, the gold layer 5 is formed on the electrode pad 2 by electroless plating, and the surface thereof is the surface protective film 3.
It was formed so as to be almost the same height as the surface of. Through the manufacturing steps so far, the electrode pad portion having the cross-sectional shape of FIG.

【0017】電極パッド2上に金層5を形成後、金層5
に,例えば,タングステン(W)を材質とするプローブ
針6を接触させる。この結果、プローブ針6は、金層5
を介して電極パッド2と電気的に接続することになる。
金の導電率は導電ペーストの導電率に比べ桁違いに大き
いため、プローブ針6と電極パッド2間に存在する金層
5の電気抵抗は全く問題とならず、精度よく半導体装置
の電気的特性を測定することが可能となる。
After the gold layer 5 is formed on the electrode pad 2, the gold layer 5
In addition, for example, a probe needle 6 made of tungsten (W) is brought into contact. As a result, the probe needle 6 has the gold layer 5
It is electrically connected to the electrode pad 2 via
Since the electrical conductivity of gold is orders of magnitude greater than that of the conductive paste, the electrical resistance of the gold layer 5 existing between the probe needle 6 and the electrode pad 2 is not a problem at all, and the electrical characteristics of the semiconductor device are accurate. Can be measured.

【0018】図1(b)は、半導体装置の電気的測定を
完了後、プローブ針6を金層5から離した状態の電極パ
ッド部の断面図である。金層5の表面には、プローブ針
の接触による針跡7が形成される。なお、図面では針跡
7の大きさを誇張して描いているが、実際は、金層5の
表面には実質的な自然酸化膜は形成されないので、プロ
ーブ針6の加圧力は小さくしても金層5と針6との接触
抵抗を小さくでき、その結果、この針跡7はその後のバ
ンプ電極形成に何ら支障を与えず、無論、電極パッド2
に達することはない。
FIG. 1B is a sectional view of the electrode pad portion in a state where the probe needle 6 is separated from the gold layer 5 after the electrical measurement of the semiconductor device is completed. On the surface of the gold layer 5, a needle mark 7 is formed by contact with the probe needle. In the drawing, the size of the needle trace 7 is exaggerated, but in reality, a substantial natural oxide film is not formed on the surface of the gold layer 5, so even if the applied pressure of the probe needle 6 is reduced. The contact resistance between the gold layer 5 and the needle 6 can be reduced. As a result, the needle trace 7 does not interfere with the subsequent bump electrode formation, and of course, the electrode pad 2
Never reach.

【0019】プローブ針の加圧力に関してより説明する
と、電極パッドにプローブ針を接触させる場合、通常
は、プローブ針の先端部が電極パッドを構成する金属層
の内部に達するまで、換言すれば、電極パッドの表面に
針跡がつく程度にプローブ針を電極パッドに押し当て
る。これは、電極パッドとなる金属層の表面に形成され
る酸化膜を突き破り、プローブ針と電極パッドの接触抵
抗を下げるためである。
The pressure applied to the probe needle will be described in more detail. When the probe needle is brought into contact with the electrode pad, normally, until the tip of the probe needle reaches the inside of the metal layer constituting the electrode pad, in other words, the electrode Press the probe needle against the electrode pad to the extent that the needle mark is on the surface of the pad. This is for breaking through the oxide film formed on the surface of the metal layer to be the electrode pad and lowering the contact resistance between the probe needle and the electrode pad.

【0020】特に、電極パッドがアルミニウムの場合、
その表面に形成されるアルミニウムの酸化膜はアルミニ
ウムに比べ硬度が高い。そのため、アルミニウムの電極
パッドにプローブ針を接触させるのに必要な圧力以上
で、プローブ針を電極パッドに接触させる必要がある。
この結果、一旦、プローブ針の先端が電極パッドを構成
するアルミニウム表面の酸化膜を突き破ると、電極パッ
ドに形成させる針跡は電極パッドが形成されている半導
体基板を露出させる程度まで広く且つ深くなる場合があ
る。このような深い針跡は、電極パッドの信頼性の低下
をもたらす。
In particular, when the electrode pad is aluminum,
The aluminum oxide film formed on the surface has higher hardness than aluminum. Therefore, it is necessary to bring the probe needle into contact with the electrode pad at a pressure higher than that required to bring the probe needle into contact with the aluminum electrode pad.
As a result, once the tip of the probe needle breaks through the oxide film on the aluminum surface constituting the electrode pad, the needle trace formed on the electrode pad becomes wide and deep enough to expose the semiconductor substrate on which the electrode pad is formed. There is a case. Such a deep needle trace results in a decrease in the reliability of the electrode pad.

【0021】本発明の第1の実施形態例に係わる金属バ
ンプを有する半導体装置の形成方法では、電極パッド2
上に金層5を形成している。金はその表面に酸化膜を形
成せず、また、プローブ針6に比べてその硬度は低いた
め、金層5とプローブ針6とを接触させるための圧力は
必要最小限でよい。この結果、電極パッド2へのダメー
ジを与えることなくプローブ針6を接触させることがで
きる。
In the method of forming a semiconductor device having metal bumps according to the first embodiment of the present invention, the electrode pad 2
A gold layer 5 is formed thereon. Since gold does not form an oxide film on its surface and its hardness is lower than that of the probe needle 6, the pressure required for bringing the gold layer 5 and the probe needle 6 into contact with each other is minimal. As a result, the probe needle 6 can be brought into contact without damaging the electrode pad 2.

【0022】図1(c)は、半導体装置の電気的特性の
測定後、半導体基板1に金スタッドバンプ81を形成し
た電極パッド部の断面図である。金スタッドバンプ81
は公知の技術によるものであり、金ワイヤーをボンディ
ングツールにより(図示せず)金層5にボンディング
し、そのワイヤーヘッド部のみを金属バンプとして残し
たものである。金スタッドバンプ81と電極パッド2間
は金層5を介して接続されているため、両者間の電気的
抵抗値が極めて小さいことは言うまでもない。
FIG. 1C is a cross-sectional view of an electrode pad portion in which a gold stud bump 81 is formed on the semiconductor substrate 1 after measuring the electrical characteristics of the semiconductor device. Gold stud bump 81
Is a known technique, in which a gold wire is bonded to the gold layer 5 (not shown) with a bonding tool, and only the wire head portion is left as a metal bump. Since the gold stud bump 81 and the electrode pad 2 are connected via the gold layer 5, it goes without saying that the electrical resistance value between them is extremely small.

【0023】本実施例では、電極パッド2上に2〜3u
mの膜厚を有する金層5を形成するため、半田バンプ以
外の金属で金属バンプを形成した。厚い膜厚の金層に形
成した半田バンプは、金層との界面がもろくなり機械的
強度が保てないからである。
In this embodiment, 2 to 3 u are formed on the electrode pad 2.
In order to form the gold layer 5 having a film thickness of m, metal bumps were formed with a metal other than the solder bumps. This is because the solder bump formed on the thick gold layer has a brittle interface with the gold layer and cannot maintain the mechanical strength.

【0024】図2は、本発明の第2の実施形態例に係わ
る金属バンプを有する半導体装置の製造工程を示す。本
実施形態は、特に、バンプ電極として半田バンプを用い
る場合に好適な例を示したものであるが、金バンプでも
同様に適用できる。なお、図1と同一の構成には同じ番
号を付けている。
FIG. 2 shows a manufacturing process of a semiconductor device having metal bumps according to the second embodiment of the present invention. This embodiment particularly shows an example suitable for the case where solder bumps are used as bump electrodes, but gold bumps can be similarly applied. In addition, the same number is attached | subjected to the structure same as FIG.

【0025】図2(a)は、半導体装置の電気的特性を
測定する直前の電極バンプ部の断面構造である。表面保
護膜3に電極パッド2を露出させる開口部4を形成し、
その開口部4をバリアメタル層51と金層52の2層構
造で充填する。バリアメタル層51としては、ニッケル
(Ni)若しくは銅(Cu)、又はそれらを主成分とす
る金属層が好適である。本実施形態例では無電解メッキ
法によりニッケルを2〜3umの膜厚で形成した。その
バリアメタル層51上に金層51を無電解メッキ法で
0.01〜0.1umの膜厚で形成した。
FIG. 2A shows the cross-sectional structure of the electrode bump portion immediately before measuring the electrical characteristics of the semiconductor device. Forming an opening 4 for exposing the electrode pad 2 in the surface protective film 3;
The opening 4 is filled with a two-layer structure of a barrier metal layer 51 and a gold layer 52. As the barrier metal layer 51, nickel (Ni) or copper (Cu), or a metal layer containing them as a main component is suitable. In this embodiment, nickel is formed with a thickness of 2 to 3 μm by electroless plating. A gold layer 51 was formed on the barrier metal layer 51 to a thickness of 0.01 to 0.1 μm by electroless plating.

【0026】半田バンプの形成は、鉛(Pb)と錫(S
n)を主成分とする半田ボール、又は、電解若しくは無
電解メッキ法による半田メッキ層を電極パッド2上に形
成後、半導体装置を加熱して電極パッド2と接合するこ
とにより行う。電極パッドがアルミニウム若しくはそれ
を主成分とする合金からなる場合,鉛と錫はアルミニウ
ムと合金を形成しないため、半田バンプは電極パッドか
ら容易に剥離する。この問題を解決するため、鉛と錫が
アルミニウムの電極パッドに到達することを防止するバ
リアメタル層51を金層52と電極パッド2との間に介
在させている。
Solder bumps are formed by using lead (Pb) and tin (S
After forming a solder ball having n) as a main component or a solder plating layer by electrolytic or electroless plating on the electrode pad 2, the semiconductor device is heated and bonded to the electrode pad 2. When the electrode pad is made of aluminum or an alloy mainly composed of aluminum, lead and tin do not form an alloy with aluminum, so that the solder bump is easily peeled off from the electrode pad. In order to solve this problem, a barrier metal layer 51 that prevents lead and tin from reaching the aluminum electrode pad is interposed between the gold layer 52 and the electrode pad 2.

【0027】また、半田バンプはその下層との良好な濡
れを必要とする。金層52はこの点においても極めて良
好な特性を示す。
Also, the solder bumps require good wetting with the lower layer. The gold layer 52 also exhibits very good characteristics in this respect.

【0028】図2(b)は、電極パッド2上にバリアメ
タル層51及び金層52を順次形成後、その表面をプロ
ーブ針7で接触した後の断面形状を示す。第1の実施形
態例と同様に、本実施形態でもプローブ針7は金層52
の表面と接触するため、必要最小限の接触圧力で行うこ
とができる。
FIG. 2B shows a cross-sectional shape after the barrier metal layer 51 and the gold layer 52 are sequentially formed on the electrode pad 2 and the surfaces thereof are contacted by the probe needle 7. Similar to the first embodiment, in this embodiment, the probe needle 7 has the gold layer 52.
Can be performed with the minimum necessary contact pressure.

【0029】本実施形態では、金層52の下には、その
金より硬度の高いニッケルを材質とするバリアメタル層
51が形成されている。したがって、金層52を非常に
薄く、例えば0.01〜0.1umと薄く形成した結果
として、プローブ針6が金層52を貫通したとしても、
その下層のバリアメタル層51がプローブ針6のパッド
電極2への到達を阻止することができる。
In this embodiment, a barrier metal layer 51 made of nickel having a hardness higher than that of gold is formed under the gold layer 52. Therefore, even if the probe needle 6 penetrates the gold layer 52 as a result of forming the gold layer 52 very thin, for example, 0.01 to 0.1 μm,
The lower barrier metal layer 51 can prevent the probe needle 6 from reaching the pad electrode 2.

【0030】図2(c)は、半導体装置の電気的特性の
測定後、半田ボール82を半導体基板1上に接着後の断
面図である。半田ボール82を金層52へフラックスに
より仮接着後、半田ボール82を電極パッド2と機械的
・電気的に接続するため、加熱処理(リフロー)を行
う。この加熱処理により半田ボールを溶融させ、電極パ
ッド2上のバリアメタル51と半田ボールとが接合され
る。
FIG. 2C is a cross-sectional view after bonding the solder balls 82 onto the semiconductor substrate 1 after measuring the electrical characteristics of the semiconductor device. After the solder balls 82 are temporarily bonded to the gold layer 52 by flux, heat treatment (reflow) is performed to mechanically and electrically connect the solder balls 82 to the electrode pads 2. The solder ball is melted by this heat treatment, and the barrier metal 51 on the electrode pad 2 and the solder ball are joined.

【0031】一方で、この加熱処理の際、金層52と半
田ボールに含まれる錫とはAu−Snの化合物を形成す
る。この金と錫の化合物が半田中に多量に存在すると半
田がもろくなるため、金層52の膜厚には上限があり、
本実施形態では最大0.1umとした。一方、半田の濡
れ性確保及びプローブ針6との良好な接触を確保するた
め金層52の膜厚には下限があり、本実施形態では最小
0.01umとした。
On the other hand, during this heat treatment, the gold layer 52 and tin contained in the solder ball form an Au-Sn compound. Since the solder becomes brittle when this gold and tin compound is present in a large amount in the solder, there is an upper limit to the film thickness of the gold layer 52,
In this embodiment, the maximum is 0.1 μm. On the other hand, there is a lower limit to the film thickness of the gold layer 52 in order to ensure solder wettability and good contact with the probe needle 6, and in this embodiment, the minimum thickness is 0.01 μm.

【0032】図2(c)に示す通り、針跡7が形成され
た金層52上に半田ボール82を仮接着後、半導体基板
1を加熱処理する。この結果、針跡7は半田ボール82
により密閉されるが、加熱処理に伴う半田ボール82と
金層52との機械的接続強度には問題がない。金層52
が薄いため針跡7の大きさ(体積)が小さいからであ
る。
As shown in FIG. 2C, after the solder balls 82 are temporarily bonded onto the gold layer 52 on which the needle marks 7 are formed, the semiconductor substrate 1 is heat-treated. As a result, the needle trace 7 becomes a solder ball 82.
However, there is no problem in the mechanical connection strength between the solder ball 82 and the gold layer 52 due to the heat treatment. Gold layer 52
This is because the size (volume) of the needle trace 7 is small because the thickness is thin.

【0033】なお、第2の実施形態例では金属バンプの
例として半田ボール82を半導体基板1に接着する場合
で説明した。金属バンプとして半田を電解若しくは無電
解メッキ法により形成する場合もよい。また、金を電解
若しくは無電解メッキ法により成長させてバンプとして
もよい。また、バリアメタル層51及び金層52を蒸着
法又はスパッタ法にて形成してもよい。
In the second embodiment, the solder ball 82 is bonded to the semiconductor substrate 1 as an example of the metal bump. Solder may be formed as a metal bump by electrolytic or electroless plating. Alternatively, gold may be grown by electrolytic or electroless plating to form bumps. Further, the barrier metal layer 51 and the gold layer 52 may be formed by vapor deposition or sputtering.

【0034】図3は、本発明の第3の実施形態例に係わ
る金属バンプを有する半導体装置の製造工程を示す。本
実施形態例では、プローブ針の接触により金層5(第1
の実施形態例)若しくは金層52(第2の実施形態例)
に形成された針跡7を、平坦化治具9により平坦化する
ものである。
FIG. 3 shows a manufacturing process of a semiconductor device having metal bumps according to the third embodiment of the present invention. In this embodiment, the gold layer 5 (first
Embodiment) or gold layer 52 (second embodiment)
The needle trace 7 formed in the above is flattened by the flattening jig 9.

【0035】平坦化治具9の先端形状は、一辺の長さが
対応する開口部の辺よりも小さく、その先端部は平面形
状を有するものである。先端部の大きさの上限は、開口
部4と平坦化治具9との機械的位置あわせ精度を考慮し
て、平坦化治具9の先端が表面保護膜3にかからない程
度とする。大きさの下限は、針跡7の平面形状を考慮
し、平坦化治具9による一度の押圧で針跡7が平坦化で
きる大きさを下限とする。
The tip shape of the flattening jig 9 is smaller in length than one side of the corresponding opening, and the tip portion has a planar shape. The upper limit of the size of the tip is set such that the tip of the flattening jig 9 does not cover the surface protective film 3 in consideration of the mechanical alignment accuracy between the opening 4 and the flattening jig 9. The lower limit of the size takes into consideration the planar shape of the needle trace 7, and the lower limit is the size that allows the needle trace 7 to be flattened with a single press by the flattening jig 9.

【0036】平坦化治具9による電極パッド2の押圧動
作は、一つの電極パッド2毎に行ってもよいし、複数の
平坦化治具9により同時に、各々対応する複数の電極パ
ッド2に対して同様の動作を行ってもよい。
The pressing operation of the electrode pad 2 by the flattening jig 9 may be performed for each electrode pad 2 or simultaneously by the plurality of flattening jigs 9 against the corresponding electrode pads 2 respectively. The same operation may be performed.

【0037】このように、本実施例はプローブ針による
テストの後であって金属バンプを形成する前に、平坦な
先端形状を有する押圧手段により前記金層表面を押圧す
る工程とを付加している。したがって、第1の実施形態
例の製造方法に対し、金層5の針跡7を平坦化治具9で
平坦化することにより、金スタッドバンプ形成をより安
定して行うことが可能となる。第2の実施形態例の製造
方法に対しては、金属バンプの加熱処理時に針跡7に起
因する問題を、より改善する効果が得られる。
As described above, this embodiment adds the step of pressing the gold layer surface by pressing means having a flat tip shape after the test with the probe needle and before the formation of the metal bump. Yes. Therefore, the gold stud bump formation can be more stably performed by flattening the needle trace 7 of the gold layer 5 with the flattening jig 9 in the manufacturing method of the first embodiment. For the manufacturing method of the second embodiment, an effect of further improving the problem caused by the needle trace 7 during the heat treatment of the metal bumps can be obtained.

【0038】[0038]

【発明の効果】以上説明したように、本発明によれば、
電極パッドへダメージを与えることなくプローブ針によ
る電気的特性の測定精度を向上でき、さらに、信頼性の
高い金属バンプの形成を実現できる。
As described above, according to the present invention,
The measurement accuracy of the electrical characteristics by the probe needle can be improved without damaging the electrode pad, and the formation of a highly reliable metal bump can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係わる半導体装置の
製造工程を示す電極パッド部の断面図である。
FIG. 1 is a cross-sectional view of an electrode pad portion showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第2の実施形態に係わる半導体装置の
製造工程を示す電極パッド部の断面図である。
FIG. 2 is a cross-sectional view of an electrode pad portion showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

【図3】本発明の第3の実施形態に係わる半導体装置の
製造工程を示す電極パッド部の断面図である。
FIG. 3 is a sectional view of an electrode pad portion showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 電極パッド 3 表面保護膜 4 開口部 5 金層 51 バリアメタル層 52 金層 6 プローブ針 7 針跡 81 金スタッドバンプ 82 半田ボール 9 平坦化治具 1 Semiconductor substrate 2 electrode pads 3 Surface protective film 4 openings 5 gold layers 51 Barrier metal layer 52 gold layer 6 Probe needle 7 Needle marks 81 gold stud bump 82 Solder balls 9 Flattening jig

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 電極パッドに金属バンプを有する半導体
装置の製造方法において、 半導体基板に電極パッドを形成する工程と、 前記電極パッド上に、その電極パッドと電気的に接続す
る金層を形成する工程と、 前記金層にプローブ針を接触させる工程と、 前記プローブ針を接触させた前記金層上に金属バンプを
形成する工程とを有することを特徴とする半導体装置の
製造方法。
1. A method of manufacturing a semiconductor device having metal bumps on an electrode pad, the step of forming the electrode pad on a semiconductor substrate, and forming a gold layer electrically connected to the electrode pad on the electrode pad. A method of manufacturing a semiconductor device, comprising: a step of bringing a probe needle into contact with the gold layer; and forming a metal bump on the gold layer in contact with the probe needle.
【請求項2】 前記金属バンプは半田バンプであり、 前記電極パッドと前記金層との間に半田成分の前記電極
パッドへの拡散を抑制するバリアメタル層を形成する工
程とを有することを特徴とする請求項1記載の半導体装
置の製造方法。
2. The metal bump is a solder bump, and includes a step of forming a barrier metal layer that suppresses diffusion of a solder component into the electrode pad between the electrode pad and the gold layer. A method for manufacturing a semiconductor device according to claim 1.
【請求項3】 前記電極パッドはアルミニウムを主成分
とする金属層であり、 前記バリアメタル層はニッケル又は銅を主成分とする金
属層であることを特徴とする請求項2記載の半導体装置
の製造方法。
3. The semiconductor device according to claim 2, wherein the electrode pad is a metal layer mainly composed of aluminum, and the barrier metal layer is a metal layer mainly composed of nickel or copper. Production method.
【請求項4】 前記金属バンプは金ワイヤーによるスタ
ッドバンプであることを特徴とする請求項1記載の半導
体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 1, wherein the metal bump is a stud bump made of a gold wire.
【請求項5】 前記プローブ針を前記金層に接触させる
工程と前記金属バンプを形成する工程との間に、平坦な
先端形状を有する押圧手段により前記金層表面を押圧す
る工程とを有することを特徴とする請求項1乃至4何れ
か1項記載の半導体装置の製造方法。
5. A step of pressing the surface of the gold layer by a pressing means having a flat tip shape between the step of bringing the probe needle into contact with the gold layer and the step of forming the metal bump. The method for manufacturing a semiconductor device according to claim 1, wherein:
【請求項6】 半導体素子の電極パッドを金層で覆い、
前記金層にプローブ針を接触させてテストを行い、しか
る後にバンプ電極を形成することを特徴とする半導体装
置の製造方法。
6. An electrode pad of a semiconductor element is covered with a gold layer,
A method for manufacturing a semiconductor device, wherein a test is performed by bringing a probe needle into contact with the gold layer, and then a bump electrode is formed.
【請求項7】 前記電極パッドを前記金層で直接覆い、
前記テストを行った後に、金でなる前記バンプ電極を形
成することを特徴とする請求項6記載の半導体装置の製
造方法。
7. The electrode pad is directly covered with the gold layer,
7. The method of manufacturing a semiconductor device according to claim 6, wherein the bump electrode made of gold is formed after the test.
【請求項8】 前記電極パッドをバリア層を介して前記
金層で覆い、前記テストを行った後に、前記バンプ電極
を形成することを特徴とする請求項6記載の半導体装置
の製造方法。
8. The method of manufacturing a semiconductor device according to claim 6, wherein the bump electrode is formed after the electrode pad is covered with the gold layer through a barrier layer and the test is performed.
【請求項9】 請求項1乃至8何れか一項記載の製造方
法による半導体装置。
9. A semiconductor device manufactured by the manufacturing method according to claim 1. Description:
JP2002154236A 2002-05-28 2002-05-28 Semiconductor device and its manufacturing method Pending JP2003347337A (en)

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Publication Number Publication Date
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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019004186A (en) * 2018-10-02 2019-01-10 株式会社ニコン Semiconductor device and method for manufacturing the same, imaging apparatus, and electronic camera

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019004186A (en) * 2018-10-02 2019-01-10 株式会社ニコン Semiconductor device and method for manufacturing the same, imaging apparatus, and electronic camera

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