JP2003234455A - Method for fabricating electronic device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for fabricating an electronic device formed on a substrate with 0.01-30 μm in thickness and an electronic device. <P>SOLUTION: The method for fabricating an electronic device comprises a step for thinning a substrate to form an extremely thin substrate, a step for mounting the extremely thin substrate fixedly on a mounting substrate, a step for forming electronic components on the extremely thin substrate placed fixedly on the mounting substrate, and a step for cutting out the extremely thin substrate on which the electronic components are formed as electronic devices. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic device, an electronic device and an electronic device apparatus in which an electronic component is formed on a substrate thinned to such a degree that it is difficult to handle by itself.

[0002]

2. Description of the Related Art A substrate for forming electronic parts represented by semiconductor devices such as MOS transistors and MOS capacitors generally requires a thickness of 200 μm to 5000 μm. The reason is as follows. First, if the thickness of the substrate is less than 200 μm, the substrate may be damaged when the substrate is transferred or handled in a semiconductor process of forming a semiconductor device on the substrate. Secondly, in a semiconductor process for forming a semiconductor device, the substrate is exposed to harsh conditions such as heat and plasma.
If it is thinner than 0 μm, the substrate may be damaged. Thirdly, if the thickness of the substrate is less than 200 μm, the substrate or the semiconductor device on the substrate may be damaged or defective when the substrate is warped or distorted due to warping or distortion and the substrate is dropped. . For this reason, the substrate for forming the semiconductor device is generally 200 μm to 5 μm.
It is said that a thickness of 000 μm is necessary.

A semiconductor device mounted on a semiconductor package has a limited thickness, and it is necessary to make the substrate thinner than 200 μm. In this case, 200 μm to 5000 μ
After forming a semiconductor device on a substrate having a thickness of m by a semiconductor process, a protective film is attached to the front surface of the substrate and the back surface of the substrate is mechanically polished to thin the substrate.

A conventional method of manufacturing such a semiconductor device will be described with reference to the drawings. 49 to 59 are cross-sectional views illustrating a process of forming a MOS transistor on a conventional semiconductor substrate. Referring to FIG. 49, the diameter 200
mm, and the thickness of 725 μm, the P-type silicon substrate 2 is washed,
After rinsing and drying, put in an oxidation furnace. And 900
A pad silicon oxide film 6 is formed on the P-type silicon substrate 2 by high temperature steam of ℃. Further, the buffer polycrystalline silicon film 7 and the silicon nitride film 8 are deposited in this order on the pad silicon oxide film 6 by using the CVD method (chemical vapor deposition method).

Referring to FIG. 50, a buffer polycrystalline silicon film formed in a region to be an element isolation region by masking a region to be an active region on the silicon nitride film 8 with a photoresist 9 by a photolithography process. 7 and the silicon nitride film 8 are removed by dry etching. Referring to FIG. 51, the buffer polycrystalline silicon film 7
A shallow trench 10 is formed by dry etching in the element isolation region where the silicon nitride film 8 and the silicon nitride film 8 have been removed.
Referring to FIG. 52, an oxide film is deposited by a CVD method using silane gas and oxygen gas as raw materials to fill the shallow trench 10.

The surface of the P-type silicon substrate 2 is flattened by the chemical mechanical polishing (CMP) method. Further, the silicon nitride film 8 is removed by hot phosphoric acid, and the buffer polycrystalline silicon film 7 is removed by dry etching or wet etching. The shallow trench insulator 11 formed in this manner electrically separates and insulates elements to be formed later.

Referring to FIG. 53, while masking the P-type MOS side with photoresist 9, boron ions are implanted into the N-type MOS side to form a P-well region 12.
Similarly, the N well region 13 is formed on the P type MOS side.

Referring to FIG. 54, the P well region 12,
A gate electrode polysilicon film 14 is grown by a CVD method so as to cover the N well region 13 and the shallow trench insulator 11. At this time, an impurity is introduced during the growth of the gate electrode polysilicon film 14, or after the growth, an impurity is introduced into the gate electrode polysilicon film 14 by ion implantation.

Referring to FIG. 55, the gate electrode polysilicon film 14 is patterned by a photolithography process and a dry etching process to form a gate electrode 15. Then, As ions are implanted under the conditions of an acceleration energy of 2 keV and a dose amount of 1 × 10 ¹⁴ atoms / cm ² , and the source / drain extension region 16 on the N-type MOS side is self-aligned with the gate electrode 15 having a role of a mask. Form. The source / drain extension region 16 is similarly formed on the P-type MOS side.

Referring to FIG. 56, the silicon oxide film is
After being deposited to a thickness of 00 nm, the sidewall 17 is etched back by anisotropic dry etching.
Is formed on the side of the gate electrode 15. Furthermore, the acceleration energy is 15 keV and the dose amount is 3 × 1 using the gate electrode 15 having the sidewalls 17 formed on the sides as a mask.
As ions are implanted under the condition of 0 ¹⁵ atoms / Cm ² to form the source / drain regions 18 in self-alignment with the sidewalls 17. At this time, since the source / drain extension region 16 is covered with the sidewall 17, the impurity concentration does not increase and is not assimilated into the source / drain region 18.

Through these steps, the semiconductor device (CMOS transistor) having the source / drain extension region 16 is manufactured. The source / drain extension region 16 is a shallow diffusion layer, and is provided to suppress the short channel effect (the effect of lowering the threshold voltage in a MOS transistor having a short gate length).

Referring to FIG. 57, a cobalt film 19 is formed in the source / drain region 18. When heat-treated in a furnace, cobalt silicide is formed, and unnecessary unreacted cobalt products on the silicon oxide film are removed by hydrofluoric acid.

Referring to FIG. 58, a thick insulating film 20 is formed by the CVD method, and a contact hole 21 for a lead electrode is opened in the insulating film 20. Referring to FIG. 59, the contact hole 21 is filled with tungsten,
The tungsten plug 22 is formed.

Although not described, in the actual manufacturing process, photoresist coating, exposure, development, etching, resist removal, and the like may be performed between the processes as needed.
Steps such as cleaning are entered.

A process of cutting a semiconductor chip from the P-type silicon substrate 2 on which the MOS transistor thus manufactured is formed will be described with reference to FIGS. 60 to 65.
Referring to FIG. 60, in the P-type silicon substrate 2, the MO
An ultraviolet curable resin film 29 is attached to the surface opposite to the surface on which the S transistor is formed.

Referring to FIG. 61, the P-type silicon substrate 2
The ultraviolet curable resin film 29 adhered to the substrate is adhered to the substrate table 30 provided in the dicing device.

Referring to FIGS. 62 and 63, the MOS
With the P-type silicon substrate 2 on which the transistor is formed being fixed to the substrate table 30 of the dicing device via the ultraviolet curable resin film 29, the diamond blade 31 rotated at a high speed is placed on the P-type silicon substrate 2 at a predetermined interval. A groove is formed on the scribe line 32 by scanning along the scribe line 32 set in a grid pattern with a space. At this time, the position of the diamond blade 31 is fixed, and by moving the substrate table 30, the diamond blade 31 is scanned along the scribe line 32. The depth of the groove can be arbitrarily changed by adjusting the height of the diamond blade 31 or the height of the substrate table 30, and the depth of the diamond blade 3 is equal to or more than the thickness of the P-type silicon substrate 2.
By inserting 1, it is possible to completely cut between the semiconductor chips.

Referring to FIG. 64, a P-type silicon substrate 2
After peeling the ultraviolet curable resin 29 adhered to the substrate from the substrate table 30, the ultraviolet curable resin 29 is irradiated with ultraviolet rays 33,
It facilitates the separation of the P-type silicon substrate 2 and the ultraviolet curable resin 29. Referring to FIG. 65, the scribe line 32 is formed from the P-type silicon substrate 2 bonded to the ultraviolet curable resin 29.
The semiconductor chip is separated along the groove formed above.

As described above, when the thickness of the semiconductor device to be mounted on the semiconductor package is limited and therefore the substrate needs to be thin, the thickness is 725 μm as described with reference to FIGS. 49 to 59. After the semiconductor device is formed on the P-type silicon substrate 2, the back surface of the P-type silicon substrate 2 is mechanically polished with the protective film attached to the front surface of the P-type silicon substrate 2.

[0020]

However, in order to reduce the thickness of the substrate by such mechanical polishing, the thickness of 100 μm can be obtained.
There is a problem that the limit is up to about m. In order to mount a semiconductor chip on a thin display device such as electronic paper which will be developed in the future, it is necessary to further thin the substrate. Further, when it is necessary to perform three-dimensional mounting in which a plurality of semiconductor chips are stacked, the restriction on the thickness dimension becomes particularly strict, and it becomes necessary to thin the substrate to 50 μm, for example. On the contrary, if the thickness of the semiconductor chip cannot be reduced, it becomes a factor that hinders the thinning of electronic devices such as electric appliances, communication devices, computers, etc., in which a semiconductor package having the semiconductor chip is mounted.

The thickness of the substrate forming the semiconductor device is 100.
When the thickness is about μm, the substrate does not have flexibility, so that application to flexible products cannot be expected. Further, if the thickness of the substrate is about 100 μm, the thickness of the IC card is restricted when it is applied to products such as IC cards.

Further, in thinning the film by mechanical polishing, it is difficult to control the film thickness because the thickness of the substrate becomes non-uniform,
The problem that the semiconductor device formed on the substrate is loaded during mechanical polishing, the problem that the working environment is polluted by the dust generated by mechanical polishing, and the substrate is damaged by mechanical polishing, and the reliability of semiconductor chips There is a problem of deterioration of sex.

The present invention is to solve the above problems, and an object of the present invention is to provide an electronic device manufacturing method, an electronic device and an electronic device apparatus in which a semiconductor device is formed on a substrate having a thickness of 0.01 μm to 30 μm. To provide.

[0024]

An electronic device manufacturing method according to the present invention comprises an ultrathin substrate forming step of forming an ultrathin substrate by thinning the substrate, and a mounting substrate thicker than the ultrathin substrate. A mounting step of mounting the ultrathin substrate in a fixed state; an electronic component forming step of forming an electronic component on the ultrathin substrate mounted in a fixed state on the mounting substrate; The step of taking out the formed ultrathin substrate by cutting it from the mounting substrate is included, whereby the above object is achieved.

The thickness of the mounting substrate may be sufficiently thick so that the ultrathin substrate is not damaged in the electronic component forming step.

The placing step may include a step of forming a bonding portion to be joined to the ultrathin substrate on the placing substrate.

The joint portion may be formed at a position that does not overlap the electronic component formed on the ultrathin substrate.

The joint portion may be formed on the peripheral edge of the mounting substrate.

The joint portion may be formed in an annular shape.

The joint portion may be formed in a dot shape at a predetermined distance from the periphery of the mounting substrate.

The joint portion may be formed in a lattice shape.

The joints may be formed in a matrix.

The bonding portion may be formed such that the ultrathin substrate bonded to the bonding portion is in close contact with the placement substrate.

The electronic component may be a semiconductor element, and the electronic component forming step may be a semiconductor process.

The thickness of the mounting substrate may be 200 microns or more and 5000 microns or less.

The ultrathin substrate may have a thickness of 0.01 micron or more and 30 micron or less.

The ultrathin substrate may be composed of a semiconductor substrate.

The ultrathin substrate may be composed of a silicon substrate.

In the ultrathin substrate forming step, the ultrathin substrate may be formed by any of a smart cut method, a hydrogen ion exfoliation method, a rare gas ion exfoliation method, a void cut method and a polishing method.

In the placing step, the ultrathin substrate is placed on the placing substrate so as not to move by any one of the anodic bonding method, the metal-semiconductor bonding technique method, the laser welding method and the heat resistant adhesive method. You may put it.

The electronic component may be a piezoelectric element.

The electronic device according to the present invention is manufactured by the method for manufacturing an electronic device according to the present invention, whereby the above object is achieved.

The ultrathin substrate may have such flexibility that it can be attached to a curved base.

The ultra-thin substrate may be attached to a curved base so as to give the electronic component lattice distortion that acts to increase the carrier mobility in the electronic component.

The electronic device device according to the present invention is an electronic device device in which the electronic devices according to the present invention are laminated, and each ultrathin substrate provided in each laminated electronic device is filled with a conductive material. Through holes are formed, and the electronic components formed on the ultrathin substrates are connected to each other through the conductive material filled in the through holes, thereby achieving the above object. .

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION In a semiconductor chip according to this embodiment, MOS transistors are formed on an ultrathin semiconductor substrate having a thickness of 0.01 μm to 30 μm. Hereinafter, a method of manufacturing a semiconductor chip according to this embodiment will be described with reference to the drawings.

FIG. 1 is a sectional view of a P-type silicon substrate 2 used in the method of manufacturing a semiconductor chip according to this embodiment, and FIG. 2 is a P-type silicon substrate on which an ultrathin semiconductor substrate 3 is formed. It is sectional drawing of FIG.

Referring to FIGS. 1 and 2, first, an ultrathin semiconductor substrate 3 is manufactured from a P-type silicon substrate 2 by the smart cut method. 2 on the surface of the P-type silicon substrate 2.
Acceleration energy of 00 KeV, areal density 3 × 10 ¹⁴ -1
Under the condition of × 10 ¹⁷ cm ⁻² , H ₂ ⁺ was injected so that a peak of the H atom profile was formed at a depth of about 1 μm, and the separation surface 3 having the peak of the H atom profile 3
6 is formed. The separation surface 36 is a brittle surface having crystal defects and crystal strain. The layer on the separation surface 36 formed on the P-type silicon substrate 2 becomes the ultrathin semiconductor substrate 3. Therefore, the thickness of the ultrathin semiconductor substrate 3 is about 1 μm.

FIG. 3 is a sectional view of the mounting substrate 4 and the ultrathin semiconductor substrate 3 mounted on the mounting substrate 4. Figure 4 (a)
[Fig. 4] is a plan view for explaining an arrangement pattern of the joint portions 5 formed on the mounting substrate 4, and Fig. 4 (b) is a sectional view taken along the line AA shown in Fig. 4 (a). A bonding portion 5 made of glass is formed on the surface of the mounting substrate 4 having a diameter of about 200 mm and a thickness of about 700 μm. The bonding portion 5 is formed on a part of the surface of the mounting substrate 4, and is formed in a substantially annular shape so as to have a constant width and depth at the peripheral edge of the mounting substrate 4.
The bonding portion 5 is an ultrathin semiconductor substrate 3 mounted on the mounting substrate 4.
The semiconductor chip to be described later is formed on the peripheral edge of the mounting substrate 4 corresponding to the peripheral edge of the ultrathin semiconductor substrate 3. In this way, the joint portion 5 is formed at a position that does not overlap the semiconductor chip formed on the ultrathin semiconductor substrate 3. Therefore, there is an advantage that the yield of semiconductor chips is not reduced. The bonding portion 5 is formed so as to slightly rise from the surface of the mounting substrate 4. An insulating layer 40 is formed inside the joint portion 5. The insulating layer 40 is
The ultrathin semiconductor substrate 3 is formed so that the surface thereof is substantially the same as the surface of the bonding portion 5 so as to be in close contact with the surface of the bonding portion 5 and the surface of the insulating layer 40.

It is preferable that the glass constituting the bonding portion 5 has mobile ions such as Na ⁺ and H ⁺ ions therein and has a thermal expansion coefficient substantially equal to that of the ultrathin semiconductor substrate 3. Further, the glass constituting the joint 5 is silicon oxide, soda-lime glass, quartz, quartz glass, borosilicate glass, fluoride glass, Pyrex (registered trademark),
It is preferably silicon fluoride or sapphire. More preferably, the mounting substrate 4 made of silicon is preferably made of a silicon oxide film obtained by oxidizing a part of the surface of the mounting substrate 4.
Further, it is desirable that the silicon oxide film is formed by using a wet oxidation method, and H ⁺ ions contained in the oxide film are used as mobile ions.

Then, the P-type silicon substrate 2 on which the ultrathin semiconductor substrate 3 is formed by the smart cut method is placed so that the ultrathin semiconductor substrate 3 and the mounting substrate 4 on which the bonding portion 5 is formed face each other. It is pressed against the surface of the substrate 4.

Next, the joint portion 5 made of glass.
The mounting substrate 4 having a part of the surface thereof and the P-type silicon substrate 2 on which the ultrathin semiconductor substrate 3 is formed are 300 ° C. or higher 6
It is heated to 00 ° C. or lower, the mounting substrate 4 side is set to a negative potential, the ultrathin semiconductor substrate 3 side is set to a positive potential, and a voltage of 30 V or more and 1000 V or less is applied. The applied voltage is the junction 5
It depends on the material of glass, the film thickness, and the bonding temperature.
In this way, the joint portion 5 and P formed on the mounting substrate 4 are
The ultrathin semiconductor substrate 3 formed on the mold silicon substrate 2 is bonded by the anodic bonding method.

After this anodic bonding, the P-type silicon substrate 2
The separation surface 36 formed on the substrate 3 and the remaining layer of the P-type silicon substrate formed on the opposite side of the separation surface 36 from the ultrathin semiconductor substrate 3 are peeled off from the ultrathin semiconductor substrate 3 bonded to the bonding portion 5. . As a method of peeling, first, heat treatment at 400 ° C. to 500 ° C. is applied. After this heat treatment, the P-type silicon substrate 2
The separation surface 36 and the remaining layer of the P-type silicon substrate formed on the substrate are peeled off from the ultrathin semiconductor substrate 3. In order to separate the layers, a shearing force may be applied to the remaining layers of the P-type silicon substrate 2, or a water jet may be applied to the separation surface 36 from the side. The separation may be triggered by laterally pressing the sharp plate-shaped blade against the separation surface 36 using a jig. The heat treatment for peeling may be the same as the heat treatment for anodic bonding.

In this way, P is obtained by the smart cut method.
The thin silicon substrate 2 is thinned to form an ultrathin semiconductor substrate 3, and the ultrathin semiconductor substrate 3 is mounted on the mounting substrate 4 by an anodic bonding method.
After being mounted on the mounting substrate 4 in a fixed state, the semiconductors are mounted on the mounting substrate 4 so as not to move on the mounting substrate 4 through the same steps as those in the conventional example. Build the device.

5 to 15 are sectional views for explaining the steps of forming a MOS transistor on the ultrathin semiconductor substrate 3 according to this embodiment. Referring to FIG. 5, a diameter of about 200
The ultrathin semiconductor substrate 3 mounted so as not to move on the mounting substrate 4 having a thickness of 700 mm and a thickness of about 700 μm is washed, rinsed and dried, and then placed in an oxidation furnace. Then, the pad silicon oxide film 6 is formed on the ultrathin semiconductor substrate 3 by high-temperature steam at 900 ° C. Further, the buffer polycrystalline silicon film 7 and the silicon nitride film 8 are deposited in this order on the pad silicon oxide film 6 by using the CVD method (chemical vapor deposition method).

Referring to FIG. 6, a buffer polycrystalline silicon film formed in a region to be an element isolation region by masking a region to be an active region on the silicon nitride film 8 with a photoresist 9 by a photolithography process. 7
And the silicon nitride film 8 are removed by dry etching.

Referring to FIG. 7, a shallow trench 10 is formed by dry etching in the element isolation region where the buffer polycrystalline silicon film 7 and the silicon nitride film 8 are removed. Referring to FIG. 8, an oxide film is deposited by a CVD method using silane gas and oxygen gas as raw materials to fill the shallow trench 10. Furthermore, chemical mechanical polishing (CMP)
The surface of the ultrathin semiconductor substrate 3 is flattened by the method. Further, the silicon nitride film 8 is removed by hot phosphoric acid, and the buffer polycrystalline silicon film 7 is removed by dry etching or wet etching. The shallow trench insulator 11 formed in this manner electrically separates and insulates elements to be formed later.

Referring to FIG. 9, while masking the P-type MOS side with photoresist 9, boron ions are implanted into the N-type MOS side to form a P-well region 12. Similarly, the N well region 13 is formed on the P type MOS side.

Referring to FIG. 10, the P well region 12,
A gate electrode polysilicon film 14 is grown by a CVD method so as to cover the N well region 13 and the shallow trench insulator 11. At this time, an impurity is introduced during the growth of the gate electrode polysilicon film 14, or after the growth, an impurity is introduced into the gate electrode polysilicon film 14 by ion implantation.

Referring to FIG. 11, the gate electrode polysilicon film 14 is patterned by a photolithography process and a dry etching process to form a gate electrode 15. Then, As ions are implanted under the conditions of an acceleration energy of 2 keV and a dose amount of 1 × 10 ¹⁴ atoms / cm ² , and the source / drain extension region 16 on the N-type MOS side is formed in self-alignment with the gate electrode 15 having a role of a mask. Form. Similarly, on the P-type MOS side, source / drain extension region 1
6 is formed.

Referring to FIG. 12, the silicon oxide film 1
After being deposited to a thickness of 00 nm, the sidewall 17 is etched back by anisotropic dry etching.
Is formed on the side of the gate electrode 15. Furthermore, the acceleration energy is 15 keV and the dose amount is 3 × 1 using the gate electrode 15 having the sidewalls 17 formed on the sides as a mask.
As ions are implanted under the condition of 0 ¹⁵ atoms / Cm ² to form the source / drain regions 18 in self-alignment with the sidewalls 17. At this time, since the source / drain extension region 16 is covered with the sidewall 17, the impurity concentration does not increase and is not assimilated into the source / drain region 18.

Through these steps, the semiconductor device (CMOS transistor) having the source / drain extension region 16 is manufactured. The source / drain extension region 16 is a shallow diffusion layer, and is provided to suppress the short channel effect (the effect of lowering the threshold voltage in a MOS transistor having a short gate length).

Referring to FIG. 13, a cobalt film 19 is formed in the source / drain region 18. When heat-treated in a furnace, cobalt silicide is formed, and unnecessary unreacted cobalt products on the silicon oxide film are removed by hydrofluoric acid.

Referring to FIG. 14, a thick insulating film 20 is formed by the CVD method, and a contact hole 21 for a lead electrode is opened in the insulating film 20. Referring to FIG. 15, tungsten is embedded in the contact hole 21,
The tungsten plug 22 is formed.

Although not described, in the actual manufacturing process, photoresist coating, exposure, development, etching, resist removal, and the like may be performed between the processes as needed.
Steps such as cleaning are entered.

A process of cutting a semiconductor chip from the P-type silicon substrate 2 on which the MOS transistor thus manufactured is formed will be described with reference to FIGS. 16 to 21.
Referring to FIG. 16, an ultraviolet curable resin film 29 is attached to the surface of the mounting substrate 4 opposite to the ultrathin semiconductor substrate 3.

Referring to FIG. 17, the ultraviolet curable resin film 29 adhered to the mounting substrate 4 is adhered to the substrate table 30 provided in the dicing device.

Referring to FIGS. 18 and 19, the MOS
In a state where the mounting substrate 4 on which the ultrathin semiconductor substrate 3 on which the transistor is formed is mounted is fixed to the substrate table 30 of the dicing device via the ultraviolet curable resin film 29, the diamond blade 31 rotated at a high speed has a predetermined width. The ultrathin semiconductor substrate 3 is scribed along the scribe lines 32 that are set in a grid pattern with a space therebetween, and grooves are formed along the scribe lines 32. At this time, the position of the diamond blade 31 is fixed, and by moving the substrate table 30, the diamond blade 31 is scanned along the scribe line 32. The portion of the ultrathin semiconductor substrate 3 surrounded by the grooves formed in the lattice shape is the semiconductor chip 1 according to the present embodiment.
Becomes The depth of the groove can be arbitrarily changed by adjusting the height of the diamond blade 31 or the height of the substrate table 30, and the diamond blade 31 is set to a depth equal to or larger than the thickness of the ultrathin semiconductor substrate 3. By inserting, the semiconductor chips 1 can be completely cut.

Referring to FIG. 20, the diamond blade 31
Semiconductor chip 1 surrounded by a groove formed by
The tip of the transfer arm 34 is placed on one of the above, and the semiconductor chip 1 on which the tip of the transfer arm 34 is placed is sucked by a suction mechanism (not shown) built in the transfer arm 34.

Referring to FIG. 21A, the transfer arm 3
When 4 is moved upward, a crack is formed in the groove formed around the semiconductor chip 1 sucked by the suction mechanism built in the transfer arm 34, and the groove is broken, so that the semiconductor sucked by the transfer arm 34 is cracked. The chip 1 is separated from the ultrathin semiconductor substrate 3 along the groove. As shown in FIG. 21B, at this time, if necessary, the notch bar 3 is provided so as to press the semiconductor chip 1 adjacent to the adsorbed semiconductor chip 1.
By inserting 7, the cracks are likely to occur in the groove formed around the semiconductor chip 1, and the adsorbed semiconductor chip 1 may be separated. The notch bar 37 may press a groove formed around the semiconductor chip 1 to be attracted.

As shown in FIG. 21 (c), the semiconductor chip 1 attracted by the notch bar 37A having a sharp tip.
You may make it divide the groove formed in the circumference | surroundings. In the scribing process, when the semiconductor chips 1 are completely cut, the semiconductor chip 1 is simply sucked by the suction mechanism built in the transfer arm 34.
Can be separated from the ultrathin semiconductor substrate 3.

FIG. 22 is a sectional view of the semiconductor chip 1 mounted on the IC card according to this embodiment. Ultrathin semiconductor substrate 3 constituting the semiconductor chip 1 according to the present embodiment
Has a thickness of about 1 μm and therefore has flexibility.
Therefore, when the semiconductor chip 1 is attached or embedded on the surface of the IC card base 96 that constitutes the IC card, the flexibility of the semiconductor chip 1 reduces the risk of the semiconductor chip 1 being defective due to cracking.

FIG. 23A is a sectional view of the semiconductor chip 1 mounted on the curved base 26 according to the present embodiment, and FIG. 23B is an enlarged view of the main part thereof. . Figure 24
FIG. 6 is a sectional view of a semiconductor chip mounted on another curved base 27. Since the ultrathin semiconductor substrate 3 forming the semiconductor chip 1 according to the present embodiment has a thin thickness of about 1 μm, it is flexible enough to be attached to a curved substrate. When the semiconductor chip 1 is attached to a curved base, the ultrathin semiconductor substrate 3 forming the semiconductor chip 1 is formed.
Bending stress is generated in the semiconductor device, and the bending stress causes lattice distortion in a semiconductor device such as a MOS transistor formed on the ultrathin semiconductor substrate 3. This lattice strain increases the carrier mobility of the semiconductor device formed on the ultrathin semiconductor substrate 3 and improves the performance of the semiconductor device.

When it is desired to apply a tensile stress out of bending stress to the semiconductor device formed on the ultrathin semiconductor substrate 3, for example, as shown in FIG. The chip 1 may be attached. FIG. 23
As shown in FIGS. 23A and 23B, when the semiconductor chip 1 is attached to the convex semiconductor chip base 26, an external compression force 42 acts on the lower portion of the ultrathin substrate 3 of the semiconductor chip 1. An external tensile force 41 acts on the side of the semiconductor device that constitutes the MOS transistor. Therefore, the gate electrode 15
A compressive stress acts inward as a reaction force of the tensile external force 41 on the channel region between the source / drain extension regions 16 formed below. When a compressive stress is applied to the channel region as a reaction force of the tensile external force 41, lattice strain occurs in the channel region and carrier mobility in the channel region of the MOS transistor increases. As a result, the performance of the MOS transistor formed on the ultrathin semiconductor substrate 3 is improved.

Si can also be formed by epitaxially growing Si constituting the channel region on the SiGe layer.
Since the lattice spacing of Ge is about 4% longer than the lattice spacing of Si, compressive stress can be applied to the channel region as a reaction force of the external tensile force, and lattice strain occurs in the channel region.
The carrier mobility in the channel region of the MOS transistor can be increased. However, this method has a problem that the cost for epitaxial growth is high and that the epitaxially grown Si has many crystal defects. According to the present embodiment, by attaching the ultrathin semiconductor substrate 3 forming the semiconductor chip 1 to the curved base, the tensile external force can be applied to the channel region without epitaxially growing Si on the SiGe layer. Compressive stress is applied as a reaction force to generate lattice strain in the channel region, and the carrier mobility in the channel region of the MOS transistor can be increased.

On the contrary, when it is desired to apply a tensile stress outward as a reaction force of the compression external force 42, the semiconductor chip 1 may be attached to the concave semiconductor chip base 27, as shown in FIG. As described above, the ultrathin semiconductor substrate 3 forming the semiconductor chip 1 has a curved surface shape so as to give a lattice distortion to the semiconductor device, which acts to enhance carrier mobility of the semiconductor device formed on the ultrathin semiconductor substrate 3. It is attached to the base of.

FIG. 25 is a sectional view of a semiconductor chip device 28 in which the semiconductor chips 1 according to this embodiment are stacked.
The semiconductor chip device 28 includes a plurality of stacked semiconductor chips 1. Each of the stacked semiconductor chips 1 includes an ultrathin semiconductor substrate 3 and an MO formed on the ultrathin semiconductor substrate 3.
Each has an S transistor 38. A through hole 39 filled with a conductive material is formed in the ultrathin semiconductor substrate 3 forming each semiconductor chip 1. MOS transistor 38 formed on each ultrathin semiconductor substrate 3
Are electrically connected to each other through a conductive material filled in a through hole 39 formed in the ultrathin semiconductor substrate 3.

In this way, the semiconductor chips 1 according to the present embodiment are stacked to perform three-dimensional mounting. Since the thickness of the ultrathin semiconductor substrate 3 forming the semiconductor chip 1 according to this embodiment is as thin as about 1 μm, the semiconductor chip 1
Even if 10 sheets are stacked, the semiconductor chip device 28 is about several tens μ
The thickness is only m. Therefore, an extremely thin and high-performance semiconductor chip device can be obtained. The semiconductor chips 1 to be stacked may be the same kind of semiconductor chips or different kinds of semiconductor chips.

If the semiconductor chip 1 according to the present embodiment is, for example, a DRAM chip, and if the capacity of each DRAM chip is 256 megabits (Mbits), then stacking ten semiconductor chips 1 results in 2560 megabits. (2.56 gigabit) ultra large capacity memory, and the total thickness is the same as the thickness of a conventional semiconductor substrate,
Alternatively, since it is thinner than that, it can be directly incorporated into a product such as a conventional computer without changing the thickness specification.

In the present embodiment, an example has been described in which the MOS transistor is formed on the ultrathin semiconductor substrate 3 mounted on the mounting substrate 4 so as not to move, but the present invention is not limited to this. Not done. Another semiconductor element may be formed on the ultrathin semiconductor substrate 3, and the semiconductor element is not limited to the semiconductor element.
For example, a piezoelectric element, a MEMS (Micro Electro Mechanical System) such as a sensor, or a solar cell may be formed.

Although an example in which the mounting substrate 4 has a thickness of 700 μm has been described, the mounting substrate 4 may be thick enough so that the ultrathin semiconductor substrate 3 is not damaged in the semiconductor process. It is preferably 200 microns or more and 5000 microns or less.

Further, the thickness of the ultrathin semiconductor substrate 3 is about 1 μm.
However, the present invention can also be applied to an ultrathin semiconductor substrate having a thickness of 0.01 μm or more and 30 μm or less.

Although an example of producing the ultrathin semiconductor substrate 3 by the smart cut method has been shown, the ultrathin semiconductor substrate 3 is produced by any one of the hydrogen ion exfoliation method, the rare gas ion exfoliation method, the void cut method and the polishing method. You may.

An example of mounting the ultrathin semiconductor substrate 3 on the mounting substrate 4 by the anodic bonding method has been described. However, the ultrathin semiconductor substrate 3 is a metal-semiconductor bonding method, a laser welding method, and a heat-resistant It may be mounted on the mounting substrate 4 by any of the adhesive methods.

Further, a film for adjusting lattice strain may be formed on the MOS transistor so that lattice strain that enhances the carrier mobility of the MOS transistor is generated. The lattice strain adjusting film may be made of, for example, a silicon nitride film.

As described above, according to the present embodiment, the ultrathin substrate forming step of forming the ultrathin semiconductor substrate 3 by thinning the P-type silicon substrate 2 and the mounting substrate thicker than the ultrathin semiconductor substrate 3 are performed. A mounting step of mounting the ultrathin semiconductor substrate 3 on the mounting substrate 4 in a fixed state, and an electronic component forming step of forming a MOS transistor on the ultrathin semiconductor substrate 3 mounted on the mounting substrate 4 in a fixed state. , And the step of taking out the ultrathin semiconductor substrate 3 on which the MOS transistors are formed by cutting it from the mounting substrate 4, the ultrathin semiconductor substrate mounted on the mounting substrate 4 so as not to move. MOS on 3
A transistor is formed. Therefore, the MOS transistor can be formed on the ultrathin semiconductor substrate 3 having a thickness of 0.01 μm to 30 μm. As a result, 0.01
It is possible to provide a method for manufacturing a semiconductor chip in which a semiconductor device is formed on an ultrathin semiconductor substrate 3 having a thickness of μm to 30 μm, a semiconductor chip, and a semiconductor chip device.

FIG. 26A is a cross-sectional view of another mounting substrate 4A and the ultrathin semiconductor substrate 3 mounted on the other mounting substrate 4A according to the embodiment. The bonding portion 5A is the mounting substrate 4
It is formed along the peripheral edge of A, and its surface is formed to be slightly raised from the surface of the mounting substrate 4A. In this case, a minute space is formed between the ultrathin semiconductor substrate 3 bonded to the bonding portion 5A and the mounting substrate 4A. The bonding portion 5A is formed in a region of the ultrathin semiconductor substrate 3 mounted on the mounting substrate 4A, which corresponds to the peripheral edge of the ultrathin semiconductor substrate 3 on which no semiconductor chip is formed. FIG. 26
As shown in (b), the bonding portion 5A is formed on the ultrathin semiconductor substrate 3
May be formed so that the surface thereof is substantially the same as the surface of the mounting substrate 4A so as to be in close contact with the mounting substrate 4A.

27 (a) and 27 (b) are sectional views of still another mounting substrate 4B and the ultrathin semiconductor substrate 3 mounted on still another mounting substrate 4B. FIG. 28 is a diagram for explaining the arrangement pattern of the bonding portions 5B formed on yet another mounting substrate 4B. 28 (a) is a plan view thereof, and FIGS. 28 (b) and 28 (c) show FIG.
It is sectional drawing which followed the line BB shown to (a). FIG. 27
As shown in (a), FIG. 28 (a) and FIG. 28 (b), the bonding portion 5B is formed in a substantially annular shape so as to have a constant width and depth slightly inside from the peripheral edge of the mounting substrate 4B. Has been done. The joint portion 5B is formed so as to be slightly raised from the surface of the mounting substrate 4B, similarly to the joint portion 5A shown in FIG. 27 (b) and 28
As shown in (c), the bonding portion 5B is formed by the ultrathin semiconductor substrate 3
May be formed so that the surface thereof is substantially the same as the surface of the mounting substrate 4B so as to be in close contact with the mounting substrate 4B.

FIG. 29 is an explanatory diagram of an arrangement pattern of the joint portions 5C formed on still another mounting substrate 4C. Figure 2
9 (a) is a plan view thereof, and FIG. 29 (b) is shown in FIG.
It is sectional drawing which followed the line CC shown to 9 (a). Joint 5
C is formed along the peripheral edge of the mounting substrate 4C. The bonding portion 5C is formed in a region of the ultrathin semiconductor substrate 3 mounted on the mounting substrate 4C, which corresponds to the peripheral edge of the ultrathin semiconductor substrate on which no semiconductor chip is formed.

FIG. 30 is an explanatory diagram of an arrangement pattern of the joint portions 5D formed on yet another mounting substrate 4D. Figure 3
0 (a) is a plan view thereof, and FIG. 30 (b) is a plan view thereof.
It is sectional drawing which followed the line DD shown to 0 (a). Joint 5
D is formed in a dot shape at a predetermined distance from the periphery of the mounting substrate 4D at a predetermined distance. Each joint 5D is
In the ultrathin semiconductor substrate 3 mounted on the mounting substrate 4D, it is formed in a region corresponding to the vicinity of the periphery of the ultrathin semiconductor substrate on which no semiconductor chip is formed.

The joint 5D is formed so as to be slightly raised from the surface of the mounting substrate 4D. As shown in FIG. 30 (c), the bonding portion 5D is an ultrathin semiconductor substrate on which the mounting substrate 4D is mounted.
May be formed so that the surface thereof is substantially the same as the surface of the mounting substrate 4D so as to be in close contact with.

FIG. 31 is an explanatory diagram of an arrangement pattern of the joint portions 5E formed on yet another mounting substrate 4E. Figure 3
1 (a) is a plan view thereof, and FIG. 31 (b) is shown in FIG.
It is sectional drawing which followed the line EE shown to 1 (a). Joint 5
E is formed in a lattice shape with the same pattern as the scribe line set for dividing the semiconductor chip 1. Since the bonding portion 5E for bonding the ultra-thin semiconductor substrate 3 to the mounting substrate 4E is formed along the scribe line for dividing the semiconductor chip, if the groove is formed along the scribe line in the scribing process, it becomes extremely thin. The advantage that the semiconductor chip 1 can be easily separated from the semiconductor substrate 3 is obtained.

The joint portion 5E is formed so as to be slightly raised from the surface of the mounting substrate 4E. As shown in FIG. 31C, an ultrathin semiconductor substrate is mounted on the mounting substrate 4E at the bonding portion 5E.
May be formed so that the surface thereof is substantially the same as the surface of the mounting substrate 4E so as to be in close contact with.

Another method of manufacturing the ultrathin semiconductor substrate according to the present embodiment will be described with reference to FIGS. Figure 3
2 is a sectional view of another P-type silicon substrate 2A according to the present embodiment, and FIG. 33 is a sectional view of a P-type silicon substrate 2A on which an ultrathin semiconductor substrate 3A is formed.

Similar to FIGS. 1 and 2, the ultra-thin semiconductor substrate 3A is manufactured from the P-type silicon substrate 2A by the smart cut method. 32 and 33, an acceleration energy of 200 KeV and an area density of 3 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-2 are formed on the surface of the P-type silicon substrate 2A.
Under these conditions, H ₂ ⁺ is injected so that a peak of the H atom profile is formed at a depth of about 1 μm, and the separation surface 36 having the peak of the H atom profile is formed.
The separation surface 36 is a fragile layer having crystal defects and crystal strain. Separation surface 3 formed on this P-type silicon substrate 2A
The layer above 6 becomes the ultrathin semiconductor substrate 3A. Therefore, the thickness of the ultrathin semiconductor substrate 3A is about 1 μm.

FIG. 34A is a sectional view of the ultrathin semiconductor substrate 3A mounted on the mounting substrate 4F, and FIG.
FIG. 34 (a) and 34
Referring to (b), the P-type silicon substrate 2A on which the ultrathin semiconductor substrate 3A is formed by the smart cut method is placed on the surface of the mounting substrate 4F so that the ultrathin semiconductor substrate 3A and the mounting substrate 4F face each other. Press against. Thereafter, the separation surface 36 formed on the P-type silicon substrate 2A and the remaining layer of the P-type silicon substrate 2A formed on the opposite side of the separation surface 36 from the ultrathin semiconductor substrate 3A are mounted on the mounting substrate 4F. The ultrathin semiconductor substrate 3A placed is peeled off.

Then, the bonding material filling hole 23 having a bottom inside the mounting substrate 4F penetrating the ultrathin semiconductor substrate 3A.
Are formed by a dry etching process at respective intersections of scribe lines set in a grid pattern for cutting out a semiconductor chip from the ultrathin semiconductor substrate 3A.

Referring to FIG. 35, each binder filling hole 23
And a silicon oxide film 24 on the surface of the ultrathin semiconductor substrate 3A.
To form. Referring to FIG. 36, the ultrathin semiconductor substrate 3A
The silicon oxide film 24 formed on the surface of is removed. In this way, the silicon oxide film 2 is filled in each of the binder filling holes 23.
4 is filled, and the ultrathin semiconductor substrate 3A is mounted on the mounting substrate 4E so as not to move by the filled silicon oxide film 24.

The bonding material filling hole 23 is formed by laser processing,
It may be formed by plasma electric discharge machining. The bottom of the bonding material filling hole 23 may be the same as the surface of the mounting substrate 4E on the ultrathin semiconductor substrate 3A side. Instead of forming the silicon oxide film 24, silicon may be formed.

Another process for cutting out a semiconductor chip from the P-type silicon substrate 2 on which the MOS transistor is formed is shown in FIG.
This will be described with reference to FIGS. Referring to FIG. 37,
Similar to FIG. 16 described above, the ultraviolet curable resin film 29 is attached to the surface of the mounting substrate 4 opposite to the ultrathin semiconductor substrate 3. Referring to FIG. 38, as in the case of FIG. 17 described above, the ultraviolet curable resin film 29 adhered to the mounting substrate 4 is
It is adhered to the substrate table 30 provided in the dicing device.

Referring to FIGS. 39 and 40, the dicing machine is equipped with a diamond blade 31. The diamond blade 31 forms a groove on the ultrathin semiconductor substrate 3 along scribe lines 32 set in a lattice pattern with a predetermined interval. The position of the diamond blade 31 is fixed, and by moving the substrate table 30, the diamond blade 31 scribes the ultrathin semiconductor substrate 3 along the scribe line 32.

The dicing device is provided with a pair of chip holders 35. The chip presser 35 is provided so as to be able to move up and down so as to press the semiconductor chip 1 adjacent to the scribe line 32 scribed by the diamond blade 31, and presses the semiconductor chip 1 adjacent to any scribe line 32. It is provided so that it can be moved.

In the dicing apparatus having such a structure, the ultraviolet curable resin film 2 adhered to the mounting substrate 4 is used.
When 9 is adhered to the substrate table 30 provided in the dicing device, the substrate table 30 moves so that the scribe line 32 to be scribed is located at a position along the diamond blade 31. The pair of chip holders 35 provided on the substrate table 30 moves to a position where the semiconductor chip 1 adjacent to the scribe line 32 located along the diamond blade 31 can be held, and descends to move to the diamond blade 31. The semiconductor chip 1 adjacent to the scribe line 32 to be scribed by is held down.

The substrate table 30 moves so that the diamond blade 31 rotating at a high speed scribes the ultrathin semiconductor substrate 3 along the scribe line 32 and forms a groove on the scribe line 32.

When the scribing along the scribing line 32 is completed, the pair of chip holders 35 are raised. The substrate table 30 moves so that the other scribe line 32 is located at a position along the diamond blade 31. The pair of chip retainers 35 moves to a position where the semiconductor chips 1 adjacent to the other scribe lines 32 can be retained, descends, and retains the semiconductor chips 1 adjacent to the other scribe lines 32. The substrate table 30 moves so that the diamond blade 31 rotating at a high speed scribes the ultrathin semiconductor substrate 3 along the other scribe line 32 and forms a groove on the other scribe line 32.

In this way, the grooves are formed in a grid shape along the scribe lines 32 set in a grid shape with a predetermined interval. The portion of the ultrathin semiconductor substrate 3 surrounded by the grooves formed in a lattice shape becomes the semiconductor chip 1 according to this embodiment. The depth of the groove can be adjusted by adjusting the height of the diamond blade 31 or the height of the substrate table 30.
It can be changed arbitrarily, and by inserting the diamond blade 31 to a depth equal to or larger than the thickness of the ultrathin semiconductor substrate 3,
It is also possible to completely cut between the semiconductor chips.

With the pair of chip holders 35, even ultra-thin semiconductor substrates having different semiconductor chip dimensions can be easily handled by simply changing the interval between the chip holders 35 according to the semiconductor chip dimensions. Therefore, the manufacturing cost can be kept low.

Referring to FIG. 41, the diamond blade 31
The tip of the transfer arm 34 is placed on one of the semiconductor chips 1 surrounded by the groove scribed by, and the semiconductor chip 1 on which the tip of the transfer arm 34 is placed is attached by a suction mechanism (not shown) built in the transfer arm 34. Adsorb.

Referring to FIG. 42, FIG.
Similarly to (a), when the transfer arm 34 is moved upward, a crack is formed in the groove formed around the semiconductor chip 1 sucked by the suction mechanism built in the transfer arm 34, and the groove is broken. The semiconductor chip 1 attracted by the transfer arm 34 is separated from the ultrathin semiconductor substrate 3 along the groove. As shown in FIG. 21 (b) described above, a cutting bar 37 is inserted so as to hold the semiconductor chip 1 adjacent to the semiconductor chip 1 adsorbed at this time as needed, so that the semiconductor chip 1 is formed around the semiconductor chip 1. The adsorbed semiconductor chip 1 may be separated so that cracks are easily generated in the formed groove. In the scribing process, when the semiconductor chips 1 are completely cut, the semiconductor chip 1 is separated from the ultrathin semiconductor substrate 3 only by adsorbing the semiconductor chip 1 by the adsorption mechanism built in the transfer arm 34. You can

As described above, according to the present embodiment, the rod-shaped chip retainers 35 provided on both sides of the scribe line 32 are used to retain the surface of each semiconductor chip 1 disposed on both sides of the scribe line 32. Scribe. Therefore, it is possible to surely form the groove in the ultrathin semiconductor substrate 3 along the scribe line, and to cut the semiconductor chip 1 from the ultrathin semiconductor chip 3 along the groove surely formed along the scribe line. You can

FIG. 43 is a plan view for explaining still another step of cutting the ultrathin semiconductor substrate 3 into semiconductor chips 1, and FIG. 44 is a sectional view thereof. 39 and 40
The same reference numerals are attached to the components described above with reference to FIG. Detailed description of these components will be omitted. As shown in FIGS. 43 and 44, a plurality of chip holders 35 for holding the semiconductor chips 1 adjacent to the scribe lines 32 set in parallel to each other are provided to cover all the semiconductor chips 1 formed on the ultrathin semiconductor substrate 3. The chip holder 35 may be pressed.

According to this structure, after scribing the scribe line 32 and then scribing another scribe line 32 set in parallel to the scribe line 32, the pair of chips described in FIGS. 39 and 40 is used. It is possible to obtain an effect that it is not necessary to move the chip retainer 35 to a position where the semiconductor chip 1 adjacent to another scribe line 32 can be retained like the retainer 35.

FIG. 45 is a plan view for explaining still another step of cutting the ultrathin semiconductor substrate 3 into semiconductor chips 1, and FIG. 46 is a sectional view thereof. 39 and 40
The same reference numerals are attached to the components described above with reference to FIG. Detailed description of these components will be omitted.

The dicing device is provided with a plurality of chip holders 35A. The chip holders 35A hold the semiconductor chips 1 formed along the scribe lines 32 set in parallel with each other. To each chip holder 35A, a chip holder block 35B in the shape of a truncated pyramid is attached. The chip pressing block 35B has a bottom surface having substantially the same shape as the surface of the semiconductor chip 1. The chip pressing block 35B presses each semiconductor chip 1 so as to cover it. The chip pressing block 35B has a function of an electrostatic chuck or a vacuum chuck.

In the dicing apparatus having such a structure, the ultraviolet curable resin film 2 adhered to the mounting substrate 4
When 9 is adhered to the substrate table 30 provided in the dicing device, each chip holder 35A provided on the substrate table 30 is attached.
Respectively move to a position where each semiconductor chip 1 formed along the scribe lines 32 set parallel to each other can be held, and descend to move the semiconductor chips 1 adjacent to each scribe line 32 to the chip pressing block. Hold with 35B. The substrate table 30 provided in the dicing device moves so that the scribe line 32 to be scribed is located at a position along the diamond blade 31.

The substrate table 30 moves so that the diamond blade 31 rotating at a high speed scribes the ultrathin semiconductor substrate 3 along the scribe line 32 to form a groove on the scribe line 32.

When the scribing along the scribing line 32 is completed, the substrate table 30 is moved to another scribing line 3
2 moves so as to be located at a position along the diamond blade 31. The substrate table 30 moves so that the diamond blade 31 rotating at a high speed scribes the ultrathin semiconductor substrate 3 along the other scribe line 32 and forms a groove on the other scribe line 32.

Also for each scribe line 32 set along the direction perpendicular to the scribe line 32, the diamond blade 31 similarly rotating at high speed scribes the ultrathin semiconductor substrate 3 to form a groove. .

In this way, the grooves are formed in a grid shape along the scribe lines 32 set in a grid shape with a predetermined interval. The portion of the ultrathin semiconductor substrate 3 surrounded by the grooves formed in a lattice shape becomes the semiconductor chip 1 according to this embodiment.

Referring to FIG. 47, each chip holder 35
A leaves the chip pressing block 35B on the semiconductor chip 1 and retreats to a predetermined position. Diamond blade 3
Chip holding block 3 left on one of the semiconductor chips 1 surrounded by the groove scribed by 1.
5B, the tip of the transfer arm 34 is placed on the transfer arm 3
The semiconductor chip 1 is sucked through a chip pressing block 35B on which the tip of the transfer arm 34 is placed, by a suction mechanism (not shown) built in the device 4.

Referring to FIG. 48, when the transfer arm 34 is moved upward, a suction mechanism built in the transfer arm 34 causes a groove formed around the semiconductor chip 1 to be sucked via the chip pressing block 35B. Cracks occur,
Since the groove is broken, the semiconductor chip 1 attracted by the transfer arm 34 via the chip pressing block 35B is separated from the ultrathin semiconductor substrate 3 along the groove.

[0122]

As described above, according to the present invention, 0.01
It is possible to provide a method for manufacturing an electronic device, an electronic device and an electronic device device in which a semiconductor device is formed on a substrate having a thickness of μm to 30 μm.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a P-type silicon substrate according to an embodiment.

FIG. 2 is a cross-sectional view of a P-type silicon substrate on which an ultrathin semiconductor substrate according to the embodiment is formed.

FIG. 3 is a cross-sectional view of an ultrathin semiconductor substrate mounted on the mounting substrate according to the embodiment.

FIG. 4 is an explanatory diagram of an arrangement pattern of joints formed on the mounting substrate according to the embodiment. (A) is the top view, (b) is sectional drawing which followed the line AA shown in (a).

FIG. 5 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 6 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 7 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 8 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 9 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 10 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 11 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 12 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 13 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 14 is a cross-sectional view illustrating a step of forming a MOS transistor on the ultrathin semiconductor substrate according to the embodiment.

FIG. 15 is a cross-sectional view illustrating a step of forming a MOS transistor on an ultrathin semiconductor substrate according to an embodiment.

FIG. 16 is a cross-sectional view illustrating a step of cutting an ultrathin semiconductor substrate having a MOS transistor according to the embodiment into a semiconductor chip.

FIG. 17 is a cross-sectional view illustrating a step of cutting an ultrathin semiconductor substrate having a MOS transistor according to the embodiment into a semiconductor chip.

FIG. 18 is a plan view illustrating a step of cutting an ultrathin semiconductor substrate having a MOS transistor according to the embodiment into a semiconductor chip.

FIG. 19 is a cross-sectional view illustrating a step of cutting an ultrathin semiconductor substrate having a MOS transistor according to the embodiment into a semiconductor chip.

FIG. 20 is a cross-sectional view illustrating a step of cutting an ultrathin semiconductor substrate having a MOS transistor according to the embodiment into a semiconductor chip.

21A is a cross-sectional view illustrating a step of cutting an ultrathin semiconductor substrate on which a MOS transistor according to the embodiment is formed into a semiconductor chip, and FIG. 21B is a cross-sectional view using a cutting bar. It is sectional drawing explaining the process of cutting a thin semiconductor substrate into a semiconductor chip. (C) is sectional drawing explaining the process of cutting out an ultrathin semiconductor substrate into a semiconductor chip using another cutting bar.

FIG. 22 is a cross-sectional view of a semiconductor chip mounted on the IC card according to the embodiment.

FIG. 23A is a sectional view of a semiconductor chip mounted on a curved base according to the embodiment. (B) is an enlarged cross-sectional view of the main part thereof.

FIG. 24 is a cross-sectional view of a semiconductor chip mounted on another curved base according to the embodiment.

FIG. 25 is a cross-sectional view of a semiconductor chip device in which semiconductor chips according to the embodiment are stacked.

FIG. 26A is a cross-sectional view of an ultrathin semiconductor substrate mounted on another mounting substrate according to the embodiment. (B) is
FIG. 6 is a cross-sectional view of an ultrathin semiconductor substrate mounted so as to be in close contact with another mounting substrate according to the embodiment.

FIG. 27A is a cross-sectional view of an ultrathin semiconductor substrate mounted on still another mounting substrate according to the embodiment.
FIG. 6B is a cross-sectional view of an ultrathin semiconductor substrate mounted so as to be in close contact with another mounting substrate according to the embodiment.

FIG. 28 is an explanatory diagram of an arrangement pattern of bonding portions formed on still another mounting substrate according to the embodiment. (A)
Is a plan view thereof, and (b) is a line BB shown in (a).
It is sectional drawing along. (C) is a sectional view for explaining an arrangement pattern of another bonding portion formed on still another mounting substrate.

FIG. 29 is an explanatory diagram of an arrangement pattern of bonding portions formed on still another mounting substrate according to the embodiment. (A)
Is a plan view thereof, and (b) is a line CC shown in (a).
It is sectional drawing along.

FIG. 30 is an explanatory diagram of an arrangement pattern of bonding portions formed on still another mounting substrate according to the embodiment. (A)
Is a plan view thereof, and (b) is a line DD shown in (a).
It is sectional drawing along. FIG. 7C is a cross-sectional view of an arrangement pattern of another bonding portion formed on yet another mounting substrate.

FIG. 31 is an explanatory diagram of an arrangement pattern of bonding portions formed on still another mounting substrate according to the embodiment. (A)
Is a plan view thereof, and (b) is a line EE shown in (a).
It is sectional drawing along. FIG. 7C is a cross-sectional view of an arrangement pattern of another bonding portion formed on yet another mounting substrate.

FIG. 32 is a cross-sectional view of another P-type silicon substrate according to the embodiment.

FIG. 33 is a cross-sectional view of another ultrathin semiconductor substrate formed from another P-type silicon substrate according to the embodiment.

FIG. 34A is a cross-sectional view of another ultrathin semiconductor substrate mounted on another mounting substrate according to the embodiment, and FIG.
FIG.

FIG. 35 is a cross-sectional view of another ultrathin semiconductor substrate mounted on another mounting substrate according to the embodiment.

FIG. 36 is a cross-sectional view of another ultrathin semiconductor substrate mounted on another mounting substrate according to the embodiment.

FIG. 37 is a cross-sectional view illustrating another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into a semiconductor chip.

FIG. 38 is a cross-sectional view illustrating another step of cutting an ultrathin semiconductor substrate having a MOS transistor according to the embodiment into a semiconductor chip.

FIG. 39 is a plan view illustrating another process of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into semiconductor chips.

FIG. 40 is a cross-sectional view illustrating another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into a semiconductor chip.

FIG. 41 is a cross-sectional view illustrating another step of cutting an ultrathin semiconductor substrate having a MOS transistor according to the embodiment into a semiconductor chip.

FIG. 42 is a cross-sectional view illustrating another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into a semiconductor chip.

FIG. 43 is a plan view for explaining still another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into semiconductor chips.

FIG. 44 is a cross-sectional view illustrating still another step of cutting out the ultrathin semiconductor substrate having the MOS transistor according to the embodiment to a semiconductor chip.

FIG. 45 is a plan view for explaining still another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into semiconductor chips.

FIG. 46 is a cross-sectional view illustrating still another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into a semiconductor chip.

FIG. 47 is a cross-sectional view for explaining still another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into semiconductor chips.

FIG. 48 is a cross-sectional view for explaining still another step of cutting the ultrathin semiconductor substrate having the MOS transistor according to the embodiment into a semiconductor chip.

FIG. 49 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 50 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 51 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 52 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 53 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 54 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 55 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 56 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 57 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 58 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 59 is a cross-sectional view illustrating a step of forming a MOS transistor on a conventional semiconductor substrate.

FIG. 60 is a cross-sectional view illustrating a step of cutting a conventional semiconductor substrate on which a MOS transistor is formed into a semiconductor chip.

FIG. 61 is a cross-sectional view illustrating a step of cutting a semiconductor substrate having a conventional MOS transistor formed into a semiconductor chip.

FIG. 62 is a plan view illustrating a step of cutting a semiconductor substrate on which a conventional MOS transistor is formed into a semiconductor chip.

FIG. 63 is a cross-sectional view illustrating a step of cutting a semiconductor substrate on which a conventional MOS transistor is formed into a semiconductor chip.

FIG. 64 is a cross-sectional view illustrating a step of cutting a conventional semiconductor substrate having a MOS transistor formed into a semiconductor chip.

FIG. 65 is a cross-sectional view illustrating a step of cutting a semiconductor substrate on which a conventional MOS transistor is formed into a semiconductor chip.

[Explanation of symbols]

1 semiconductor chip 2 P-type silicon substrate 3 Ultra-thin semiconductor substrate 4 Placement board 5 joints 28 Semiconductor chip device

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Norito Shimizu             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd.

Claims (22)

[Claims] 1. An ultrathin substrate forming step of forming an ultrathin substrate by thinning the substrate, and a placing step of placing the ultrathin substrate in a fixed state on a placing substrate thicker than the ultrathin substrate. An electronic component forming step of forming an electronic component on the ultrathin substrate fixedly mounted on the mounting substrate, and cutting out the ultrathin substrate on which the electronic component is formed from the mounting substrate The manufacturing method of the electronic device including the extraction process which takes out as an electronic device by. 2. The method of manufacturing an electronic device according to claim 1, wherein the thickness of the mounting substrate is sufficiently thick so that the ultrathin substrate is not damaged in the electronic component forming step. 3. The placing step includes the step of forming a bonding portion to be joined to the ultrathin substrate on the placing substrate.
The method for manufacturing an electronic device according to claim 1. 4. The method of manufacturing an electronic device according to claim 3, wherein the joint portion is formed at a position that does not overlap with the electronic component formed on the ultrathin substrate. 5. The method of manufacturing an electronic device according to claim 3, wherein the bonding portion is formed on a peripheral edge of the mounting substrate. 6. The method of manufacturing an electronic device according to claim 3, wherein the joint portion is formed in an annular shape. 7. The method of manufacturing an electronic device according to claim 3, wherein the joint portion is formed in a dot shape at a predetermined distance from the periphery of the mounting substrate. 8. The method of manufacturing an electronic device according to claim 3, wherein the joint portion is formed in a lattice shape. 9. The method of manufacturing an electronic device according to claim 3, wherein the joint portion is formed in a matrix. 10. The method of manufacturing an electronic device according to claim 3, wherein the bonding portion is formed such that the ultrathin substrate bonded to the bonding portion is in close contact with the placement substrate. 11. The electronic component is a semiconductor element,
The method of manufacturing an electronic device according to claim 1, wherein the electronic component forming step is a semiconductor process. 12. The method of manufacturing an electronic device according to claim 1, wherein the thickness of the mounting substrate is 200 microns or more and 5000 microns or less. 13. The method of manufacturing an electronic device according to claim 1, wherein the ultrathin substrate has a thickness of 0.01 μm or more and 30 μm or less. 14. The method of manufacturing an electronic device according to claim 1, wherein the ultrathin substrate is a semiconductor substrate. 15. The method of manufacturing an electronic device according to claim 1, wherein the ultrathin substrate is a silicon substrate. 16. The ultra-thin substrate forming step forms the ultra-thin substrate by any one of a smart cut method, a hydrogen ion exfoliation method, a rare gas ion exfoliation method, a void cut method and a polishing method. Manufacturing method of electronic device. 17. The placing step is the anodic bonding method, the metal-
The method of manufacturing an electronic device according to claim 1, wherein the ultrathin substrate is mounted on the mounting substrate so as not to move by any one of a semiconductor joining technique method, a laser welding method, and a heat-resistant adhesive method. 18. The method of manufacturing an electronic device according to claim 1, wherein the electronic component is a piezoelectric element. 19. An electronic device manufactured by the manufacturing method according to claim 1. 20. The electronic device according to claim 19, wherein the ultrathin substrate is flexible enough to be attached to a curved base. 21. The ultrathin substrate is attached to a curved base so as to give the electronic component lattice distortion that acts to enhance carrier mobility in the electronic component. Electronic device. 22. An electronic device device in which the electronic device according to claim 19 is laminated, wherein through holes filled with a conductive material are formed in each ultra-thin substrate provided in each laminated electronic device. In the electronic device device, the electronic components formed on the ultra-thin substrates are connected to each other through the conductive material filled in the through holes.