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JP2003218520A - Build-up board and its manufacturing method - Google Patents

Build-up board and its manufacturing method

Info

Publication number
JP2003218520A
JP2003218520A JP2002017623A JP2002017623A JP2003218520A JP 2003218520 A JP2003218520 A JP 2003218520A JP 2002017623 A JP2002017623 A JP 2002017623A JP 2002017623 A JP2002017623 A JP 2002017623A JP 2003218520 A JP2003218520 A JP 2003218520A
Authority
JP
Japan
Prior art keywords
insulating layer
hole
build
glass cloth
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002017623A
Other languages
Japanese (ja)
Inventor
Setsu Ariga
節 有賀
Hideaki Yoshizawa
秀明 吉沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastern Co Ltd
Original Assignee
Eastern Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastern Co Ltd filed Critical Eastern Co Ltd
Priority to JP2002017623A priority Critical patent/JP2003218520A/en
Publication of JP2003218520A publication Critical patent/JP2003218520A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a build-up board, in which there is no trouble due to the generation of a crack in an insulating layer in the case of a high temperature in the build-up board with the insulating layer formed by impregnating glass cloth with a resin, and its manufacturing method. <P>SOLUTION: In the build-up board in which wiring patterns 2 are formed in multilayers through the insulating layers 4 and 6 formed by impregnating the glass cloth 4a and 6a with the resins 4b and 6b and the wiring patterns 2 in upper layers and lower layers are connected electrically through through- holes 10 formed to the insulating layers 4 and 6 or conductor sections 8 formed in via holes 12, cutting sections 16 are formed near the through-holes 10 or the via holes 12 of the glass cloth 4a of the insulating layer 4 adjacent to the insulating layers 4 and 6, to which the through-holes 10 or the via holes 12 are formed. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ビルドアップ基板
とその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a build-up board and a manufacturing method thereof.

【0002】[0002]

【従来の技術】ビルドアップ基板の絶縁層の材料として
は、一般的には樹脂が使用される。しかし、最近、ビル
ドアップ基板の強度を大きくするため、ガラスクロスに
樹脂を含浸させた材料が試みられている。ガラスクロス
に樹脂を含浸させた材料を絶縁層に使用した、従来のビ
ルドアップ基板の例を、図3を用いて説明する。図3
(a)において、Bは従来のビルドアップ基板の一部の
断面図である。6は絶縁層としてのコア基板であり、ガ
ラスクロス6aにエポキシ等の樹脂6bを含浸させて形
成されている。4は、コア基板に積層された絶縁層であ
り、コア基板6と同様、ガラスクロス4aにエポキシ等
の樹脂4bを含浸させて形成されている。2は、コア基
板6または絶縁層4を介して多層に形成された配線パタ
ーンである。10はコア基板6に形成されたスルーホー
ルであり、コア基板6の表裏に形成された配線パターン
2、2は、スルーホール10内に設けられた導体部8を
介して電気的に接続されている。12は、絶縁層4に形
成されたビアホールであり、絶縁層4の上層と下層の配
線パターン2、2は、ビアホール12内に設けられた導
体部8を介して電気的に接続されている。なお、各配線
パターン2および各導体部8は、銅で構成されるのが一
般的である。
Resin is generally used as a material for an insulating layer of a build-up substrate. However, recently, in order to increase the strength of the build-up substrate, a material in which a glass cloth is impregnated with a resin has been tried. An example of a conventional build-up substrate using a material obtained by impregnating glass cloth with a resin for an insulating layer will be described with reference to FIG. Figure 3
In (a), B is a partial cross-sectional view of a conventional build-up substrate. Reference numeral 6 denotes a core substrate as an insulating layer, which is formed by impregnating glass cloth 6a with resin 6b such as epoxy. Reference numeral 4 denotes an insulating layer laminated on the core substrate, and like the core substrate 6, is formed by impregnating the glass cloth 4a with a resin 4b such as epoxy. Reference numeral 2 is a wiring pattern formed in multiple layers via the core substrate 6 or the insulating layer 4. Reference numeral 10 denotes a through hole formed in the core substrate 6, and the wiring patterns 2 and 2 formed on the front and back of the core substrate 6 are electrically connected to each other through a conductor portion 8 provided in the through hole 10. There is. Reference numeral 12 denotes a via hole formed in the insulating layer 4, and the upper and lower wiring patterns 2 and 2 of the insulating layer 4 are electrically connected to each other through a conductor portion 8 provided in the via hole 12. The wiring patterns 2 and the conductor portions 8 are generally made of copper.

【0003】この様な、ガラスクロス6a、4aを含む
絶縁層6、4を持つ多層のビルドアップ基板Bは、基板
の物理的な強度が高い。そのため、例えば、ビルドアッ
プ基板B上の配線パターン2にワイヤボンディングを施
す際、絶縁層4にワイヤを圧接する圧力によって絶縁層
4の樹脂が横に逃げるといった現象が起こりにくく、ワ
イヤボンディングの作業スピードを上げられる等の利点
を有する。
The multilayered build-up substrate B having the insulating layers 6 and 4 including the glass cloths 6a and 4a has a high physical strength. Therefore, for example, when wire bonding is performed on the wiring pattern 2 on the build-up substrate B, the phenomenon that the resin of the insulating layer 4 laterally escapes due to the pressure of pressing the wire against the insulating layer 4 is unlikely to occur, and the wire bonding work speed It has the advantage of being able to raise

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記の
様にビルドアップ基板の絶縁層にガラスクロスに樹脂を
含浸させた材料を用いることにより、ワイヤボンディン
グやはんだリフロー等の工程で高温にさらされた際に、
絶縁層4、6のランド(スルーホール10やビアホール
12の端部)の近傍にクラックが生ずる場合があるとい
う、新たな課題が発生している。絶縁層にクラックが生
じると、クラック内に空気が入って、温度変化によって
膨張収縮を繰り返してクラックが広がるなど、ビルドア
ップ基板Bの故障につながることが多い。
However, as described above, by using a material obtained by impregnating glass cloth with resin for the insulating layer of the build-up substrate, it is exposed to high temperature in the steps such as wire bonding and solder reflow. When
There is a new problem that cracks may occur near the lands of insulating layers 4 and 6 (ends of through holes 10 and via holes 12). When a crack occurs in the insulating layer, air is introduced into the crack and the expansion and contraction are repeated due to a temperature change to spread the crack, which often leads to a failure of the build-up substrate B.

【0005】本発明は上記課題を解決すべくなされ、そ
の目的とするところは、ガラスクロスに樹脂を含浸させ
て形成された絶縁層を有するビルドアップ基板で、高温
時に絶縁層内にクラックが生じることによる故障がない
ビルドアップ基板およびその製造方法を提供することに
ある。
The present invention has been made to solve the above problems, and an object thereof is a build-up substrate having an insulating layer formed by impregnating glass cloth with a resin, and cracks occur in the insulating layer at high temperature. It is an object of the present invention to provide a build-up board and a method for manufacturing the build-up board, which are free from failures.

【0006】[0006]

【課題を解決するための手段】本発明者らは、ビルドア
ップ基板が高温の際、樹脂とガラスクロスの熱膨張率の
差が絶縁層内にストレスを生じさせ、ランドの近傍に前
記クラックを生じさせると考え、鋭意検討して本発明を
完成した。本発明は、上記課題を解決するために、以下
の構成を備える。即ち、ガラスクロスに樹脂を含浸させ
て形成された絶縁層を介して配線パターンが多層に形成
され、上層と下層の配線パターンが絶縁層に形成された
スルーホールまたはビアホール内に設けられた導体部を
介して電気的に接続されたビルドアップ基板であって、
前記スルーホールまたはビアホールが形成された絶縁層
に隣接する絶縁層のガラスクロスの該スルーホールまた
はビアホールの近傍に、切断部が形成されている。ま
た、本発明に係るビルドアップ基板の製造方法は、以下
の構成を備える。即ち、絶縁層に、該絶縁層の下層の配
線パターンに連通するスルーホールまたはビアホールを
形成する工程と、前記スルーホールまたはビアホール内
に、前記絶縁層の上層と下層とを繋ぐ導体部を設ける工
程と、前記絶縁層の表面に配線パターンを形成する工程
と、ガラスクロスに樹脂を含浸させて形成されたプリプ
レグの少なくともガラスクロスに、前記絶縁層に形成さ
れた前記スルーホールまたはビアホールの配置に合わせ
て切断部を形成する工程と、前記プリプレグのガラスク
ロスに形成された切断部を前記絶縁層の前記スルーホー
ルまたはビアホールに位置合わせして、該プリプレグを
該絶縁層の上層に積層する工程とを含む。
The inventors of the present invention have found that when the build-up substrate is at a high temperature, the difference in the coefficient of thermal expansion between the resin and the glass cloth causes stress in the insulating layer, causing the cracks in the vicinity of the land. The present invention has been completed through intensive studies and thought that it would occur. The present invention has the following configuration in order to solve the above problems. That is, a wiring pattern is formed in multiple layers via an insulating layer formed by impregnating glass cloth with a resin, and a conductor portion provided in a through hole or a via hole in which the upper and lower wiring patterns are formed in the insulating layer. A build-up board electrically connected via
A cut portion is formed in the glass cloth of the insulating layer adjacent to the insulating layer in which the through hole or via hole is formed, in the vicinity of the through hole or via hole. Further, the method for manufacturing a buildup substrate according to the present invention has the following configuration. That is, a step of forming a through hole or a via hole communicating with a wiring pattern of a lower layer of the insulating layer in the insulating layer, and a step of providing a conductor portion connecting the upper layer and the lower layer of the insulating layer in the through hole or the via hole. And a step of forming a wiring pattern on the surface of the insulating layer, and at least a glass cloth of a prepreg formed by impregnating a glass cloth with a resin is arranged according to the arrangement of the through hole or the via hole formed in the insulating layer. A step of forming a cut portion by aligning the cut portion formed on the glass cloth of the prepreg with the through hole or via hole of the insulating layer, and stacking the prepreg on the upper layer of the insulating layer. Including.

【0007】上記構成により、クラックの発生を防止で
きる理由は、以下の様に考えられる。ビルドアップ基板
Bは、例えばはんだリフローを行う際などに、240〜
250℃程度の高温となり、絶縁層4、6の樹脂4b、
6bのガラス転移点を超える。特に、最近、環境に対す
る配慮から推奨される鉛フリーはんだを用いる場合に
は、はんだリフローの際に、270℃程度といった、更
なる高温にさらされる。樹脂4b、6bとしてエポキシ
樹脂が使用されている場合、ガラス転移点を超えた場合
の樹脂4b、6bの膨張率は、1℃当たり200ppm
程度となる。一方、配線パターン2や導体部8に使用さ
れる銅の膨張率は1℃当たり16ppm程度であり、ガ
ラスクロス4a、6aも膨張率が非常に小さい。
The reason why the above structure can prevent the occurrence of cracks is considered as follows. The build-up board B is 240-
It reaches a high temperature of about 250 ° C., and the resin 4b of the insulating layers 4 and 6
Exceeds the glass transition point of 6b. Particularly, when using a lead-free solder which has been recently recommended in consideration of the environment, it is exposed to a further high temperature such as about 270 ° C. during solder reflow. When an epoxy resin is used as the resins 4b and 6b, the expansion coefficient of the resins 4b and 6b when the glass transition point is exceeded is 200 ppm per 1 ° C.
It will be about. On the other hand, the coefficient of expansion of copper used for the wiring pattern 2 and the conductor portion 8 is about 16 ppm per 1 ° C., and the coefficient of expansion of the glass cloths 4a and 6a is also very small.

【0008】従って、ビルドアップ基板Bは、前記ガラ
ス転移点を超える高温になった場合に、図3(b)に示
すように変形する。絶縁層4、6の樹脂4b、6bはス
ルーホール10およびビアホール12内の導体部8
(銅)で繋がれた配線パターン2、2(銅)に挟まれて
いるため、樹脂4b、6bが膨張した際には、挟まれた
絶縁層4、6には、その膨張する力に抗する応力90が
働く。また、応力90は、前記挟まれた絶縁層4、6に
隣接する絶縁層4に対しては、前記挟まれた絶縁層4、
6側に引っ張る力として働く。また、応力90によっ
て、前記挟まれた絶縁層4、6に隣接する絶縁層4のガ
ラスクロス4aはスルーホール10およびビアホール1
2側に引っ張られるが、ガラスクロス4aの膨張率が低
いため、ガラスクロス4aがもとの形状に戻ろうとする
応力92が働く。このように、絶縁層4のスルーホール
10およびビアホール12のランドの近傍14には、互
いに逆方向の応力90および応力92が働くことによ
り、絶縁層4の樹脂4bにクラックが生ずるものと考え
られる。
Therefore, the buildup substrate B is deformed as shown in FIG. 3B when the temperature rises above the glass transition point. The resin 4b, 6b of the insulating layers 4, 6 is the conductor portion 8 in the through hole 10 and the via hole 12.
Since it is sandwiched between the wiring patterns 2 and 2 (copper) connected by (copper), when the resins 4b and 6b expand, the sandwiched insulating layers 4 and 6 resist the expanding force. A stress 90 is applied. Further, the stress 90 is applied to the insulating layer 4 adjacent to the sandwiched insulating layers 4 and 6 with respect to the sandwiched insulating layer 4,
It works as a pulling force to the 6 side. Further, due to the stress 90, the glass cloth 4 a of the insulating layer 4 adjacent to the sandwiched insulating layers 4 and 6 has a through hole 10 and a via hole 1.
Although the glass cloth 4a is pulled to the 2nd side, the stress 92 that acts to restore the glass cloth 4a to its original shape acts because the expansion coefficient of the glass cloth 4a is low. As described above, it is considered that the stress 90 and the stress 92 in opposite directions act on the vicinity 14 of the land of the through hole 10 and the via hole 12 of the insulating layer 4 to cause cracks in the resin 4b of the insulating layer 4. .

【0009】そこで、本発明の構成を採ることで、ガラ
スクロスの上記切断部により、絶縁層の樹脂が膨張した
際のガラスクロスの張力が弱められ、前記応力92が小
さくなる。従って、絶縁層のランドの近傍14に掛かる
負荷が小さくなり、前記クラックの発生が抑えられるも
のと考えられる。
Therefore, by adopting the configuration of the present invention, the cut portion of the glass cloth weakens the tension of the glass cloth when the resin of the insulating layer expands, and the stress 92 is reduced. Therefore, it is considered that the load applied to the vicinity 14 of the land of the insulating layer is reduced and the occurrence of the crack is suppressed.

【0010】[0010]

【発明の実施の形態】以下、本発明に係るビルドアップ
基板およびその製造方法の実施の形態を図面に基づいて
詳細に説明する。図1は、本発明に係るビルドアップ基
板の一部の断面図である。なお、図1のビルドアップ基
板Aにおいて、従来のビルドアップ基板Bと同一の部材
については同一の番号を付して説明を省略する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a build-up substrate and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view of a part of a build-up board according to the present invention. In the build-up board A of FIG. 1, the same members as those of the conventional build-up board B are designated by the same reference numerals and the description thereof will be omitted.

【0011】図1(a)に示すように、本発明に係るビ
ルドアップ基板Aは、スルーホール10またはビアホー
ル12が形成された絶縁層4、6に隣接する絶縁層4
の、スルーホール10またはビアホール12に重なる位
置に、切断部16が形成されている。切断部16は、絶
縁層4を厚み方向に貫通する孔状に、スルーホール10
またはビアホール12よりも小径に形成される。なお、
切断部16としての孔の形状は、円状、矩形状等、どの
ような形状に形成してもよい。
As shown in FIG. 1A, the build-up substrate A according to the present invention has an insulating layer 4 adjacent to the insulating layers 4 and 6 having through holes 10 or via holes 12 formed therein.
The cutting portion 16 is formed at a position overlapping the through hole 10 or the via hole 12. The cut portion 16 has a shape of a hole penetrating the insulating layer 4 in the thickness direction, and the through hole 10 is formed.
Alternatively, the diameter is smaller than that of the via hole 12. In addition,
The shape of the hole as the cutting portion 16 may be any shape such as a circular shape or a rectangular shape.

【0012】ここで、切断部16は、必ずしも絶縁層4
を厚み方向に貫通していなくてもよく、少なくともガラ
スクロス4aに形成されていればよい。また、切断部1
6は、必ずしも孔状に形成しなくてもよく、ガラスクロ
ス4aの繊維が切断されて形成されていれば、形状は問
わない。
Here, the cutting portion 16 does not always have to be the insulating layer 4.
Does not have to penetrate in the thickness direction, and may be formed on at least the glass cloth 4a. Also, the cutting unit 1
6 does not necessarily have to be formed in a hole shape, and may have any shape as long as it is formed by cutting the fibers of the glass cloth 4a.

【0013】図1(b)に、このビルドアップ基板A
が、例えばはんだリフローの工程などで、絶縁層4、6
を構成する樹脂のガラス転移点以上の温度に加熱された
際の状態を示す。この場合、絶縁層4、6の樹脂は、従
来のビルドアップ基板Bの場合と同様に膨張する。する
と同様に、絶縁層4、6には応力90が働く。また、応
力90によってガラスクロス4aはスルーホール10お
よびビアホール12側に引っ張られる。この際、切断部
16によって、ガラスクロス4aがもとの形状に戻ろう
とする応力92は非常に小さくなる。従って、絶縁層4
は応力90に従って柔軟に変形し、絶縁層4、6のスル
ーホール10およびビアホール12の近傍14には強い
引っ張り力が働かず、クラックの発生を防止することが
できる。
FIG. 1 (b) shows this build-up board A.
However, for example, in the process of solder reflow, the insulating layers 4, 6
2 shows a state when heated to a temperature equal to or higher than the glass transition point of the resin constituting the. In this case, the resin of the insulating layers 4 and 6 expands as in the case of the conventional buildup board B. Then, similarly, the stress 90 acts on the insulating layers 4 and 6. Further, the stress 90 causes the glass cloth 4 a to be pulled toward the through hole 10 and the via hole 12. At this time, the stress 92 that causes the glass cloth 4a to return to its original shape by the cutting portion 16 becomes extremely small. Therefore, the insulating layer 4
Is flexibly deformed according to the stress 90, a strong tensile force does not act on the vicinity 14 of the through holes 10 and the via holes 12 of the insulating layers 4 and 6, and it is possible to prevent the occurrence of cracks.

【0014】次に、上記ビルドアップ基板Aの製造方法
を、図2を用いて説明する。図2(a)において、6は
絶縁層としてのコア基板であり、ガラスクロス6aにエ
ポキシ等の樹脂6bを含浸させて形成され、表裏に銅箔
24が貼り付けられている。第1の工程では、コア基板
6の所定の位置に、銅箔24をエッチングすると共にコ
ア基板6にレーザー光線18を照射して、コア基板6の
表裏を貫通して結ぶスルーホール10を形成する。
Next, a method for manufacturing the buildup substrate A will be described with reference to FIG. In FIG. 2A, 6 is a core substrate as an insulating layer, which is formed by impregnating glass cloth 6a with resin 6b such as epoxy, and copper foils 24 are attached to the front and back. In the first step, the copper foil 24 is etched and the core substrate 6 is irradiated with the laser beam 18 at predetermined positions of the core substrate 6 to form the through holes 10 penetrating the front and back of the core substrate 6 and connecting them.

【0015】続く第2の工程では、図2(b)に示すよ
うに、コア基板6の両面およびスルーホール10内に、
銅の無電解めっきを施す。さらに、その無電解めっき層
に通電して、無電解めっき層の表面に電解めっき層を形
成する。これにより、コア基板6の両面には銅箔24と
銅めっき層とによって構成された導体層20が形成され
ると共に、スルーホール10内にコア基板6の表裏の導
体層20を結ぶ導体部8が形成される。
In the subsequent second step, as shown in FIG. 2B, both surfaces of the core substrate 6 and the through holes 10 are
Apply electroless plating of copper. Further, the electroless plated layer is energized to form an electrolytic plated layer on the surface of the electroless plated layer. As a result, the conductor layer 20 composed of the copper foil 24 and the copper plating layer is formed on both surfaces of the core substrate 6, and the conductor portion 8 connecting the conductor layers 20 on the front and back sides of the core substrate 6 in the through holes 10. Is formed.

【0016】続く第3の工程では、図2(c)に示すよ
うに、導体層20を、公知の技術を用いて選択的にエッ
チングすることによって、コア基板6の表裏面に配線パ
ターン2を形成する。
In the subsequent third step, as shown in FIG. 2C, the conductor layer 20 is selectively etched using a known technique to form the wiring pattern 2 on the front and back surfaces of the core substrate 6. Form.

【0017】続く第4の工程では、図2(d)に示すよ
うに、プリプレグ22に、スルーホール10の配置に合
わせて切断部としての孔部22cを形成する。プリプレ
グ22は、ガラスクロス22aにエポキシなどの樹脂2
2bを含浸させて形成され、その樹脂22bがBステー
ジまで硬化されたシート状部材であり、配線パターン2
が形成されたコア基板6の表裏面を覆って積層される絶
縁層4の材料となるものである。孔部22cを形成する
方法としては、プリプレグ22にレーザーを照射する方
法を採用するとよい。あるいは、プリプレグ22を打ち
抜き加工することで孔部22cを形成してもよい。いず
れの方法を採った場合でも、孔部22cは、少なくとも
ガラスクロス22aの繊維を切断して形成する。なお、
この第4の工程は、第1〜第3の工程と別工程で、ある
いは、平行して行ってもよい。
In the subsequent fourth step, as shown in FIG. 2D, a hole portion 22c as a cut portion is formed in the prepreg 22 in accordance with the arrangement of the through hole 10. The prepreg 22 includes a glass cloth 22a and a resin 2 such as epoxy.
2b is a sheet-shaped member formed by impregnation with 2b, and the resin 22b is cured to the B stage.
It is a material of the insulating layer 4 which is laminated to cover the front and back surfaces of the core substrate 6 on which is formed. As a method of forming the holes 22c, a method of irradiating the prepreg 22 with a laser may be adopted. Alternatively, the hole 22c may be formed by punching the prepreg 22. Whichever method is used, the hole 22c is formed by cutting at least the fibers of the glass cloth 22a. In addition,
The fourth step may be performed separately from the first to third steps or in parallel.

【0018】続く第5の工程では、図2(e)に示すよ
うに、孔部22cをスルーホール10に位置あわせし
て、プリプレグ22をコア基板の表裏のそれぞれの上層
に積層する。積層されたプリプレグ22は、加熱処理に
よって熱硬化し、絶縁層4となる(図示せず)。
In the subsequent fifth step, as shown in FIG. 2E, the hole 22c is aligned with the through hole 10 and the prepreg 22 is laminated on each of the upper and lower layers of the core substrate. The laminated prepreg 22 is heat-cured by heat treatment to become the insulating layer 4 (not shown).

【0019】その後、配線パターン2を多層に形成する
ために、上記とほぼ同様の工程を繰り返す。即ち、絶縁
層4にレーザー光線でビアホール12を形成し、絶縁層
4の表裏面およびビアホール12内にめっきを施し、絶
縁層4表面のめっき層をエッチングすることで配線パタ
ーン2を形成し、プリプレグ22に絶縁層4に形成され
たビアホール12の配置に合わせて孔部22cを形成
し、孔部22cをビアホール12に位置あわせしてその
プリプレグ22を絶縁層4の表面(上層)に積層し、新
たな絶縁層4を形成するという工程のサイクルを、多数
回繰り返す。
Thereafter, in order to form the wiring pattern 2 in multiple layers, the same steps as above are repeated. That is, the via hole 12 is formed in the insulating layer 4 by a laser beam, the front and back surfaces of the insulating layer 4 and the inside of the via hole 12 are plated, and the plating layer on the surface of the insulating layer 4 is etched to form the wiring pattern 2, and the prepreg 22 A hole portion 22c is formed in accordance with the arrangement of the via hole 12 formed in the insulating layer 4, the hole portion 22c is aligned with the via hole 12, and the prepreg 22 is laminated on the surface (upper layer) of the insulating layer 4. The cycle of the process of forming the different insulating layer 4 is repeated many times.

【0020】この様にすることで、図1(a)に示す様
な、ガラスクロス4aに樹脂を含浸させて形成された絶
縁層4、6を介して配線パターン2が多層に形成され、
上層と下層の配線パターン2が絶縁層4、6に形成され
たスルーホール10またはビアホール12内に設けられ
た導体部8を介して電気的に接続され、スルーホール1
0またはビアホール12が形成された絶縁層4、6に隣
接する絶縁層4のガラスクロス4aのスルーホール10
またはビアホール12の近傍に、切断部16が形成され
ていることを特徴とするビルドアップ基板Aを得ること
ができる。
By doing so, the wiring pattern 2 is formed in multiple layers via the insulating layers 4 and 6 formed by impregnating the glass cloth 4a with a resin as shown in FIG.
The upper and lower wiring patterns 2 are electrically connected to each other through a through hole 10 formed in the insulating layers 4 and 6 or a conductor portion 8 provided in a via hole 12, and the through hole 1
0 or the through hole 10 of the glass cloth 4a of the insulating layer 4 adjacent to the insulating layers 4 and 6 in which the via hole 12 is formed.
Alternatively, it is possible to obtain the buildup substrate A in which the cut portion 16 is formed in the vicinity of the via hole 12.

【0021】なお、ビルドアップ基板Aの製造方法とし
て、本実施形態では、あらかじめ銅箔24が付いたコア
基板6を用いたが、銅箔24などの導体箔がついていな
いコア基板に無電解めっきおよび電解めっきを施すこと
で導体層20を形成する方法を採っても良い。また、プ
リプレグ22としては、表裏面に銅箔などの導体箔がつ
いていないものを用いたが、片面側に銅箔などの導体箔
が付けられたものを積層する方法を採用することもでき
る。
As the method of manufacturing the build-up board A, in this embodiment, the core board 6 having the copper foil 24 attached beforehand was used, but electroless plating is applied to the core board having no conductor foil such as the copper foil 24. Alternatively, a method of forming the conductor layer 20 by performing electrolytic plating may be adopted. Further, as the prepreg 22, the one having no conductor foil such as copper foil attached to the front and back surfaces was used, but a method of laminating one having a conductor foil such as copper foil attached to one side can also be adopted.

【0022】[0022]

【発明の効果】本発明に係るガラスクロスに樹脂を含浸
させて形成された絶縁層を備えるビルドアップ基板およ
びその製造方法によれば、高温時に絶縁層が膨張した際
に、ガラスクロスの張力によって絶縁層内にクラックが
生じることによる故障がないビルドアップ基板を得るこ
とができる。
According to the build-up substrate having the insulating layer formed by impregnating the glass cloth with the resin and the method for manufacturing the same according to the present invention, when the insulating layer expands at a high temperature, the tension of the glass cloth causes It is possible to obtain a build-up substrate that does not have a failure due to the generation of cracks in the insulating layer.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るビルドアップ基板の一部の断面図
であり、(a)は常温の状態、(b)は絶縁層の樹脂の
ガラス転移点を超えた温度の状態を示す。
FIG. 1 is a partial cross-sectional view of a build-up substrate according to the present invention, in which (a) shows a room temperature state and (b) shows a temperature state exceeding a glass transition point of a resin of an insulating layer.

【図2】本発明に係るビルドアップ基板の製造方法を示
す説明図であり、(a)はコア基板にスルーホールを形
成している状態、(b)はコア基板の表面およびスルー
ホール内に導体層および導体部を形成した状態、(c)
は配線パターンを形成した状態、(d)はプリプレグに
切断部を形成した状態、(e)はプリプレグを絶縁層の
上層に積層した状態を示す。
FIG. 2 is an explanatory view showing a method for manufacturing a build-up board according to the present invention, in which (a) shows a state in which through holes are formed in the core board, and (b) shows the surface of the core board and the inside of the through holes. A state in which a conductor layer and a conductor portion are formed, (c)
Shows a state where a wiring pattern is formed, (d) shows a state where a cut portion is formed in a prepreg, and (e) shows a state where a prepreg is laminated on an insulating layer.

【図3】従来のビルドアップ基板の一部の断面図であ
り、(a)は常温の状態、(b)は絶縁層の樹脂のガラ
ス転移点を超えた温度の状態を示す。
FIG. 3 is a cross-sectional view of a part of a conventional build-up substrate, in which (a) shows a state at room temperature and (b) shows a state at a temperature exceeding a glass transition point of a resin of an insulating layer.

【符号の説明】[Explanation of symbols]

A 本発明のビルドアップ基板 B 従来のビルドアップ基板 2 配線パターン 4 絶縁層 4a ガラスクロス 4b 樹脂 6 コア基板 6a ガラスクロス 6b 樹脂 8 導体部 10 スルーホール 12 ビアホール 16 切断部 22 プリプレグ 22a ガラスクロス 22b 樹脂 22c 孔部(切断部) 24 銅箔 A Build-up substrate of the present invention B Conventional build-up board 2 wiring pattern 4 insulating layers 4a glass cloth 4b resin 6 core substrate 6a glass cloth 6b resin 8 conductor 10 through holes 12 beer hall 16 cutting part 22 prepreg 22a glass cloth 22b resin 22c Hole (cutting part) 24 copper foil

フロントページの続き Fターム(参考) 5E317 AA24 BB02 BB12 CC31 CD31 GG05 5E346 AA01 AA12 AA15 AA32 AA38 AA43 BB01 CC02 CC08 CC31 DD02 DD31 EE33 FF04 GG15 GG17 GG28 HH11 Continued front page    F term (reference) 5E317 AA24 BB02 BB12 CC31 CD31                       GG05                 5E346 AA01 AA12 AA15 AA32 AA38                       AA43 BB01 CC02 CC08 CC31                       DD02 DD31 EE33 FF04 GG15                       GG17 GG28 HH11

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ガラスクロスに樹脂を含浸させて形成さ
れた絶縁層を介して配線パターンが多層に形成され、上
層と下層の配線パターンが絶縁層に形成されたスルーホ
ールまたはビアホール内に設けられた導体部を介して電
気的に接続されたビルドアップ基板であって、 前記スルーホールまたはビアホールが形成された絶縁層
に隣接する絶縁層のガラスクロスの該スルーホールまた
はビアホールの近傍に、切断部が形成されていることを
特徴とするビルドアップ基板。
1. A wiring pattern is formed in multiple layers with an insulating layer formed by impregnating glass cloth with a resin, and wiring patterns of upper and lower layers are provided in through holes or via holes formed in the insulating layer. A build-up substrate electrically connected via a conductor part, wherein a cut portion is formed in the vicinity of the through hole or via hole of the glass cloth of the insulating layer adjacent to the insulating layer in which the through hole or via hole is formed. A build-up substrate characterized by being formed.
【請求項2】 絶縁層に、該絶縁層の表裏を結ぶスルー
ホールまたはビアホールを形成する工程と、 前記スルーホールまたはビアホール内に、前記絶縁層の
上層と下層とを繋ぐ導体部を設ける工程と、 前記絶縁層の表面に配線パターンを形成する工程と、 ガラスクロスに樹脂を含浸させて形成されたプリプレグ
の少なくともガラスクロスに、前記絶縁層に形成された
前記スルーホールまたはビアホールの配置に合わせて切
断部を形成する工程と、 前記プリプレグのガラスクロスに形成された切断部を前
記絶縁層の前記スルーホールまたはビアホールに位置合
わせして、該プリプレグを該絶縁層の上層に積層する工
程とを含むことを特徴とするビルドアップ基板の製造方
法。
2. A step of forming a through hole or a via hole connecting the front and back of the insulating layer in the insulating layer, and a step of providing a conductor portion connecting the upper layer and the lower layer of the insulating layer in the through hole or the via hole. A step of forming a wiring pattern on the surface of the insulating layer, and at least a glass cloth of a prepreg formed by impregnating a glass cloth with a resin, in accordance with the arrangement of the through hole or the via hole formed in the insulating layer. And a step of forming a cut portion, aligning the cut portion formed on the glass cloth of the prepreg with the through hole or the via hole of the insulating layer, and laminating the prepreg on an upper layer of the insulating layer. A method for manufacturing a build-up board, comprising:
JP2002017623A 2002-01-25 2002-01-25 Build-up board and its manufacturing method Pending JP2003218520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002017623A JP2003218520A (en) 2002-01-25 2002-01-25 Build-up board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002017623A JP2003218520A (en) 2002-01-25 2002-01-25 Build-up board and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2003218520A true JP2003218520A (en) 2003-07-31

Family

ID=27653246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002017623A Pending JP2003218520A (en) 2002-01-25 2002-01-25 Build-up board and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2003218520A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112526653A (en) * 2015-07-31 2021-03-19 索尼半导体解决方案公司 Lens substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112526653A (en) * 2015-07-31 2021-03-19 索尼半导体解决方案公司 Lens substrate

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