JP2003218245A - Method of manufacturing non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that there is a deterioration of transistor characteristics and of a scaling property due to the influence by nitrogen in an ordinary MOS transistor section. <P>SOLUTION: A non-volatile semiconductor memory device comprises a memory transistor having such a structure that a first gate electrode 30a is formed on a semiconductor 10 where a channel is formed, via a first gate dielectric film SI which comprises a plurality of dielectric films 21 and 22 of different compositions and has an electric charge accumulating capacity; and a peripheral transistor having such a structure that a second gate electrode 30a' is formed on a different part of the semiconductor 10, via a second gate dielectric film 21a' having no electric charge accumulating capacity. If there is a heating process using gases such as nitrogen in the middle of formation of the multilayer dielectric film SI (for example, a thermal nitriding process for suppressing an incubation time) in the manufacture of the non-volatile semiconductor memory device, the heating process is performed after a nitrogen stop film (41: not shown in the figure) for protecting the peripheral transistor is formed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor transistor in which a gate dielectric film has a plurality of laminated films having a charge storage ability and a peripheral transistor whose gate dielectric film has no charge storage ability in the same semiconductor. The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having different locations above.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device, the threshold voltage of a storage element is shifted depending on the presence or absence of charges existing in a charge storage means (conductor or charge trap level) formed in a dielectric film, and after the shift. The threshold voltage value of is associated with the write and read signals.

For example, electrons are stored in the charge storage means of a non-volatile semiconductor memory device, and the storage element is an NMO.
If S, then the threshold voltage has shifted in the positive direction. At the time of reading, a voltage is applied to the corresponding memory cell, but since the threshold voltage is higher than this applied voltage due to the electrons stored in this charge storage means, no current flows in the bit line or it flows. hard. vice versa,
When electrons are not stored in the charge storage means or when holes are stored, the threshold voltage shifts in the negative direction, so that a current flows through the bit line at the gate voltage during reading or It becomes easy to flow. This current “flows”
Or "easy to flow", "no flow" or "difficult to flow",
In other words, the basic operation principle of the non-volatile semiconductor memory device is to associate the large and small currents (including 0) with the logic "0" and "1" of the stored data.

One of the storage elements is a MONOS (M) which has a charge storage film made of a nitride film sandwiched between oxide films from above and below.
There is an et al-Oxide-Nitride-Oxide-Semiconductor) type memory transistor. FIG. 1A is a cross-sectional view showing the configuration of a non-volatile memory in which the MONOS type memory transistor and peripheral circuit transistors (including not only memory peripheral circuits but also logic circuit transistors and the like) are integrated on the same substrate. It is a figure. In the figure, the memory transistor is formed in the region on the left side. A first dielectric film 21a made of, for example, silicon oxide is formed on a P-type well (hereinafter, P well) 11 of the semiconductor substrate 10 separated by the dielectric separation layer 20. First dielectric film 21
A second dielectric film 22a made of, for example, silicon nitride is formed on a, and a third dielectric film 23a made of, for example, silicon oxide is further formed thereon. A laminated dielectric film SI having a charge storage function is formed from these first to third dielectric films. On the upper layer of the third dielectric film 23a, a gate electrode 30a made of, for example, doped polycrystalline silicon is formed. An LDD (Lightly Doped Drain) diffusion layer 14 containing a low concentration of N-type impurities and a source / drain diffusion layer 15 containing a high concentration of N-type impurities are formed in the semiconductor substrate 10 on both sides of the gate electrode 30a. ing. This memory transistor is an n-channel type field effect transistor having a laminated dielectric film SI between the gate electrode 30a and the channel formation region in the semiconductor substrate 10. An interlayer insulating film 25 made of, for example, silicon oxide is formed to cover the gate electrode 30a, a contact hole reaching the source / drain diffusion layer 15 is opened, and a source / drain electrode 31 is formed.

Peripheral circuit transistors are formed in the region on the right side of FIG. Dielectric isolation layer 20
The gate dielectric film 21 made of, for example, silicon oxide is formed on the P well 11 ′ of the semiconductor substrate 10 separated by
a'is formed, and a gate electrode 30a 'made of, for example, doped polycrystalline silicon is formed thereon. Further, in the semiconductor substrate 10 on both sides of the gate electrode 30a ', the LDD diffusion layer 14' containing a low concentration of N-type impurities.
And a source / drain diffusion layer 15 'containing a high concentration is formed. Further, an interlayer insulating film 25 made of, for example, silicon oxide is formed so as to cover the gate electrode 30a ′, a contact hole reaching the source / drain diffusion layer 15 ′ is opened, and the source / drain electrode 31 is formed.
'Is formed.

In the MONOS type memory transistor having the above structure, the laminated dielectric film SI is composed of the second dielectric film 2
Charge trap (bulk trap) in the bulk of 2a,
It has a function of holding charges in a charge trap (interface trap) formed at the interface between the second dielectric film 22a and the third dielectric film 23a. Gate electrode 30a, semiconductor substrate 1
By applying an appropriate voltage to the source / drain diffusion layer 15 and the semiconductor substrate 10, the Fowler
A Nordheim (FN) tunneling current is generated, electrons are injected from the P well 11 into the laminated dielectric film SI through the first dielectric film 21a, and this is conducted by the electric field formed by the above voltage and trapped by the trap. . Alternatively, conversely, electrons are emitted from the laminated dielectric film SI to the P well 11 through the first dielectric film 21a.

The above memory transistors are arranged in a matrix N
An equivalent circuit diagram of a memory cell array operably connected is shown in FIG. For example, the gate electrode of the memory transistor of cell 1 is connected to word line WL1, and the source / drain diffusion layers are connected to bit lines BL1a and BL1b, respectively. Further, the gate electrode of the memory transistor of the cell 2 is connected to the word line WL1, and the source / drain diffusion layers are connected to the bit lines BL2a and BL2b, respectively. In this way, the memory transistors connected to each line are connected in a NOR-type matrix to form a memory array.

A method of manufacturing a nonvolatile semiconductor memory device having the MONOS type memory transistor will be described with reference to the drawings. 9 (a) to 11 (h),
FIG. 6 is a cross-sectional view of a nonvolatile semiconductor memory device formed by a conventional manufacturing method.

As shown in FIG. 9A, a dielectric isolation layer 20 made of silicon oxide is formed on the silicon semiconductor substrate 10 by, for example, the LOCOS method. here,
The active region on the left side of the drawing separated by the dielectric isolation layer 20 is the memory transistor forming region, and the active region on the right side of the drawing is the peripheral circuit transistor forming region.

The peripheral circuit transistor formation region is protected by a resist film or the like, and impurity ion implantation for adjusting the threshold voltage or ion implantation for forming a well is performed in the memory transistor formation region. As a result, as shown in FIG. 9B, for example, the P well 11 is formed only in the memory transistor formation region.

As shown in FIG. 9C, a silicon oxide film is formed on the entire surface by, for example, a thermal oxidation method to form a first dielectric film 21.

As shown in FIG. 10D, for example, CV
By D (Chemical Vapor Deposition) method, the first dielectric film 21 on the active region is covered and silicon nitride is deposited on the entire surface to form the second dielectric film 22.

As shown in FIG. 10E, the entire surface of the second dielectric film 22 is thermally oxidized by, for example, a thermal oxidation method to form a silicon oxide film, and a third dielectric film 23 is formed.

As shown in FIG. 10 (f), for example, CV
Doped polycrystalline silicon is deposited on the third dielectric film 23 by the D method, the resist film is patterned by a photolithography process, and etching such as RIE (reactive ion etching) is performed to form the gate electrode 30a. To do. At this time, the laminated dielectric film SI including the first dielectric film 21a, the second dielectric film 22a, and the third dielectric film 23a, which has a charge storage function, is simultaneously processed in the same pattern as the gate electrode. .

As shown in FIG. 11 (g), the memory transistor formation region is protected by a resist film and subjected to etching such as RIE to form a first peripheral circuit transistor formation region.
The dielectric film 21, the second dielectric film 22, and the third dielectric film 23 are removed to expose the semiconductor substrate 10 in the peripheral circuit transistor formation region.

The memory transistor formation region is protected by a resist film or the like, and impurities are ion-implanted in the peripheral circuit transistor formation region to adjust the threshold voltage, or ions are formed to form a well or the like. As a result, as shown in FIG.
'Is formed. For example, a silicon oxide film is formed on the entire surface by a thermal oxidation method, and a gate dielectric film 21 'for peripheral circuit transistors is formed. At this time, also in the memory transistor formation region, P on both sides of the gate electrode 30a is formed.
A silicon oxide film is also formed on the surface of the well 11 and the surface of the gate electrode 30a. For example, doped polycrystalline silicon is deposited by a CVD method and patterned by a photolithography process to form a gate electrode 30a 'for a peripheral circuit transistor. Next, ion implantation is performed using the gate electrodes 30a and 30a 'as masks to form LDD diffusion layers 14 and 14' containing N-type impurities at a low concentration.

In the subsequent steps, for example, silicon oxide is deposited by the CVD method and etched back to form a side wall dielectric film (not shown) on the sides of the gate electrode 30a and the gate electrode 30a '. Is used as a mask to perform ion implantation to form source / drain diffusion layers 15 and 15 'containing N-type conductive impurities at a high concentration. As a result, memory transistors and peripheral circuit transistors are formed. After that, for example, by CVD, these transistors are covered and silicon oxide is deposited on the entire surface to form an interlayer insulating film 25.
A contact hole reaching the drain diffusion layers 15 and 15 'is opened. For example, a conductive film such as an aluminum alloy is deposited by a sputtering method and patterned to form the source / drain electrodes 31, and the basic structure of the nonvolatile semiconductor memory device shown in FIG. 1A is completed.

[0018]

In this conventional method of manufacturing a non-volatile semiconductor memory device, a nitride film such as silicon nitride is used as the second dielectric film when the laminated dielectric film SI of the MONOS type memory transistor is formed. Need to be formed. As a forming method at this time, for example, a mixed gas of dichlorosilane (DCS) and ammonia NH ₃ is used, and the substrate temperature is set to a value higher than 600 ° C. to perform CVD of the silicon nitride film.

At this time, when the underlying layer is silicon oxide or the like, if a second dielectric film such as silicon nitride having a different composition is attempted to be deposited on it by CVD, a first certain time is spent for nucleation of silicon nitride. , There are times when the growth rate is extremely low. This is called an incubation time, which varies depending on the surface condition of the underlying layer, so that the CVD film thickness controllability is impaired. Therefore, in order to suppress this incubation time, it is usually necessary to thermally nitrid the surface of the first dielectric film (for example, a silicon oxide film) before forming the second dielectric film (for example, a silicon nitride film). is there. For example, the substrate temperature is about 800 ° C to 100
While maintaining the temperature at 0 ° C., the surface of the silicon oxide film is exposed to ammonia NH ₃ for several tens of minutes to nitride the surface of the silicon oxide film. This thermal nitriding treatment generally nitrids a silicon surface layer of several tens nm, and in some cases, several μm, depending on the conditions.

The introduction of nitrogen into such a substrate is particularly problematic except in the memory section. That is, in the peripheral transistor portion, it is necessary to remove the ONO film (storage dielectric film SI) in the step of FIG. 11G and reattach the gate oxide film 21 ′ in the next step of FIG. 11H. However, at this time, the growth of the thermal oxide film is hindered by the presence of nitrogen atoms. Further, since the amount of nitrogen atoms varies, the thermal oxide film thickness varies. As a result, there are disadvantages such that the threshold voltage of transistors other than the memory transistor (for example, memory peripheral circuits, logic transistors, etc.) fluctuates, or mobility decreases.

In order to avoid such a disadvantage, before forming the gate oxide film of the peripheral circuit or the logic transistor,
A sacrificial oxidation and sacrificial oxide film removing step is inserted, and the surface of the silicon substrate is thinly shaved to take measures such as removing the effect of nitriding. Since this sacrificial oxide film is removed by wet etching, the silicon surface layer consumed during sacrificial oxidation is etched uniformly and without leaving any damage. However, the operations added to this normal process include various things such as (1) increase in mask process, (2) decrease in element isolation film thickness during wet etching, and (3) deterioration in scaling property due to increase in heat process. Cause more problems.

An object of the present invention is to provide a non-volatile semiconductor memory device in which, in addition to a non-volatile memory transistor, a normal MOS transistor is integrated on the same substrate. This is to prevent the increase of the manufacturing cost and improve the transistor characteristic and the scaling property.

[0023]

A non-volatile semiconductor memory device according to a first aspect of the present invention is to solve the above-mentioned problems and has a different composition on a semiconductor in which a channel is formed. A memory transistor in which a first gate electrode is laminated with a first gate dielectric film having a plurality of dielectric films and having a charge storage capacity interposed, and a memory transistor formed at different locations on the same semiconductor as the memory transistor. A method for manufacturing a non-volatile semiconductor memory device, comprising: a peripheral transistor having a second gate electrode stacked with a second gate dielectric film having no charge storage capability interposed between the first gate dielectric and the peripheral transistor. When there is a heating process using a gas containing nitrogen in the process of stacking the dielectric films forming the film, a nitrogen blocking film for protecting the peripheral transistor is formed,
The heating process is performed.

In this manufacturing method, a nitrogen blocking film is formed,
For example, the nitrogen blocking film in the memory portion is selectively removed using lithography and etching techniques. In this case, one more photomask is added and heated to some extent when the nitriding stop film is formed, but at this time, it does not require a temperature as high as the thermal oxidation of the substrate in the conventional sacrificial oxidation method. Further, since a stress relaxation buffer layer such as a dielectric film (for example, a silicon oxide film) can be previously provided under the nitrogen blocking film, the nitrogen blocking film can be removed by dry etching.
Therefore, there is no need for a wet etching step and the element isolation film thickness does not decrease.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described below with reference to the drawings. FIG. 1A is a cross-sectional view of the nonvolatile memory device according to this embodiment, which has the same structure as the conventional example.

In the figure, a memory transistor is formed in the left region. P-type well (hereinafter, P-well) 1 of the semiconductor substrate 10 separated by the dielectric separation layer 20
A first dielectric film 21a made of, for example, silicon oxide is formed on the first dielectric film 21a. On the first dielectric film 21a,
A second dielectric film 22a made of, for example, silicon nitride is formed, and a third dielectric film 23a made of, for example, silicon oxide is further formed thereon. The first to third dielectric films form a laminated dielectric film SI having a charge storage capability.

On the upper layer of the third dielectric film 23a, a gate electrode 30a made of, for example, doped polycrystalline silicon is formed. Further, in the semiconductor substrate 10 on both sides of the gate electrode 30a, LDD containing a low concentration of N-type impurities.
A (Lightly Doped Drain) diffusion layer 14 and a source / drain diffusion layer 15 containing a high concentration are formed. This memory transistor has a laminated dielectric film SI between the gate electrode 30a and the channel formation region in the semiconductor substrate 10.
It is an n-channel type field effect transistor having.
An interlayer insulating film 25 made of, for example, silicon oxide is formed to cover the gate electrode 30a, a contact hole reaching the source / drain diffusion layer 15 is opened, and a source / drain electrode 31 is formed.

On the other hand, peripheral circuit transistors are formed in the region on the right side of FIG. P well 11 ′ of the semiconductor substrate 10 separated by the dielectric separation layer 20
A gate dielectric film 2 made of, for example, silicon oxide
1a 'is formed, and a gate electrode 30a' made of, for example, doped polycrystalline silicon is formed thereon. Further, in the semiconductor substrate 10 on both sides of the gate electrode 30a ', the LDD diffusion layer 14' containing a low concentration of N-type impurities.
And a source / drain diffusion layer 15 'containing a high concentration is formed. Further, an interlayer insulating film 25 made of, for example, silicon oxide is formed so as to cover the gate electrode 31a ′, a contact hole reaching the source / drain diffusion layer 15 ′ is opened, and the source / drain electrode 31 is formed.
'Is formed.

In the memory transistor having the above structure, the laminated dielectric film SI includes the charge traps (bulk traps) in the bulk of the second dielectric film 22a and the second dielectric film 22a and the third dielectric film 22a. It has a function of retaining charges in a charge trap (interface trap) formed at the interface of the film 23a. By applying an appropriate voltage to the gate electrode 30a, the source / drain diffusion layer 15 in the semiconductor substrate 10, and the semiconductor substrate 10, a Fowler-Nordheim (FN) tunneling current is generated, and the first dielectric film 2 is formed.
Electrons are injected from the P-well 11 into the laminated dielectric film SI through 1a, and the electrons are conducted by the electric field formed by the voltage and trapped by the trap. Or vice versa,
Electrons are emitted from the laminated dielectric film SI to the P well 11 through the first dielectric film 21a.

The memory transistors are arranged in a matrix form N
An equivalent circuit diagram of a memory cell array operably connected is shown in FIG. For example, the gate electrode of the memory transistor of cell 1 is connected to word line WL1, and the source / drain diffusion layers are connected to bit lines BL1a and BL1b, respectively. Further, the gate electrode of the memory transistor of the cell 2 is connected to the word line WL1, and the source / drain diffusion layers are connected to the bit lines BL2a and BL2b, respectively. In this way, the memory transistors connected to each line are connected in a NOR type matrix,
Configure a memory array.

When charges are accumulated in the above-mentioned laminated dielectric film SI, an electric field is generated by the accumulated charges, so that the threshold voltage of the memory transistor changes. This change makes it possible to store data. For example, when electrons are accumulated in the laminated dielectric film SI of the cell 1, and the memory transistor is an n-channel type, the threshold voltage thereof is shifted in the positive direction. At the time of reading, a voltage is applied to the gate electrode (word line WL1) of the corresponding memory cell, but since the threshold voltage of the memory transistor is higher than the applied voltage due to the charges accumulated in this laminated dielectric film SI, No current flows between the bit lines BL1a and BL1b. On the contrary, when holes are accumulated in the laminated dielectric film SI, the threshold voltage of the memory transistor is shifted in the negative direction, so that a current flows between the bit lines BL1a and BL1b at the gate voltage during reading. 1-bit binary data can be stored by associating "current" and "current not flow" with the logic "0" and "1". Alternatively, if the threshold distribution width is divided into a plurality of values, it is possible to make multi-value. From the above, the laminated dielectric film SI
Data can be written to and read from the field-effect transistor having the.

In erasing, the accumulated charge is FN tunneled,
It is pulled out to the substrate side by direct tunneling or some other method, or charges of opposite polarity are injected. As a result, the threshold voltage of the memory transistor shifts to a low level in the erased state. This erasing is usually done in a batch of memory cell arrays,
Although predetermined sub-array units of the memory cell array are collectively performed, it is possible to erase each bit.

A method of manufacturing the nonvolatile semiconductor memory device having the above memory transistor will be described with reference to the drawings. 2A to 5L are cross-sectional views of the nonvolatile semiconductor memory device manufactured by the manufacturing method according to the present embodiment in the process of being manufactured.

As shown in FIG. 2A, a dielectric isolation layer 20 made of silicon oxide is formed on the silicon semiconductor substrate 10 by, for example, the LOCOS method. here,
The active region on the left side of the drawing separated by the dielectric isolation layer 20 is the memory transistor forming region, and the active region on the right side of the drawing is the peripheral circuit transistor forming region.

The peripheral circuit transistor formation region is protected by a resist film or the like (not shown), and impurities are ion-implanted in the memory transistor formation region for adjusting the threshold voltage, or ions are formed to form a well or the like.
As a result, as shown in FIG. 2B, for example, the P well 11 is formed only in the memory transistor formation region.

As shown in FIG. 2C, a stress relaxation buffer layer 40 made of a silicon oxide film or the like is formed on the entire surface by, for example, a thermal oxidation method. This silicon dioxide film thickness is a film necessary as needed when the nitrogen blocking film to be formed next is made of silicon nitride or the like, and the film thickness is not limited, but a relatively thin film for that purpose. Is enough.
Subsequently, as shown in FIG. 3D, for example, a silicon nitride film is deposited as the nitrogen blocking film 41. This nitrogen blocking film thickness is generally at least 2 to 3 nm or more, and more preferably 4 nm or more, although it depends on the conditions of the thermal nitriding treatment on the memory transistor side described later. In order to control the etching at the time of removal with good control, a thicker film,
For example, 10 nm or more is more desirable. The nitrogen blocking effect of the nitrogen blocking film 41 will be described later.

As shown in FIG. 3E, a resist film R1 covering the peripheral transistor forming region is formed by photolithography, and these films 4 are formed by a dry etching method or a wet etching method using the resist film R1 as a mask.
0 and 41 are selectively removed in the memory transistor formation region.

After removing the resist film R1, in the step of FIG. 3F, a film to be a laminated dielectric film having a charge storage capacity of the memory transistor is sequentially formed. First, as the first dielectric film 21, a silicon oxide film (so-called tunnel oxide film in the case of FN tunneling operation) is formed by, for example, a method of thermally oxidizing the surface of the substrate. The thickness of the first dielectric film 21 is not limited, but is, for example, 0.5 to 3.5.
Generally, about nm. Next, for the purpose of suppressing the so-called incubation time, the first dielectric film 21 is
The surface of is heat-nitrided. Although this processing condition is arbitrary, for example, the surface of the silicon oxide film (first dielectric film 21) is exposed to ammonia NH ₃ for several tens of minutes while the substrate temperature is kept at about 800 ° C. to 1000 ° C. The surface of the silicon oxide film is nitrided. Then, the second dielectric film 22 that functions as a charge storage layer is deposited. Second dielectric film 22
In this example, a silicon nitride film, a silicon oxynitride film, or a silicon fluoride nitride film is used in this example. Alternatively, it may be a laminated film of these films. These films have a total thickness of, for example, about 2 to 10 nm and are deposited by the CVD method. For example, when depositing silicon nitride, dichlorosilane (DCS)
And a substrate gas temperature of 73 by using a mixed gas of ammonia and NH _3.
The temperature of the silicon nitride film is set to about 0 ° C. and CVD is performed. Finally, the entire surface of the second dielectric film 22 is thermally oxidized by, for example, a thermal oxidation method to form a silicon oxide film with a thickness of, for example, 3 nm to
Form about 5 nm. Thereby, the third dielectric film 23
Is formed. By the formation of these laminated films,
In the peripheral circuit transistor region, the nitrogen blocking film is thickened (reference numeral 41 '), and a silicon oxide film is formed on the surface thereof.

In the step shown in FIG. 4G, for example, CV
Doped polycrystalline silicon is deposited on the third dielectric film 23 by the D method, the resist film is patterned by photolithography, and etching such as RIE (reactive ion etching) is performed to form the gate electrode 30a. .

As shown in FIG. 4H, a resist film R2 covering the memory transistor formation region is formed by photolithography, and all films 40 on the substrate are formed by a dry etching method or a wet etching method using the resist film R2 as a mask. , 41 ', 23 are selectively removed in the peripheral circuit transistor formation region. At this time, the final silicon oxide film 40 serving as the stress relaxation buffer layer may be removed by wet etching in order to reduce substrate damage. However, even in this case, the film thickness of the dielectric isolation layer 20 is reduced because the film thickness is extremely thin. There is almost no. Subsequently, while the memory transistor formation region is protected by the same resist film R2, ion implantation of impurities for adjusting the threshold voltage or ion implantation for forming a well or the like is performed in the peripheral circuit transistor formation region. As a result, FIG.
As shown in (h), for example, a P well 11 'is formed.

In the step of FIG. 4I, a silicon oxide film is formed on the entire surface by, for example, a thermal oxidation method to form a gate dielectric film 21 'for peripheral circuit transistors. At this time, a silicon oxide film is also formed on the surface of the gate electrode 30a in the memory transistor formation region.

In the step of FIG. 5 (j), doped polycrystalline silicon is deposited by, for example, a CVD method and patterned by a photolithography step to form a gate electrode 30a 'for a peripheral circuit transistor.

Next, RIE or the like is performed using the gate electrode 30a 'and the gate electrode 30a of the memory transistor formed previously as a mask. As a result, FIG.
As shown in FIG. 3, a laminated dielectric having a gate dielectric film 21 ′ of a peripheral circuit transistor, a first dielectric film 21 a, a second dielectric film 22 a, and a third dielectric film 23 a and having a charge storage capability. The body film SI is simultaneously processed in the same pattern as the gate electrode.

As shown in FIG. 5L, the gate electrode 30
a, the gate electrode 30a 'is used as a mask for ion implantation,
LDD diffusion layers 14, 14 containing a low concentration of N-type impurities
To form ´.

In the subsequent steps, for example, silicon oxide is deposited by the CVD method and etched back to form a side wall dielectric film (not shown) on the side portions of the gate electrode 30a and the gate electrode 30a '. Is used as a mask to perform ion implantation to form source / drain diffusion layers 15 and 15 'containing N-type conductive impurities at a high concentration. As a result, memory transistors and peripheral circuit transistors are formed. After that, for example, by CVD, these transistors are covered and silicon oxide is deposited on the entire surface to form an interlayer insulating film 25.
A contact hole reaching the drain diffusion layers 15 and 15 'is opened. For example, a conductive film such as an aluminum alloy is deposited by a sputtering method and patterned to form the source / drain electrodes 31 and 31 '.
The basic structure of the nonvolatile semiconductor memory device shown in is completed.

In this method of manufacturing a non-volatile memory device,
Nitrogen blocking film (and stress relaxation buffer layer) film forming process (FIGS. 2 (c) and 3 (d)), photolithography and etching process (FIG. 3 (e)), etching process (FIG. 4 (h)) The effect of the thermal nitriding process at the time of forming the memory transistor can be prevented on the peripheral transistor side only by adding The photolithography process of FIG. 4 (h) is originally necessary to form the well 11 ', and is not an additional process.

FIG. 6 shows the nitrogen concentration of the single crystal silicon substrate.
Shows the results of preliminary experiments that investigated the relationship between the
It is a graph. In addition, FIG. 7 was used in this preliminary experiment.
A graph showing the nitrogen concentration on the substrate surface of various samples in comparison.
It is. From the graph of Fig. 6, the oxidation conditions aiming at 19 nm
And the substrate nitrogen concentration is 1 × 10^{Two 0}cm^-3Acid from nearby
The oxide film thickness starts to decrease and the nitrogen concentration of the substrate is 1 × 10²¹c
m ^-3If it exceeds, the film thickness will decrease by 10 to 30%.
I understand. Further, as can be seen from the graph of FIG.
Applied sample A (thickness of nitrogen blocking film 41: 10 n
m) is a reference sensor that has not been thermally nitrided at all.
The nitrogen concentration is similar to that of the sample D. This allows
It can be confirmed that the nitrogen blocking film 41 is functioning effectively.
It was At this time, the sample A is treated with a nitrogen blocking measure or a sacrificial acid.
When compared with Samples B and C that were not subjected to
The plate nitrogen concentration is reduced to more than one digit and nearly two digits.

By using the manufacturing method of the present invention, it is possible to effectively prevent the deterioration or variation in the oxidation rate of the peripheral circuit transistors, the accompanying decrease in the threshold voltage, and the decrease in the mobility. It became possible to form in the circuit area. Further, the addition of the above-mentioned steps does not significantly increase the cost from the viewpoint of the whole steps. Furthermore, since it is possible to reduce the film thickness of the dielectric isolation layer and suppress the increase in the total heating amount (thermal budget), it is possible to realize a memory-embedded LSI having excellent scaling properties.

The structure and manufacturing method of the non-volatile semiconductor memory device of the present invention are not limited to the above embodiments.
For example, in the above description, the method of forming the gate electrodes of the transistors in the memory portion and the other portions separately is described, but the laminated dielectric film SI of the memory portion and the gate dielectric film 21 'of the peripheral circuit portion are formed. After that, it is possible to form the gate electrodes 30a and 30a 'at the same time.

Further, the above-mentioned silicon dioxide film which is the stress relaxation buffer layer and the silicon nitride film which is the nitrogen blocking film may be left in a part of the element isolation region or the like due to the mask alignment margin. Alternatively, if the mask alignment margin is not taken, etching may progress through the gap due to the alignment shift, and a part of the dielectric isolation layer may be dug. FIG. 8A shows a state where a part of the laminated film remains on the dielectric isolation layer, and FIG. 8B shows a state where the surface portion of the dielectric isolation layer is slightly dug. It should be noted that such a trace of application of the present invention can be seen in FIG.
This is caused by misalignment of lithography when forming the resist film R2 in (h).

The memory transistor structure is not limited to the MONOS type, but may be a so-called MNOS type. Further, although the gate electrodes 30a and 30a 'have one layer, they may have a multilayer structure such as polycide. The source / drain diffusion layer may have a structure other than the LDD structure. Further, the cell array system of the semiconductor memory device may be any one of an AND type, a DINOR type, a NAND type in addition to the NOR type. The injection of charges into the charge storage layer may correspond to either data writing or data erasing. The charge injection method is also not limited to FN tunneling. Besides, various modifications can be made without departing from the scope of the present invention.

[0052]

According to the method of manufacturing a non-volatile semiconductor memory device of the present invention, in the non-volatile semiconductor memory device in which a normal MOS type transistor other than the non-volatile memory transistor is integrated on the same substrate, a normal MOS type By using a simple method, it is possible to prevent the influence of nitrogen on the transistor portion, and it is possible to improve the transistor characteristics and the scaling property while suppressing an increase in manufacturing cost as much as possible.

[Brief description of drawings]

FIG. 1A is a cross-sectional view of a nonvolatile semiconductor memory device according to an embodiment of the present invention and a conventional example. (B) is an equivalent circuit diagram of four memory cells of the nonvolatile semiconductor memory device.

FIGS. 2A to 2C are cross-sectional views in manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention, showing up to formation of a stress relaxation buffer layer.

3 (d) to (f) are cross-sectional views in a process following FIG. 2 (c), showing up to formation of a laminated dielectric film of a memory transistor.

4 (g) to (i) are cross-sectional views in a step following FIG. 3 (f) showing up to formation of a gate dielectric film of a peripheral circuit transistor.

5 (j) to (l) are cross-sectional views in a step following FIG. 4 (i) showing up to formation of an LDD diffusion layer.

FIG. 6 is a graph showing the results of a preliminary experiment in which the relationship between the nitrogen concentration of a single crystal silicon substrate and the reoxidized film thickness was investigated.

FIG. 7 is a graph showing a comparison of the nitrogen concentrations on the substrate surface of various samples used in the preliminary experiment, showing the effect of the present invention.

8A is a cross-sectional view showing a state where a part of a laminated film remains on a dielectric isolation layer and FIG. 8B is a state where a surface portion of the dielectric isolation layer is slightly dug.

9A to 9C are cross-sectional views in manufacturing a conventional nonvolatile semiconductor memory device, showing up to formation of a first dielectric film.

10 (d) to (f) are cross-sectional views in a process following FIG. 9 (c), showing up to the gate processing of the memory transistor.

11 (g) and 11 (h) are cross-sectional views in a process following FIG. 10 (f), showing up to the formation of the LDD diffusion layer.

[Explanation of symbols]

10 ... (Silicon) semiconductor substrate, 11, 11 '... P well, 14 ... LDD diffusion layer, 15 ... Source / drain diffusion layer, 20 ... Dielectric isolation layer, 21, 21a ... First dielectric film, 22, 22a ... 2nd dielectric film, 23, 23a ... 3rd dielectric film, 25 ... Interlayer insulation film, 30 ... Conductive film used as a gate electrode, 30a ... Gate electrode, 31, 31 '... Source / drain electrodes, 40 ... Stress relaxation buffer layer, 4
1 ... Nitrogen blocking film, R1, R2 ... Resist film, SI ... Stacked dielectric film, BL1a etc .... Bit line, WL1 etc .... Word line

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 EP18 EP23 EP63 EP68 ER03                       ER14 ER22 ER23 JA19 JA32                       PR03 PR05 PR12 PR15 PR21                       PR29 PR45 PR55 ZA07                 5F101 BA45 BB05 BC02 BD02 BD33                       BE02 BE05 BE07 BH02 BH03                       BH06 BH14 BH15 BH19 BH21

Claims (7)

[Claims] 1. A first semiconductor device comprising a plurality of dielectric films having different compositions on a semiconductor on which a channel is formed and having a charge storage capability.
A memory transistor in which a first gate electrode is laminated with a gate dielectric film interposed, and a second gate dielectric film formed at a different location on the same semiconductor as the memory transistor and having no charge storage capability on the semiconductor. A method for manufacturing a non-volatile semiconductor memory device having a peripheral transistor having a second gate electrode stacked with a nitrogen film interposed, wherein nitrogen is added during a process of stacking a dielectric film forming a first gate dielectric film. When there is a heating process using a gas containing
A method for manufacturing a non-volatile semiconductor memory device, comprising forming a nitrogen blocking film for protecting peripheral transistors and performing the heating step. 2. The method according to claim 1, wherein the nitrogen blocking film is formed on the peripheral transistor portion on the semiconductor, and the semiconductor exposed in the memory transistor portion is heated by using the gas containing nitrogen. Forming a gate dielectric film; removing all films on the semiconductor including the nitrogen blocking film in the peripheral transistor section; and forming the second gate dielectric film on the semiconductor exposed in the peripheral transistor section 2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising the step of: and a step of forming the first gate electrode and the second gate electrode individually or collectively. 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the nitrogen blocking film is made of silicon nitride. 4. The step of forming the first gate dielectric film includes the step of forming a first dielectric film on the semiconductor, and the step of forming a first dielectric film on the first dielectric film. 3. The method for manufacturing a non-volatile semiconductor memory device according to claim 2, further comprising the step of forming second dielectric films having different compositions by a chemical vapor deposition method. 5. The first dielectric film is formed after the formation of the first dielectric film.
5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, further comprising the step of subjecting the surface of the dielectric film to nitriding treatment by heating with a gas containing nitrogen. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the second dielectric film is made of one or a plurality of materials selected from silicon nitride, silicon oxynitride, and silicon fluoronitride. 7. The method for manufacturing a non-volatile semiconductor memory device according to claim 3, further comprising the step of forming a stress relaxation buffer layer between the nitrogen blocking film and the semiconductor when the nitrogen blocking film may directly contact the semiconductor. .