JP2003218180A - Wafer-level burn-in and test - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for performing a wafer-level burn-in and test. <P>SOLUTION: The technique includes a test substrate 108 having active electronic components 106 and metallic spring contact elements 110 for connections with a plurality of devices-under-test (DUTs) 102 on a wafer-under-test 104. The test substrate 108 receives a plurality of signals for testing the DUTs 102 over relatively few signal lines from a host controller 116 and transmits these signals over relatively many interconnections between the test substrate 108 and the DUTs 102. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

[Cross Reference to Related Applications] This patent application has a common ownership and is pending US patent application Ser. No. 08 / 452,255 filed May 26, 1995 (hereinafter referred to as “original patent application”). )) And its corresponding PCT Patent Application No. US95 / 14909 filed on November 13, 1995, both of which have common ownership, 1994 A continuation-in-part application of pending US patent application Ser. No. 08 / 340,144 filed November 15, and its corresponding PCT patent application US94 / 13373 filed November 16, 1994, In addition, all of these have a common owner, 19
Pending US Patent Application No. 08/1 filed November 16, 1993
52,812 (currently U.S. Pat.No. 5,476,211, December 1995 1
9 days), part of the continuation-in-part application, all of which are incorporated herein by reference.

This patent application is also a continuation-in-part of the following pending US patent applications with common ownership.

No. 08 / 526,246 filed September 21, 1995 (PCT
/ US95 / 14843, November 13, 1995), No. 08 / 533,584 1995
Filed on October 18, (PCT / US95 / 14842, November 13, 1995),
No. 08 / 554,902 Submitted on November 09, 1995 (PCT / US95 / 14844,
No. 08 / 558,332, filed Nov. 15, 1995 (PCT / US95 / 14885, Nov. 15, 1995), No. 08 / 573,945.
Issued December 18, 1995 (PCT / US96 / 07924, May 24, 1996)
No. 08 / 602,179 Submission February 15, 1996 (PCT / US96 /
08328, May 28, 1996), No. 60 / 012,027 February 2, 1996
One day submission (PCT / US96 / 08117, May 24, 1996), No. 60/01
No. 2,040 Submission February 22, 1996 (PCT / US96 / 08275, 1996
May 28), No. 60 / 012,878 filed March 05, 1996 (PCT /
US96 / 08274, May 28, 1996), No. 60 / 013,247 1996
Submitted on March 11 (PCT / US96 / 08276, May 28, 1996), 6th
No. 0 / 005,189 Submitted May 17, 1996 (PCT / US96 / 08107,199
May 24, 6). All of these (except the provisional patent application) are continuation-in-part applications of the above-referenced original patent application, all of which are incorporated herein by reference.

This patent application is also a continuation-in-part of the following pending US patent applications with common ownership: That is, Khandros and Peders, submitted November 13, 1996.
No. 06 / 030,697 by en and No. 06 / -tbd- by Khandros and Pedersen, submitted on December 13, 1996.

[0005]

FIELD OF THE INVENTION The present invention relates generally to testing semiconductor devices, and more particularly to performing known good die (KGD) testing and burn-in. More specifically, (they are separated into one, or "chip")
Related to testing semiconductor devices at the wafer level (prior to being done).

[0006]

Semiconductor devices are manufactured by performing a series of long processing steps, such as etching, masking, coating, etc., on a silicon wafer, from the microprocessor to the memory chips. A typical silicon wafer is in the shape of a disk with a diameter of 6 inches or more. Many semiconductor devices, which are generally identical to one another, are fabricated on a single silicon wafer by regularly arranging them in a rectangular array. Cut lines (scribe streets) are located between adjacent semiconductor devices on the wafer. Finally, the semiconductor device (hereinafter, also simply referred to as a device) is cut along the scribe street and separated from the wafer.

Some of the devices do not work as designed because of defects in the wafer or in one or more processing steps. These defects may appear early or may only become apparent after the devices have been operating for a long period of time. Therefore, it is important to test and electrically test devices over an extended period of time to see which devices are good and which are bad.

In general, semiconductor devices end another long series of "back-end" processing steps that separate (separate) the devices from the wafer and assemble them into a final "packaged" form. After being tested for the first time (burned-in and tested).

"Overall", a typical prior art "back end" process flow is as follows (starting with wafer fabrication):

Wafer screening part 1, Laser Repair, Wafer screening part 2, Wafer Saw, Chip bonding, Wire bonding, Encapsulation, Lead adjustment and formation, Package assembly steps such as lead plating, Electrical testing, burn-in, electrical testing, product marking and product shipping.

Current semiconductor devices often include hundreds of terminals (ie, "pads" for power, ground, input / output, etc.), and current semiconductor wafers are
Often, it contains hundreds of semiconductor devices, resulting in each wafer having tens of thousands of pads, or test points, that can be tested and / or tested at the wafer level before the semiconductor device is separated from the wafer. Or it needs to be accessed to burn-in (ie test all devices at once). Precise alignment is also an important issue when dealing with cases where the spacing (pitch) between adjacent pads is as close as 4 mils . Nevertheless, performing testing and / or burn-in on semiconductor devices prior to separating the semiconductor devices from the wafer has long been an attempt to overcome.

US Pat. No. 5,570,032 (Atkins et al., "Mic
ron Patent ”; 10/96), a wafer scale burn-in apparatus and process.
and process) in which a burned-in wafer (14) uses small conductive posts (15) on a printed circuit board to electrically contact pads on each chip of the wafer. Printed circuit board (1
3). Precise alignment of the entire wafer with the printed circuit board allows all chips on the wafer to be tested simultaneously, eliminating the need to inspect each chip individually Needed for. The device is attached to heating elements and cooling channels to generate the required wafer temperature for burn-in and testing. By using this technique, it is possible to eliminate the processing of defective chips that burn-in and testing cannot cover. FIG. 1 of the "Micron patent" shows an overall overview of the processing steps according to the prior art from wafer production to removal and shipment. "Mi
Figure 8 of the "cron patent" shows the disclosed wafer scale burn-in and test.
from the manufacture of the wafer when using d testing)
The outline of the processing steps corresponding to this before taking out and shipping is shown. In the "Micron patent",
It has been suggested that it is also possible to have less connection and control logic (microprocessors, multiplexers, etc.) on the printed circuit board and to include complete test electronics on the printed circuit board.

US Pat. No. 5,532,610 (Tsujide, et al. "NE
C Patent ", 7/96) discloses an apparatus for testing semiconductor wafers. The device includes a test substrate, active circuitry disposed on the test substrate for activating (activating) chips disposed on the wafer under test, and a plurality of pads disposed on the surface of the test substrate. And these pads are arranged to align with the bonding pads of the chips located on the wafer when the test substrate is overlaid on the wafer. The test substrate (2) can be a wafer and can be made of the same material as the wafer (1) to be tested. On the test substrate (wafer) (2), a lead wire 7 extends from the pad 4 and is connected to a power supply, a ground (ground) wire 8, one I / O wire 9, and a chip selection wire 10. In Figure 4 of "NEC Patent",
Shown is a test device 16 made from a silicon wafer, the back of which has a square pyramid shaped opening.
21 has been etched. This opening can serve as a mark of alignment,
This facilitates alignment of the test substrate (16) with the wafer (17) to be tested.

US Pat. No. 5,434,513 (Fujii et al., "Rohm
Patent ”; 7/95), an intermediate semiconductor wafer (inter
A semiconductor wafer test apparatus using a mediate semiconductor wafer is disclosed. In this device, a bump electrode is formed on the bottom surface of an intermediate semiconductor wafer used as a test substrate, and a pickup electrode and a control electrode are on the upper side of the test substrate. It is formed on the surface (opposite side). A switch circuit is formed on the intermediate semiconductor wafer, and this circuit connects the electrode selected from the bump electrodes to the pickup electrode according to the switching control signal supplied from the tester via the control electrode. To function. The pickup electrode and the control electrode are connected to the tester via a pogo pin.

US Pat. No. 5,497,079 (Yamada, et al., "Ma
tsushita Patent ”; 3/96), semiconductor test equipment,
A semiconductor test circuit chip and a probe card are disclosed. Here, a large number of semiconductor test chips (2)
Are mounted on one side of the motherboard (4), and a number of likewise semiconductor integrated circuit chips (1) to be tested are mounted on the other side of the motherboard (4). A computer (3) is provided to control the semiconductor test chip (2). The computer (3) for collecting the test results can be a low cost computer, since most of the test functions are built into the test circuit chip (2).
5, 7 and 10 of "Matsushita Patent" show a test pattern generation means, a driver for giving a test pattern to a device to be tested, a data storage means, and whether stored output data indicates a failure state. Shown is a typical semiconductor test circuit chip (2) having decision means for making a decision and means for transferring the decision result to a workstation. `` Matsushita P
FIG. 12 of "atent" shows the structure of a semiconductor test device used in a wafer test, in which a large number of semiconductor test chips (2) are connected to a probe card (10).
3) and attached to the wafer (106) to be tested, a plurality of probe needles (104) extend from the probe card (possibly from the opposite surface of the probe card). When the control signal is transferred from the workstation to the semiconductor test circuit chip, the semiconductor test chip starts the test of the semiconductor integrated circuit formed on the semiconductor wafer.

[0016] In general, conventional attempts to implement techniques for performing wafer level testing provide a number of contact elements on a test substrate for contacting corresponding pads on the wafer being tested. I needed it. As mentioned above, this may require tens of thousands of such contact elements and highly complex interconnect substrates. As an example, an 8-inch wafer can contain 500 16Mb DRAMs, each with 60 bond pads, resulting in a total of 30,00.
Has 0 connections. 30,0 for wafer under test (WUT)
There are 00 connections, 30,000 additional connections to the intermediate board, another 30,000 connections to the test electronics, and an undetermined number of connections to the control electronics. In addition, the current fine pitch requirements of semiconductor devices require maintaining extremely precise tolerances when aligning a test substrate with a wafer to be tested.

[0017]

It is an object of the present invention to provide an improved technique for performing wafer level burn-in and testing.

It is an object of the present invention to enable a series of wafer level processing steps that result in a finished device with physical properties and levels of reliability that are superior to those of the prior art. Therefore, the manufacturing cost of the semiconductor is reduced.

[0019]

According to the invention, semiconductor devices are tested at the wafer level before they are separated from the silicon wafers from which they are manufactured. As used herein, the phrase "exercise" includes, but is not limited to, performing burn-in and functional tests on semiconductor devices. Many pressure connections
is made between many unisolated semiconductor devices under test (DUTs, DUTs) on the wafer under test (WUT) and the test substrate, but springs are used to make the pressure connection between them. Contact element (spring contact ele
ment) is used. The spring contact elements are preferably attached by their base directly to the WUT (ie, the DUTs on the WUT) so that they have free ends extending toward a common plane on the surface of the WUT. The test board should have a coefficient of thermal expansion that closely matches that of the WUT. Alternatively, the spring contact element is attached to the test board.

According to one aspect of the invention, the spring contact elements are arranged on the WUT so that they are wider at the tip than at the base, ie with a larger pitch. The spring contact element is a suitable composite interconnect element, as described in the original patent application.

In one embodiment of the invention, the test board is
It consists of a relatively large interconnect board and a number of relatively small boards mounted and connected to the interconnect board, each smaller board having a size (area) larger than one size (area) of the DUTs. Is small. A small substrate is placed on the surface (facing the WUT) of the interconnect (support) substrate. Making one small board larger than an individual DUT and "mate" with more than one DUT.
s) ”is also possible. Small substrates are suitable active semiconductor devices such as application specific integrated circuits (ASICs, ASICs).

The design of the ASIC depends on the external sources (eg
It is possible to minimize the number of signals supplied to the test board from the host controller).

In the case of spring contact elements mounted on DUTs, it is desirable that the tips of the spring contact elements be widened so that they are more spaced apart than their mounted bases, and the ASIC relaxes alignment tolerances. Therefore, it is provided with a capture pad (terminal) that can be made large.
The tips of the spring contact elements are expandable and are located in a region that is smaller than and within the area of the DUT to which they are attached. DUT
The ASIC for testing the is sized to correspond to the area of the tip of the spring contact element.

In one embodiment of the invention, the ASICs are provided with indentations in their upper surface. Each recess houses the tip of a corresponding spring contact element attached to the DUT. These depressions are
It can be formed directly on the surface of the ASIC or it can be provided by a layer disposed on the surface of the ASIC. After housing the tip, the ASIC can be moved laterally or rotated (in a plane) to engage the tip of the spring contact element with the side of the recess.

According to one aspect of the invention, a number of ASICs
Means are provided to ensure that s is accurately aligned with the interconnect (supporting) substrate. The means has a recess on the backside of the ASIC, a recess corresponding to the upper surface of the interconnect substrate, and further has a sphere located between the ASIC and the interconnect substrate.

According to one aspect of the invention, the test board is
It is kept below the temperature of the WUT. This allows the WU to accelerate burn-in without adversely affecting the average life of the ASICs mounted on the interconnect board.
The DUT on T can be raised to a higher temperature. If the coefficient of thermal expansion of the test board closely matches the coefficient of thermal expansion of the WUT, the amount of thermal expansion of the test board will be trivial and much smaller than that of the WUT. The large temperature difference between the WUT and the test board causes the entire device (WU
It can be easily held by inserting T and the test board).

In use, the test substrate is placed in contact with the WUT at room temperature. The capture properties (capture properties, eg, depressions) of the upper surface of the ASIC allow the spring contact elements to be held in place.
Then the DUT is powered up (powered to the DUT). Due to the vacuum environment, the heat from the activated DUT is ASI
Prevents heating of C, which causes the ASIC to
It is possible to operate at a temperature much lower than the burn-in temperature of.

In accordance with one aspect of the present invention, the signal for testing the DUT is transmitted over a relatively small number of lines in a first format, such as serial stream data, to a plurality of sources by an external source (host controller). A second, such as an individual signal for each of a relatively large number of spring contact elements provided to the ASIC that contacts the DUT.
Is converted to the format. Alternatively, at least some of the signals for testing the DUT can be generated within the ASIC rather than provided by an external host controller.

According to one aspect of the invention, the ASIC can store (record) test results from the DUT for subsequent transfer to the host controller. This information (test results) can be used to characterize each DUT on each substrate. In addition, based on the test results from the DUT, the ASIC can further test and / or test the DUT that fails the critical test.
Or you can stop burning.

In another embodiment of the invention, the ASIC is fabricated directly on the silicon wafer rather than mounted on it. Defective
Redundancy is provided so that the ASICs or portions thereof can be electrically replaced with each other.

An advantage of the present invention is that each "type" of ASIC can be individually designed to accommodate (combine) to a particular type of DUT, which can be inexpensively manufactured. is there.

Conventional burn-in techniques require placing the DUT in a convection oven to raise the temperature of the DUT. In the context of the present invention, exposing the ASIC to such repeated heating cycles is generally undesirable. Conversely, according to the present invention, the DUT and ASIC are brought into contact with each other and the DUT is powered up (powered on) to perform the burn-in. This results in heat being generated by the DUT, but in most cases this heat is sufficient to meet the temperature rise requirements of the DUT without the need for another heat source.

According to another aspect of the invention, the assembly of the DUT and test board (interconnect board plus ASIC attached to it) is placed in a vacuum environment and the only heat the ASIC receives is the ASIC and There will be a small amount of heat conducted to the ASIC along the spring contact element that creates the electrical connection between the DUTs. The DUT board and test board are
Is in contact with a liquid cooled chuck,
The liquid in this chuck is going to another controller. The DUT board is brought to a high temperature, which is typically higher than the temperature that can be imparted to the packaged components, and the test board allows for the electrically advanced operation of advanced testers. It is kept at room temperature or lower than room temperature.

An advantage of the present invention is that the DUT is in indirect contact with the ASIC and the interconnect board supporting the ASIC is a very low density wiring board that receives very few signals from the host controller. , And the ASIC itself produces most of the very large number of signals (eg, 30,000) needed to test a large number of DUTs on a WUT.

An advantage of the present invention is that it confirms the operation of the DUT over a wide temperature range from well below room temperature to the maximum temperature allowed in semiconductor processing without thermally stressing the ASIC. It means that you can

The present invention provides the enabling technology for a complete wafer level assembly process.

Other objects, features and advantages of the present invention will become apparent by consideration of the following description thereof.

[0038]

Reference will now be made in detail to the examples of the preferred embodiments of the present invention, which are illustrated in the accompanying drawings. While the present invention is described in the context of these preferred embodiments, it is to be understood that it is not intended to limit the spirit and scope of the invention to these particular embodiments. Should be.

Referring to FIG. 1A, an apparatus 1 for performing a wafer level burn-in and test method in accordance with the present invention.
Indicates 00. The wafer under test (WUT) is
Semiconductor devices 102a, 102 formed above (generally referred to herein as elements 102).
b, 102c, 102d are placed (contained) on a suitable support, such as a temperature controlled vacuum chuck 104, facing upwards (as shown).

Many (four of which are shown) relatively small active electronic components 106a, 106b, 106c, such as application specific integrated circuits (ASICs, commonly referred to as elements 106), and 106d
Is attached to a relatively large interconnect substrate (base slab) 108 that is typically the same size (ie, the same diameter) as WUT 102. For example, interconnect substrate 108 and WUT 102 are both 8 inches or 12 inches in diameter. The electronic component (ASIC) 106 and the interconnect substrate 108 together form a "test board".

The WUT 102 comprises a number of semiconductor devices 102 (of which four are shown) to be tested.
a, 102b, 102c, 102d, that is, devices under test (DUTs).

A number of spring contact elements 110 (four of which are shown) are attached by their bases to the front (top as shown) surface of each DUT, and to the top surface of the DUT. It has a tip that extends to the upper common plane. These spring contact elements are suitable, but are self-supporting as in the original patent application,
It is not limited to elongated, compound interconnect elements.

During use, the test board (106, 108)
The tip of the spring contact element 110 is
Pressure-contact electrical connection to a corresponding terminal (capture pad) 120 (see FIG. 1D) on the upper surface of 106.
Until they are connected in a predetermined alignment (with respect to each other). Accurate alignment can be reliably ensured by the guide pins 112 arranged on the periphery of the WUT and the test board. (The diameter of the interconnect substrate can be larger than the diameter of the WUT, and the guide pins can pass through the corresponding guide holes in the interconnect substrate). A properly placed compression stop (block ring) 114 on the surface of the WUT will displace the tip of the spring contact element 110 when displaced, ie when displaced relative to the capture pad 120. Limit the distance.

As shown in FIG. 1A, the host computer 116 connects to the ASIC 1 via the interconnect board 108.
Signal to 06. These signals are test signals for testing multiple DUTs. Since the DUTs on the WUT are generally identical to each other, a single set of test signals (vectors) can be generated for multiple DUTs.
Alternatively, test vectors are generated by individual ASICs under the overall control of the host computer. The power (eg, Vdd and Vss) is also the power source 118.
Through the ASIC 106 to the DUT as appropriate (eg, directly through the ASIC).

Interconnect substrate 108 is essentially a wiring (interconnect) substrate, preferably a silicon wafer having the same coefficient of thermal expansion as WUT 102. ASIC1
06 is suitably coupled to the interconnect substrate by a bond wire extending between the surface of the ASIC (bottom as shown) and the surface of the support substrate (top as shown).

An important feature of the present invention is that there is a direct connection (by the spring contact element 110) between the DUT and the ASIC. This is where most of the connections in the overall system are made, and as will be explained in more detail below, very few connections need to be made within the interconnect substrate (108) itself. Direct connection between the ASIC and the DUT is facilitated by placing the ASIC on the DUT-side surface (front surface) of the interconnect board. For example, tens of thousands (eg, 30,000) connections to the DUT are placed via the interconnect board (ie, not on the ASIC, but on the interconnect board, regardless of where the ASIC is placed). Tens of thousands of connections, if made by some type of spring contact element), must pass through the interconnect substrate. As will be explained in more detail below, these tens of thousands of signals can be directly generated by the ASIC itself and sent to the DUT as very few (eg, four) signals. This signal is sent from the host controller to the ASIC through the interconnect board.

WUT 102 and test board 106/108
Is a hermetic communication with a vacuum source (not shown) so that the techniques of the present invention can be performed in at least partial vacuum conditions, including high vacuum conditions, or other controlled air conditions. Appropriately placed in container 130. As mentioned above, vacuum conditions are convenient for thermally isolating the DUT from the ASIC.

According to a feature of the invention, the test substrate 106
/ 108 WUT1 this test board during burn-in
Temperature controlled chuck (corresponding to 104) so that it can be maintained at a temperature that is completely independent of the 02 temperature (typically well below the temperature of the WUT).
4a is attached. Broadening the Tip of the Spring Contact Element As mentioned above, current semiconductor devices often include a large number of bond pads arranged at a fine pitch of approximately 4 mils. Spring contact element (1
10) are attached by their bases to the bond pads of the DUT. If the spring contact element is DU
If they were evenly protruding from T (eg, parallel to each other), their tips would also be 4 mil pitch and alignment of the corresponding capture pads on the ASIC would be difficult.

As shown in FIG. 1B, each DUT, eg, DUT
102a has a number of bond pads 107 (of which 24 are shown) arranged along the centerline of the DUT (shown as squares in the figure). Freestanding spring contact element (110)
Are attached to their respective bond pads and are typically placed at a 90 degree angle to the centerline of the DUT. As shown in FIG. 1B, the spring contact elements can be arranged not only with alternating lengths but also extending in opposite directions. For example, the first spring contact element 110a is relatively long and extends a first distance from the centerline of the DUT 106 in a first direction, and the second spring contact element 110b is relatively long, Extending a first distance from the centerline of the DUT 106 in a second direction opposite the first direction, the third spring contact element 110c is relatively short and extends from the centerline of the DUT 106 in the first direction. The second spring contact element 1 extends over a second distance which is shorter than the first distance.
10d is relatively short and extends a second distance from the centerline of the DUT 106 in the second direction.

As best shown in FIG. 1B, the tips of the spring contact elements 110 (shown as circles) are all located in an area smaller than the area (within the outer edge) of the DUT 106a. The small area is the area of the corresponding ASIC 106a, the outer edge of which is represented by the dotted rectangle. With this approach, it is easy to make the pitch (spacing) of the free ends (tips) of the spring contact elements 110 larger (rougher) than the pitch of the bond pads (107) of the DUT to which they are attached.

It is within the scope of the invention to tuck the tip of the spring contact element into a smaller area than that shown by the dotted rectangle of FIG. 1B, for example to accommodate a smaller DUT.

FIG. 1C is a schematic perspective view of the DUT 102a of FIG. 1B with the tip of the base of the spring contact element 110 located along the centerline of the DUT.

An advantage of the present invention is that the "capture" (bond) pad 1 on the ASIC 106 is shown in FIG. 1D.
20 can be made larger (than the size of the bond pad 107 on the DUT), which can relax the tolerance limits on the positioning of the tip of the spring contact element (110).

The original patent application describes several ways in which a resilient interconnect element can be attached to a semiconductor device while the pitch is widened between the base of the interconnect element and its tip. Has been done.

The interface between the test board and the WUT is shown as having one ASIC for each DUT, each ASIC being aligned with a corresponding DUT. It is also within the scope of the invention that other relationships can be established. For example, as shown in FIG. 1E, one ASIC 126 (its outer edge is shown as a dotted rectangle) has two adjacent DUTs 102.
It can "straddle" a and 102b.

An important feature of the present invention is that the ASIC (10) is located as close as possible to the DUT (102), ie, on the DUT side of the interconnect substrate (108).
It means that it is easy to provide 6) as a product with built-in functions. This has many favorable consequences. Significantly less signal needs to be provided from the host computer 116 to the interconnect board 108, and further less signal needs to pass through the interconnect board. By relaxing the limitation of transmitting signals in the interconnection board in this way, the degree of freedom in the material, design and realization of the interconnection board is greatly increased, and as a result, the cost can be reduced. ASIC
The close proximity to the DUT and the direct connection between them facilitates testing the DUT at high speeds, avoiding undesirably long signal paths.

As mentioned above, any spring contact element can be utilized to make the pressure connection between the ASIC and the DUT.

It is also within the scope of the invention that the spring contact element be attached to the ASIC rather than the DUT. This is shown in FIG. 2, in which many (of which four are shown) spring contact elements 210 (corresponding to 110) have their ASICs 206 (which correspond to Mounted on the DUT 202 (corresponding to 106), and the tip (end) of the spring contact element 210 is
It is arranged for pressure connection to a corresponding bond pad (not shown) on the top (corresponding to 102). Ie AS
Any suitable means for achieving a connection between an IC and DUT can be utilized to implement the techniques of this invention. ASIC and DUT other than spring contact elements
It is also within the scope of the present invention that it can be utilized to provide a connection between, which is not limited to microbumps and the like. As discussed above for capturing the leading end portion of the spring contact element, the distal end portion of the spring contact elements attached to the DUT, by pressing the corresponding capture pads on the ASIC, briefly "capture (ca
It has been shown that the tolerance limits can be relaxed by making pitch expansion on the spring contact elements and by making the capture pad on the ASIC larger. Other techniques for achieving the connection between the tip of the spring contact element and the ASIC are described below.

FIG. 3A illustrates the tip of a spring contact element 310 (which corresponds to 110) attached to a DUT 302 (which corresponds to 102), which is attached to the ASIC.
The basic embodiment of capturing is shown with a capture pad that is a bond pad 308 (which corresponds to 120) located on the surface of 306 (which corresponds to 106).

In accordance with an aspect of the present invention, a geometric "capture" feature is formed in or on the surface of the ASIC to secure the tip of the spring contact element during burn-in and testing. Can be reliably aligned with the ASIC.

FIG. 3B shows an interconnection substrate (not shown, 108).
AS of one of many ASICs installed in
An IC 326 (which corresponds to 106), a DUT 322 (which corresponds to 102a) of one of many DUTs, and a technique for securely pressurizing the two are shown. As in the previous example, many spring contact elements 330 (which correspond to 110) are attached to and extend from the surface of the DUT 322 by their bases. In this example, the spring contact elements are arranged such that their tip (end) pitch is greater (rougher) than their base pitch.

A large number of wells (two of which are shown) 328 of a suitable shape of a pyramid having at least three sides extend into the ASIC 326 from its surface. These depressions 328, like the other depressions described below, are micromachined.
ng) and can be easily formed using conventional semiconductor manufacturing techniques.

Metallic coatings (not shown) are applied to the sides of these recesses 328 to allow electrical communication with active elements (not shown) of ASIC 326.

During use, the ASIC 326 and DUT 322 are attracted so that the tip of the spring contact element 330 enters the recess 328, after which the ASIC is moved laterally slightly (across the page as shown). Moving or rotating (around a vertical axis on the page) ensures that the tips of the spring contact elements 330 are on the sides of the indentations 328 and make the electrical pressure connection between them. Engage (engage) with sufficient force to
You can be sure that.

An alternative technique for capturing (engaging) the tips of spring contact elements is shown in FIG. 3C. In this case, ASIC 346 (which corresponds to 326) comprises a number of pads (terminals) 344 (two of which are shown) formed on its surface in a conventional manner. The layer 350 made of an insulating material such as a silicon chip (silicon die) is used as the ASIC 34.
6 is disposed on the surface of 6 but extends through this layer and is aligned with the contact pad 344,
A lot of openings 3 (two of which are shown)
Micromachined to have 48 (which corresponds to 328). That is, this alternative technique
Rather than forming depressions (328) directly on the surface of (346), a separate superposition structure 350 provides an equivalent capture feature (34).
8) is provided. Similar to the previous example, the sides of the capture feature 348 can be metallized and the ASIC can be DU (not shown).
Move or rotate laterally to T to move ASI
C346 and spring contact element 340 (this is
(Corresponding to 330) can be ensured. The silicon die 350 may be an insulating nitride.

It should be understood that the means on the ASIC that are contacted by the tip of the spring contact element must be robust. For this purpose, for example, the capture pad (120 or 308 or 344) is protected (eg, plated) with a conductive material such as nickel that is resistant to 0.5 to 1.0 mils wear. be able to. Similarly, the depressions (capture features) 328 can be protected with an equivalent amount of nickel. Aligning Small Boards to Interconnect Boards As mentioned above, many electronic components, such as ASICs, are desired to be attached to larger interconnect boards. This avoids the need to make good active devices on the entire surface of the interconnect substrate. (That is, in the case of a silicon wafer interconnect substrate, the ASIC circuitry is
Can be incorporated directly on a silicon wafer). Clearly, a proper mechanism must be provided to ensure that many ASICs are accurately aligned with the interconnect board.

FIG. 4 illustrates a number of ASICs 406 (one of which is shown) 106, 206, 3
06, 326 and 346) to ensure accurate alignment with the larger interconnect substrate 408 (which corresponds to 108).
00 is shown. In this case, each ASIC40
On the back surface of 6 (top surface in the figure), the above-mentioned recess 32 is formed.
At least 2 in a similar manner to 8 and 348
Two (only two shown) recesses 412 are created, which are of a suitable pyramid shape that extend into the back of the ASIC 406. These dimples 412
Can be lithographically defined and formed to close tolerances using conventional semiconductor manufacturing techniques.

Equal depressions 414 form the interconnection substrate 40.
8 surface (bottom surface as shown). The interconnect substrate is a suitable semiconductor wafer as described above. These depressions 414 can likewise be formed using conventional semiconductor manufacturing techniques to have tight tolerances (which correspond to 306).

The indentations 412 and 414 are of a size ("width (breadt)" measured across the surface of the ASIC 406 or the surface of the interconnect substrate 408 on which they are formed, respectively.
h) ”each has. The width of the ASIC depression 412 is
Desirably, it is the same width as the recess 414 in the interconnect substrate and both are in the range of 3-5 mils , such as 4 mils .

To assemble the ASIC 406 onto the interconnect substrate 408, a small sphere (ball, spherical element) 42 having a diameter equal to the width of the recesses 412 and 414.
A zero is placed between the recess 412 and the corresponding recess 414 to ensure accurate placement of the ASIC 406 on the surface of the interconnect substrate 408. The diameter of the ball 420 is preferably slightly larger than the size (width) of the indentations 412 and 414, eg, 2 ± 1 mils , and the backside of the ASIC 406 (top side as shown) and the interconnect substrate 408. There will be a small size controlled gap to the surface (bottom surface as shown). For example, the size of the gap (vertical in the figure), 2
It is in the 5 mil range.

A suitable thermally conductive adhesive (not shown) is preferably placed in the gap (ie, between the ASIC and the opposing surface of the interconnect substrate) to secure the ASIC to the interconnect substrate. It An example of a suitable adhesive is silver-filledepoxy, which is preferably removed by removing the defective ASIC (eg, using a suitable solvent or heat). , Of the kind that can be replaced.

It is within the scope of the invention to utilize any suitable mechanism for aligning the ASIC with the interconnect substrate. For example, PCT / US with the same owner
96/08117, a small substrate (eg 62
Of interest are alignment techniques for aligning 0) to a larger substrate (eg, 622). For example, AS
Providing a fairly large amount of solder features (such as a 10 mil x 20 mil rectangle) on the back side of the IC, and equipping the front side of the interconnect board with solder features of similar size, and in advance. Formed solder (or
It is within the scope of the invention to place gold-tin) between them for reflow, and the surface tension exerted by the liquid state solder ensures accurate alignment of the ASIC to the interconnect substrate. Will Connecting the ASIC to the Interconnect Board As previously mentioned, the ASIC is properly electrically connected to the interconnect board using conventional wire bonding techniques.

A relatively large amount of power is required to supply power (start up the DUT) to many DUTs on the WUT for the purpose of burning in the DUT. For example, all WU
On the order of hundreds of watts for T. Because of the physical layout of the system of the present invention, this power
And through a corresponding spring contact element. In the following description, the ASIC is "directly through"
3 illustrates a technique for supplying power.

FIG. 5 typically shows a bond wire (510).
And interconnect board 508 (which corresponds to 108)
ASIC 506 electrically coupled to the
6, 306, 326, 346, and 406) are shown. Significant power is required to power the DUT and perform burn-in, as opposed to the ASIC requiring relatively few connections to initiate signal delivery to the DUT (not shown). Quantities are required, and a correspondingly significant number of bond wires between the ASIC and the interconnect substrate. The number of bond wire connections between the ASIC and the interconnect substrate is approximately equal to the number of power bonds made (via the spring contact element 110) to the DUT (eg, 102), even 100 or more. Can be.

According to one aspect of the invention, power is transferred between the interconnect board and the ASIC using interconnect means capable of carrying more power (watts) than conventional bond wires. , Which reduces the number of connections required.

FIGS. 5A, 5B and 5C show a technique 520 for making an electrical connection between an ASIC and an interconnect substrate.
Is shown.

FIG. 5A shows an ASIC 526 having a number of small holes 522 (one of which is shown) extending completely through the body of the ASIC 526 from the front surface 526a of the ASIC 526 to its back surface 526b. 1
(Corresponding to 06, 206, 306, 326, 406 and 506). These holes 522 are for the ASIC 30.
Forming a depression 308 in the front surface of 6 and the ASIC 40
6 is suitably formed in a manner similar to that used to form the depression 412 in the back surface of 6. That is, the depression (first portion of the hole 522) 522a is formed in the front surface 526a of the ASIC 526 to a depth of at least half the thickness (vertically as shown) of the ASIC 526 and the depression (first portion of the hole 522). The second hole 522b is located inside the back surface 526b of the ASIC 526, and the second hole 522b
It is formed to a sufficient depth continuous with 22a. Hole 52
The size of 2a and 522b should be sufficient to ensure the presence of a continuous opening extending through the ASIC chip 526.

FIG. 5B shows the next step in the process, where a conductive layer (eg, tungsten, titanium-tungsten, etc.) is deposited, eg, by sputtering into the first and second holes. As a result, the first conductive layer portion 524a extends into the first hole portion 522a and the second conductive layer portion 524b extends into the second hole portion 522b. . As shown, there is a discontinuity between these two conductive layer portions 524a and 524b. As shown, the conductive layers 524a and 524b are
It preferably extends to the respective surfaces 526a and 526b of the IC 526.

In practice, the side of one of the holes 522a and 522b (left or right in the figure) may receive more sputtered material than the side of the opposite side of the hole (right or left in the figure). it can.

FIG. 5C shows the next step in the process, where two conductive layer sections 524a and 52 are shown.
The discontinuities between 4b are connected (filled) by an object (mass) 528 made of a conductive material (eg, gold, nickel, etc.). The object is suitably applied by plating (ie, dipping the ASIC in a plating bath and plating well enough to connect the two conductive layers).

The process described above for forming conductive vias in an ASIC is equally applicable to the interconnect substrate of the present invention.

A chunk of conductive material (eg, silver-filled epoxy) is placed in the hole to fill the discontinuity (ie, rather than plate to fill the discontinuity). It is within the scope of the present invention. Spring contact element FIG. 1 (element 110) and FIG. 2 (element 21)
0), self-supporting elongate spring contact elements, and methods of attaching such spring contact elements to substrates with semiconductor devices are described in many of the above-referenced US and PCT patent applications, such as US patent application Ser. 08 / 452,255 and corresponding PCT patent application US
95/14909 for further details. Such spring contact elements described in them also
Also referred to as "composite interconnect element", "elastic contact structure" and the like, it is common practice to wire bond a soft (eg gold) wire to a terminal of an electronic component, with the axis of the wire It is necessary to form and cut the wire so that it has a shape that allows it to move elastically, and to overcoat the axis of the wire and the area of the adjacent terminals with at least one layer of a hard material (eg nickel). To do. Such a composite interconnection element also has a sacrificial substrat.
e) Can be fabricated on and then attached to electronic components.

It is within the scope of the present invention to use any suitable spring contact element to implement the wafer level burn-in and testing of the present invention.

6A-6C illustrate an alternative technique for forming a spring contact element that can be used with the present invention. These spring contact elements are "manufactured" rather than "synthesized."

As shown in FIG. 6A, one example of a technique 600 for making a resilient, self-supporting contact structure includes several patterned insulating layers 604 (three shown). , 606, 608 over the semiconductor device 602. Semiconductor device 6
02 has a number of bond pads 612 (one shown) on its surface (or a surface accessible from that surface). This layer was patterned and aligned with the bond pad (as shown).
Has an opening such that the opening in one layer (eg, 608, 606) is below the layer (eg,
606 and 604), respectively, and are sized and formed to be larger than the bond pad from the bond pad. A layer 614 of electrically conductive material is applied to the opening. Next, the object 620 made of a conductive material is
It can be formed in the opening by electroplating or the like. As shown, the object is a bond pad 61.
After being fixed at 2 and having the insulating layer removed (as best shown in FIG. 6B), it stands unsupported (freestanding) (with only one end attached). With proper selection of materials and geometric shapes, these objects 6
20 can function as an elastic, self-supporting contact structure. As best shown in FIG. 6C, the manufactured contact structure 620 of FIGS. 6A and 6B extends not only vertically on the surface of the component (semiconductor device) 602, but also horizontally. in this way,
The contact structure 620 is oriented along the z-axis (as shown by arrow 622) as well as the xy plane (parallel to the surface of component 602 as shown by arrow 624). Easily designed. Burning in a DUT The process of burning in a semiconductor device involves powering the device at an elevated temperature, accelerating the failure of a latent defective chip (ie, carefully causing an "initial failure"). . It is known that this acceleration can be accelerated by increasing the temperature and the applied operating voltage. However, if the semiconductor device is already packaged, the material of the package (eg, plastic) provides a limit (barrier) to the temperature to which the packaged semiconductor device is exposed in the burn-in furnace. Added. Most packages cannot withstand prolonged exposure to high temperatures. This is especially the case when organic materials are included in the packaging.

The general burn-in method requires heating the packaged semiconductor device to a temperature of 125 ° C. for 96 hours. Generally, the burn-in time can be halved for every 10 degrees Celsius rise in junction temperature. For example, if the DUT needs to be burned in at 150 ° C for one day, they are
At 0 ° C, burn-in can be done in substantially half a day.

Another obstacle to raising the burn-in temperature is that any test device in the burn-in furnace will also be heated, accelerating its failure. For example, the ASIC of the present invention accelerates failure when exposed to the same burn-in temperature as the DUT.

According to one aspect of the invention, the burn-in is
It is carried out at a temperature of at least 150 ° C. DUT is not yet packaged and DUT (or ASIC)
Since the spring contact element attached to the is completely metallic, it is possible at this stage of the process to expose the DUT to a temperature that will destroy the packaged semiconductor device. It contains materials that cannot withstand such high temperatures. Burn-in can be performed on a semiconductor device (DUT) that is present on all wafers (not isolated) or on selected portions of the semiconductor devices that are present on the wafer.

As mentioned above, the ASIC (106) and the WUT
(102) is simply placed in a container that can be evacuated to create a substantial vacuum and the WUT (10)
2) is easily mounted on the temperature controlled chuck (104). The power required to initiate burn-in produces heat, which in most cases is DU
The temperature-controlled chuck (104) has more than enough heat to raise T to the desired burn-in temperature.
Operates in cooling mode. Because of the vacuum, the heat transfer path between the DUT and the ASIC other than the spring contact element (110) is minimal, which allows the ASIC to operate well below the burn-in temperature of the DUT. is there. Reduction of Required Connections and Other Benefits FIG. 7 illustrates a system 700 (equivalent to 100) of the present invention.
Of the present invention, showing some features that are applicable to various examples of the techniques of the present invention. These features are
There are a number of ASICs 706 (corresponding to 106) attached to an interconnect (supporting) substrate 708 (corresponding to 108), and many DUTs 702 (corresponding to 102) with spring contact elements 710, the spring contact elements being To contact the front surface of the ASIC
Mounted on the front surface of the DUT. Power supply 718 (1
18) corresponds to the interconnection board 708, the ASIC 706.
And powering the DUT 702 via the means (710) for interconnecting the ASIC and the DUT and activating it for burn-in.

Host controller 716 (corresponding to 116) provides signals to ASIC 706 via interconnect board 708. Many ASICs 70 (one of which is shown) mounted on interconnect board 708
Very few signals need to be provided to each ASIC 706 to individually control the six. This signal is, for example, serial stream data.

The example shown in FIG. 7 is an example of a system for testing a memory device DUT. The host controller 716 is connected to many ASICs 706 via a data bus that requires few (eg, four) lines. These four lines are the data output line (displayed with DATA OUT), the data back line (displayed with DATA BACK), and the line for resetting the ASIC (MASTER R
It is a line for displaying a clock signal (displayed by CLOCK). All ASICs mounted on the interconnect board are connected to these four "common" lines, which are:
Connected to all ASICs in the interconnect board. This shows that it is easy to implement (ie, manufacture) an interconnect substrate (708) adapted to test many complex electronic components (DUTs) in service.

The power supply (labeled + V) and ground (labeled GROUND) are similarly easily handled within the interconnect board. In essence, two lines are required in the interconnect substrate, which are preferably implemented as planes (ie, power plane and ground plane) in the multilayer interconnect substrate.

A problem with the conventional technique of powering many DUTs is that the power supply drops through the interconnect board. In the present invention, this problem is caused by the ASIC (706).
Is overcome by incorporating a high voltage into the ASIC and incorporating voltage regulation (here a voltage regulator) into the ASIC.

Those of ordinary skill in the art to which the present invention is most closely related will appreciate that additional functionality, not specifically shown, can be readily incorporated into the ASIC. . For example, each AS
The IC can be given its own address and address decoding function, and its response to the serial stream data coming from the controller 716 can be handled individually.

As mentioned above, the interconnect substrate requires very few individual lines or nodes. In addition, the ASIC can easily communicate directly with the DUT via a number of interconnect elements (spring contact elements) to which the DUT is directly connected. Also,
Many ASICs on the interconnect board can communicate as many times as many connections between the ASIC and the DUT. This is an important advantage over prior art techniques. For example, in the case of the "Matsushita Patent" system, there are many (eg 500) significant DUTs.
For applications requiring testing (eg, 16Mb DRAM), the interconnect board (4) can become very complex (eg, 30,000 connections between each pin of the test circuit chip (2) and interconnects). There will be a corresponding 30,000 contact elements between the connection board (4) and the DUT (1), respectively, and as a result it will be very difficult to manufacture and produce.

A significant advantage of the present invention is that the total "connection count" is
Can be significantly reduced, and this reduction is most pronounced within the interconnect substrate. As mentioned earlier, an 8-inch wafer requires 500 16Mb DRAMs.
, Each having 60 bond pads, so there are a total of 30,000 connections. By using the techniques of the present invention, these 30,000 connections are made directly between the ASIC and the DUT, from the ASIC, through the interconnect (support) substrate, and back to the host controller. For example, power supply (2 lines) and serial signal path (2 lines including ground line from power supply)
There is. This means that even if the prior art techniques use the ASIC of the present invention or similar means, the means for interconnecting the interconnect substrate to the DUT will be provided through the interconnect substrate to the AS.
It is a marked departure from prior art techniques that require connecting ICs. The present invention eliminates this problem altogether and greatly reduces the number of nodes required on the interconnect substrate by making a direct connection between the ASIC and the DUT.

Another advantage of the present invention is that the ASIC is a support substrate WU.
It is on the T-side, which minimizes the signal path between the ASIC and the DUT and facilitates fast testing of the DUT. Mounting the array differently, for example, mounting the ASIC on the opposite side of the supporting (wiring) board (as viewed from the WUT) introduces signal delays and unwanted parasitics, thereby implementing a feasible system. Requires additional design.

The techniques described so far provide the following backend flows: Fabrication of interconnect elements (eg, spring contact elements) on non-isolated semiconductor devices, wafer level burn-in and testing (at higher temperatures to facilitate burn-in), encapsulation (free choice). Possible),
High-speed sorting at the wafer level, wafer cutting and separation, and product shipment.

While the invention has been illustrated and described in detail in the drawings and foregoing description, it should be considered that these are illustrative and not restrictive in character. It will be appreciated that all changes and modifications that have been shown and described only in the preferred embodiment, are within the spirit of the invention. Obviously, those of ordinary skill in the art to which the present invention is most closely related may refer to the "theme" mentioned above.
As will be noted many other "modifications" of such modifications are intended to be within the scope of the invention herein disclosed. Some of these changes are described in the original patent application.

For example, a test can be executed during burn-in, an active semiconductor device such as an ASIC is mounted on a test board, and a certain test sequence is
It is also within the scope of the invention that a relatively small number of signals to the IC can be controlled to obtain some result, in response to which the ASIC begins operation.

For example, rather than mounting many ASICs on a single support (interconnect) substrate, the interconnect substrate can be a silicon wafer, and conventional semiconductor fabrication techniques can be used to convert the ASIC to that wafer. It can be formed directly in. In such cases, redundant test elements can be placed in the wafer to test the wafer,
It is an advantage to ensure that the elements that are determined to be operational are powered on (and that the elements that are determined to be non-operational are not powered on).

[Brief description of drawings]

FIG. 1A is a side cross-sectional view of an apparatus for performing a wafer level burn-in and test method according to the present invention.

FIG. 1B is a DUT (shown in solid lines) according to the present invention.
FIG. 6 is a plan view of a small test board, such as an ASIC (shown in dotted lines) above.

1C is a schematic perspective view of the DUT of FIG. 1B in accordance with the present invention.

1D is a plan view of the top surface of the ASIC of FIG. 1B in accordance with the present invention.

FIG. 1E is a plan view of a small test board such as an ASIC (shown in dotted lines) over two DUTs (shown in solid lines) according to the present invention.

FIG. 2 is a side view of an alternative embodiment for making contact between an ASIC and a DUT according to the present invention.

FIG. 3A illustrates multiple ASICs with capture features in accordance with the present invention.
Figure 1 is a side cross-sectional view of one of the
1D for capturing (contacted by) the tip of a spring contact element attached to the
Bond pad as shown in FIG.

FIG. 3B is a side sectional view of an alternative embodiment of one of a plurality of ASICs having features for capturing the tip of a spring contact element attached to a DUT in accordance with the present invention.

FIG. 3C is a side cross-sectional view of an ASIC showing an alternative embodiment of features for trapping the tip of a spring contact element attached to a DUT according to the present invention.

FIG. 4 is a side cross-sectional view of one of a plurality of ASICs with features on the back for ensuring accurate alignment with an interconnect substrate in accordance with the present invention.

FIG. 5 is a side view showing a technique for making an electrical connection between an ASIC and an interconnect substrate according to the present invention.

FIG. 5A is a cross-sectional side view of a technique according to the present invention for providing an electrical path from the top surface of an electrical component such as the ASIC of the present invention to the back surface of the ASIC.

FIG. 5B is a side cross-sectional view showing a technique according to the present invention for providing an electrical path from the top surface of an electrical component such as the ASIC of the present invention to the back surface of the ASIC.

FIG. 5C is a side cross-sectional view showing a technique in accordance with the present invention for providing an electrical path from the top surface of an electrical component such as the ASIC of the present invention to the back surface of the ASIC.

FIG. 6A shows a spring contact element according to the invention.
FIG. 6 is a side sectional view showing a technique for attachment to a DUT.

FIG. 6B shows a spring contact element according to the invention.
FIG. 6 is a side sectional view showing a technique for attachment to a DUT.

6C is a perspective view of the spring contact element of FIG. 6B in accordance with the present invention.

FIG. 7 is a schematic diagram of a system of the invention (corresponding to FIG. 1A) showing the connections and overall functionality for a particular example of the invention.

Continued front page    (31) Priority claim number 60 / 024,405 (32) Priority date August 22, 1996 (August 22, 1996) (33) Priority claiming countries United States (US) (31) Priority claim number 60 / 024,555 (32) Priority date August 26, 1996 (August 26, 1996) (33) Priority claiming countries United States (US) (31) Priority claim number 60 / 030,697 (32) Priority date November 13, 1996 (November 13, 1996) (33) Priority claiming countries United States (US) (31) Priority claim number 60 / 032,666 (32) Priority date December 13, 1996 (December 13, 1996) (33) Priority claiming countries United States (US) (31) Priority claim number 60 / 034,053 (32) Priority date December 31, 1996 (December 31, 1996) (33) Priority claiming countries United States (US) (31) Priority claim number 08 / 784,862 (32) Priority date January 15, 1997 (January 15, 1997) (33) Priority claiming countries United States (US) (31) Priority claim number 08 / 788,740 (32) Priority date January 24, 1997 (January 24, 1997) (33) Priority claiming countries United States (US) (31) Priority claim number 08 / 802,054 (32) Priority date February 18, 1997 (February 18, 1997) (33) Priority claiming countries United States (US) (31) Priority claim number 08 / 819,464 (32) Priority date March 17, 1997 (March 17, 1997) (33) Priority claiming countries United States (US) (31) Priority claim number 08 / 852,152 (32) Priority date May 6, 1997 (May 5, 1997) (33) Priority claiming countries United States (US) (72) Inventor Pedersen, David, Buoy             California 95066, USA,             Scotts Valley, Sterling Ray             6 F-term (reference) 2G003 AA10 AC01 AG03 AG08                 2G132 AA00 AB04 AE10 AF01 AF10                       AG09 AL05                 4M106 AA01 AA02 AC13 BA01 CA31                       CA59 DD03

Claims (60)

[Claims] 1. A method for performing wafer level burn-in and testing of a plurality of semiconductor devices (DUTs) on a semiconductor wafer, the method comprising providing a plurality of active electronic components having terminals on their surface. Providing means for achieving a direct electrical connection between the terminals of the plurality of DUTs and the terminals of the active electronic component. 2. The method of claim 1, wherein the terminals of the active electronic component are capture pads. 3. The method of claim 2, further comprising stiffening the capture pad. 4. The method of claim 1, wherein the terminals of the electronic component are capture features. 5. The method of claim 1, wherein the ratio of the number of DUTs to the number of active electronic components is 1: 1. 6. The method of claim 1, wherein the ratio of the number of DUTs to the number of active electronic components is at least 2: 1. 7. The method of claim 1, wherein the means for achieving the direct electrical connection comprises a spring contact element attached to the DUT. 8. The method of claim 1, wherein the means for achieving the direct electrical connection comprises a spring contact element mounted on the active electronic component. 9. The method of claim 1, wherein the active electronic component comprises an ASIC. 10. The method of claim 1, further comprising mounting the active electronic component on an interconnect substrate. 11. The method of claim 10, further comprising: providing a host controller and connecting the host controller to the active electronic component via the interconnect substrate. 12. To test the DUT further comprises providing a test signal from the host controller to the interconnect board and from the interconnect board to the active electronic component via a few common lines. 13. The method of claim 11, comprising: 13. The DUT is selectively burned in.
13. The method of claim 12, further comprising selectively activating the active electronic component to test a selected one of the. 14. The method further comprising providing a power supply and connecting the power supply to the active electronic component via the interconnect substrate.
the method of. 15. The method of claim 1, further comprising providing voltage regulation within the active electronic component.
Method 4 16. The method of claim 1, further comprising holding the active electronic components at a temperature below the DUTs when burning in the DUT. 17. A system for performing wafer level burn-in and testing of a plurality of semiconductor devices (DUTs) on a semiconductor wafer (WUT), the system being a test board and attached to the test board. The test substrate comprising a plurality of individual active electronic components, and a plurality of semiconductor devices (D) on the semiconductor wafer (WUT), the means being arranged on the active electronic components.
UT) and a means adapted to receive a direct connection from the UT) adapted in use. 18. The means for receiving a direct connection is a capture pad on the active electronic component, wherein the direct connection is made by a spring contact element attached to the DUT, 18. The system of claim 17, comprising adapted for use in a pressure connection to the capture pad. 19. The means for receiving a direct connection is a capture feature on the active electronic component, wherein the direct connection is made by a spring contact element attached to the DUT, 18. The system of claim 17, wherein the system comprises being adapted for use in pressure connection with the capture feature. 20. The system of claim 17, further comprising a plurality of interconnect elements extending directly between the DUT and the active electronic component. 21. The interconnect element comprises the DUT.
21. The system of claim 20, which comprises spreading from a fine pitch at to a coarse pitch at the active electronic component. 22. The interconnect element comprises the DUT
21. The system of claim 20, comprising being attached to. 23. The interconnection element comprises being attached to the active electronic component.
System. 24. The system of claim 20, wherein the interconnection element comprises a spring contact element. 25. The system of claim 24, wherein said spring contact element is a composite interconnect element. 26. The system of claim 24, wherein said spring contact element comprises a manufactured interconnection element. 27. The system of claim 17, further comprising a vacuum vessel adapted for use to house the test substrate and the WUT. 28. The system of claim 17, wherein the test substrate is a semiconductor wafer and the active electronic components are embedded within the test substrate. 29. The system of claim 17, wherein said active electronic component comprises an ASIC mounted on the front surface of an interconnect substrate. 30. The system of claim 17, further comprising means for aligning the ASIC with the interconnect substrate. 31. In use, said active electronic component receives a signal from an external host computer via a relatively small number of signal lines and sends said signal to said DUT via a relatively large number of interconnect elements. 18. The system of claim 17, comprising sending. 32. In use, the active electronic component responds to a control signal from an external host controller in response to a control signal from the DU.
18. The method of claim 17, comprising generating at least some of the plurality of signals required to test T. 33. A method of performing burn-in on a semiconductor device, the test substrate being at least one semiconductor device (DUT).
Connecting to the at least one DUT, supplying power to the at least one DUT, maintaining the at least one DUT at a first temperature, and connecting the test substrate to a second temperature independent of the first temperature. Holding at temperature. 34. The method of claim 33, wherein the second temperature is lower than the first temperature. 35. The method of claim 33, wherein the second temperature is not higher than the first temperature. 36. Placing the test board and the at least one DUT in a vacuum environment, the vacuum environment providing a thermal barrier between the at least one DUT and the test board. 34. The method of claim 33, further comprising: 37. The method of claim 33, wherein the at least one DUT comprises a plurality of semiconductor devices on a semiconductor wafer (WUT). 38. The method of claim 33, further comprising connecting the test substrate to the at least one DUT with a plurality of spring contact elements. 39. The method of claim 33, further comprising connecting the test substrate to the at least one DUT with a plurality of spring contact elements attached to the at least one DUT. 40. The spring contact elements are elongate and attached to the at least one DUT at their bases, with free ends, and further, at their free ends rather than their bases. 40. The free end of the spring contact element is flared to have a greater pitch.
the method of. 41. A method of testing a semiconductor chip before being separated from the semiconductor wafer, wherein a plurality of spring contact elements each having a free end are attached to the plurality of semiconductor chips on a first semiconductor wafer. And pulling a test substrate having a plurality of terminals toward the surface of the chip to make a plurality of pressure connections between each terminal and the free end of the spring contact element, and And testing the semiconductor chip by feeding the semiconductor chip through the chip. 42. The method of claim 41, wherein said spring contact element comprises a composite interconnect structure. 43. After testing the semiconductor chip,
42. The method of claim 41, further comprising separating the chips from the wafer. 44. The method of claim 41, wherein the test substrate is a second semiconductor wafer. 45. The method of claim 41, wherein the test board comprises a relatively large interconnect board and a plurality of relatively small electronic components mounted on the front surface of the interconnect board. 46. The method of claim 41, further comprising performing burn-in on at least a portion of the semiconductor chip while the test substrate and the semiconductor chip are connected. 47. The method of claim 46, further comprising placing the test substrate and the semiconductor chip in a vacuum while performing burn-in. 48. The method of claim 46, further comprising holding the test substrate below the temperature of the semiconductor chip while performing burn-in. 49. A method of aligning a plurality of electronic components with an interconnect substrate, the method comprising forming indentations on a back surface of each electronic component and forming corresponding indentations on a front surface of the interconnect substrate. Forming, and disposing a spherical element between said depression and said corresponding depression. 50. The electronic component is an ASIC, and the ASIC and the interconnect substrate comprise a test substrate of a system for performing wafer level burn-in and testing of semiconductor devices. Method. 51. A method of making a connection between a tip of an elongated interconnection element extending from a first electronic component and a second electronic component, the indentation on a front surface of the second electronic component. Forming, pulling the first and second electronic components such that the tip of the elongated interconnection element is located within the recess, and selecting from a set consisting of a lateral or rotational direction. Moving the second electronic component in a positive direction to make a pressure connection between the tip of the elongated interconnection element and the side of the recess. 52. The method of claim 51, wherein said elongate interconnect element is a spring contact element. 53. The method of claim 51, wherein the first electronic component comprises at least one semiconductor device. 54. The method of claim 51, wherein the first electronic component comprises a plurality of semiconductor devices on a semiconductor wafer. 55. The method of claim 51, wherein the second electronic component comprises a test board. 56. The method of claim 51, wherein the second electronic component is an ASIC mounted on a test board of a system for performing wafer level burn-in of semiconductor devices. 57. At least one semiconductor device (DU
T) in which an active electronic component is placed in direct electrical contact with at least one DUT, and an interconnect substrate in an electrical path between the active electronic component and the DUT. By passing power and signals through interconnection elements that extend directly between the terminals on the active electronic component and the terminals on the DUT without using other means such as And a method that consists of starting. 58. The method of claim 57, wherein the interconnection element comprises a spring contact element. 59. Attaching a plurality of active electronic components to an interconnect substrate, sending a relatively small number of signals from a host controller to the active electronic component through the interconnect substrate, and the active electronic component. A relatively large number of signals from the at least one DUT to the plurality of DUTs directly through the interconnection elements extending between the plurality of DUTs and the plurality of active electronic components. 58. The method of claim 57, further comprising: 60. The method of claim 57, wherein the active electronic component comprises an ASIC.