JP2003209359A - Core board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a core board for allowing a multilayer circuit board effectively using build-up layers on both surfaces of the core board, and to provide a method for simply manufacturing the same. <P>SOLUTION: The method for manufacturing the core board comprises the steps of roughing copper foil surfaces of a copper foil-clad laminate having copper foils of a thickness of a range of 5 to 12 μm on both surfaces of a core material, emitting a laser to perforate a plurality of through holes at least partially including through holes having an inner diameter of a range of 0.05 to 0.15 mm and a pitch of a range of 0.2 to 0.3 mm, filling conductive paste in the holes, surface smoothing the laminate, then electroless plating to form a substrate power supply layer on the overall surface, precipitating a conductive material on the substrate power supply layer by electrolytic plating with a desired electric insulation pattern as a mask, forming desired wirings including the land for blocking the opening of the hole, and thereafter removing unnecessary substrate power supply layer by etching. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a core board used for a multilayer wiring board and a manufacturing method thereof, and in particular, it enables a multilayer wiring board having build-up layers with high-density wiring on both sides of the core board. And a manufacturing method for manufacturing such a core substrate.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been becoming more highly integrated and higher in performance, and the number of terminals has increased remarkably. For example, QFP (Quad Flat)
In the surface mount package such as the package, the external terminal pitch has been narrowed to cope with the increase in the number of terminals without increasing the package size. But,
As the pitch of the external terminals becomes narrower, the width of the external terminals themselves becomes narrower and the strength decreases, so it becomes difficult to cope with skew of the external terminals in the post process such as forming and to maintain flatness. There was a problem that it became difficult to maintain the mounting accuracy of. That is, QF
Even with P, it is difficult to cope with further increase in the number of terminals.

In order to deal with this, BGA (Ball)
A package having a multi-layer resin printed circuit board represented by a Grid Array as an interposer has been developed. This BGA is one in which a semiconductor chip is usually mounted on one surface of a double-sided board and spherical solder balls are provided on the other surface as external terminals, and the terminals of the semiconductor chip and the external terminals (solder balls) are electrically connected. Yes, this package has improved mountability.

Recently, a bare chip mounting method has been proposed in which a chip (bare chip) having no package is directly mounted on a multilayer wiring board. In the bare chip mounting method, bonding wires, bumps made of solder, metal balls, etc., anisotropic conductive films, conductive adhesives, light-shrinkable resins, etc. are formed on the connection pad parts of the wiring previously formed on the multilayer wiring board. The semiconductor device chip is mounted by using the connecting means. Since the chip is not enclosed in the package,
Since the connection path between the wiring on the multilayer wiring board and the chip can be simplified and shortened, and the packaging density is improved, the distance between the chip and another chip can also be shortened. Therefore, not only the reduction in size and weight but also the speeding up of signal processing can be expected.

A multilayer wiring board compatible with the bare chip mounting method as described above usually uses a double-sided board having a low-density wiring manufactured by a subtractive method or the like as a core board, and both sides of the core board are formed by a build-up method. It is manufactured by forming density wiring. FIG. 9 is a process diagram showing an example of a conventional core substrate manufacturing method. First, a copper-clad laminated substrate 52 provided with copper foils 54a on both surfaces of a core material 53 is mechanically passed through a drill machine. A hole 58 is formed (FIG. 9A). Next, the inside of the through hole 58 is washed and electroless copper 54b is formed by electroless plating to make the inside of the through hole 58 conductive, and thereafter, a copper plating layer 54c is formed on the entire surface with a predetermined thickness by electrolytic copper plating. , Through hole 58
The inside is electrically connected (FIG. 9 (B)). Next, a filling member 55 made of a conductive metal material or a non-conductive paste is filled in the through holes 58, and a surface smoothing process is performed by physical polishing (FIG. 9C). After that, a film formation process is performed using a dry film resist or a liquid resist, and a predetermined pattern exposure and development are performed to form a resist pattern. Using this resist pattern as a mask, the copper plating layer 54c, the electroless copper 54b and the copper foil 54a are formed. By pattern etching, the plated through holes 54,
A desired circuit wiring (not shown) is formed, and the core substrate 51 is formed.
Are manufactured (FIG. 9 (D)).

FIG. 10 is a schematic sectional view showing an example of a multilayer wiring board manufactured by forming high-density wiring on both surfaces of the core board 51 manufactured as described above by a build-up method. The multilayer wiring board 60 shown in FIG. 10 can be manufactured as follows. That is, insulating layers 61 of glass cloth epoxy resin (prepreg) are formed on both surfaces of the core substrate 51, and a carbon dioxide laser or UV-Y is used.
A small diameter hole is formed at a predetermined position of each insulating layer 61 so that the plated through hole 54 on the core substrate and a desired portion of the circuit wiring are exposed by using an AG laser. Then, after cleaning, a conductive layer is formed in the hole by electroless plating, a dry film resist is laminated, and a predetermined pattern is exposed and developed to form a resist pattern,
Using this resist pattern as a mask, a via portion 62 is formed by electrolytic plating in the exposed portion including the above hole portion to form a first buildup layer. By repeating this operation, a plurality of build-up layers (two layers on each side in the illustrated example) are formed to manufacture the multilayer wiring board 60. Then, in the buildup layer on the outermost surface on the semiconductor chip mounting side, together with necessary wiring, the connection pad portion 64 for mounting the semiconductor chip is provided.
Are formed. In such a multilayer wiring board 60,
The semiconductor chip 81 can be mounted on the connection pad portion 64 for mounting the semiconductor chip via the metal bumps 82 such as solder. Further, an external connection terminal 65 is provided on the back surface side of the multilayer wiring board 60 and can be mounted on a printed wiring board (motherboard). In the illustrated example, the number of plated through holes, the number of bumps of the semiconductor chip, and the number of connection terminals of the semiconductor chip are four for simplification.

[0007]

However, the conventional core substrate having the plated through holes has a large diameter and a large pitch of the plated through holes, which makes it difficult to cope with high density due to the increase in the number of pins of the semiconductor chip. There is a problem that is. That is, from the viewpoint of migration (exudation of the plating solution into the core material 53) that occurs during the plating step in forming the plated through holes, there is a limit to the narrowing of the pitch of the plated through holes, and the connection pads for mounting semiconductor chips are limited. It is unavoidable that there is a large gap between the pitch of the parts and the pitch of the plated through holes. For this reason,
In order to connect the semiconductor chip mounting connection pad portion to each plated through hole of the core substrate, it is necessary to route fine wiring to the build-up layer or increase the number of stacked build-up layers. In the above-mentioned example of the multilayer wiring board 60, each chip mounting connection pad portion 64 to the core board 5 is mounted.
In order to route the wiring for connection to each plated through hole 54 of No. 1, two build-up layers are required on the chip mounting side. On the other hand, the two build-up layers on the back surface of the core substrate 51 do not require wiring, and the external connection terminals 6
Only a via portion for connecting to No. 5 is formed.

However, in order to perform a balance maintaining action such as warpage prevention of the multilayer wiring board 60, it is necessary to provide two build-up layers equivalent to those on the chip mounting side also on the back surface of the core substrate 51. That is, in the conventional multilayer wiring board, the routing of the wiring for connecting the semiconductor chip mounting connection pads to each plated through hole of the core board is concentrated in the build-up layer on the chip mounting side of the core board, and It is difficult to effectively use the build-up layer, which is one of the factors that hinders the miniaturization and simplification of manufacturing of the multilayer wiring board. Therefore, it has been desired to put a multilayer wiring board into practical use in which the buildup layers on both sides of the core board are effectively used. The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a core substrate that enables the production of a multilayer wiring substrate that effectively uses the build-up layers on both sides of the core substrate, and a production method for easily producing such a core substrate.

[0009]

In order to achieve such an object, the present invention has a plurality of build-up layers on both surfaces of a core substrate, and has a connection pad portion for mounting a semiconductor chip on one surface. In the core board used for the multilayer wiring board having external connection terminals on the other surface, a core material having a plurality of through holes filled with a conductive paste is provided inside, and the openings of the through holes are The through hole is closed by a land portion that is electrically connected to the conductive paste, and at least a part of the plurality of through holes has an inner diameter of 0.05 to 0.15 m.
The range is m and the pitch is in the range of 0.2 to 0.3 mm.

In a preferred aspect of the present invention, the through holes are each configured to have an inner diameter of 0.05 to 0.15 mm. In a preferred aspect of the present invention, the through holes each have an inner diameter of 0.05 to
The configuration is such that the range is 0.15 mm and the pitch is in the range of 0.2 to 0.3 mm. Furthermore, as a preferred aspect of the present invention, the conductive material contained in the conductive paste is a copper particle having a surface coated with silver.

According to the method for producing a core substrate of the present invention, the surface of the copper foil of a copper clad laminate having copper foil with a thickness of 5 to 12 μm on both sides of the core material is subjected to a roughening treatment, and then a laser is applied. A first step of irradiating to form a plurality of through holes including at least a part thereof having an inner diameter of 0.05 to 0.15 mm and a pitch of 0.2 to 0.3 mm; The second step of filling the hole with a conductive paste and then performing a surface smoothing treatment by physical polishing,
A third step of forming an underlying power feeding layer on the entire surface by electroless plating, forming a desired electrically insulating pattern on the underlying power feeding layer, and using the electrically insulating pattern as a mask to deposit a conductive material on the underlying power feeding layer. A fourth step of forming a land portion which is deposited on the through hole and closes the opening portion of the through hole while being connected to the conductive paste filled in the through hole, and the electrically insulating pattern is removed. Then, a fifth step of etching and removing the exposed unnecessary underlying power supply layer is adopted.

Further, in the method for manufacturing a core substrate of the present invention, the surface of the copper foil of the copper clad laminate having the copper foil having a thickness of 5 to 12 μm on both surfaces of the core material is subjected to a roughening treatment, and then, A first step of irradiating a laser to form a plurality of through holes including at least a part thereof having an inner diameter of 0.05 to 0.15 mm and a pitch of 0.2 to 0.3 mm; Second, the conductive paste is filled in the through holes, and then the surface is smoothed by physical polishing.
The third step of forming an underlayer feeding layer on the entire surface by electroless plating and depositing a conductive material on the underlayer feeding layer by electrolytic plating to form a conductive layer; forming a desired resist pattern on the conductive layer; A land which is formed, removes the conductive layer and the underlying power supply layer by etching using the resist pattern as a mask, and closes the opening of the through hole while being connected to the conductive paste filled in the through hole. And a fourth step of removing the resist pattern is performed.

As a preferred aspect of the present invention, in the fourth step, a desired wiring is formed simultaneously with the land portion. In a preferred aspect of the present invention, the core material is configured to have wiring inside. As a preferred embodiment of the present invention, the laser is configured to use a carbon dioxide gas laser. Further, as a preferred aspect of the present invention, the conductive paste is configured to contain a conductive material composed of copper particles coated with silver on the surface.

As described above, the core substrate has a through hole having an inner diameter in the range of 0.05 to 0.15 mm, which is filled with the conductive paste and whose opening is closed by the land portion.
Since the pitch is in the range of 2 to 0.3 mm, at least one layer of the build-up layer on the semiconductor chip mounting surface side is provided with wiring for connecting the semiconductor chip mounting connection pad portion and a part of the land portion. Provided, at least one of the buildup layers on the external connection terminal side is provided with wiring for connecting the external connection terminal and a part of the land portion, and the required wiring is distributed to the buildup layers on both sides of the core substrate. It becomes possible. In addition, the conductive paste filled in the through holes in the second step of the manufacturing method does not cause migration between the through holes and enables a narrow pitch of the through holes.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Core Substrate FIG. 1 is a partial vertical sectional view showing an embodiment of the core substrate of the present invention. In FIG. 1, a core substrate 1 of the present invention includes a core material 2, a plurality of through holes 3 having an inner diameter d1 formed at a pitch P1 so as to penetrate the core material 2, and
It is provided with a plurality of through holes 6 having an inner diameter d2 formed at a pitch P2. A conductive paste 4 is filled in each of the through holes 3 and 6, and the opening 3 a of the through hole 3 is filled with the conductive paste 4.
Is closed by a small-diameter land portion 5 that conducts with, and the opening 6a of the through hole 6 is closed by a large-diameter land portion 8 that conducts with the conductive paste 4. In the present invention, of the through holes 3 and 6, the small diameter through hole 3 is used.
Has an inner diameter d1 of 0.05 to 0.15 mm, preferably 0.
Range of 08 to 0.10 mm, pitch P1 is 0.20
It is characterized by being in the range of 0.30 mm, preferably 0.20 to 0.225 mm. The inner diameter d2 of the large-diameter through hole 6 is in the range of 0.15 to 0.25 mm,
The pitch P2 can be set in the range of 0.80 to 1.27 mm.

In the above embodiment, in order to simplify the drawing, two through holes 3 having an inner diameter d1 formed at a pitch P1 and two through holes 6 having an inner diameter d2 formed at a pitch P2 are provided. , Respectively, the pitch P1
The number of through-holes 3 formed on the core substrate 1 and the formation portion on the core substrate 1, the number of through-holes 6 formed on the pitch P2 and the formation portion on the core substrate 1, and
The positional relationship between the site where the plurality of through holes 3 are formed and the site where the plurality of through holes 6 are formed can be set as appropriate.

FIG. 2 is a partial vertical sectional view showing another embodiment of the core substrate of the present invention. In FIG. 2, a core substrate 11 of the present invention includes a core material 12, a plurality of through holes 13 having an inner diameter d1 formed at a pitch P1 so as to penetrate the core material 12, and an inner diameter formed at a pitch P2. d
The plurality of through holes 17 are provided. The inside of each of the through holes 13 and 17 is filled with the conductive paste 14, and the opening 13 a of the through hole 13 is closed by the land portion 15 that is electrically connected to the conductive paste 14, and the through hole 17 of the through hole 17 is closed. Opening 17
Also a is closed by the land portion 15 that is electrically connected to the conductive paste 14. In the present invention, the above through hole 1
The inner diameter d1 of 3, 17 is in the range of 0.05 to 0.15 mm, preferably 0.08 to 0.10 mm, the through hole 13
The pitch P1 is in the range of 0.20 to 0.30 mm, preferably 0.20 to 0.225 mm. Further, the pitch P2 of the through holes 17 having a large formation pitch can be set in the range of 0.80 to 1.27 mm.

Further, the core substrate 11 is provided with desired wiring 19 on the core material 12, and the line and space of such wiring 19 is 30 μm / 30 μm to 50 μm /.
The range can be about 50 μm. Like the core substrate 11, the above-mentioned core substrate 1 can also be provided with desired wiring on the core material 2.

In the above embodiment, in order to simplify the drawing, two through holes 13 having an inner diameter d1 formed at a pitch P1 and two through holes 17 having an inner diameter d1 formed at a pitch P2 are formed. , Respectively, the number of through holes 13 formed at the pitch P1 and the formation site on the core substrate 11, the number of through holes 17 formed at the pitch P2 and the formation site on the core substrate 11, and a plurality of The positional relationship between the portion where the through holes 13 are formed and the portion where the plurality of through holes 17 are formed can be set appropriately.

FIG. 3 is a partial vertical sectional view showing another embodiment of the core substrate of the present invention. In FIG. 3, a core substrate 21 of the present invention includes a core material 22 and a plurality of through holes 23 having an inner diameter d1 formed at a pitch P1 so as to penetrate the core material 22. Is filled with a conductive paste 24, and the opening 23 a of the through hole 23 is closed by a land 25 that is electrically connected to the conductive paste 24. In the present invention, the inner diameter d1 of the through hole 23 is in the range of 0.05 to 0.15 mm, preferably 0.08 to 0.10 mm, and the pitch P1 of the through hole 23 is 0.20 to 0.30 mm, preferably It is characterized in that it is in the range of 0.20 to 0.225 mm. Also in the core substrate 21, similar to the core substrate 11 described above, desired wiring can be provided on the core material 22. In the above embodiment, four through holes 23 having the inner diameter d1 formed at the pitch P1 are shown for simplification of the drawing, but the number of the through holes 23 formed at the pitch P1 and the cores are shown. Board 21
The number of formation sites, the number of sites where the plurality of through holes 23 are formed, and the like can be set appropriately.

The core materials 2, 12, 22 constituting the above-mentioned core substrates 1, 11, 21 are core materials made of epoxy resin, polyimide resin, polyphenylene ether resin, fluororesin or the like reinforced with glass cloth or aramid fiber. For example, conventionally known materials can be used. The thickness of such core materials 2, 12, 22 can be appropriately set within a range of 0.1 to 1.0 mm. In addition, the core material 2, 12,
22 may have one layer or two or more layers of wiring inside, and these wirings may be formed as necessary.
Conductive paste 4 and 1 filled in the above through holes
It is possible to establish electrical continuity with other wiring and a buildup layer described later through 4, 24.

If the inner diameter d1 of the through holes 3, 13, 23 among the through holes formed in the core materials 2, 12, 22 is less than 0.05 mm, it becomes difficult to drill the core material. However, it becomes difficult to fill the conductive paste. On the other hand, when the inner diameter d1 exceeds 0.15 mm, the diameter of the land portions 5, 15 and 25 for closing the opening of the through hole becomes large, and the electrical conductivity of each through hole becomes large. The pitch of through holes is set to 0.
It is difficult to set the thickness in the range of 2 to 0.3 mm, which is not preferable. Further, when the pitch of the through holes 3, 13, 23 exceeds 0.3 mm, the difference from the pitch of the bumps of the semiconductor chip (the pitch of the connection pad portions of the multilayer wiring board) becomes large, and the effect of the present invention can be obtained. Not desirable.

The conductive pastes 4, 14 and 24 constituting the core substrates 1, 11 and 21 are obtained by containing a particle-shaped conductive material in the paste, and as the conductive material, gold, silver,
Metal particles such as copper, composite metal particles such as copper particles having a surface coated with silver, and the like can be used. The particle size of such a conductive material is preferably about 2 to 7 μm. As the paste, epoxy resin, bisphenol resin or the like can be used. The content of the conductive material in the conductive paste is 80 to 90% by weight, preferably 85 to 95% by weight.
It can be in the range of 90% by weight.

The land portions 5, 15, 25 and the land portion 8 forming the core substrates 1, 11, 21 close the openings of the through holes 3, 13, 17, 23 and the through hole 6 and, on the core substrate, It serves as a connection pad with each wiring and the like of the build-up layer formed on. Such a land portion is usually formed by using copper, and has such a size that it can close the opening of the through hole and can keep a distance of 30 μm or more between the adjacent land portions. In addition, the wiring formed on the surface of the core substrate described above,
It can also be designed to include the land portion described above.

An example of a multilayer wiring board using such a core substrate is shown in FIG. 4, taking the core substrate 1 as an example. In FIG. 4, the multilayer wiring board 41 includes buildup layers 42 and 43 of one layer on both surfaces of the core board 1. The build-up layers 42 and 43 are connected to desired portions of the insulating layers 44a and 44b with lands 5 and 8 on the core substrate 1 and desired portions of wiring (the wiring is not provided in the illustrated core substrate 1). Via portions 45a and 45b are formed, and predetermined wirings 46a and 46b are formed. The core substrate 1 of the present invention includes the through holes 3 having an inner diameter in the range of 0.05 to 0.15 mm and a pitch in the range of 0.2 to 0.3 mm.
It is almost the same as the formation pitch of the bumps of the semiconductor chip. Therefore, the connection pad portion 4 for mounting the semiconductor chip is formed on the via portion 45a of the build-up layer 42 formed in the land portion 5 on the semiconductor chip mounting side without interposing wiring.
7a can be provided directly. The land portion 8 that closes the through hole 6 having a large formation pitch is connected to the connection pad portion 47a via the wiring 46a of the buildup layer 42.
Can be connected with. Then, the connection pad portion 47a
The semiconductor chip 81 can be mounted on the semiconductor chip via metal bumps 82 such as solder.

On the other hand, the buildup layer 4 on the external connection terminal side
3, a plurality of external connection terminals 48 are formed, and the multilayer wiring board 41 can be mounted on a printed wiring board (motherboard) via the external connection terminals 48. Therefore, the pitch of the external connection terminals 48 is larger than the pitch of the through holes 3 of the core substrate 1. Therefore, the land portion 5 that closes the through hole 3 is
Wiring 4 formed on the build-up layer 43 on the external connection terminal side
It can be connected to a predetermined external connection terminal 48 via 6b. Further, the land portion 8 that closes the through hole 6 having a large formation pitch does not include the wiring, but the via portion 4
The external connection terminal 48 can be directly connected by 5b.

As described above, by using the core substrate 1 of the present invention, the connection pad portion 47 for mounting the semiconductor chip is formed.
A part of a is a via portion 45a without passing through the wiring 46a.
Can be directly connected to the land portion 5 via the wiring pad 47, and only for the other connection pad portion 47a, the wiring 46a for connecting to the land portion 8 can be formed in the buildup layer 42 on the semiconductor chip mounting surface side. On the other hand, although the pitch of the plurality of lands 5 on the external connection terminal side is smaller than the pitch of the external connection terminals 48, they are connected to the external connection terminals 48 by the wiring 46b formed in the buildup layer 43 on the external connection terminal side. be able to. As a result, necessary wiring can be distributed to the buildup layers on both sides of the core substrate, and wiring concentration on the buildup layers on the semiconductor chip mounting surface side can be prevented.

Manufacturing Method of Core Substrate Next, a manufacturing method of the core substrate of the present invention will be described with reference to the drawings. FIG. 5 and FIG. 6 are process diagrams showing an embodiment of the core substrate manufacturing method of the present invention using the above-described core substrate 1 as an example.

[First Step] In this embodiment, in the first step, a copper-clad laminate 30 having copper foils 31 having a thickness of 5 to 12 μm on both surfaces of the core material 2 is prepared (FIG. 5).
(A)). If the thickness of the copper foil 31 is less than 5 μm, the function of protecting the core material in forming a through hole by a laser, which will be described later, becomes insufficient and the accuracy of forming the through hole decreases. Further, if the thickness of the copper foil 31 exceeds 12 μm, the power of the laser required for forming a through hole by the laser, which will be described later, increases, which is not preferable because the working efficiency is reduced. As the core material 2 constituting the copper-clad laminate 30, a conventionally known material such as an epoxy resin, a polyimide resin, a polyphenylene ether resin, a fluorocarbon resin or the like reinforced with glass cloth or aramid fiber can be used. . The thickness of such a core material 2 is 0.1 to 1.0 mm.
Can be appropriately set within the range. Further, the core material 2 may have one layer or two or more layers of wiring inside.

Next, the surface of the copper foil 31 is subjected to a roughening treatment, and thereafter, a predetermined portion is irradiated with a laser to form through holes 3 with an inner diameter d1 at a pitch P1 and through holes 6 with an inner diameter d2. It is formed at the pitch P2 (FIG. 5B).
The roughening treatment of the copper foil 31 is intended to prevent reflection of the laser irradiated on the copper foil 31 and concentrate the laser power at a predetermined location to improve processing efficiency. Roughening treatment can be performed by CZ treatment or the like. The laser used may be a carbon dioxide gas laser, a UV-YAG laser, an excimer laser, or the like. Of these, a carbon dioxide gas laser is particularly preferable. The through hole 3 formed by such a laser has an inner diameter d1 of 0.05 to 0.15 mm, preferably 0.08 to 0.10 mm, and a pitch P1 of 0.2.
0 to 0.30 mm, preferably 0.20 to 0.225 m
The range is m. The large-diameter through hole 6 can have an inner diameter d2 in the range of 0.15 to 0.25 mm and a pitch P2 in the range of 0.80 to 1.27 mm.

[Second Step] Next, in the second step, the through holes 3 and 6 are filled with the conductive paste 4 (FIG. 5C), and then the surface is smoothed by physical polishing. (FIG. 5 (D)). As the conductive paste, the above-mentioned conductive paste can be used, and the through holes 3 and 6 can be filled by a screen printing method or the like.

After the conductive paste filled in the through holes 3 and 6 is hardened, the surface of the conductive paste that is hardened and projected on the surface of the copper clad laminate is polished to expose the exposed conductive paste. The surface is smoothed so that the surface and the copper foil surface are flush with each other. Examples of the surface smoothing treatment by physical polishing include treatment methods such as buff polishing, belt sander and CMP. In the present invention, unlike the conventional formation of plated through holes, the conductive paste is filled in the through holes to establish conduction between the front and back sides, so that migration between the through holes does not occur and the pitch P1 is 0.2 to 10.
Even if the pitch is as narrow as 0.3 mm, electrical independence between the through holes can be secured.

[Third Step] Next, in a third step, the copper foil 31 is removed by etching (FIG. 5 (E)), and then the entire surface of the core material 2 and the conductive paste 4 is electroless plated. The base feeding layer 32 is formed (see FIG. 6).
(A)). The copper foil 31 can be removed by etching using, for example, a ferric chloride-based etching solution. The underlying power supply layer 32 can be formed as a conductive layer having a thickness of about 0.3 to 1.0 μm by electroless copper plating or the like. Although the copper foil 31 is removed by etching in the above embodiments, the copper foil 31 may be left as it is without being removed by etching, and the base feeding layer 32 may be provided on the copper foil 31.

[Fourth Step] Next, in the fourth step, a desired electrically insulating pattern 33 is formed on the underlying power supply layer 32.
Are formed (FIG. 6 (B)). Next, a conductive material is deposited on the underlying power supply layer 32 by electrolytic plating using the electrically insulating pattern 33 as a mask to form lands 5 and 8 that close the openings 3a and 6a of the through holes 3 and 6 (FIG. 6 (C)). The electrically insulating pattern 33 can be formed by performing a film formation process using an electrically insulating dry film resist or a liquid resist, and performing predetermined pattern exposure and development. Such an electrically insulating pattern 33 serves as an opening pattern for forming a land portion, can close the openings 3a, 6a of the through holes 3, 6, and can keep a distance of 30 μm or more between adjacent land portions. Such an opening pattern is provided. The electrolytic plating is usually electrolytic copper plating, and the land portions 5 and 8 thus formed are connected to the conductive paste 4 filled in the through holes 3 and 6. . When manufacturing a core substrate having wiring on its surface, such as the core substrate 11 shown in FIG.
By forming the electrically insulating pattern 33 including the opening pattern for forming the land portion and the opening pattern for forming the wiring, the land portion and the wiring can be formed at the same time. The wiring to be formed has a line and space of 30μ.
Fine wiring of about m / 30 μm to 50 μm / 50 μm can be formed.

[Fifth Step] Next, the electrically insulating pattern 33 is removed, and the exposed unnecessary underlying power supply layer 32 is removed by etching (FIG. 6D). Thereby, the core substrate 1 of the present invention can be obtained. The above etching can be performed by flash etching using a perhydrous sulfuric acid-based etching solution.

FIGS. 7 and 8 are process diagrams showing another embodiment of the core substrate manufacturing method of the present invention using the above-mentioned core substrate 1 as an example. [First Step] The first step of this embodiment is the same as that of the above-described embodiment, and the thickness of the core material 2 is 5 to 12 μm on both surfaces.
The copper clad laminate 30 having the copper foil 31 in the range of is prepared (FIG. 7 (A)), the surface of the copper foil 31 is roughened, and then,
By irradiating a predetermined portion with a laser, through holes 3 having an inner diameter d1 are formed at a pitch P1, and through holes 6 having an inner diameter d2 are formed at a pitch P2 (FIG. 7B).

[Second Step] The second step of this embodiment is also the same as that of the above-described embodiment. In the second step, the conductive paste 4 is placed in the through holes 3 and 6. Filling (FIG. 7C), conductive paste 4
After being cured, the surface is smoothed by physical polishing (FIG. 7 (D)).

[Third Step] Next, in a third step, an underlayer feeding layer 32 is formed on the entire surface of the copper foil 31 and the conductive paste 4 by electroless plating, and the underlayer feeding layer 32 is formed.
A conductive layer 34 having a predetermined thickness is formed thereon by electrolytic plating (FIG. 8A). The base feeding layer 32 can be formed as a conductive layer having a thickness of about 0.3 to 1.0 μm by electroless copper plating or the like. The electrolytic plating is electrolytic copper plating, and the conductive layer 34 can have a thickness of about 15 to 20 μm.

[Fourth Step] Next, in the fourth step, a film formation process is performed using a dry film resist or a liquid resist, and predetermined pattern exposure and development are performed to form a desired resist pattern on the conductive layer 34. 35 is formed (FIG. 8B). Then, the conductive layer 34, the underlying power feeding layer 32, and the copper foil 31 are removed by etching using the resist pattern 35 as a mask, and the through holes 3,
The land portions 5 and 8 for closing the openings 3a and 6a of 6 are formed, and then the resist pattern 35 is removed (FIG. 8).
(C)). Thereby, the core substrate 1 of the present invention can be obtained.

The resist pattern 35 is a covering pattern for forming land portions, which can close the openings 3a, 6a of the through holes 3, 6 and can keep a distance of 30 μm or more between adjacent land portions. It shall be provided with such a coating pattern. The core substrate 11 shown in FIG.
As described above, when a core substrate having wiring on the surface is manufactured, the land portion formation and the wiring are formed by forming the resist pattern 35 including the coating pattern for forming the land portion and the coating pattern for forming the wiring. The formation can be done simultaneously. The wiring to be formed has 3 lines and spaces.
Fine wiring of about 0 μm / 30 μm to 50 μm / 50 μm can be formed.

[0041]

The present invention will be described in more detail with reference to specific examples. [Example 1] First step 0.8 mm thick made of bismaleimide triazine resin
The starting material is a copper clad laminate having a copper foil with a thickness of 12 μm on both sides of the core material, and the copper foil of the copper clad laminate is spray-etched using a perhydro sulfuric acid-based etching solution to obtain a copper foil. The thickness was reduced to about 5 μm, washed with water and dried.

Next, a roughening treatment liquid (CZ8100 manufactured by MEC Co., Ltd.) is applied to the copper foil surface of the copper clad laminate provided with the thin copper foil.
Roughening treatment was performed to obtain a rough surface having an uneven shape of about 2 μm, washed with water and dried. Then, carbon dioxide gas laser was irradiated to a predetermined portion (pulse width: 50 μsec, shot number: 20 shots) to form through holes having an inner diameter of 0.1 mm at a pitch of 0.25 mm. After that, for the purpose of removing the contamination around the through holes due to copper scattering during processing, after surface treatment with a perhydrogen sulfate soft etching agent (Pre-posit 746W made by Shipley Co., Ltd.), washing with high pressure spray water is performed. Was applied.

Second Step Next, a conductive paste containing copper particles coated with silver to a thickness of about several Å (AE15 manufactured by Tatsuta Electric Wire Co., Ltd.).
66) was filled in the above through holes with a screen printer (manufactured by New Long). The screen printing conditions were as follows. (Screen printing conditions) -Screen plate: 180 mesh (Tetron screen) Emulsion thickness = 20 μm-Squeegee: 30 ° cut squeegee with hardness of 80 ° -Setting conditions: Clearance = 2.0 mm, printing pressure = 2.0 mm Squeegee speed = 36 mm / Second

Next, the conductive paste filled in the through holes is cured (80 ° C., 60 minutes and 160 ° C.,
After the two-step treatment for 60 minutes), the surface of the conductive paste that has hardened and protruded onto the surface of the copper-clad laminate is polished with a hub polisher (manufactured by Ishii Inscription Co., Ltd.) to expose the exposed conductive layer. Was subjected to a flattening surface treatment so that the surface of the conductive paste and the surface of the copper foil were flush with each other.

Third Step Next, the copper foil was removed by etching using the perhydrous sulfuric acid type etching solution used in the first step. Then, electroless copper plating was performed on the entire surface of the core material and the conductive paste by electroless plating under the following conditions to form a base feeding layer. (Electroless copper plating conditions) -Conditioner: 5.0 minutes-Soft etching: 1.0 minutes-Pickling: 0.5 minutes-Pre-dip: 1.0 minutes-Catalyst: 5.0 minutes-Accelerator: 7 0.0 minutes, electroless copper plating: 20.0 minutes

Fourth Step Next, heat treatment at 120 ° C. for 1 hour is performed, and pickling treatment is performed.
After drying, a dry film resist (NIT225 manufactured by Nichigo Morton Co., Ltd.) was laminated on the underlying power supply layer. Then, it is exposed (8 by an alignment exposure machine having an ultra-high pressure mercury lamp through a photomask for forming a circuit).
0 mJ / cm ² ) and then spray development with 0.8% sodium carbonate was carried out to form a desired electrically insulating pattern having openings for forming land portions and circuit wiring. Then, electrolytic plating is performed in a copper sulfate plating bath using the above-described electrically insulating pattern as a mask (current density = 3.5 A).
/ Dm ² , energization time = 30 minutes), a conductive material is deposited on the underlying power supply layer, and copper plating with a thickness of about 20 μm is selectively applied to the circuit forming portion including the land portion that closes the opening of the through hole. Formed.

Fifth Step Next, the electrically insulating pattern is removed by spraying a sodium hydroxide bath at 45 ° C., and the exposed unnecessary underlying power supply layer is treated with a perhydrosulfuric acid-based etching solution at 30 ° C. It was removed by spray etching. As a result, the inner diameter is 0.1 m
m, pitch 0.25 mm, through holes are formed, and the land portion (diameter 0.15 mm) that conducts with the conductive paste filled in the through holes is 0.25 mm.
A core substrate of the present invention having circuit wirings formed with a pitch and a space of 50 μm was obtained. With this core substrate, there is no migration between through holes,
Electrical independence between adjacent land parts was secured.

[Embodiment 2] First step, and second step After the first step and the second step similar to those of the first embodiment, the surface of the conductive paste filled in the through hole is formed. A copper clad laminate having the same surface as the copper foil surface was produced.

Third Step Next, electroless copper plating was applied to the entire surface of the copper foil and the conductive paste by electroless plating under the following conditions to form a base feeding layer. (Electroless copper plating conditions) -Conditioner: 5.0 minutes-Soft etching: 1.0 minutes-Pickling: 0.5 minutes-Pre-dip: 1.0 minutes-Catalyst: 5.0 minutes-Accelerator: 7 0.0 minutes, electroless copper plating: 20.0 minutes, then electrolytic plating in a copper sulfate plating bath (current density =
A conductive material was deposited on the underlying power feeding layer at 3.5 A / dm ^{2 for} a current of 30 minutes to form a conductive layer made of a copper plating layer having a thickness of about 20 μm.

Fourth Step Next, a dry film resist (NIT225 manufactured by Nichigo Morton Co., Ltd.) is laminated on the conductive layer and exposed by an alignment exposure machine having an ultrahigh pressure mercury lamp through a photomask for forming a circuit. (80 mJ / cm ² ) and then
Spray development was performed with 0.8% sodium carbonate to form a resist pattern having a coating pattern for forming land portions and circuit wiring. Then, using the resist pattern as a mask, by spray etching using an iron chloride-based etching solution, the conductive layer, the underlying power supply layer,
By removing the copper foil, a land portion for closing the opening of the through hole and a circuit wiring were formed. Then, the resist pattern was removed by spraying a sodium hydroxide bath at 45 ° C.

As a result, the inner diameter is 0.1 mm and the pitch is 0.
A circuit wiring having a through hole formed with a width of 25 mm, a land portion (diameter 0.15 mm) that conducts the conductive paste filled in the through hole is formed at a pitch of 0.25 mm, and a space is 50 μm. The provided core substrate of the present invention was obtained. In this core substrate, migration between through holes did not occur, and electrical independence between adjacent land portions was secured.

[0052]

As described in detail above, according to the present invention, the conduction between the front and back of the core substrate is performed by the conductive paste filled in the through holes and the land portion connected to the conductive paste. , The through hole has an inner diameter of 0.
Range of 05-0.15mm, pitch 0.2-0.3m
Since those having a range of m are provided and these pitches are almost the same as the pitch of the connection pads for mounting the semiconductor chip, a part of the connection pads for mounting the semiconductor chip is not connected via wiring but via the via part. It is possible to directly connect to the land portion, and only for the other connection pad portion, wiring for connecting to the land portion may be formed in the build-up layer on the semiconductor chip mounting surface side, while the pitch is 0.2. ~ 0.3 mm
Although the pitch of multiple lands on the external connection terminal side that closes the through-holes, which is the range of, is smaller than the pitch of the external connection terminal, it is connected to the external connection terminal by the wiring formed in the buildup layer on the external connection terminal side. You can
As a result, necessary wiring can be distributed to the build-up layers on both sides of the core substrate to prevent wiring concentration on the build-up layers on the semiconductor chip mounting surface side, and downsizing by reducing the number of build-up layers stacked. By relaxing the design rules, it is possible to improve the yield of manufacturing a multilayer wiring board. Further, in the manufacturing method of the present invention, since conductive paste is filled in the through holes formed in the copper clad laminate using a laser to establish conduction between the front and back sides, migration between the through holes does not occur and the inner diameter is 0. It is possible to form through holes with a narrow pitch in the range of .05 to 0.15 mm and the pitch is in the range of 0.2 to 0.3 mm, and at the same time as the formation of lands that block the openings of the through holes, the desired The effect that the wiring can be formed on the core substrate can also be achieved.

[Brief description of drawings]

FIG. 1 is a partial vertical cross-sectional view showing an embodiment of a core substrate of the present invention.

FIG. 2 is a partial vertical cross-sectional view showing another embodiment of the core substrate of the present invention.

FIG. 3 is a partial vertical cross-sectional view showing another embodiment of the core substrate of the present invention.

FIG. 4 is a partial vertical cross-sectional view showing an example of a multilayer wiring board using the core substrate of the present invention.

FIG. 5 is a process drawing showing an embodiment of a method of manufacturing a core substrate of the present invention.

FIG. 6 is a process chart showing an embodiment of a method for manufacturing a core substrate of the present invention.

FIG. 7 is a process drawing showing another embodiment of the method for manufacturing a core substrate of the present invention.

FIG. 8 is a process drawing showing another embodiment of the core substrate manufacturing method of the present invention.

FIG. 9 is a process drawing showing an example of a conventional core substrate manufacturing method.

FIG. 10 is a partial vertical cross-sectional view showing an example of a multilayer wiring board using a conventional core board.

[Explanation of symbols]

1, 11, 21, core substrate 2, 12, 22, core material 3, 6, 13, 17, 23 ... through holes 3a, 6a, 13a, 17a, 23a ... through hole openings 4, 14, 24 ... conductive Paste 5, 8, 15, 25 ... Land portion 19 ... Wiring 30 ... Copper clad laminate 31 ... Copper foil 32 ... Underlayer power supply layer 33 ... Electrical insulating pattern 34 ... Conductive layer 35 ... Resist pattern 41 ... Multilayer wiring board 42 , 43 ... Build-up layer 47a ... Connection pad portion 48 ... External connection terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 3/40 H05K 3/40 K F term (reference) 5E317 AA24 BB01 BB12 CC17 CC25 GG16 GG20 5E343 AA12 BB24 BB67 BB72 BB72 DD02 DD33 DD43 GG20 5E346 AA43 CC08 CC32 DD12 DD22 EE01 EE19 FF18 GG15 HH07 HH22 HH33

Claims (10)

[Claims] 1. A core for use in a multilayer wiring board having a plurality of build-up layers on both sides of a core substrate, having a connection pad portion for mounting a semiconductor chip on one surface and having external connection terminals on the other surface. The substrate is provided with a core material having a plurality of through holes filled with a conductive paste, the openings of the through holes are closed by a land portion that is electrically connected to the conductive paste, and the plurality of through holes are provided. At least part of the inner diameter is in the range of 0.05 to 0.15 mm and the pitch is in the range of 0.2 to 0.
A core substrate having a range of 3 mm. 2. The core substrate according to claim 1, wherein each of the through holes has an inner diameter in the range of 0.05 to 0.15 mm. 3. The through holes each have an inner diameter in the range of 0.05 to 0.15 mm and a pitch of 0.2 to 0.
The core substrate according to claim 1, wherein the core substrate has a range of 3 mm. 4. The core substrate according to claim 1, wherein the conductive material contained in the conductive paste is copper particles having a surface coated with silver. 5. A copper clad laminate having a copper foil with a thickness in the range of 5 to 12 μm on both sides of a core material is subjected to a roughening treatment and then irradiated with a laser to have an inner diameter of 0.05. ~
A first step of forming a plurality of through holes including at least a part of through holes having a range of 0.15 mm and a pitch of 0.2 to 0.3 mm; filling the inside of the through holes with a conductive paste; Then, a second step of performing a surface smoothing treatment by physical polishing, a third step of forming an underlayer feeding layer on the entire surface by electroless plating, forming a desired electrically insulating pattern on the underlayer feeding layer, A land is formed by depositing a conductive material on the underlying power supply layer by electrolytic plating using the electrically insulating pattern as a mask, and closing the opening of the through hole while being connected to the conductive paste filled in the through hole. A fourth step of forming a part, and a fifth step of removing the electrically insulating pattern and removing the exposed unnecessary underlying power supply layer by etching. Of manufacturing a core substrate. 6. A copper-clad laminate having a copper foil having a thickness of 5 to 12 μm on both sides of a core material is subjected to a roughening treatment, and then a laser is irradiated to the inner diameter of 0.05. ~
A first step of forming a plurality of through holes including at least a part of through holes having a range of 0.15 mm and a pitch of 0.2 to 0.3 mm; filling the inside of the through holes with a conductive paste; Then, a second step of performing a surface smoothing treatment by physical polishing, a base feeding layer is formed on the entire surface by electroless plating, and a conductive material is deposited on the base feeding layer by electrolytic plating to form a conductive layer. The step of forming a desired resist pattern on the conductive layer, removing the conductive layer and the underlying power supply layer by etching using the resist pattern as a mask, and connecting to the conductive paste filled in the through hole. A fourth step of forming a land portion that closes the opening of the through hole in the above state, and then removing the resist pattern. Method of manufacturing the A board. 7. The method of manufacturing a core substrate according to claim 5, wherein in the fourth step, desired wiring is simultaneously formed together with the land portion. 8. The method of manufacturing a core substrate according to claim 5, wherein the core material has wiring inside. 9. The method of manufacturing a core substrate according to claim 5, wherein a carbon dioxide laser is used as the laser. 10. The method of manufacturing a core substrate according to claim 5, wherein the conductive paste contains a conductive material made of copper particles having a surface coated with silver.