JP2003208136A - Image display method, image display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of display tearing involved with refreshing of a display memory 120 when grayscale data corresponding to pixels are read from the memory 120 and displayed on a display panel 140. <P>SOLUTION: When a refresh occurs during reading and scanning of the memory 120, a display controller 130 skips the reading of the grayscale data corresponding to rows subsequent to the row that is read and scanned when the refresh occurs. Moreover, the contents of the skipped pixels are held in the contents of the frame immediately before the frame in which the refresh has occurred. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display method, an image display device and an electronic device which prevent deterioration of display quality when data is read from a display memory and an image is displayed.

[0002]

2. Description of the Related Art In a bit map type display panel such as an organic EL (Electro Luminescent) device and a liquid crystal device, a read address is sequentially designated (read scan is performed from a display memory in synchronization with vertical scanning and horizontal scanning). ), The method of displaying according to the read gradation data is general. Here, the address of the display memory (sometimes called a frame memory or a video memory) has a one-to-one correspondence with the pixels making up the display, and each address has a gradation of the corresponding pixel. Gradation data defining (density, brightness) is stored. Therefore, when the upper control circuit such as the CPU sequentially rewrites the stored contents of the display memory, the image displayed on the display panel is also rewritten appropriately.

If the upper control circuit rewrites the stored contents of the display memory during the read scanning, the display in one vertical scanning period (one frame) in which the rewriting has occurred is as follows.
The display based on the stored content before the rewriting and the display based on the stored content after the rewriting are mixed (disruption display), and the display quality may be significantly deteriorated.

Therefore, in order to prevent such deterioration of the display quality, the upper control circuit needs to take a procedure in synchronization with the read scanning, for example, instructing the rewriting of the gradation data in a period other than the read scanning. There is.

[0005]

However, when such a procedure is taken, the load of the higher-order control circuit increases, so that there is a problem that the function executed by the higher-order control circuit deteriorates.

It is to be noted that the display memory has two screens (two frames), and in a certain one frame, reading and scanning is performed from one display memory (one screen) and writing is performed to the other display memory. In one frame, a method of reading and scanning from the other display memory and writing to one display memory is also proposed,
In this method, the display quality is prevented from deteriorating, but on the other hand, the capacity of the display memory is doubled, so that it cannot be easily adopted.

In order to solve the above problems, the object of the present invention is to:
An object of the present invention is to provide an image display method, an image display device, and an electronic device capable of preventing deterioration of display quality without increasing the load of the upper control circuit.

[0008]

In order to achieve the above object, an image display method according to the present invention has an address corresponding to each pixel in a display panel, and defines the gradation of the pixel at each address. For the display memory that stores the gradation data to be read, the read address is specified in the order synchronized with the vertical scanning and the horizontal scanning of the display panel, the gradation data is sequentially read from the read address, and the pixel of the display panel is read. Is an image display method in which is a gradation defined by the gradation data,
A first step of determining whether or not a specific rewriting that may deteriorate display quality has occurred in the display memory during the read scanning period for designating the read address, and it is determined that the specific rewriting has occurred in the first step. In the reading scan in which the specific rewriting has occurred, at least the reading of the grayscale data from the address in which the specific rewriting has occurred is skipped, and the pixel corresponding to the skipped address is placed before the reading scan. And a second step of maintaining the gradation defined by the gradation data read out.

According to the present invention, the grayscale data can be written in the display memory regardless of the scanning by the read address, so that the load of the upper control circuit for performing the writing is reduced and the display quality is improved. Since the reading from the address where the specific rewriting that may decrease is skipped and the pixel corresponding to the address is held at the gradation specified by the previously read gradation data, As a result of preventing the broken display screen, the display quality does not deteriorate.

Further, in the image display method according to the present invention, in the above-mentioned image display method, in the first step, when the gradation data is rewritten during the read scanning period, the rewriting occurs at the time when the rewriting occurs. It is characterized in that it is determined that the specific rewriting has occurred regardless of the read address.

Further, in the image display method according to the present invention, in the above-mentioned image display method, when the gradation data is rewritten in the read scanning period in the first step, all the addresses in which the rewriting has occurred are rewritten. Is included in the area already designated as the read address in the read scan in which the rewriting has occurred, and the read address at the completion of the rewriting is predicted, and all the addresses in which the rewriting has occurred are the predicted values. Determine whether it is included in the area after the read address,
When the determination results of both are negative, it is determined that the specific rewriting has occurred.

Further, in the image display method according to the present invention, in the image display method described above, when it is determined in the second step that the specific rewriting has occurred in the second step, reading at the time of the determination is performed. It is characterized in that reading from the row subsequent to the row including the address is skipped, and pixels located after the pixel row corresponding to the skipped row address are held.

Further, in the image display method according to the present invention, in the above-described image display method, the write polarity for the same pixel is set at every one or more vertical scanning periods according to a polarity instruction flag which indicates the write polarity. When it is determined that the specific rewriting has occurred in the first step in the case of reversing, the read scanning next to the reading scanning in which the specific rewriting has occurred is followed by the skipped address after the second step. The third step of writing the corresponding pixel in the opposite polarity to the polarity in the read scan in which the specific rewriting has occurred, regardless of the polarity instruction flag, and the read scan in which the write in the third step has occurred When the opposite polarity written in the pixel corresponding to the skipped address is the same as the write polarity instructed by the write instruction in the read scanning of, Causes skip reading from the address to respond, the pixels corresponding to the address obtained by skipping, characterized in that it comprises a fourth step of holding the gradation burned with opposite polarities.

Further, the image display device according to the present invention has a display memory having an address corresponding to each pixel in the display panel and storing gradation data defining a gradation of the pixel at each address. The display memory includes a designating unit for designating a read address in an order synchronized with vertical scanning and horizontal scanning of the display panel, and a reading unit for sequentially reading grayscale data from the read address. In the image display device in which the gradation is defined by the gradation data, whether or not a specific rewriting that may deteriorate the display quality occurs in the display memory during the reading scanning period for designating the reading address. When the specific rewriting is determined to have occurred by the determining means, the read scan in which the specific rewriting has occurred determines at least the number in which the specific rewriting has occurred. A first holding unit for skipping the reading of the gradation data from the pixel and holding the pixel corresponding to the skipped address at the gradation defined by the gradation data read before the reading scan. And is provided.

Further, in the image display device according to the present invention, in the above-mentioned image display device, in the determination means, when the gradation data is rewritten during the read scanning period, the rewriting occurs at the time when the rewriting occurs. It is characterized in that it is determined that the specific rewriting has occurred regardless of the read address.

Further, in the image display device according to the present invention, in the above-mentioned image display device, when the gradation data is rewritten in the reading scanning period in the discrimination means, all the addresses where the rewriting is generated. Is included in the area already designated as the read address in the read scan in which the rewriting has occurred, and the read address at the completion of the rewriting is predicted, and all the addresses in which the rewriting has occurred are the predicted values. It is characterized in that it is determined whether or not it is included in the area after the read address, and when both determination results are negative, it is determined that the specific rewriting has occurred.

Further, in the image display device according to the present invention, in the image display device described above, in the first holding means, when it is determined by the determining means that the specific rewriting has occurred, at the time of the determination. The reading of the row subsequent to the row including the reading address is skipped, and the pixels located after the pixel row corresponding to the skipped row address are retained.

Further, in the image display device according to the present invention, in the above-mentioned image display device, the write polarity for the same pixel is set every one or more vertical scanning periods according to a polarity instruction flag which indicates the write polarity. When the specific rewriting is determined to have occurred by the determining means in the case of reversing to the above, the process is skipped in the read scan next to the read scan in which the specific rewrite has occurred after the processing of the holding means is performed. Irrespective of the polarity designating flag, the writing means for writing the pixel corresponding to the address with a polarity opposite to the polarity in the reading scan in which the specific rewriting has occurred, and the reading in which the writing by the writing means has occurred. In the read scan after the scan,
When the opposite polarity written in the pixel corresponding to the skipped address is the same as the write polarity instructed by the write instruction, reading from the address corresponding to the pixel is skipped and the skipped address is skipped. And a second holding unit that holds the pixel corresponding to the gray level written in the opposite polarity.

Furthermore, an electronic apparatus according to the present invention is characterized by including the image display device according to the present invention.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a block diagram showing the overall configuration of a display device to which an image display method according to a first embodiment of the present invention is applied.

As shown in this figure, the display device 100
Is an upper control circuit 110, a display memory 120, a display controller 130, a display panel 140,
It includes a Y driver 150 and an X driver 160.

Of these, the upper control circuit 110 is a control entity that executes various functions according to instructions from an operation switch (not shown), and in particular, in this embodiment,
The data WD is generated according to the content to be displayed, and the command WCM including the fact that the data WD has been generated and the information regarding the write address of the data WD is issued.

The display memory 120 is a dedicated memory for screen display, and its storage address is the display panel 140.
The gradation data defining the gradation of the corresponding pixel is stored at each address in a one-to-one correspondence with the pixel. The storage capacity of the display memory 120 may be larger than the display capacity of the display panel 140. In this case, a part of the storage area of the display memory 120 and the pixels of the display panel 140 are in one-to-one correspondence.

The display controller 130 steps in a read address Rad for reading grayscale data in the order of vertical scanning and horizontal scanning, and generates various clock signals in synchronization with the step. When the command WCM is received from the upper control circuit 110, the step of the read address Rad is stopped as described later, and
The generation timings of various clock signals are changed in accordance with this step stop. Furthermore, the display controller 1
30 interprets the received command WCM and generates the write address Wad of the data WD.

The clock signal and the like generated by the display controller 130 are, in this embodiment,
Start pulse DY, clock signal YCK, start pulse DX, clock signal XsCK and latch pulse L
P.

The display panel 140 includes m scanning lines 1410 and n data lines 1 provided so as to intersect each other.
Organic E with pixels 1400 at each intersection with 420
L device. The Y driver 150 has scanning signals Y1 and Y.
2, Y3, ..., Ym are sequentially supplied to each of the scanning lines 1410 from the first row to the m-th row. The X driver 160 has data signals X1, X2, X3, ..., According to the gradation data RD read from the display memory 120.
Xn is generated and the data lines 142 from the first column to the n-th column are generated.
0 is supplied all at once.

<Pixel Configuration> Next, the above-described pixel 140
Details of 0 will be described. FIG. 2 shows i adjacent to each other.
The scanning line 1410 of the row and the (i + 1) th row and the data line 142 of the jth column and the (j + 1) th row which are adjacent to each other.
FIG. 6 is a circuit diagram showing a configuration of a total of 4 pixels provided corresponding to an intersection with 0. Here, i is a symbol used to generally describe the scan line 1410, and 1 ≦ i ≦ m.
Is an integer that satisfies. Similarly, j is the data line 1420.
Is a symbol used to generally describe
It is an integer that satisfies ≦ n.

As shown in FIG. 2, each pixel 1400
Have thin film transistors (hereinafter abbreviated as “TFT”) 1432 and 1434 and an EL element 1450, respectively.

For the sake of convenience, when attention is paid to the pixel 1400 located in the i-th row and the j-th column corresponding to the intersection of the i-th scanning line 1410 and the j-th column data line 1420, the TF of the pixel 1400 is concerned.
T1432 is the j-th column data line 1420 and the TFT 14
It is inserted between 34 and the gate g. TFT143
Since the gate of 2 is connected to the scanning line 1410 of the i-th row, the TFT 1432 functions as a switch that is turned on when the scanning signal Yi becomes H level.

Further, the gate g of the TFT 1434 (TFT
A capacitance 1440 is parasitic on the drain of 1432. In the present embodiment, the capacity 1440 is set to TF.
Although the parasitic capacitance of T1434 is used,
It is also possible to provide a capacitor between the gate g and the power supply line (for example, ground line) having a constant potential, and use the capacitor as the capacitance 1440.

The EL element 1450 is inserted in the forward direction between the power supply line of the power supply voltage Vdd and the drain of the TFT 1434. Specifically, the anode of the EL element 1450 is connected to the power supply line of the power supply voltage Vdd, while
The cathode of 50 is connected to the drain of TFT 1434. Further, the source of the TFT 1434 has a reference voltage Gnd.
Grounded to. The EL element 1450 has a light emitting (EL) layer sandwiched between an anode that is a common electrode and a cathode that is a pixel electrode, and emits light with a brightness according to a current, but since the details are not directly related to this case, description thereof will be made. Is omitted. Further, the EL element 1450 can be replaced with a light emitting diode.

In this pixel 1400, the scanning signal Yi is H
When the level is reached, the TFT 1432 turns on, so
The gate g of the TFT 1434 is the data line 142 of the j-th column.
It becomes the voltage of the data signal Xj applied to 0, and
The charge according to the voltage is accumulated in the capacitor 1440. Therefore, when the scanning signal Yi becomes H level, EL
A current according to the voltage of the data signal Xj flows through the element 1450 by the TFT 1434.

On the other hand, when the scanning signal Yi becomes L level,
Although the TFT 1432 is turned off, the gate g of the TFT 1434 is held by the capacitor 1440 at the voltage of the data signal Xj immediately before the TFT 1432 is turned off. Therefore, even if the scanning signal Yi changes from the H level to the H level, the EL element 1450 holds the held data signal Xj.
The current corresponding to the voltage of 1 continues to flow through the TFT 1434.

<Y Driver> Next, details of the Y driver 150 described above will be described. FIG. 3 shows the Y driver 1
It is a block diagram which shows the structure of 50.

As shown in this figure, the Y driver 15
Reference numeral 0 is a kind of shift register, which includes a transfer circuit (TU) 1515 corresponding to each row of the scanning line 1410.

The Y driver 150 has a clock signal Y generated by the display controller 130.
CK and start pulse DY are supplied respectively.

Of these, the former clock signal YCK is
Normally, it has a frequency represented by the reciprocal of one horizontal scanning period (1H), but when a skip process described later is executed, the frequency becomes sufficiently higher than usual (for example, 100
0 times), and the high frequency state continues for at least m cycles or more. The latter start pulse DY is 1
It defines the start of frame (1F).

The transfer circuit 1515 on the i-th row latches the input signal to the level immediately before the rise of the clock signal YCK, and the latched signal is transferred to the scanning line 14 on the i-th row.
10 as a scanning signal Yi, and also as an input signal to the transfer circuit 1515 in the next (i + 1) th row. However, the input signal of the transfer circuit 1515 in the first row is the start pulse DY.

In such a configuration, the clock signal Y
If CK is normal, as shown in FIG.
The signal DY supplied at the beginning of the frame (1F) is sequentially shifted at each rising edge of the clock signal YCK, and the shifted signals are 1, 2, 3, respectively.
The scanning signals Y1, Y2, Y3, Y4, ..., Ym are output to the scanning lines 1410 of the fourth, ..., Mth rows, respectively.

Therefore, the scanning signals Y1, Y2, Y3, Y
, ..., Ym sequentially become H level for one horizontal scanning period (1H) from the timing when the clock signal YCK rises for the first time when the signal DY becomes H level.

On the other hand, when the clock signal YCK is in the high frequency state, for example, when the scanning signal Y3 is in the high frequency state at the timing of transition from the H level to the L level, scanning is performed as shown in FIG. 4 (b). Signals Y1, Y2, Y3
Indicates one horizontal scanning period (1
H) only goes to H level, but Y4, Y5, ..., Ym
It only goes high for a moment.

As described above, when the scanning signal Yi becomes the H level, the capacitance 1440 in the pixel 1400 in the i-th row.
, Are respectively charged and discharged according to the voltages of the data signals X1, X2, X3, ..., Xn, but if the period of the H level is extremely short, the amount of accumulated charges hardly changes. Therefore, due to the high frequency state of the clock signal YCK, even if the scanning signal Yi goes to the H level for a moment, there is almost no change in the amount of charges accumulated in each of the capacitors 1440, and therefore the corresponding EL element 145.
The brightness of 0 will also be maintained.

<X Driver> Next, details of the X driver 160 described above will be described. FIG. 5 shows the X driver 1
It is a block diagram which shows the structure of 60.

As shown in this figure, the X driver 16
0 corresponds to each column of the data line 1420 and corresponds to the transfer circuit (TU) 1615 and the register (Reg) 162.
0, the latch circuit (L) 1630, and the D / A converter 16
40 and.

The X driver 160 has a clock signal X generated by the display controller 130.
The sCK, the start pulse DX, the latch pulse LP, and the gradation data RD read from the display memory 120 are respectively supplied.

Of these, the clock signal XsCK is a signal for transferring the input signal to the transfer circuit 1615, and has the same cycle as the step interval of the read address Rad.
The start pulse DX is output at the read start timing of the grayscale data RD for one row. Latch pulse LP
Is output at a timing immediately after the last n-column grayscale data of one row is read, and defines the start of one horizontal scanning period.

The transfer circuit 1615 of the j-th column latches the input signal to the level immediately before the rise of the clock signal XsCK, outputs the latched signal as the sampling control signal Xsj, and is the next stage (j +
1) It is supplied as an input signal to the transfer circuit 1615 in the column. However, the input signal of the transfer circuit 1615 in the first column is
This is the start pulse DX.

Then, the register (Reg) 16 of the j-th column
20 is gradation data RD supplied through the data bus
Is sampled at the rising edge of the sampling control signal Xsj output from the transfer circuit 1615 of the j-th column and held.

Further, the latch circuit (L) 163 of the j-th column
0 also latches and outputs the grayscale data RD held by the register 1620 of the jth column at the rising edge of the latch pulse LP.

Then, the j / th column D / A converter 1640
Converts the gradation data RD latched by the latch circuit 1630 in the jth column into an analog voltage and outputs the analog voltage to the data line 1420 in the jth column as a data signal Xj.

FIG. 6 is a timing chart for explaining the operation of the X driver 160. As shown in this figure, when the start pulse DX rises to the H level prior to the timing when the latch pulse LP is output and the scanning signal Yi transitions to the H level, the i-th row is 1, 2, 3 , ..., gradation data R corresponding to the pixels in the nth column
D is sequentially read from the display memory 120 and supplied.

Among them, when the sampling control signal Xs1 rises to the H level at the timing when the grayscale data RD corresponding to the pixel in the i-th row and the 1st column is supplied, the grayscale data is stored in the register 1620 ( In FIG. 6, it is sampled by "1: Reg".

Next, when the sampling control signal Xs2 rises to the H level at the timing at which the grayscale data RD corresponding to the pixel in the i-th row and the 2nd column is supplied, the grayscale data is stored in the register 1620 (in the second column). In FIG. 6, it is sampled by “2: Reg”.
Similarly, the gradation data RD corresponding to the pixels in the third, fourth, ..., Nth columns are sampled by the registers 1620 in the third, fourth ,.

Subsequently, when the latch pulse LP is output, the grayscale data RD sampled by the registers 1620 of each column are latched all at once by the latch circuits 1630 corresponding to the columns.

The gradation data RD latched in the 1, 2, 3, ..., N columns are respectively 1, 2, 3 ,.
, N columns of D / A converters 1640 convert the data and output them as data signals X1, X2, X3 ,.

The scanning signal Yi becomes L level in synchronization with the simultaneous output of the data signals for one row, that is, in synchronization with the output of the latch pulse LP, and the scanning line 1410 of the i-th row is selected. Will be.

Although the output operation of the data signal corresponding to the pixel located on the i-th row has been described here, such output operation is actually performed on the first, second, and third rows, respectively. , ..., The scanning lines 1410 on the m-th row are sequentially executed.

<Display Controller> Next, the details of the processing executed by the display controller 130 will be described. FIG. 7 is a flowchart showing the processing contents of the main routine in the display controller 130.

As shown in this figure, immediately after power-on or reset, the display controller 1
The frame 30 executes frame processing (step S10).

Next, after the frame processing, the display controller 130 determines whether or not a period corresponding to one vertical scanning period (one frame) has elapsed from the start of the frame processing (step S12).

When the determination result is negative, the display controller 130 executes the processing procedure in step S12.
While waiting, the frame processing is executed again when the result is affirmative. That is, the frame processing in step S10 is executed every other frame.

Details of the frame processing will be described. The frame process is a read process from the display memory 120, and a write process when the command WCM is received from the upper control circuit 110 is excluded.

Regarding the writing process, when the command WCM is received from the upper control circuit 110, the data WD is changed to the display controller 13 regardless of the reading scan.
By 0, it is written in the display memory 120 at the write address included in the instruction WCM. Therefore, the upper control circuit 110 can transfer the data WD and issue the command WCM without considering the designation of the read address (read scan) by the display controller 130, and the load is accordingly increased. Is reduced. However, in the present embodiment, it is assumed that data is not rewritten for two consecutive frames.

FIG. 8 is a flowchart showing details of frame processing.

First, the display controller 130
Sets "1" to the variable p (step S10)
2). Here, the variable p is set to any integer from "1" to "m", which is the number of scanning lines 1410, in order to indicate the pixel row to be read out. When "1" is set to the variable p in step S102, the pixel row that is the target of the read scan is the first row.

Next, the display controller 130
Performs the read scan for the pixel row specified by the variable p (step S110). More specifically, the display controller 130 is arranged in the p-th row and the first to n-th columns.
The read address Rad is stepped in synchronization with the clock signal XsCK so as to sequentially specify the addresses in which the gradation data of the pixels located up to the column are stored (step S110).
By this step, pixel 1 from p row 1 column to p row n column
The gradation data RD for rows is sequentially read from the display memory 120 and supplied to the X driver 160.

Subsequently, the display controller 130
Determines whether or not specific rewriting has occurred in the read scanning in step S110 (step S114).

Here, the specific rewriting means the rewriting in which the display quality may be deteriorated due to the fracture display, and in the present embodiment, the specific rewriting simply means the rewriting of the gradation data of the display memory 120. . The rewriting of the gradation data always occurs when the command WCM is received from the upper control circuit 110. Therefore, the occurrence of the specific rewriting is synonymous with the reception of the command WCM in the present embodiment.

When such specific rewriting has not occurred (command WCM has been received), the display controller 13
0 indicates that the variable p at the present time is the number m of scanning lines 1410.
Whether or not the target of the read scan is the last m.
It is determined whether or not it is a line (step S116).

When the result of this determination is negative, the display controller 130 increments the variable p by "1" in order to set the read scanning target to the next pixel row (step S118), and the processing procedure is performed again. Step S11
Return to 0. This causes step S11 to be executed again.
At 0, the read scan for the next row is executed.

As described above, the read scanning in step S110 is as long as the determination result in step S114 is negative.
The variable p is repeatedly executed from "1" to "m", that is, every line from the first line to the m-th line.

Therefore, when the determination result of step S116 is affirmative, it means that the reading scanning up to the last m-th row has been completed in the current frame, and therefore the display controller 130 terminates the frame processing. Then, it stands by until the start of the next frame processing (step S12).

On the other hand, when it is determined in step S114 that the specific rewriting has occurred, the display controller 1
30 temporarily raises the frequency of the clock signal YCK after the timing when the scanning signal Yp supplied to the p-th scanning line 1410 transitions from the H level to the L level (step S122). After that, the display controller 130 ends the current frame processing and waits for the next one frame.

That is, if a specific rewrite occurs during the read scan of the p-th row, the current frame processing is completed without executing the read scan of the (p + 1) -th row.
The grayscale data corresponding to the pixels from the (+1) th row to the final mth row is not read from the display memory 120.

Further, the scanning signal supplied to the scanning line 1410 from the (p + 1) th row to the last m-th row is H for a moment.
Since the level does not reach the level, the brightness of each EL element 1450 from the (p + 1) th row to the final m-th row remains maintained from the immediately preceding frame. Therefore, the first one
The display contents of the pixels 1400 from the first row to the final m-th row do not change even if the rewriting of the display memory 120 occurs in the read scanning period from the first row to the m-th row.

<Comparison with Comparative Example> Here, a comparative example with respect to this embodiment will be described. FIG. 9A is a chart showing how the grayscale data is read out from the display memory 120 for each row in each frame in the comparative example, and FIG. When the grayscale data is read out as shown in a), the display panel 140
It is a figure which shows simply the display content of every frame. In addition, in FIG. 9A, the number of display lines of the display panel 140 is 18 in order to simplify the description. Also, in FIG. 9 and the like, the alphabets indicate patterns to be displayed.

Since the higher-order control circuit of the comparative example instructs writing to the display memory regardless of the reading scan from the display memory (asynchronously), the contents of the display memory may be rewritten during the reading scan. It can happen.

For example, in FIG. 9A, in frames 1 and 2, the grayscale data related to the pattern A is read from the display memory, but in frame 3, the grayscale data of the eighth row is read and scanned. While being displayed, the display memory 120
Is rewritten to the gradation data related to the pattern B.

Therefore, as shown in FIG. 10A, in frames 1 and 2, (strictly speaking, read scanning is completed, and further, all scanning lines 14 in display panel 140 are completed.
10 is selected), the display panel 140 displays the pattern A (a diagonally parallel black parallelogram to the left in the figure) over the entire row.
Is correctly displayed, but in frame 3, the 1st to 8th lines are the pattern A, and the 9th and subsequent lines are the pattern B (in the figure, the diagonally right black parallelogram), and the upper half of the screen is displayed. The display quality is remarkably deteriorated because the display is inconsistent with the lower half (fracture display).

In the frames 3 and 4, the display memory 120 cannot be rewritten during the read scanning period as shown in FIG. 9A, so that the display panel 140 shown in FIG.
As shown in (a), the pattern B is correctly displayed over all the lines.

Further, although the display contents of the display panel 140 after the frame 6 are omitted in FIG. 10A, as shown in FIG. 9A, rewriting in the middle of the read scanning period is as follows. It occurs even while the grayscale data on the 10th row is being read and scanned in frame 7 and during the grayscale data on the 7th row is being read and scanned in frame 10. Therefore, the tear display also occurs in the frames 7 and 10.

On the other hand, in this embodiment, the frame 3
When the grayscale data is rewritten during the period in which the grayscale data of the eighth row is read and scanned at, the grayscale data of the ninth and subsequent rows is read as indicated by "←" in FIG. 9B. The scan is skipped.

This operation will be described with reference to the frame processing in FIG. 8. In the frame processing corresponding to the frame 3, every time the variable p is set to a value from "1" to "8", the reading in step S110 is performed. Although scanning is executed, in the state where the variable p is set to "8", step S11
Since the determination result of No. 4 is negative, as a result of branching to step S122, the scanning of reading the grayscale data of the ninth and subsequent rows is skipped.

Therefore, in the display panel 140, the pixels from the first row to the eighth row follow the gradation data read by the frame processing in the current frame 3, as shown in FIG. 10B. Therefore, the pattern A is displayed, but the pixels on the ninth and subsequent rows are displayed according to the gradation data read by the previous frame processing (that is, the frame processing in the frame 2), and thus the display of the pattern A is maintained. Will be done.

Although not shown in FIG. 10 (b), FIG. 9 (b)
The same applies to frames 7 and 10 in FIG.

Therefore, according to the present embodiment, even if rewriting occurs in the middle of the read scanning period, the breakage display unlike the comparative example does not occur, so that the deterioration of the display quality can be prevented.

Since the lower half of the screen is not refreshed over two frames, frames 2 and 3, the capacity 144 included in the pixels of the lower half (9th row and subsequent rows) is
In 0, the upper half (1
As compared with the capacitor 1440 included in the pixels on the 8th to 8th rows), the leakage of accumulated charge progresses, which results in FIG.
As shown in (b), the brightness is slightly lowered.

<Second Embodiment> The first embodiment described above is a display method for preventing a broken display in a display device using an element such as the EL element 1450 which is basically driven by direct current. The present invention is not limited to this, and can be applied to a display device using an element such as a liquid crystal element which is driven by an alternating current in principle.

Here, if the read scan is skipped due to the occurrence of the specific rewriting, the pixel corresponding to the skipped address is not refreshed, so that the pixel has the polarity designated in the next frame and the frame concerned. The voltage corresponding to the grayscale data read by the read scan in is written.

However, if the write polarity for the liquid crystal element is inverted for each frame for AC drive, the data signals of the same polarity are continuously written in the pixels corresponding to the skipped addresses. The reason for this is that after writing with one polarity, writing is performed again with one polarity instead of writing with the other polarity due to the occurrence of skip.

As a result, the principle of AC driving is broken, so that for a display device using a liquid crystal element, simply,
The first embodiment cannot be applied.

Therefore, when the read scanning is skipped,
A second embodiment in which the pixels corresponding to the skipped addresses are prevented from being written with the same polarity will be described.

The display device to which the display method according to the second embodiment is applied is different from the display device to which the display method according to the first embodiment is applied in the following three points. That is, the pixel configuration is different (difference), and the X driver 1
60 is different in configuration (difference) and frame processing (reading processing) in the display controller 130
Are different points (differences), and these three points will be described in order. Other than that, the description is omitted because it already overlaps with the first embodiment.

<Pixel> FIG. 11 is a circuit diagram showing a pixel of a display device to which the display method according to the second embodiment is applied.

As shown in this figure, each pixel 1400
Has a TFT 1462 and a liquid crystal element 1470, respectively. Here, focusing on the pixel 1400 located at the i-th row and the j-th column corresponding to the intersection of the i-th scanning line 1410 and the j-th column data line 1420, the TF of the pixel 1400 is detected.
T1462 is the data line 1420 of the j-th column and the liquid crystal element 1
It is inserted between one end of 470. In addition, TFT1
The gate of 462 is connected to the i-th scanning line 1410. Therefore, the TFT 1462 functions as a switch that is turned on when the scanning signal Yi becomes H level.

The liquid crystal element 1470 forms a kind of capacitance by a rectangular pixel electrode which is one end, a counter electrode which is the other end, and a liquid crystal sandwiched between both electrodes, and the amount of charge accumulated in the capacitance. The orientation of the liquid crystal molecules changes according to the above.

Here, the counter electrode is common to each pixel 1400, and its potential is also constant with time. Therefore, in the present embodiment, positive writing means writing a voltage higher than the counter electrode potential, and negative writing means writing a voltage lower than the counter electrode potential. Means

Note that the drain D (pixel electrode) of the TFT 1462 may be provided with a storage capacitor separately in order to reduce the leakage of charges accumulated in the liquid crystal element.

In the structure shown in FIG. 11, when the scanning signal Yi becomes H level, the pixel 1400 in the i-th row has a T-value.
Since the FT 1462 is turned on, the potential of the pixel electrode, which is one end of the liquid crystal element 1470, becomes the voltage of the data signal Xj in the i-th row and the j-th column, for example. Therefore, charges corresponding to the voltage of the data signal Xj are accumulated in the liquid crystal element. After the charge accumulation, the scanning signal Yi becomes L level,
Even if the TFT 1462 is turned off, the accumulation of charges in the liquid crystal element 1470 is maintained.

Here, as a result of the alignment state of the liquid crystal molecules changing in accordance with the amount of charge accumulated in the liquid crystal element 1470, the liquid crystal element 1470 passes through the liquid crystal element 1470 and is emitted from a polarizer (not shown) to be visually recognized by the user. The amount of light emitted also changes according to the amount of accumulated charges.

Therefore, even if the scanning signal changes from the H level to the L level, the pixel 1400 maintains the state defined by the data signal Xj at the H level.

As the pixel 1400 using a liquid crystal element, in addition to the structure shown in FIG. 11, a two-terminal type non-linear element having a bidirectional diode characteristic (for example, a thin film diode) and a liquid crystal element 1470 are used. Scan line 1410
And a data line 1420 may be inserted in series. Furthermore, a passive matrix type configuration for driving a liquid crystal element without using a three-terminal type non-linear element such as a TFT or a two-terminal type non-linear element having a bidirectional diode characteristic, specifically, a scanning line 1410 A passive matrix type configuration in which the data line 1420 itself is used as one end of the liquid crystal element 1470 and the data line 1420 itself is used as the other end of the liquid crystal element 1470 may be used. Further, here, the voltage modulation method using the D / A circuit is taken as an example of the method of displaying the gradation, but of course, the pulse width modulation method or another method may be used.

<X Driver> FIG. 12 is a block diagram showing the configuration of the X driver 160 applied to the second embodiment. 5 is different from the configuration shown in FIG. 5 in that the D / A converter 1640 in each column is replaced by a D / A converter 1650 and that each of the D / A converters 1650 is different. Signal AK is respectively supplied.

Here, the signal AK is a signal generated by the display controller 130 and indicates the polarity of the output signal to the D / A converter 1650. Specifically, the signal AK indicates a positive polarity when it is at L level, and a negative polarity when the signal AK is at H level.

The D / A converter 1650 in the j-th column converts the grayscale data latched by the rising edge of the latch pulse LP into an analog signal having the polarity designated by the signal AK, and outputs it as the data signal Xj in the j-th column. Eye data line 1
Output to 420.

<Display Controller> Next, the second
Display controller 130 applied to the embodiment
The details of the processing executed by will be described.
FIG. 13 is a flowchart showing the processing contents of the main routine in the display controller 130.

As shown in this figure, immediately after power-on or reset, the display controller 1
30 executes an initialization process (step S2). Specifically, the display controller 130 has a register Mod for setting a value for defining the operation mode.
Is reset to zero and "1" is set in each of the registers L-1, L-2, L-3, ..., Lm provided corresponding to each row.

If the values set in the register Mod are "0", "1", "2", and "3", the operation modes are normal (N) mode, rewrite (W) mode, and The exclusive (X) mode and the skip (S) mode are assumed. Therefore, the operation mode is set to the normal (N) mode by the initialization processing in step S2.

Registers L-1, L-2, L-3, ..., L
-M is 1, 2, 3 in the immediately preceding frame,
.. indicates the writing polarity for the pixels in the m-th row, and in the present embodiment, “0” means positive polarity and “1” means negative polarity. Since the immediately preceding frame does not exist in the first frame, it is assumed that the initialization process in step S2 has performed the negative writing on each row in the immediately preceding frame that does not exist.

After this initialization processing, the display controller 130 executes frame processing (step S).
20). Next, after the frame processing, the display controller 130 determines whether or not a period corresponding to one vertical scanning period (one frame) has elapsed since the start of the frame processing (step S22).

If the determination result is negative, the display controller 130 proceeds to step S22.
While waiting, the frame processing is executed again when the result is affirmative. That is, the frame processing in step S20 is executed every other frame, as in the first embodiment.

Details of frame processing will be described below. 14, FIG. 15 and FIG. 16 are flowcharts showing details of frame processing in the second embodiment.

First, at the start of frame processing, the display controller 130 sets "1" to the variable p for specifying the pixel row to be the target of read scanning (step S202).

Next, the display controller 130
Is whether the value of the variable Mod is “0”, that is,
It is determined whether or not the operation mode is the normal (N) mode (step S204).

When the result of this determination is affirmative, the display controller 130 executes read-out scanning for the pixel row specified by the variable p, as in step S110 in the first embodiment (step S210). By this scanning, the grayscale data for one row of pixels from p rows and 1 columns to p rows and n columns are sequentially read from the display memory 120 and supplied to the X driver 160.

After reading the grayscale data of p rows and n columns and before outputting the latch pulse LP, the display controller 130 outputs the signal AK at the level of the write polarity instructed by the polarity instructing flag Pol. (Step S21
1).

Here, the polarity designation flag Pol indicates which polarity the grayscale data read by this frame processing is written to the pixel 1400. Specifically, in the present embodiment, it is an odd frame. Is "0" to instruct writing of positive polarity, while it is "1" in even-numbered frames to instruct writing of negative polarity.

As described above, the X driver 160 temporarily latches the read grayscale data for one row by the latch circuit 1630, and then the D / A converter 1650.
Is converted into a data signal and supplied to the data line 1420, the step S2 is performed after the gradation data of the last n columns of p rows is read and before the output of the latch pulse LP.
When the signal AK is set to the logic level instructed by the polarity instruction flag Pol in 11, the D / A converter 165
The data signal of 0 has the polarity designated by the polarity designation flag Pol, and is actually written in the pixel 1400 in the p row.

Next, in the present frame processing, the display controller 130 registers the register corresponding to the p-th row in order to record that the pixel 1400 in the p-th row is written with the polarity designated by the polarity designation flag Pol. Lp
Then, the current value of the polarity instruction flag Pol is set (step S212).

Subsequently, the display controller 130
Determines whether or not specific rewriting has occurred in the read scanning in step S211 (step S214).
Here, the specific rewriting simply means rewriting the gradation data in the display memory 120, as in the first embodiment.

When the determination result is negative, the display controller 130 determines whether or not the variable p at the present time is equal to the number m of scanning lines 1410 (step S216).

When the result of this determination is negative, the display controller 130 increments the variable p by "1" in order to set the read scanning target to the next pixel row (step S218), and the processing procedure is performed again. Step S21
Return to 0.

When the determination result of step S216 is affirmative, the display controller 130 ends the current frame processing and waits until the start of the next frame (step S22).

When it is determined in step S210 that the specific rewriting has occurred, the display controller 1
30 shifts the operation mode to the rewrite (W) mode,
"1" is set to the variable Mod (step S22)
0).

Next, the display controller 130
Is the scanning signal Yp supplied to the p-th scanning line 1410.
The clock signal YCK is temporarily increased in frequency after the timing when H changes from H level to L level (step S222).

Then, the display controller 130
Sets "2" to the variable Mod in order to set the operation mode in the next frame processing to the exclusive (X) mode (step S224), and thereafter ends the current frame processing and continues until the start of the next frame. stand by.

That is, if a specific rewrite occurs during the read scan of the p-th row, the frame processing this time is completed without executing the read scan of the (p + 1) -th row.
The grayscale data corresponding to the pixels from the (+1) th row to the final mth row is not read from the display memory 120.

Further, the scanning signal supplied to the scanning line 1410 from the (p + 1) th row to the final mth row is H for a moment.
Since the level does not reach the level, the densities of the liquid crystal elements 1470 from the (p + 1) th row to the last m-th row remain maintained from the immediately preceding frame. Therefore, the first one
The display contents of the pixels 1400 from the first row to the final m-th row do not change even if the rewriting of the display memory 120 occurs in the read scanning period from the first row to the m-th row.

As described above, in the normal (N) mode, 1
The gradation data is read by sequentially performing scanning from the row to the m-th row, and the gradation data is read from the polarity instruction flag P.
The operation of converting into an analog signal of the polarity designated by ol and writing it into the pixel 1400 is executed. However, if the specific rewriting occurs during the read scanning from the first row to the m-th row, the mode shifts to the rewriting (W) mode, and the read scanning after the row following the row in which the specific rewriting has occurred is skipped. There is no change in the display by the pixels 1400 in the selected row.

On the other hand, the display controller 130
Indicates that the value of the variable Mod is “0” in step S204.
If not, it is further determined whether or not the value of the variable Mod is “2”, that is, whether or not the operation mode is the exclusive (X) mode (step S20).
6).

Here, the variable Mod is set to "2" when the initial operation mode in the previous frame processing is the normal (N) mode or the skip (S) mode which will be described in detail later. And, only when the specific rewriting occurs (step S224).

Therefore, in the frame next to the frame in which the specific rewriting has occurred, the reading process in the exclusive (X) mode shown in FIG. 15 is executed.

First, the display controller 130
Performs the read scan for the pixel row specified by the variable p, as in step S210 in the normal (N) mode (step S240). By this scanning, the gradation data for one row of pixels from p row 1 column to p row n column is sequentially read from the display memory 120, and the X driver 16
The point of being supplied to 0 is the same as step S210 in the normal (N) mode.

After reading the grayscale data of p rows and n columns and before the output of the latch pulse LP, the display controller 130 indicates the signal AK by the inverted value of the value set in the register Lp. The data is output at the write polarity level (step S241).

That is, in the exclusive (X) mode, p
When the grayscale data for one row of pixels is read out, the grayscale data is read as a polarity indication flag Pol that indicates the write polarity.
However, it is converted into an analog signal having a polarity opposite to the polarity written immediately before, and the pixel 140
Will be written to zero.

Next, in the present frame processing, the display controller 130 records the fact that the pixel 1400 in the p-th row is written with the polarity indicated by the inverted value of the value set in the register L-i. Is the register L
The value set in −p is rewritten to the inverted value (step S242).

Subsequently, the display controller 130
Determines whether the current variable p is equal to the number m of scanning lines 1410 (step S256).

When the result of this determination is negative, the display controller 130 increments the variable p by "1" in order to set the read scanning target to the next pixel row (step S258), and then the processing procedure is performed again. Step S24
Return to 0.

If the determination result of step S256 is affirmative, the display controller 130 sets the variable Mod to "3" to set the operation mode to the skip (S) mode in the next frame processing ( (Step S260) After that, the current frame processing is ended, and the process waits until the start of the next frame (step S260).
22).

As described above, in the exclusive (X) mode, the gray scale data is read by sequentially performing the read scanning from the first row to the m-th row, and the gray scale data is read as the polarity instruction flag Pol.
Regardless of this, the operation of converting into an analog signal having a polarity opposite to the polarity written immediately before and writing to the pixel 1400 is executed.

By the way, the display controller 13
When 0 determines that the value of the variable Mod is not “2” in step S206, the value of the variable Mod is
In this embodiment, it is limited to "3". The value of the variable Mod may take "1" (step S220),
In this case, the variable Mod is reset to "2" immediately before the rewriting (W) mode ends (step S2).
24) The variable Mod can take only "0", "2" or "3" at the time of the determination in steps S204 and S206.

The value of the variable Mod at the start of a certain frame process is "3" only when the operation mode in the previous frame process is the exclusive (X) mode.

Therefore, in the frame next to the frame executed in the exclusive (X) mode, the read process in the skip (S) mode shown in FIG. 16 is executed.

First, the display controller 130
Determines whether the value of the register L-p corresponding to the row specified by the variable p matches the polarity instruction flag Pol (step S270).

As described above, when the data signal is actually written in the pixel of a certain i-th row, a value indicating the polarity of the data signal is set in the register L-i corresponding to the i-th row, so that the step S270 is performed. At, it is determined whether or not the write polarity in the previous frame (that is, in the exclusive (X) mode) and the original write polarity in the current frame match each other.

When the determination result is affirmative, in order to avoid reading the same gradation data and writing the same polarity,
The display controller 130 shifts the processing procedure to step S286 described below.

On the other hand, when the result of the determination in step S270 is negative, the display controller 130
Similar to steps S210 and S240, the read scan is executed for the pixel row specified by the variable p (step S).
280). By this scanning, the grayscale data for one row of pixels from p row 1 column to p row n column are sequentially displayed in the display memory 120.
The point of being read out from and supplied to the X driver 160 is also similar to steps S210 and S240.

After this reading and before the output of the latch pulse LP, the display controller 130 sets the signal AK to the polarity instruction flag Pol as in step S211.
It is output at the level of the write polarity instructed by (step S281). When the latch pulse LP is output, the read grayscale data is converted into an analog signal of the original write polarity instructed by the polarity instructing flag Pol and is written in the pixel 1400 in the p row. Become.

Then, in order to record the writing, the display controller 130 rewrites the register Lp to the value of the writing polarity designated by the polarity designating flag Pol (step S282).

Subsequently, the display controller 130
Determines whether or not specific rewriting has occurred in the read scanning in step S280 (step S284).

When the determination result is affirmative, the display controller 130 shifts the processing procedure to the above-described step S220 and sets the rewriting (W) mode.

On the other hand, when this determination result is negative,
The display controller 130 determines whether or not the current variable p is equal to the number m of scanning lines 1410 (step S286).

When the result of this determination is negative, the display controller 130 increments the variable p by "1" in order to set the read scanning target to the next pixel row (step S288), and the processing procedure is performed again. Step S27
Return to 0.

When the determination result of step S286 is affirmative, the display controller 130 sets the variable Mod to "0" so as to return to the normal (N) mode in the next frame processing (step S290). After that, the current frame processing is ended, and the process waits until the start of the next frame (step S22).

Thus, in the skip (S) mode, 1
The gradation data is read by sequentially performing scanning from the row to the m-th row, and the gradation data is read from the polarity instruction flag P.
The operation of converting into an analog signal of the original polarity according to ol and writing the analog signal in the pixel 1400 is executed. However, if the polarities set in the register Lp and the polarities designated by the polarity designating flag Pol are the same, the read scanning / writing operation of the p-th row is skipped. Further, when a specific rewriting occurs in the middle of the read scanning, the mode shifts to the rewrite (W) mode and the read scanning of the next row and thereafter is skipped. Therefore, the display by the pixels 1400 of the skipped row does not change. This is similar to the normal (N) mode.

<Specific Operation> Next, a specific operation in the display method of the second embodiment will be described. FIG. 17
3 is a chart showing, for each frame, how the grayscale data is read from the display memory 120 by the display method.

In this figure, the alphabet indicates the pattern to be displayed, and "+" following this alphabet.
Alternatively, "-" indicates the polarity actually written to the pixel.

The polarity to be originally written in the pixel is indicated by the polarity indicating flag Pol as described above, and in the present embodiment, it is positive in odd frames and negative in even frames. is there.

Therefore, the gradation data of the pattern A read in the frame 1 is converted into a positive polarity analog data signal and written in the pixel, and the subsequent gradation data of the pattern A read in the frame 2 is:
It is converted into a negative polarity data signal and written in the pixel.

In frame 3, the grayscale data relating to the pattern A from the first row to the eighth row is read out, converted into a negative polarity data signal and written in the pixel. Since the specific rewriting as pattern B has occurred in the middle of the scanning (when the value of the variable p is "8", the determination result of step S214 is affirmative), the reading scanning of the ninth and subsequent rows is skipped. (Step S222). Therefore, the pixels in the ninth and subsequent rows maintain the pattern A written in the frame 2 with the positive polarity, so that the tear display is prevented.

Since the specific rewriting has occurred in the frame 3, the frame 4 is in the exclusive (X) mode. For this reason,
The grayscale data relating to the pattern B from the first row to the eighth row read in the frame 4 is not the original write polarity but the negative polarity data that is the opposite polarity to the write polarity in the frame 3. It is converted into a signal and written in the pixel. However, since the frame 4 is an even frame, the original write polarity is also negative. For this reason, frame 4
In the case of 1st row to 8th row, it is not necessary to discuss whether writing is performed according to the original writing polarity.

In frame 3, since the data signal was not written in the pixels in the 9th row and thereafter due to the skip of the read scanning, the value in register L-9 and thereafter indicates the negative polarity writing set in frame 2. It is a value. Therefore, the grayscale data related to the pattern B on and after the ninth row read in the frame 4 is not the original write polarity but a positive polarity data signal having the opposite polarity to the write polarity in the frame 2. It is converted and written in the pixel.

Since frame 4 was in the exclusive (X) mode, frame 5 is in the skip (S) mode. Therefore, the grayscale data related to the pattern B from the first row to the eighth row read in the frame 5 has a positive polarity which is opposite to the writing polarity in the frame 4, that is, the original writing. It is converted into a polarity data signal and written in the pixel.

In frame 4, pattern B on the ninth and subsequent lines
In the frame 5, the value after the register L-9 is a value indicating the positive polarity writing because the grayscale data related to is converted into the positive polarity data signal and written in the pixel.
Therefore, the value after the register L-9 matches the original write polarity in the frame 5 (when the value of the variable p is "9" or more, the determination result of step S270 is affirmative. ), And reading from the 9th row onward is skipped.

Since frame 5 is in the skip (S) mode and no specific rewrite has occurred, frame 6 returns to the normal (N) mode. Therefore, the grayscale data of the pattern B read in the frame 6 is converted into a negative polarity data signal having the original write polarity and written in the pixel.

The frame 5 is an example of a frame in the skip (S) mode in which the specific rewriting does not occur, but naturally there is also a frame in the skip (S) mode in which the specific rewriting occurs. obtain.

Such frames are the frames 12, 17, and 19 in FIG.

Of these, the frame 19 shows the following four states in particular. That is, in the frame 19, when the value of the variable p is from "1" to "6", the determination result of step S270 is negative, and therefore the gradations of the pattern G from the first row to the sixth row. The data has a polarity opposite to the write polarity in the frame 18, that is, the first state in which the data is converted into an original positive polarity data signal and written in the pixel, and the values of the variable p are “7” and “8”. , The determination result of step S270 is affirmative, so the second state in which the reading scans of the seventh and eighth rows are skipped and the value of the variable p is from “9” to “12”. , The grayscale data relating to the pattern G from the 9th row to the 12th row has a positive polarity that is opposite to the writing polarity in the frame 18. Is converted into the data signal of When a third of the state to be written come, the value of the variable p is "12",
Since the determination result of step S284 is affirmative, 1
The read scanning of the third and subsequent rows was skipped (step S2
22) The fourth state is shown.

When the specific rewriting occurs in the skip (S) mode, the rewriting (W) mode is changed,
In the next frame, the exclusive (X) mode is set, and then the skip (S) mode is set. If no specific rewriting occurs in the skip (S) mode, the normal (N) mode is restored again. Become.

As described above, in the second embodiment, similarly to the first embodiment, even if rewriting occurs in the middle of the read scanning, the fracture display does not occur, so that the deterioration of the display quality can be prevented. . Further, according to the second embodiment, even in the pixel corresponding to the address for which the read scanning is skipped, the polarity of the data signal is inverted and written, so that continuous writing with the same polarity is avoided. Therefore, according to the second embodiment, it is possible to prevent the deterioration of the display quality and the deterioration of the liquid crystal characteristics due to the application of the DC component to the liquid crystal element.

In the second embodiment, the original write polarity is simply reversed every frame, and the rows have the same polarity. Not only inversion like this,
As shown in FIG. 18, the write polarity may be inverted every row. In order to invert the write polarity for each such row, the write polarity flag Pol indicates, for example, a positive polarity if it is an odd frame and an odd row and a negative polarity if it is an even row, and vice versa. Internal processing may be performed so as to instruct negative polarity in an even-numbered frame and odd-numbered rows and positive polarity in an even-numbered row. Further, adjacent columns may have opposite polarities.

<Application Example> The present invention is not limited to the above-described first and second embodiments, and various applications and modifications are possible.

In the first and second embodiments described above, it is determined that the specific rewriting has occurred if the grayscale data is simply rewritten in the display memory 120. This is because the rewriting of the gradation data in the display memory 120 occurs when the command WCM is received from the upper control circuit 110. Therefore, the display memory 120 depends on whether or not the command WCM is received.
This is because it is possible to indirectly grasp the rewriting of the gradation data in the above.

However, when the grayscale data in the display memory 120 is rewritten, 100% of the fracture display as described above does not occur. That is, the tear display may not occur depending on the relationship between the read scan range and the rewrite area.

For example, as shown in FIG. 19, in a certain frame, the read address R for the display memory 120 is read.
When the gradation data is rewritten when ad corresponds to the address (a1) where the gradation data of the pixel in the i-th row and the j-th column is stored, it is included in the rewriting range like the range R1. If all of the addresses to be read have already been read and scanned in the frame, the rewriting range is read and scanned in the next frame, so that the tear display does not occur.

In a certain frame, the read address Rad when the gradation data is rewritten is the address (a1).
When it is estimated that the read address when the rewriting is completed will be located at the address (a2) where the grayscale data of the pixel in the (i + 1) th row (j + 4) th column is stored. , If all of the addresses included in the rewriting range precede the estimated address (a2), such as range R2,
Since the rewriting range is read and scanned in the frame, the tear display does not occur.

However, when all the addresses included in the rewriting range have not been read and scanned in a certain frame, as in the range R3, or when all the addresses included in the rewriting range do not precede the estimated addresses. As a result, the rewriting range is divided into addresses that are read-scanned and addresses that are not read-scanned in the frame, and as a result, tearing display occurs.

Therefore, for example, when the display controller 130 receives the command WCM, the display controller 130 obtains the rewriting range from the command WCM, and further predicts the time required for rewriting the data from the number of addresses included in the rewriting range. , Estimate how much the read address when receiving the command WCM advances when the predicted time elapses, and further, based on these read addresses, rewriting range, and estimated address, any of the above applies. When it is determined not to do so, it is desirable to determine for the first time that the specific rewriting that may deteriorate the display quality due to the tear display has occurred.

Further, in the first and second embodiments, it is assumed that all the rows may be rewritten all the time. Therefore, when a specific rewriting occurs in the reading scanning period of a certain row in a certain frame, the frame concerned is rewritten. In, the read scanning for the next and subsequent rows was skipped. Here, depending on the conditions / settings, the gradation data may be rewritten only for a predetermined row.

As described above, when the gradation data is rewritten only in a predetermined row, when the gradation data is rewritten, the read scanning may be skipped only within the range of the predetermined row.

For example, in FIG. 20, when there is a possibility that 4th to 15th rows will be rewritten (during reading scanning), when gradation data is rewritten, the range from 4th to 15th rows This is an example in which the read scanning is skipped only in the above.

In the first and second embodiments, when the read scanning is skipped, the step of the read address with respect to the display memory 120 is stopped, but it may not be stopped. This is because the grayscale data is actually read out unless it is stopped, but the skipped row is not substantially selected by the Y driver 150, and as a result, the writing to the pixel 1400 is invalid.

When skipping the read scanning,
Since the frequency of the clock signal YCK is temporarily increased to shorten the selection period of the row to be skipped (the period in which the scanning signal is at the H level), the skip requires some time.

Here, each transfer circuit 1 of the Y driver 150
If the reset mechanism is provided in 515, the selection period of the row to be skipped becomes zero, which is ideal.

Alternatively, in FIG. 3, in the case where the output of the transfer circuit 1515 is originally at the H level and the scanning line 1410 is to be selected, skipping is performed.
The output of the transfer circuit 1515 may be forcibly set to the L level and the scanning line 1410 may not be selected. As such a configuration, for example, a 2-input AND circuit may be provided between the output of the transfer circuit 1515 and the corresponding scanning line 1410. Specifically, in the two-input AND circuit, the output signal of the transfer circuit 1410 is supplied to one input, the skip control signal is supplied to the other input, and the output signal of the AND circuit is supplied to the scan line 1410. It may be configured to. According to this configuration, even when the transfer circuit 1515 corresponding to the scanning line 1410 of a certain row outputs the H level signal indicating that the row should be selected, the skip control is performed when the row is to be skipped. By setting the signal to the L level, the output of the 2-input AND circuit is forcibly set to the L level, so that the scanning line 1410 in the row is not selected. Therefore, the clock signal YCK
There is no need to increase the frequency.

However, if the reset mechanism and the 2-input logical product circuit are provided, the configuration becomes complicated accordingly. Therefore, in reality, whether the reset mechanism or the 2-input logical product circuit is provided in the configuration of the Y driver. , And if not provided,
The frequency of the clock signal YCK for skipping,
The extent to which the frequency is increased when skipping is a matter to be determined in consideration of various conditions. Further, although the EL device and the liquid crystal device have been described as an example so far, the scope of application of the present invention is not limited to these, and for example, a digital micromirror device (DMD), plasma emission or fluorescence due to electron emission, or the like. It is needless to say that the present invention can be applied to an electro-optical device using various electro-optical elements using the above and an electronic device including the electro-optical device.

[0188]

As described above, according to the present invention, the grayscale data can be written in the display memory regardless of the scanning by the read address, so that the load of the upper control circuit for performing the writing is reduced. In addition, the reading from the address where the specific rewriting that may deteriorate the display quality occurs is skipped, and the pixel corresponding to the address is defined by the grayscale data read previously. Since the gradation is maintained, the broken display screen is prevented and, as a result, the display quality of the moving image is not deteriorated. Therefore, it is possible to prevent the display quality from deteriorating without increasing the load of the upper control circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device to which an image display method according to a first embodiment of the present invention is applied.

FIG. 2 is a circuit diagram showing a configuration of a pixel of the display device.

FIG. 3 is a block diagram showing a configuration of a Y driver of the display device.

4A and 4B are timing charts for explaining the operation of the Y driver.

FIG. 5 is a block diagram showing a configuration of an X driver of the display device.

FIG. 6 is a timing chart for explaining the operation of the X driver.

FIG. 7 is a flowchart for explaining a main operation of a display controller in the display device.

FIG. 8 is a flowchart for explaining frame processing in the same main operation.

FIG. 9A is a diagram for explaining a specific operation of image display in the related art, and FIG. 9B is a diagram for explaining a specific operation of image display in the same embodiment.

FIG. 10A is a diagram for explaining a conventional display method, and FIG. 10B is a diagram for explaining a display method in the same embodiment.

FIG. 11 is a circuit diagram showing a pixel configuration of a display device to which an image display method according to a second embodiment of the present invention is applied.

FIG. 12 is a block diagram showing a configuration of an X driver of the display device.

FIG. 13 is a flowchart for explaining a main operation of a display controller in the display device.

FIG. 14 is a flowchart for explaining frame processing in the same main operation.

FIG. 15 is a flowchart for explaining frame processing in the same main operation.

FIG. 16 is a flowchart for explaining frame processing in the same main operation.

FIG. 17 is a chart for explaining a specific operation of image display in the display device.

FIG. 18 is a chart for explaining a specific operation of image display in an application example of the display device.

FIG. 19 is a diagram for explaining another example of determination of specific rewriting in the first or second embodiment.

FIG. 20 is a chart for explaining an application example of the image display method according to the first or second embodiment.

[Explanation of symbols]

100 ... Display device 110 ... Upper control circuit 120 ... Display memory 130 ... Display controller 140 ... Display panel 150 ... Y driver 160 ... X driver

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 631 G09G 3/20 631B 631R 641 641C H04N 5/66 H04N 5/66 B 102 102B 5/70 5/70 AF terms (reference) 2H093 NA15 NA16 NA33 NA51 NC15 NC29 NC34 NC50 NC71 ND39 ND60 NE10 5C006 AA01 AA16 AC28 AF02 AF03 AF04 AF44 AF45 AF51 AF53 AF61 AF71 AF83 BB16 BC03 BC12 BC16 BF02 BF03 BF04 BF04 FA21 BF0 FA14 BF0 FA14 AA12 BA35 BB13 5C080 AA05 AA06 AA10 BB05 DD03 DD22 EE29 GG12 JJ01 JJ02 JJ07

Claims (11)

[Claims] 1. A vertical scanning and horizontal scanning of the display panel with respect to a display memory having an address corresponding to each pixel in the display panel and storing gradation data defining a gradation of the pixel at each address. An image display method, wherein a read address is designated in an order synchronized with scanning, gradation data is sequentially read from the read address, and a pixel of the display panel has a gradation defined by the gradation data. A first step of determining whether or not a specific rewriting that may deteriorate the display quality has occurred in the display memory over the read scanning period for designating the read address, and it is determined by the first step that the specific rewriting has occurred. In this case, in the read scan in which the specific rewriting has occurred, at least the reading of the grayscale data from the address in which the specific rewriting has occurred is skipped, and the skipped address is skipped. Corresponding pixels, an image display method characterized in that it comprises a second step of holding the gradation defined by the tone data read out before the read scanning. 2. In the first step, when the gradation data is rewritten during the reading scanning period, it is determined that the specific rewriting has occurred regardless of the read address at the time when the rewriting occurs. The image display method according to claim 1, wherein: 3. In the first step, when rewriting of gradation data occurs during a read scanning period, all of the addresses where the rewriting has occurred have already been designated as read addresses in the read scanning where the rewriting occurred. Whether it is included in the area, and the read address at the time of completion of the rewriting is predicted, and whether all the addresses where the rewriting has occurred are included in the area after the predicted read address are determined. The image display method according to claim 1, wherein when the determination results of both are negative, it is determined that the specific rewriting has occurred. 4. In the second step, when it is determined that the specific rewriting has occurred in the first step, the reading of the line after the line including the read address at the time of the determination is skipped and the skip is performed. The image display method according to claim 1, wherein pixels located after a pixel row corresponding to the row address are held. 5. The specific rewriting is generated by the first step when the write polarity for the same pixel is inverted every one or more vertical scanning periods according to a polarity instruction flag which indicates the write polarity. When it is determined that the read scan subsequent to the read scan in which the specific rewriting has occurred is performed after the second step,
The third step of writing the pixel corresponding to the skipped address in the polarity opposite to the polarity in the read scan in which the specific rewriting has occurred, regardless of the polarity instruction flag, and the writing of the third step occurs. When the opposite polarity written in the pixel corresponding to the skipped address is the same as the write polarity instructed by the write instruction in the read scan next to the read scan performed, the read from the address corresponding to the pixel is performed. The image display method according to claim 4, further comprising: a fourth step of skipping the reading and holding the pixel corresponding to the skipped address at the gradation written with the opposite polarity. 6. A display memory, which has an address corresponding to each pixel in the display panel, and stores gradation data defining a gradation of the pixel at each address; and the display panel with respect to the display memory. Of the display panel, and a reading means for sequentially reading the gradation data from the reading address, and a reading means for sequentially reading the gradation data from the reading address. An image display device using gradation, which determines whether or not specific rewriting that may degrade display quality has occurred in a display memory during a read scanning period for designating the read address; When it is determined by the means that the specific rewriting has occurred, in the reading scan in which the specific rewriting has occurred, at least the reading of the gradation data from the address where the specific rewriting has occurred is skipped. And a first holding unit for holding the pixel corresponding to the skipped address at the gradation defined by the gradation data read before the reading scan. Display device. 7. When the gradation data is rewritten during the reading scanning period, the judging means judges that the specific rewriting has occurred regardless of the read address at the time when the rewriting occurred. The image display device according to claim 6. 8. When the gradation data is rewritten in the read scanning period, all the addresses in which the rewriting has occurred are already designated as the read addresses in the read scanning in which the rewriting has occurred. Whether it is included in the area, and the read address at the time of completion of the rewriting is predicted, and whether all the addresses where the rewriting has occurred are included in the area after the predicted read address are determined. The image display device according to claim 6, wherein when the determination results of both are negative, it is determined that the specific rewriting has occurred. 9. The first holding means, when the discrimination means discriminates that the specific rewriting has occurred, skips the reading from the row following the row including the read address at the time of the discrimination. The image display device according to claim 6, wherein the pixel located after the pixel row corresponding to the skipped row address is held. 10. The specific rewriting is generated by the discriminating means when the write polarity for the same pixel is inverted every one or more vertical scanning periods according to a polarity instruction flag for instructing the write polarity. When it is determined that the pixel corresponding to the skipped address is read in the read scan next to the read scan in which the specific rewriting has occurred, regardless of the polarity indication flag, A writing unit that writes in a polarity opposite to the polarity in the reading scan in which the specific rewriting has occurred, and a pixel corresponding to the skipped address in the reading scan next to the reading scan in which the writing by the writing unit has occurred. When the opposite polarity written in is the same as the writing polarity instructed by the writing instruction, reading from the address corresponding to the pixel is skipped and Pixels corresponding to Tsu address obtained by flop, the image display apparatus according to claim 9, characterized in that it comprises a second holding means for holding the gradation burned with opposite polarities. 11. An electronic apparatus comprising the image display device according to claim 6.