JP2003297749A - Semiconductor device and its forming method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for reducing an optical leakage current in order to perform superior display. <P>SOLUTION: Microcrystals of polysilicon or the like containing a large number of carrier traps are distributed in a silicon film 102 which can obtain high- field effect mobility such as a continuous grain boundary crystal. Discontinuous crystal grain boundaries and in-grain defects of the microcrystal are made to function as trap sites for optical pumping charges, thereby providing a technique for obtaining a TFT in which high carrier mobility and a low optical leakage current are made compatible with each other. Since the TFT itself can reduce optical sensitivity (optical leakage current), a simpler light-shielding structure can be adopted, and manufacturing cost reduction is also enabled. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a technique for forming a crystalline silicon film. Further, the present invention relates to a semiconductor device including a crystalline silicon film obtained by applying the present invention and a manufacturing technique thereof.

[0002]

2. Description of the Related Art Transistors, especially field-effect transistors, typically M, are used as semiconductor elements utilizing semiconductor characteristics.
Examples thereof include an OS (Metal Oxide Semiconductor) transistor and a thin film transistor (TFT). Among them, a thin film transistor (Thin) using a crystalline silicon film for a semiconductor layer (including at least a channel formation region, a source region and a drain region) is particularly preferable. Fil
(m Transistor: TFT), or an active matrix type display device in which a circuit is formed by combining TFTs and is built in and used as a drive circuit has been widely used.

The crystalline silicon film is a field effect mobility (0.5 to 1) of a TFT using an amorphous silicon film up to that point.
Higher field effect mobility (high-speed movement of carriers) than that of cm ² / Vs) can be obtained. As a result, TFTs using crystalline silicon films have high current drive capability, and are therefore considered suitable not only for display devices that require ever higher resolution, but also for drive circuit integration. The technological development for obtaining a silicon film with better crystallinity is under way.

For example, Japanese Unexamined Patent Publication No. 10-223533 describes the following crystallization method in which a metal element is added to an amorphous silicon film and heat treatment is performed.

An amorphous silicon film is formed on a substrate. After performing hydrofluoric acid treatment to remove impurities adhering to the surface and a natural oxide film formed on the surface, the surface of the amorphous silicon film is irradiated with ultraviolet light for 5 minutes in an oxygen atmosphere.
An oxide film having a thickness of 5 nm is formed, Ni acetate solution having a Ni concentration of 100 ppm is dropped, and spin drying is performed to apply Ni element. Heat treatment is performed at 600 ° C. for 4 hours in a nitrogen atmosphere to form a crystalline silicon film. The crystalline silicon film is irradiated with laser light (eg, pulse oscillation type KrF laser). After removing the silicon oxide film on the surface by hydrofluoric acid treatment, a 100 nm-thick silicon oxide film is deposited on the silicon film by a plasma CVD method. The silicon oxide film is etched to form an opening and a mask is formed. Using this mask, phosphorus is selectively implanted into the crystalline silicon film. The dose amount is, for example, 5 × 10 ¹⁴ atoms / cm
^Set to ² . Heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere.
By this step, the Ni element below the mask irreversibly moves (getters) to the region where phosphorus is implanted. Next, the region where the Ni element has moved (gettering region) is patterned and removed.

In the silicon film obtained by the crystallization method described in the above publication, a large number of columnar crystal aggregates are formed, and all the crystals in one crystal aggregate have the same orientation. When this film is observed with a high-resolution transmission electron microscope, no lattice mismatch is observed at the crystal grain boundaries, and the grains are continuous (linear) continuous grain boundary crystals. This indicates that there are no (less) dangling bonds at the grain boundaries, and high mobility can be secured without trapping carriers, that is, it was produced using the crystalline silicon film obtained by this crystallization method. This is the reason why it is said that the TFT has the same electrical characteristics as when the TFT is manufactured using a single crystal silicon film.

When a TFT is formed using a crystalline silicon film obtained by applying the crystallization method disclosed in the above publication, a high field effect mobility of 200 to 300 cm ² / Vs can be actually obtained. .

The present applicants obtained by adding a catalytic element to a crystalline silicon film (hereinafter simply referred to as polysilicon) obtained by performing a heat treatment without using a catalytic element and then performing a heat treatment. The crystalline silicon film is distinguished as a crystalline silicon film having continuous grain boundaries (referred to as a continuous grain boundary crystal or a continuous grain boundary silicon film). The nuclei generated by adding the catalytic element and heat treatment are called continuous grain boundary crystal nuclei for convenience. Further, in this specification, since polysilicon has smaller crystal grains than a crystalline silicon film having continuous grain boundaries, it is also referred to as a microcrystalline grain, and a polysilicon generation nucleus is also referred to as a microcrystalline grain nucleus. I will.

[0009]

A display device including a TFT manufactured by using the crystalline silicon film obtained by the above method is applied to a liquid crystal projector as shown in FIG. 14, for example.

The light source used in the liquid crystal projector is
In order to perform bright display, intense light such as xenon arc lamp is generated, and the light from the light source is TF.
Although it is designed so that it does not enter T, stray light due to reflection / diffraction inside the device enters the semiconductor layer of the TFT, and this light induces carriers in the silicon, causing leakage due to light. There was a problem that an electric current was generated.

Particularly in a crystalline silicon film having continuous grain boundaries, the lattice matching of the grain boundaries is good, so that the energy barrier of the grain boundaries is small, and the crystal defects in the crystal grains are few, so that the carrier lifetime is long. . As a result, TF using a crystalline silicon film grown from continuous grain boundary crystal nuclei
T has good characteristics. However, on the other hand, since the lifetime of the electron / hole pair (carrier) excited by light is long in the environment under the light irradiation, the TFT by the photoexcited carrier is used.
The leakage current will also increase. Since the leak current of the TFT is also a cause of deterioration of display quality, it is an important issue to reduce the light leak current.

On the other hand, in the case of a general polysilicon film (a crystalline silicon film obtained only by heat treatment of an amorphous silicon film), the energy barrier at the crystal grain boundary is large, and Since the defect density is also high, the lifetime of the electron / hole pair excited by light is short and is lost by the recombination of the electron / hole pair, and as a result, the light leak current can be reduced. However, low electric field effect mobility of carriers (about 100 cm ² / Vs) is due to “large energy barrier” and “high defect density in crystal grains” which are the reasons for obtaining the effect of reducing light leakage current.
As a result, the on-characteristics of the TFT itself are low, the circuit performance is not improved, and the conventional TFT characteristics cannot be obtained.

In view of the above problems, it is an object of the present invention to provide a technique for realizing a semiconductor device capable of excellent display while maintaining high TFT performance (carrier mobility) and reducing light leak current.

[0014]

In order to solve the above-mentioned problems, the present inventors have made a polysilicon film containing a large amount of carrier traps in a silicon film capable of obtaining a high field effect mobility like a continuous grain boundary crystal. We provide a technology that can realize a TFT that has both high carrier mobility and low photoleakage current by distributing microcrystals such as and functioning discontinuous crystal grain boundaries and intragranular defects of microcrystals as trap sites for photoexcited charges. To do.

A crystalline semiconductor film made of continuous grain boundary crystals has a semiconductor layer containing fine crystal grains surrounded by grain boundaries discontinuous with the continuous grain boundary crystals.

Further, it is characterized in that a crystalline semiconductor film made of continuous grain boundary crystals has a semiconductor layer containing fine crystal grains.

In the above invention, the average grain size of the fine crystal grains is 0.01 to 1 μm.

Further, a step of forming an amorphous silicon film on the insulator, a step of adding a metal element to the amorphous silicon film, a step of performing heat treatment to form a crystalline silicon film, It is characterized by including.

Further, 5 × 10 ^{6 to} 5 × 10 ¹¹ are formed on the insulator.
A step of forming an amorphous silicon film having crystal nuclei at a density of pcs / cm ² , a step of adding a metal element to the amorphous silicon film, and a heat treatment to form a crystalline silicon film It is characterized by including and.

Further, a step of forming an amorphous silicon film on the insulator, a step of forming a mask insulating film on the amorphous silicon film, and an opening of the mask insulating film of the amorphous silicon film. The method is characterized by including a step of adding a metal element to a selected region exposed from the portion and a step of performing heat treatment to form a crystalline silicon film.

In addition, the step of forming an amorphous silicon film on the insulator and the first heat treatment are performed, and the amorphous silicon film is formed at a density of 5 × 10 ^{6 to} 5 × 10 ¹¹ pieces / cm ² . The method includes: a step of generating crystal nuclei; a step of adding a metal element to the amorphous silicon film having the crystal nuclei; and a step of performing a second heat treatment to form a crystalline silicon film. I am trying.

Further, a step of forming an amorphous silicon film on the insulator, a step of adding a metal element to the amorphous silicon film, and a first heat treatment are performed to form a crystalline silicon film. And a barrier layer on the crystalline silicon film,
A step of forming a semiconductor film containing a rare gas element on the barrier layer, and a step of performing a second heat treatment to move the metal element added to the crystalline silicon film to the semiconductor film. Is characterized by.

Further, a step of forming an amorphous silicon film on the insulator, a step of forming a mask insulating film on the amorphous silicon film, and the amorphous film exposed from the opening of the mask insulating film. Of a metal element to a selected region of the crystalline silicon film, a step of performing a first heat treatment to form a crystalline silicon film, and the crystalline silicon film exposed from the opening of the mask insulating film. A step of adding an element having a gettering effect to the selected region, and a step of performing a second heat treatment to move the metal element to the region to which the element having a gettering effect is added. It is characterized by that.

In the above invention, the metal element is Ni, Fe, Co, Sn, Pb, Ru, Rh, P.
It is characterized in that it is any one kind or plural kinds of elements of d, Os, Ir, Pt, Cu, and Au.

Further, in the above invention, the average grain size and density of the fine crystal grains are TF without impairing the characteristics of the continuous grain boundary crystals.
The range in which the light leakage of T can be effectively suppressed is given.
Except when the size of the fine crystal grains is significantly smaller than the channel width of the TFT to be manufactured, the characteristics of the fine crystal grains having low characteristics become the controlling factor of the TFT performance and deteriorate the TFT performance. The same is true when the density of fine crystal grains is excessively high. On the other hand, when the density of fine crystal grains is excessively low, the trap sites themselves of photoexcited carriers are reduced, and as a result, the effect of reducing photoleakage current is diminished. . Therefore, as in the present invention, it is possible to suppress the light leakage of the TFT while maintaining the TFT performance by setting the appropriate size and density of the fine crystal grains.

As described above, a catalyst metal is added to amorphous silicon containing fine crystals (polysilicon) in advance, and continuous grain boundary silicon crystals are grown while suppressing the generation of more polysilicon due to the catalytic effect. It is possible to obtain a thin film in which fine crystal grains are uniformly distributed in the continuous grain boundary crystal thin film. Although the TFT made of this crystalline thin film has high carrier mobility, when the TFT is turned off, photoexcited carriers are lost by trapping / recombination due to discontinuous grain boundaries around fine grains (polysilicon) or defects in crystal grains. Therefore, it is possible to have the characteristic that the light leakage current is small.

[0027]

Embodiment Mode 1 A method for forming a crystalline silicon film using the present invention will be described with reference to FIGS.

A base insulating film 101 is formed on the substrate 100. As the base insulating film 101, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like can be used. When quartz is used as the substrate, the base insulating film 1
The step of forming 01 can be omitted.

Then, a silicon film 102 is formed as a semiconductor film on the base insulating film 101. In this embodiment, the silicon film is formed by the low pressure CVD method. As raw material gas,
A silicon film having a thickness of 20 to 150 nm is formed at 450 to 600 ° C. using silane or disilane. In this embodiment, 465 ° C., 0.5 torr, Si ₂ H ₄ / He
A silicon film having a film thickness of 50 nm is formed under the condition that the gas flow rate ratio is 250/300 sccm. The silicon film formed here contains 5 × 10 5 minute crystal grains (polysilicon).
It is an amorphous silicon film containing ^{6 to} 5 × 10 ¹¹ pieces / cm ² .

Subsequently, impurities and natural oxide film adhering to the surface of the obtained amorphous silicon film are removed by hydrofluoric acid for cleaning, and the surface is further treated with ozone water to obtain an extremely thin film (1-5 nm). After forming the oxide film, a catalytic element-containing layer 103 is formed by coating the silicon film with a catalytic metal element, such as nickel acetate solution containing nickel at a concentration of 5 ppm. As a metal element (also referred to as a catalyst element) serving as a catalyst, in addition to nickel (Ni), Fe, Co, Sn, P
b, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au
It is possible to apply any one kind or plural kinds of elements.

As a method of adding the catalyst element, a method of adding the catalyst element by using a sputtering method or a vapor deposition method may be used instead of applying the solution containing the catalyst element by spin coating as shown in the present embodiment. .

Next, before the crystallization step,
It is desirable that heat treatment be performed at 500 ° C. for about 1 hour so that hydrogen in the silicon film is released. After that, heat treatment is performed at 550 ° C. to 700 ° C. in a nitrogen atmosphere. In this embodiment, the crystalline silicon film 104 is formed by performing heat treatment at 570 ° C. for 12 hours. During this heat treatment, the growth of continuous grain boundary crystals due to the catalytic metal preferentially progresses due to the catalytic effect, and new generation of fine crystals (polysilicon) does not occur.

The crystallinity can be further improved by irradiating the crystalline silicon film thus obtained with laser light. As laser light,
A second harmonic wave, a third harmonic wave, or the like of an excimer laser or a YAG laser with a wavelength of 400 nm or less may be used. ~ 400m
The crystalline silicon film may be irradiated with light having a J / cm ² concentration and an overlap ratio of 90 to 95%.

By the crystallization method as described above, a crystalline silicon thin film in which fine crystal grains (polysilicon) are uniformly distributed in continuous grain boundary crystals can be obtained.

(Embodiment 2) An example of a method of manufacturing a crystalline silicon film different from that of Embodiment 1 will be described with reference to FIG.

A base insulating film 201 is formed on the substrate 200. The base insulating film is a silicon nitride film, a silicon oxide film,
Any of the silicon oxynitride films may be applied, and those films may be stacked and used. Note that when quartz is used for the substrate, the step of forming the base insulating film 301 can be omitted.

A silicon film 202 is formed on the base insulating film 201 by a low pressure CVD method (FIG. 2A). 450 to 600 ° C. using silane or disilane as a source gas
A silicon film having a film thickness of 20 to 150 nm is formed by. In this embodiment, 465 ° C., 0.5 torr, Si ₂ H ₄ /
A silicon film having a film thickness of 50 nm is formed under the film forming condition that the He gas flow rate ratio is 250/300 sccm. The silicon film formed here is composed of microcrystals (polysilicon).
It is an amorphous silicon film containing x10 ^{6 to} 5x10 ¹¹ pieces / cm ² .

Next, the surface of the amorphous silicon film 202 is treated with hydrofluoric acid to be cleaned, and then CVD is performed on the silicon film 202.
Method is used to form silicon oxide, and an opening is formed by etching to form a mask insulating film 203 (FIG. 2).
(B)).

Impurities and natural oxide films adhering to the surface of the silicon film exposed from the openings of the mask insulating film 203 are removed with hydrofluoric acid or the like, and then treated with ozone water to have a film thickness of about 1 to 5 nm on the silicon film surface. Forming an oxide film. Then, a Ni acetate solution containing Ni at a concentration of 100 ppm is applied and a catalytic element is added to the silicon film to form a catalytic element containing layer 2
To form 04. As a metal element (also referred to as a catalyst element) serving as a catalyst, in addition to nickel, Fe, Co, Sn, P
b, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au
It is possible to apply any one kind or plural kinds of elements.

As a method of adding the catalytic element, a method of adding the catalytic element by using a sputtering method or a vapor deposition method may be used in addition to applying the solution containing the catalytic element by spin coating as shown in the present embodiment. .

Next, before the crystallization step,
It is desirable that heat treatment be performed at 500 ° C. for about 1 hour so that hydrogen in the silicon film is released. Then, in a nitrogen atmosphere, heat treatment is performed at 550 to 600 ° C., and in this embodiment at 570 ° C. for 12 hours, whereby continuous grain boundary crystal nuclei are generated in the region to which the catalyst element is added, and FIG.
Crystal growth is performed as shown by an arrow in FIG. 2C to form a crystalline silicon film 205 (FIG. 2C). During this heat treatment, the growth of continuous grain boundary crystals due to the catalytic metal preferentially progresses due to the catalytic effect, and new generation of fine crystals (polysilicon) does not occur.

The crystallinity can be further improved by irradiating the crystalline silicon film 205 thus obtained with laser light. As the laser light, an excimer laser having a wavelength of 400 nm or less or a second harmonic or a third harmonic of a YAG laser may be used. In any case, a pulsed laser having a repetition frequency of about 10 to 1000 Hz is used to generate the laser light. 100 ~ 4 with optical system
The crystalline silicon film may be irradiated with light having a concentration of 00 mJ / cm ² and an overlap rate of 90 to 95%.

By the crystallization method as described above, a crystalline silicon thin film in which fine crystal grains of polysilicon are uniformly distributed in continuous grain boundary crystals can be obtained.

(Embodiment 3) An example of a method of manufacturing a crystalline silicon film different from those of Embodiments 1 and 2 will be described with reference to FIGS.

The base insulating film 30 is formed on the substrates 300 and 400.
1, 401 are formed. The base insulating film is a silicon nitride film,
It may be formed using a silicon oxide film or a silicon oxynitride film. Subsequently, first amorphous silicon films 302 and 402 having a film thickness of 20 to 100 nm are formed. Note that the base insulating films 301 and 401 may have a stacked structure. When quartz is used for the substrate, the base insulating film 301,
The step of forming 401 can be omitted (FIG. 3).
(A), FIG. 4 (A)).

After forming the first amorphous silicon film, 55
A heat treatment is performed at 0 to 700 ° C., 650 ° C. in the present embodiment for 1 hour to generate fine crystal (polysilicon) nuclei in the amorphous silicon film, and second fine grains having uniform fine crystal (polysilicon) nuclei are formed. Amorphous silicon films 303 and 403 are formed (FIGS. 3B and 4B).

Subsequently, a catalyst element is added uniformly to the second amorphous silicon films 303 and 403 containing fine crystal nuclei (polysilicon) to form catalyst element containing layers 304 and 405. As a method of adding the catalytic element, the method of forming the catalytic element-containing layer 304 on the entire surface as in the first embodiment or the mask insulating film 404 described in the second embodiment is formed and exposed through the opening of the mask insulating film 404. Any of the methods for forming the catalyst element containing layer 405 in the selected region of the formed silicon film may be used (FIGS. 3C and 4C).

After adding the catalytic element, heat treatment is performed to form a crystalline silicon film. In this embodiment, the amorphous silicon film is subjected to heat treatment to generate fine crystal nuclei (polysilicon), and then a second heat treatment is performed by further adding a catalytic element to the continuous grain boundary crystal nuclei. Is being generated. By performing the treatment as described above, during the second heat treatment, the growth of the continuous grain boundary crystals due to the catalytic metal preferentially progresses due to the catalytic effect, and the generation and growth of new fine crystal nuclei (polysilicon) is prevented. Without being performed, crystalline silicon films 305 and 406 in which fine crystal grains (polysilicon) are distributed in the continuous grain boundary crystal thin film can be obtained (FIG. 3).
(D), FIG. 4 (D). At this time, the grain boundaries between the continuous grain boundary crystals and the polysilicon fine crystal grains are discontinuous grain boundaries.

(Embodiment 4) A crystalline silicon film produced by using the crystallization method of Embodiments 1 to 3 contains a catalytic element in a concentration of 1 × 10 ¹⁹ / cm ^{3 in} the film. If a semiconductor element typified by a TFT is formed while containing an element, a problem such as a sudden increase in off-current will occur. Therefore, it is desirable to reduce the concentration of the catalytic element contained in the silicon film. Therefore, an example of a method for reducing the concentration of the catalytic element will be described with reference to FIG.

A mask insulating film 1001 having an opening is formed on the crystalline silicon film manufactured by any of the methods of the first to third embodiments.

Next, an element having a gettering action on the crystalline silicon film exposed from the opening (an element belonging to Group 15 of the periodic table, typically phosphorus or an element belonging to Group 18 of the periodic table, typically Argon) is added to form a gettering region (region where the catalytic element moves) 1002.

For example, using a furnace at 450 to 800 ° C.,
By performing the heat treatment for 4 to 24 hours, the catalytic element moves by the gettering action of the element added to the gettering region and is captured in the gettering region. As a result, the concentration of the catalytic element contained in a region which will be a device region (a channel formation region or a junction region between the channel formation region and the source region or the drain region) later can be reduced. By this gettering step, a good quality crystalline silicon film can be obtained.

This embodiment can be applied in combination with any of the crystallization methods of Embodiments 1 to 3.

(Embodiment 5) An example of a method for reducing the concentration of a catalyst element different from that of Embodiment 4 will be described with reference to FIG.

A barrier layer 1101 is formed on the crystalline silicon film manufactured by any of the methods of the first to third embodiments. This barrier layer protects the crystalline silicon film from the etchant (not etched) in the step of removing the gettering region after the gettering step.
Since the layer is provided as described above, it is referred to as such.

The barrier layer 1101 has a thickness of about 1 to 10 nm, and a chemical oxide formed by simply treating with ozone water may be used as the barrier layer. Also,
The chemical oxide can be similarly formed by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid and the like are mixed with hydrogen peroxide. As another method, plasma treatment may be performed in an oxidizing atmosphere, or ozone may be generated by ultraviolet irradiation in an oxygen-containing atmosphere to perform the oxidizing treatment. Further, it may be used as a barrier layer by forming a thin oxide film by heating to about 200 to 350 ° C. using a clean oven. Alternatively, plasma CVD method, sputtering method, vapor deposition method, etc., 1 to 5 nm
A barrier layer may be formed by depositing an oxide film of a certain degree. In any case, during the gettering step, the catalytic element can move to the gettering site side, and during the gettering site removing step, the etching solution does not soak (protects the crystalline silicon film from the etching solution) film, for example, A chemical oxide film, a silicon oxide film (SiOx), or a porous film formed by treating with ozone water may be used.

Next, a rare gas element is added to the barrier layer 1101 as a gettering site by sputtering in an amount of 1 ×.
A second semiconductor film (typically, an amorphous silicon film) 1102 containing a concentration of 10 ²⁰ / cm ³ or more is formed to a thickness of 25 to 250 nm. Gettering site 11 to be removed later
In order to increase the selection ratio of 02 to the crystalline silicon film, it is preferable to form a low density film.

The gettering site 1102 has a gas (Ar) flow rate of 50 (sccm) and a film forming power of 3 kW.
When a film is formed at a substrate temperature of 150 ° C. and a film forming pressure of 0.2 to 1.0 Pa, the rare gas element is added at 1 × 10 ¹⁹ / cm ³ to 1 × 1.
0 ²² / cm ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / c
A semiconductor film containing m ³ and more preferably 5 × 10 ²⁰ / cm ³ and having a gettering effect can be formed by a sputtering method.

Since the rare gas element itself is inactive in the semiconductor film, it does not adversely affect the crystalline semiconductor film 105. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. The present invention uses these rare gas elements as an ion source to form gettering sites, and forms a semiconductor film containing these elements,
The feature is that this film is used as a gettering site.

In order to surely achieve gettering, it is necessary to perform heat treatment thereafter. The heat treatment is performed by a furnace annealing method or an RTA method. When performing by the furnace annealing method, 450 to 600 ° C. in a nitrogen atmosphere
The heat treatment is performed for 0.5 to 12 hours. When the RTA method is used, a lamp light source for heating is used for 1 to 60 seconds,
It is preferably turned on for 30 to 60 seconds, and it is turned on 1 to 10 times,
It is preferably repeated 2 to 6 times. The light emission intensity of the lamp light source is arbitrary, but the semiconductor film is momentarily 600 to 1
The heating is performed up to 000 ° C., preferably 700 to 750 ° C.

In gettering, the catalytic element in the gettered region (capture site) is released by thermal energy and moves to the gettering site by diffusion. Therefore, the gettering depends on the processing temperature, and the higher the temperature is, the shorter the gettering progresses. In the present invention, the distance that the catalytic element moves during gettering is about the thickness of the semiconductor film, as indicated by the arrow in FIG. 9D, and the gettering should be completed in a relatively short time. You can

After the gettering process is completed, the gettering region 1102 is selectively etched and removed. Examples of the etching method include dry etching without plasma using ClF ₃ , hydrazine, and tetraethylammonium hydroxide (chemical formula (CH ₃ )
It can be performed by wet etching using an alkaline solution such as an aqueous solution containing ₄ NOH). At this time, the barrier layer 11
01 functions as an etching stopper. Further, the barrier layer 1101 may be removed thereafter with hydrofluoric acid.

Thus, the concentration of the catalytic element is 1 × 10 ¹⁷ / cm ³
A crystalline silicon film reduced to the following can be obtained. This embodiment can be used in combination with any of the crystallization methods described in Embodiments 1 to 3.

(Embodiment 6) In this embodiment, a step of forming an active matrix substrate by using the crystallization method shown in Embodiments 1 to 4 will be described with reference to FIGS. In this specification, an active matrix substrate means an n-channel type TFT and a p-channel type T
A substrate in which a driver circuit having an FT and a pixel portion having a pixel TFT and a storage capacitor are provided over the same substrate.

As the substrate 500, a quartz substrate, a glass substrate, a ceramic substrate or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. When a glass substrate is used, it may be preheated at a temperature 10 to 20 ° C. lower than the glass strain point.

A polysilicon film and a WSi film are formed on the substrate 500, and these films are patterned to form a lower light-shielding film 501. As the lower light-shielding film 501, a polysilicon film or WSi _x (X = 2.0 to 2.8) is used.
A film, a film made of a conductive material such as Al, Ta, W, Cr, and Mo, and a laminated structure thereof can be used. In this embodiment, the lower light-shielding film 501 is formed at a predetermined interval by using a conductive material having a high light-shielding property of a laminated structure of a WSi _x (film thickness: 100 nm) film 501b and a polysilicon film (film thickness: 50 nm) 501a. . Since the lower light-shielding film 501 has a function as a gate line, the portion corresponding to the lower light-shielding film is hereinafter referred to as a gate line.

A first insulating film 502 is formed so as to cover the gate line 501. The first insulating film 502 has a film thickness of about 100 nm. As the first insulating film 502, an insulating film containing silicon formed by a plasma CVD method, a sputtering method, or the like is used. In addition, the first insulating film 502 is
It may be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film in which these are combined.

Next, a reduced pressure C is formed on the first insulating film 502.
An amorphous semiconductor film is formed by the VD method. The material of the amorphous semiconductor film is not particularly limited, and a silicon film is used in this embodiment. 20-150 nm (preferably 30-80 n
A semiconductor film (amorphous semiconductor film, typically an amorphous silicon film) 502 having a thickness of m) and containing microcrystalline (polysilicon) nuclei is formed by a low pressure CVD method or a plasma CVD method. In this embodiment, a plasma CVD method is used,
The film formation temperature is 250 to 350 ° C., and in this embodiment, it is 320 ° C. and monosilane (SiH ₄ ) is used. Not limited to monosilane, disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. P these
Introduced into the CVD equipment at a pressure of 3 Pa, 13.56 MH
A high frequency power of z was applied to form a film. At this time, the high frequency power is suitably 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane is 20 sccm. As described above, the amorphous silicon film 502 was formed to have a thickness of 65 nm.

Since the base insulating film 501 and the amorphous silicon film 502 can be formed by the same film forming method, they may be continuously formed. After forming the base insulating film 501, it is possible to prevent the surface from being contaminated by not exposing it to the air atmosphere once, and it is possible to reduce the characteristic variations of the TFT to be manufactured and the variation of the threshold voltage (FIG. 7). (A)).

Next, the amorphous silicon film 503 is crystallized to form a crystalline silicon film 504. First, impurities and natural oxide film adhering to the surface of the amorphous silicon film 503 having uniform fine crystal (polysilicon) nuclei are removed and cleaned with hydrofluoric acid, and then the surface is further treated with ozone water. After forming a thin (1 to 5 nm) oxide film, a metal element serving as a catalyst, for example, nickel (5 p) is formed on the silicon film.
Apply Ni acetate solution containing pm concentration. In addition to the spin coating method described above, the catalyst element can be added by a sputtering method, an evaporation method, or the like (FIG. 7B).

Next, prior to the crystallization step, 400-
It is desirable that heat treatment be performed at 500 ° C. for about 1 hour so that hydrogen in the silicon film is released. Then, in a nitrogen atmosphere, by performing heat treatment at 550 to 600 ° C., 570 ° C. for 12 hours in the present embodiment, continuous grain boundary crystal nuclei are generated and grown in the region to which the catalytic element is added, and the crystallinity increases. A silicon film is formed. Note that after the crystallization step, the crystalline silicon film may be irradiated with laser to improve the crystallinity of the crystalline silicon film.

Next, a barrier layer 506 is formed on the crystalline silicon film 505. In this embodiment, the film forming temperature is 40
0 ° C., gas flow SiH ₄ : N ₂ O 4/800 sccm,
Pressure 0.399 × 10 ² Pa, RF power density 10/6
A silicon oxide film was formed at 00 W / cm ² .

Then, a second semiconductor film 507 to be a gettering region is formed on the barrier layer 506. A silicon film may be used for the second semiconductor film 507. Also,
The second semiconductor film 507 contains 1 × 10 ¹⁹ to 2 × 1 of a rare gas element or carbon so that the gettering is sufficiently performed.
It is added at a concentration of 0 ²² / cm ³ . As an example of a method for forming a semiconductor film containing a rare gas element, a target made of silicon is used in an atmosphere containing a rare gas element,
The gettering region 507 made of an amorphous silicon film may be formed. Further, as a rare gas element, helium (H
e), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used, and one or more kinds thereof are used. Among them, argon (Ar), which is a cheap gas, is used.
Is preferred.

When the gettering region is formed using a target containing phosphorus, which is an impurity element of one conductivity type, in addition to gettering by a rare gas element, gettering is performed by utilizing the Coulomb force of phosphorus. You can also

Further, since the second semiconductor film (gettering region) 507 is removed by etching after the gettering step, it is easy to remove, for example, the first semiconductor film (crystalline silicon film 505 and etching are selected). An amorphous semiconductor film may be used as the film having a large ratio.

The crystalline silicon film 505 is subjected to heat treatment.
Gettering is performed to move the catalyst element (nickel) remaining therein to the gettering region 507 to reduce or remove the concentration. As the heat treatment for performing gettering, strong light irradiation or heat treatment is performed, and almost no nickel contained in the crystalline silicon film 505 exists, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less. desirably sufficiently gettered to be less than ^{1 × 10 1 7 / cm 3} ( Fig. 7 (C)).

Then, only the gettering region 507 is etched and selectively removed using the barrier layer 506 as an etching stopper, and then the barrier layer 506 is removed using hydrofluoric acid or the like.

In this way, a crystalline silicon thin film in which fine crystal grains of polysilicon are uniformly distributed in the continuous grain boundary crystal can be obtained. After that, oxidation treatment is further performed for the purpose of further improving the quality of the crystalline silicon film 505.
A silicon oxide film having a thickness of 20 nm is formed by a low pressure CVD apparatus (not shown), and a thermal oxidation process is performed at 950 ° C. to obtain a silicon oxide film / a portion where the silicon oxide film is oxidized = 20: 6.
A thermal oxide film is formed at a ratio of 0 (nm).

After etching the thermal oxide film, the crystalline silicon film 505 having a thickness of 35 nm is patterned by the thermal oxidation process to form semiconductor layers 508 to 511 having a shape as shown in FIG. 7D, for example. .

Next, the semiconductor layers 508 to 511 are covered with 30 n as a second insulating film (gate insulating film) 512.
A silicon oxide film having a thickness of m is formed. Then, in order to use the semiconductor layer 511 in the region to be the storage capacitor 204 later as a lower electrode of the storage capacitor, a mask 513 made of a resist for selectively etching the gate insulating film in the region directly above the semiconductor layer 511 is formed. After formation, the gate insulating film is removed and phosphorus is added (FIG. 8A).

After that, the mask 513 made of resist is removed, and 50 n is formed as the second-layer gate insulating film 512b.
A silicon oxide film having a thickness of m is formed (FIG. 8B).

After forming the semiconductor layers 508 to 511, T
A slight amount of impurity element (boron or phosphorus) may be doped to control the threshold value of FT. This impurity addition step may be performed either before the semiconductor film crystallization step, after the semiconductor film crystallization step, or after the step of forming the gate insulating film 512a.

After that, the first insulating film 502 and the gate insulating film 512 are selectively etched to form a contact hole reaching the gate line 501. Next, a conductive film is formed on the gate insulating film 512 and patterned to form the gate electrode 51 on the channel formation region of each pixel.
4 to 516 and capacitor wiring (upper electrode of storage capacitor) 517 are formed. Since the gate insulating film 512 in the region where the capacitor wiring 517 is formed is only the second-layer gate insulating film, the gate insulating film 512 is thinner than the other regions, so that the storage capacitance is increased. Further, the gate electrode 516 is electrically connected to the gate line 501 through a contact hole (FIG. 8).
(C)).

The conductive film for forming the gate electrode and the capacitor wiring is a polysilicon film to which an impurity element imparting a conductivity type is added, a WSi _x film (x = 2.0 to 2.8), A
Although it is formed with a film thickness of about 300 nm by a conductive material such as l, Ta, W, Cr, and Mo and its laminated structure,
It may be a single layer of the above-mentioned conductive material.

Next, in order to form a TFT in which the semiconductor layers 508 to 511 are active layers, an impurity element that selectively imparts n-type or p-type to the semiconductor layer (hereinafter referred to as an n-type impurity element or a p-type impurity element). ) Is added to form low-resistance source and drain regions, and LDD regions. An impurity element is added to this LDD region similarly to the source region and the drain region.

Thus, a channel formation region sandwiched between the source region and the drain region is formed in the semiconductor layers 508 to 511 (FIG. 9A).

Next, a third insulating film (first interlayer insulating film) 518 is formed to cover the gate electrodes 514 to 516 and the capacitor wiring 517. The third insulating film 518 is a silicon oxide film, a silicon nitride film, a silicon oxynitride film,
Alternatively, a laminated film in which these films are combined may be formed to have a thickness of approximately 70 nm (FIG. 9B).

Next, a fourth insulating film (second interlayer insulating film) 519 is formed. The fourth insulating film is formed with a thickness of 800 nm using any of an organic insulating material film, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film as a material.

Then, the semiconductor layer 508 is formed on the gate insulating film 512, the third insulating film 518, and the fourth insulating film 519.
A contact hole leading to 510 is formed. Then, a conductive film reaching the semiconductor layers 508 to 511 through contact holes is formed over the fourth insulating film 519 and patterned to form connection wirings and source lines 520 to 525 for electrically connecting the respective TFTs. .
Conductive films for forming these wirings are made of Al, W, T
A film containing i, TiN as a main component, or a conductive film having a laminated structure thereof (in this embodiment, a three-layer structure in which an Al film containing Ti is sandwiched between Ti layers) is formed to a thickness of 500 nm.
Is formed and patterned. Note that the source line 525 passes through the storage capacitor and passes through the semiconductor layer 510.
Is electrically connected to (FIG. 9 (C)).

Then, a fifth insulating film 52 for covering the connection wiring is formed.
6 is formed in a thickness of 1000 nm from an organic insulating film such as acrylic (FIG. 10A). Al on the fifth insulating film 526,
A light-shielding film 527 is formed by patterning a film having a high light-shielding property such as Ti, W, Cr, or black resin. The light-shielding film 527 is arranged in a mesh shape so as to shield the portions other than the openings of the pixels from light. Furthermore, the sixth insulating film 52 made of the same material as the fifth insulating film 526 is formed so as to cover the light shielding film 527.
8 is formed, and a contact hole communicating with the connection wiring 524 is formed in the fifth insulating film 526 and the sixth insulating film 528.

Next, a transparent conductive film such as ITO is deposited to 100 n.
Then, the pixel electrode 529 is formed by forming the pixel electrode 529 with a thickness of m (FIG. 10B).

FIG. 11 shows a top view of the state so far formed, and a schematic cross-sectional view taken along the line AA ′ in the drawing is a line AA ′ part of FIG. 10B. Equivalent to B-
A schematic cross-sectional view taken along the line B'corresponds to the line BB 'of FIG. 10 (B).

An alignment film for aligning the liquid crystal layer is formed on the active matrix substrate thus formed, and the counter substrate having the counter electrode and the alignment film formed thereon is bonded to the active matrix substrate by using a known cell assembly technique. Then, a liquid crystal was injected and sealed to complete an active matrix type liquid crystal display device.

(Embodiment 7) In this embodiment, the structure of the active matrix liquid crystal display device manufactured in Embodiment 6 will be described.

In FIG. 8, the active matrix substrate is composed of a pixel portion formed on the substrate 500, a driving circuit 605 and other signal processing circuits. A pixel TFT 603 and a storage capacitor 604 are provided in the pixel portion, and a driver circuit provided in the periphery of the pixel portion is basically formed of a CMOS circuit.

The capacitor wiring 517 is provided in a direction parallel to the source line 523 and functions as an upper electrode of the storage capacitor 604.

From the drive circuit 605, the gate line 501 and the source line 523 extend to the pixel portion, respectively, and the pixel TFT
It is connected to 603. A flexible printed circuit (FPC) 701 is connected to an external input terminal 702 and used to input an image signal or the like. The FPC 701 is firmly adhered by a reinforcing resin, and is connected to each drive circuit by connection wiring. Although not shown, the counter substrate 700 is provided with a light shielding film and a transparent electrode. This embodiment can be manufactured using an active matrix substrate formed by any of the methods disclosed in Embodiments 1 to 3.

(Embodiment 8) The CMOS circuit and the pixel portion formed by implementing the present invention can be used for an active matrix type liquid crystal display (liquid crystal display device).
That is, the present invention can be applied to all electric appliances in which the liquid crystal display device is incorporated in the display section.

A projector can be used as such an electric appliance. An example of a projector
3 and 14 are shown.

First, FIG. 13A shows an example of a single plate type projector. The projector illustrated in FIG. 13A includes a light source optical system 2501, a liquid crystal display device 2502, a projection optical system 2503, and a retardation plate 2504. The projection optical system 2503 is composed of a plurality of optical lenses including a projection lens. The projection optical system 2503 may be composed of one projection lens. Although not shown, a liquid crystal display device 250 is provided for colorizing the display.
2 has a color filter formed thereon.

Further, the single-plate type projector shown in FIG. 13B is an application example of FIG. 13A, in which an RGB rotating color filter disc 2505 is used instead of providing a color filter for a pixel. This is an example of performing colorization of.

Further, the single plate type projector shown in FIG. 13C is called a color filterless single plate type projector, in which a liquid crystal display device 2516 is provided with a microlens array 2515, and B dichroic mirrors 2512, G are provided. The display image is colorized by using the R dichroic mirror 2513 and the R dichroic mirror 2514. The projection optical system 2517 is composed of a plurality of optical lenses including a projection lens. Note that it may be composed of one lens.

Next, FIG. 14A shows a front type projector. The front type projector includes a projection device 2601, a screen 2602, and the like.

FIG. 14B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, screen 2704 and the like.

Note that FIG. 14C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 14A and 14B. Projection device 2601, 27
02 is a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280.
9, a projection optical system 2810. Projection optical system 28
Reference numeral 10 is composed of an optical system including a projection lens. 14
The practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting the phase difference, an IR film, etc. in the optical path indicated by the arrow in (C).

FIG. 14D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 14C. In the present embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
2814, polarization conversion element 2815, condenser lens 2816
Composed of. The light source optical system shown in FIG. 14D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, the projector shown in FIG. 14 shows a case where a transmissive electro-optical device is used, and an application example of a reflective liquid crystal display device is not shown.

As described above, the liquid crystal display device manufactured by using the present invention can be applied to a projector.

[0109]

The crystalline silicon film obtained by the present invention contains fine crystal grains (polysilicon) in the crystalline semiconductor film composed of continuous grain boundary crystals, and this serves as a trap site for carriers. Even if the semiconductor layer is irradiated with light and carriers are excited, the lifetime of the electron / hole pair can be shortened, the light leakage current can be reduced, and high field effect mobility can be maintained. be able to.

Such a crystalline silicon film is used, for example, as a switching element (switching TF) in a pixel portion of a display device.
When used for T), even if stray light is generated inside the device and enters the semiconductor layer of the TFT to induce carriers, the light leak current can be suppressed.
Further, since the TFT itself can reduce the photosensitivity (light leakage current), it is possible to adopt a simpler light-shielding structure and reduce the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a crystallization method using the present invention (Embodiment 1).

FIG. 2 is a diagram showing an example of a crystallization method using the present invention (Embodiment 2).

FIG. 3 is a diagram showing an example of a crystallization method using the present invention (Embodiment 3).

FIG. 4 is a diagram showing an example of a crystallization method using the present invention (Embodiment 3).

FIG. 5 is a diagram showing an example of an embodiment (Embodiment 4).

FIG. 6 is a diagram showing an example of an embodiment (Embodiment 5).

FIG. 7 is a diagram (1) showing a process for manufacturing a display device using the present invention.

FIG. 8 is a view (No. 2) showing a process for manufacturing a display device using the present invention.

FIG. 9 is a view (No. 3) showing a process for manufacturing a display device using the present invention.

FIG. 10 is a view (No. 4) showing a process for manufacturing a display device using the present invention.

FIG. 11 is a top view of a display device manufactured using the present invention.

FIG. 12 illustrates a structure of an active matrix liquid crystal display device manufactured by using the present invention.

FIG. 13 is a diagram showing an example of an electric appliance using a display device obtained by applying the present invention.

FIG. 14 is a diagram showing an example of an electric appliance using a display device obtained by applying the present invention.

[Explanation of symbols]

100 Substrate 101 Base Insulating Film 102 Amorphous Silicon Film 103 Containing Fine Crystal (Polysilicon) Nuclei Uniformly 103 Catalyst Element-Containing Layer 104 Crystalline Silicon Containing Crystal Grains Uniformly Grown from Spontaneous Nuclei and Continuous Grain Boundary Crystal Nuclei film

Continued front page    (72) Inventor Toru Ueda             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company F-term (reference) 2H092 JA25 JA29 JA33 JA38 JA42                       JA46 JB13 JB38 JB42 JB51                       JB63 JB69 MA07 MA12 MA29                       MA35 MA37                 5F052 AA02 AA11 AA17 BA02 BB02                       BB07 DA01 DA02 DB02 EA16                       FA06 FA19 JA01                 5F110 AA01 AA21 BB02 BB04 CC02                       DD01 DD02 DD03 DD05 DD13                       DD14 DD15 DD17 DD25 EE03                       EE04 EE05 EE09 EE14 FF02                       FF09 GG02 GG13 GG14 GG25                       GG32 GG45 GG47 GG51 GG58                       GG60 HL01 HL03 HL04 HL06                       HL12 HM15 NN03 NN04 NN22                       NN23 NN24 NN27 NN42 NN44                       NN46 NN47 NN48 NN49 NN72                       NN73 PP01 PP03 PP04 PP05                       PP10 PP13 PP23 PP29 PP34                       PP35 QQ09 QQ28

Claims (10)

[Claims] 1. A semiconductor device having a semiconductor layer containing fine crystal grains in a crystalline semiconductor film formed of continuous grain boundary crystals. 2. A semiconductor device comprising a crystalline semiconductor film composed of continuous grain boundary crystals, and a semiconductor layer containing fine crystal grains surrounded by grain boundaries discontinuous with the continuous grain boundary crystals. . 3. The semiconductor device according to claim 1 or 2, wherein the average grain size of the fine crystal grains is 0.01 to 1 μm. 4. A step of forming an amorphous silicon film on an insulator, a step of adding a metal element to the amorphous silicon film, a step of performing heat treatment to form a crystalline silicon film,
A method for manufacturing a semiconductor device, comprising: 5. An insulator, 5 × 10 ^{6 to} 5 × 10 ¹¹ pieces / c
a step of forming an amorphous silicon film having crystal nuclei at a density of m ² , a step of adding a metal element to the amorphous silicon film, a step of performing heat treatment to form a crystalline silicon film,
A method for manufacturing a semiconductor device, comprising: 6. A step of forming an amorphous silicon film on an insulator, a step of forming a mask insulating film on the amorphous silicon film, and an opening of the mask insulating film of the amorphous silicon film. A step of adding a metal element to a selected region exposed from the part, a step of performing a heat treatment to form a crystalline silicon film,
A method for manufacturing a semiconductor device, comprising: 7. A step of forming an amorphous silicon film on an insulator and a first heat treatment are performed to form 5 × 10 ^{6 on the} amorphous silicon film.
A step of generating crystal nuclei at a density of ˜5 × 10 ¹¹ pieces / cm ² , a step of adding a metal element to the amorphous silicon film having the crystal nuclei, a second heat treatment, and crystalline silicon A method of manufacturing a semiconductor device, comprising the step of forming a film. 8. A crystalline silicon film is formed by performing a step of forming an amorphous silicon film on an insulator, a step of adding a metal element to the amorphous silicon film, and a first heat treatment. A step of forming a barrier layer on the crystalline silicon film, a step of forming a semiconductor film containing a rare gas element on the barrier layer, and a second heat treatment for adding a metal element to the crystalline silicon film. And a step of moving the semiconductor film to the semiconductor film. 9. A step of forming an amorphous silicon film on an insulator, a step of forming a mask insulating film on the amorphous silicon film, and the amorphous material exposed from an opening of the mask insulating film. A metal element to a selected region of the crystalline silicon film, performing a first heat treatment to form a crystalline silicon film, and exposing the crystalline silicon film from the opening of the mask insulating film. A step of adding an element having a gettering effect to the selected region, and a step of performing a second heat treatment to move the metal element to the region to which the element having a gettering effect is added. A method for manufacturing a semiconductor device, comprising: 10. The metal element according to claim 4, wherein the metal element is Ni, Fe, Co, Sn or P.
b, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au
2. A method for manufacturing a semiconductor device, characterized in that it is any one kind or plural kinds of elements.