JP2003295220A - Matrix board for liquid crystal, manufacturing method therefor, and method for forming connection part of electronic circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a matrix board for a liquid crystal with the necessary number of photo masks reduced, and to provide a matrix board for a liquid crystal. <P>SOLUTION: A TFT active matrix board 1 is manufactured by forming a TFT element part 31 laminated with a gate electrode film 12, a gate insulating film 14, a 1st semiconductor layer 15, a 2nd semiconductor layer 16, a source-drain electrode film 17, and a passivation film 19, forming a projection part 40 at a predetermined position of the TFT element part 31, forming an acrylic resin film 20 so that it covers the projection part 40 and the TFT element part 31 where the projection part 40 is not formed, etching the acrylic resin film 20 to expose the projection part 40 and form a pixel electrode 21a on the surface of the projection part 40 and the acrylic resin 20, and connecting the projection part 40 with the pixel electrode 21a. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal matrix substrate, a method for manufacturing a liquid crystal matrix substrate, and a method for forming a connection portion of an electronic circuit board.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal display device, a thin film transistor (abbreviation: TFT) has been used.
An active matrix type liquid crystal display device using a switching element is widely used. A TFT active matrix type liquid crystal display device using a TFT as a switching element uses a TFT active matrix substrate in which a TFT active matrix circuit including a plurality of TFT elements is formed on the surface of a glass substrate having a light transmitting property. T
The FT active matrix substrate is manufactured by using a plurality of photomasks and repeating fine patterning by a photolithography process. From the viewpoints of improving the productivity and manufacturing yield of liquid crystal display devices, and keeping costs low, reduction of the number of photomasks used in the manufacturing process of the TFT active matrix substrate, that is, reduction of the photolithography process has been studied. ing.

Further, from the viewpoint of achieving low power consumption and high brightness of the TFT active matrix type liquid crystal display device, it is required to increase the light transmittance of the liquid crystal cell. In order to increase the light transmittance of the liquid crystal cell, it is necessary to improve the aperture ratio of the TFT active matrix substrate. The aperture ratio represents the area ratio of the pixel electrode for applying an electric field to the liquid crystal cell to all the pixels in percentage.
As a technique for improving the aperture ratio, a pixel electrode is formed on a flat insulating protective film covering the TFT element part, and the TFT element part and the pixel electrode are three-dimensionally separated and stacked by interposing the protective film. There is known a technique of widening a pixel region by overlapping the TFT element portion and the pixel electrode on a plan view seen from the stacking direction. Such a state in which the TFT element portion and the pixel electrode are three-dimensionally separated and stacked and overlapped in a plan view is hereinafter referred to as a three-dimensionally overlapped state. With this conventional technique, a high aperture ratio exceeding 80% has been realized. FIG. 18 is a diagram showing an example of a high aperture ratio TFT active matrix substrate obtained by a conventional technique. FIG. 18A is a plan view showing a part of the configuration of the TFT active matrix substrate 5 having a high aperture ratio. FIG.
18B is a cross-sectional view showing a cross-sectional structure taken along the section line II-II ′ of the TFT active matrix substrate 5 shown in FIG. In FIG. 18B, the gate electrode film 5
The gate electrode wiring 74 for scanning and the source
The G-S crossing portion 70 where the data source electrode wiring 75 formed by the drain electrode film 58 intersects, the TFT element portion 71 which is a switching element, and the pixel portion 7 which is a display region.
2 and the cross-sectional structure of the terminal portion 73 provided around the TFT active matrix substrate 5 are shown side by side on the assumption that they are connected in series for convenience of explanation. The TFT active matrix substrate 5 includes a gate electrode film 52, a gate insulating film 54, a first semiconductor layer 55 having a channel region, a second semiconductor layer 56, a source / drain electrode film 58 and a passivation film 60 on a glass substrate 51. Stacked,
The pixel electrode 64a is formed on the flat photosensitive acrylic resin film 61 formed so as to cover these layers. As shown in FIGS. 18A and 18B, in the TFT active matrix substrate 5, the gate electrode film 52 and the pixel electrode 64a are stacked and formed by interposing the photosensitive acrylic resin film 61, Since the TFT element portion 71 and the pixel electrode 64a can be three-dimensionally overlapped, a high aperture ratio can be obtained.

A manufacturing process of the TFT active matrix substrate 5 having a high aperture ratio shown in FIG. 18 will be described. 19 to 3
4 is a cross-sectional view schematically showing a state in each step of manufacturing the TFT active matrix substrate 5. Figure 1
9 to 34, similar to FIG. 18B, FIG.
Of the cross-sectional structure taken along the section line II-II ′ in FIG.
The cross-sectional configurations of the S-intersection portion 70, the TFT element portion 71, the pixel portion 72, and the terminal portion 73 are shown side by side on the assumption that they are connected in series for convenience of explanation.

First, one surface 51a of the glass substrate 51
As a whole, chromium (C
At least one gate electrode material selected from r), aluminum (Al), tantalum (Ta), etc. is formed to form the gate electrode film 52 as a metal film.
FIG. 19 is a diagram showing a state in which the gate electrode film 52 is formed on the entire one surface 51 a of the glass substrate 51.

A photoresist is uniformly coated on the surface of the gate electrode film 52, and then patterned using a first photomask to form a resist pattern 53. The resist pattern 53 includes the G-S intersection 7
0, the TFT element portion 71 and the terminal portion 73, but not the pixel portion 72. FIG. 20 shows the gate electrode film 5
FIG. 3 is a diagram showing a state in which a resist pattern 53 is formed on top of FIG.

Etching is performed using the resist pattern 53 as a mask to pattern the gate electrode film 52.
FIG. 21 is a diagram showing a state in which the gate electrode film 52 is patterned.

After removing the resist pattern 53, the gate insulating film 54, the first semiconductor layer 55 and the second semiconductor layer 5 are removed.
The three layers of No. 6 are processed by plasma chemical vapor deposition.
osition; abbreviated name: CVD) method or sputtering method or the like. The gate insulating film 54, the first semiconductor layer 55, and the second semiconductor layer 56 are continuously formed. The gate insulating film 54 is formed of, for example, a silicon nitride (SiN _x ) film. First semiconductor layer 55
Is, for example, amorphous silicon (hereinafter, “a-S
abbreviated as "i"). Second semiconductor layer 56
Is formed of a silicon (hereinafter abbreviated as "n ⁺ -Si") film in which an n-type impurity, for example, a pentavalent element such as phosphorus, arsenic, and antimony is mixed at a high concentration. Figure 2
2 is the gate insulating film 54, the first semiconductor layer 55 and the second
It is a figure which shows the state in which the three layers of the semiconductor layer 56 were formed.

After applying a photoresist to the entire surface of the second semiconductor layer 56, a resist pattern 57 is formed using a second photomask. Resist pattern 57
Are formed in the G-S intersection portion 70 and the TFT element portion 71, and are not formed in the pixel portion 72 and the terminal portion 73. FIG. 23 is a diagram showing a state in which a resist pattern 57 is formed on the second semiconductor layer 56.

Etching is performed using the resist pattern 57 as a mask to pattern the two layers of the first semiconductor layer 55 and the second semiconductor layer 56 of the TFT element portion 71 into island shapes. At this time, the GS intersection 70 and the source electrode wiring 7
The two layers of the first semiconductor layer 55 and the second semiconductor layer 56 at the position 5 are also left. FIG. 24 is a diagram showing a state in which two layers of the first semiconductor layer 55 and the second semiconductor layer 56 of the TFT element part 71 are patterned in an island shape.

After removing the resist pattern 57, a metal film is formed on the entire surface by at least one metal material selected from chromium (Cr), aluminum (Al), tantalum (Ta) and the like by a sputtering method or the like. Then, the source / drain electrode film 58 is formed. Figure 2
FIG. 5 is a diagram showing a state where the source / drain electrode film 58 is formed.

After applying a photoresist to the entire surface of the source / drain electrode film 58, a resist pattern 59 is formed using a third photomask. The resist pattern 59 is formed at the G-S crossing portion 70 and the TFT element portion 71, but is not formed at the channel portion forming position 59a of the TFT element portion 71. FIG. 26 is a diagram showing a state in which a resist pattern 59 is formed on the source / drain electrode film 58.

Etching is performed using the resist pattern 59 as a mask. Since the resist pattern 59 is not formed at the channel portion forming position 59a, the source / drain electrode film 58 and the second semiconductor layer 56 are removed by this etching, and the source / drain electrode for separating the source electrode and the drain electrode is formed. The film 58 is patterned. Further, the first semiconductor layer 55 is also partially etched, and the first semiconductor layer 55 at the channel portion forming position 59a is formed.
The channel portion 55a is formed in the first semiconductor layer 55 by performing channel etching for adjusting the thickness of the first semiconductor layer 55. FIG. 27
FIG. 6 is a diagram showing a state where etching is performed using the resist pattern 59 as a mask.

Next, the resist pattern 59 is removed. FIG. 28 is a diagram showing a state in which the resist pattern 59 is removed.

After removing the resist pattern 59, a silicon nitride (SiN _x ) film or the like is formed on the entire surface of the substrate by a sputtering method or the like to form a passivation film 60 as a protective film. FIG. 29 is a diagram showing a state in which the passivation film 60 is formed.

An acrylic resin having photosensitivity is applied on the passivation film 60 to form a photosensitive acrylic resin film 61 having a flat surface. FIG. 30 is a diagram showing a state in which the photosensitive acrylic resin film 61 is formed.

The photosensitive acrylic resin film 61 is patterned using a fourth photomask to form through holes 62a and 62b reaching the passivation film 60 from the surface of the photosensitive acrylic resin film 61. FIG. 31 is a diagram showing a state in which the photosensitive acrylic resin film 61 is patterned.

The passivation film 60 is etched by using the patterned photosensitive acrylic resin film 61 as a mask to remove the source / source from the surface of the photosensitive acrylic resin film 61.
A contact hole 63a reaching the drain electrode separated from the source electrode in the drain electrode film 58 is formed. At this time, at the same time, in the terminal portion 73, the passivation film 60 and the gate insulating film 54 are etched, and a contact hole 63b reaching from the surface of the photosensitive acrylic resin film 61 to the gate electrode film 52 is formed. Figure 32
FIG. 6 is a diagram showing a state in which contact holes 63a and 63b are formed.

The entire surface of the photosensitive acrylic resin film 61 and the surface of the contact hole 63a, that is, the source / drain electrode film 58 facing the contact hole 63a, the passivation film 60, and the photosensitive acrylic resin film 6
1 and the surface of the contact hole 63b, that is, the surface of the gate electrode film 52, the gate insulating film 54, the passivation film 60, and the photosensitive acrylic resin film 61 facing the contact hole 63b by an indium-based film by a sputtering method or the like. The light-transmitting conductive film 64 is formed by forming a film with at least one electrode material selected from tin oxide (Indium-Tin Oxide; abbreviated name: ITO) and tin oxide (SnO ₂ ). FIG. 33 is a diagram showing a state in which the transparent conductive film 64 is formed.

The transparent conductive film 64 is patterned using a fifth photomask to form a pixel electrode 64a.
The TFT active matrix substrate 5 is obtained as described above. FIG. 34 is a diagram showing a state in which the pixel electrode 64a is formed. As shown in FIG. 34, the pixel electrode 64 a is formed by interposing the photosensitive acrylic resin film 61,
Since it can be formed so as to be three-dimensionally overlapped with the T element portion 71, the TFT active matrix substrate 5
Can realize a high aperture ratio.

In the manufacturing process of the TFT active matrix substrate 5 described above, FIG. 20, FIG. 23, FIG. 26 and FIG.
One photomask is used in each of the five steps shown in FIG. 1 and FIG. 34, and a total of five photomasks are used. This causes a long process time and a reduction in manufacturing yield.

A prior art relating to reducing the number of photomasks used in the process of manufacturing a TFT active matrix substrate is disclosed in Japanese Patent Laid-Open No. 5-303111. In this prior art, first, a transparent conductive film is formed on a substrate and patterned as a base layer for pixel electrodes and gate electrodes. Electrolytic plating is selectively performed on the obtained base layer of the gate electrode to form the gate electrode. In this way, the patterning of the pixel electrode and the patterning of the gate electrode can be performed at the same time, so that the number of photomasks used in the manufacturing process can be reduced.

Another prior art is Japanese Patent Laid-Open No. 2000-206.
No. 571 is disclosed. In this prior art, a concept is shown in which resist patterns having different thicknesses are formed and the steps of forming the TFT element portion corresponding to the above-described manufacturing steps shown in FIGS. 23 to 27 are performed with a single photomask. In other words, it has succeeded in reducing the number of photomasks used by one by performing two-step etching by utilizing the portions having different thicknesses of the resist pattern. The resist patterns having different thicknesses can be formed by changing the exposure amount as disclosed in JP-A-61-181130. In Japanese Patent Laid-Open No. 61-181130, a resist pattern is formed by changing the exposure amount in order to form a highly accurate pattern even in a portion having a step.

A technique similar to the technique disclosed in Japanese Patent Laid-Open No. 2000-206571 is described in "A Novel Fou" by CW Kim et al.
r-Mask-Count Process Architecture for TFT-LCDs ''
(SID 2000 Digest, pages 1006 to 1009
Page), and "Mikuni Electronics IPS TFT-LCD 2P
We devised a process to manufacture with EP-Halftone exposure of TFT channel part "(monthly FPD intelligence 1999
May issue, pages 31 to 35).

Further, such a photolithography process is applied not only to the manufacturing process of the TFT active matrix substrate, but also to the manufacturing process of the wiring substrate for forming an electronic circuit, for example, the connection between the multilayer wirings of the substrate and the wiring between the substrate and the external wiring. It is also widely used in the step of forming a connection portion with.

[0026]

As described above, a total of five photomasks are required in the manufacturing process of the TFT active matrix substrate 5 exhibiting a high aperture ratio, which requires a long process time and a high manufacturing yield. Has become a factor in the decline. In the prior art disclosed in JP-A-5-303111, a transparent conductive film formed on a substrate is used as a base layer for a pixel electrode and a gate electrode, the gate electrode is formed by electrolytic plating, and a photo process is performed. By patterning the gate electrode film without using, the number of photomasks used in the manufacturing process of the TFT active matrix substrate is reduced. However, this prior art also requires the same five photomasks as in the manufacturing process of the TFT active matrix substrate 5 having a high aperture ratio described above,
This causes a longer process time and a lower manufacturing yield. In addition, since the light-transmitting conductive film formed over the substrate is used as the base layer of the pixel electrode and the gate electrode, the gate electrode and the pixel electrode cannot be overlapped,
It is not possible to obtain a high aperture ratio. Furthermore, since the gate electrode is manufactured by electrolytic plating, the nonuniformity of the film thickness is likely to become very large due to the potential drop during the manufacturing, and it is difficult to maintain the film thickness uniformity especially in the case of a large substrate.

Further, the above-mentioned Japanese Patent Laid-Open No. 2000-206571.
With the technique disclosed in Japanese Patent Laid-Open Publication No. 2003-12075, which uses a resist pattern having a different thickness, it is possible to reduce the number of photomasks used by one in the process of forming the TFT element portion. Further, this prior art mainly describes only an in-plane switching (abbreviation: IPS) type TFT active matrix type liquid crystal display device. Regarding the possibility of further reducing the number of photomasks used in the manufacturing process of the TFT active matrix substrate in which the TFT element portion and the pixel electrode are three-dimensionally overlapped and the aperture ratio is increased, other than the step of forming the TFT element portion Is not shown.

An object of the present invention is to provide a liquid crystal matrix substrate manufacturing method and electronic circuit substrate connection which can reduce the number of photomasks used in the manufacturing process of a wiring substrate for forming an electronic circuit such as a TFT active matrix substrate. A part forming method and a matrix substrate for liquid crystal are provided.

[0029]

The present invention is a liquid crystal matrix substrate in which a matrix circuit for forming a liquid crystal cell is formed on an electrically insulating substrate, and is formed so as to cover the matrix circuit. An electrically insulating layer, a protrusion that is formed so as to protrude from a predetermined position of the matrix circuit, and penetrates the electrically insulating layer; and a protrusion that is formed on the surface of the protrusion and the electrically insulating layer. A liquid crystal matrix substrate including a pixel electrode electrically connected to a matrix circuit.

According to the present invention, in the matrix substrate for liquid crystal, the matrix circuit for forming the liquid crystal cell is formed on the electrically insulating substrate, and includes the electrically insulating layer, the protrusion and the pixel electrode. The electrically insulating layer is formed to cover the matrix circuit. The protrusion is formed so as to protrude from a predetermined position of the matrix circuit,
Penetrate the electrically insulating layer. The pixel electrode is formed on the surface of the protrusion and the electric insulating layer, and is electrically connected to the matrix circuit by the protrusion. As a result, the number of photomasks used during manufacturing can be reduced, and the pixel electrodes and the matrix circuit can be three-dimensionally overlapped with each other through the electrically insulating layer, and a liquid crystal matrix substrate with an increased aperture ratio can be obtained. .

Further, according to the present invention, the matrix circuit is a thin film transistor active matrix circuit including a plurality of thin film transistors, and the thin film transistor active matrix circuit has a first semiconductor having a gate electrode layer, a gate insulating layer, and a channel region. A layer, a second semiconductor layer which is an ohmic contact layer, a metal layer which becomes a source electrode and a gate electrode, and a passivation film.

According to the present invention, a thin film transistor active matrix circuit including a plurality of thin film transistors is provided.
It includes a gate electrode layer, a gate insulating layer, a first semiconductor layer having a channel region, a second semiconductor layer which is an ohmic contact layer, a metal layer serving as a source electrode and a gate electrode, and a passivation film. As a result, the pixel electrode and the thin film transistor active matrix circuit are three-dimensionally overlapped via the electrical insulating layer, and a TFT active matrix substrate having an increased aperture ratio can be obtained.

Further, in the invention, the protrusion is at least selected from the gate electrode layer, the gate insulating layer, the first semiconductor layer, the second semiconductor layer, the metal layer and the passivation film. It is characterized by having a laminated structure of one layer and a resist layer.

According to the present invention, the protrusion is selected from the gate electrode layer, the gate insulating layer, the first semiconductor layer, the second semiconductor layer, the metal layer and the passivation film. It has a laminated structure of at least one layer and a resist layer. As a result, the pixel electrode and the thin film transistor active matrix circuit can be electrically connected by the protrusion formed at the same time as the thin film transistor active matrix circuit.

The present invention also includes a step of forming a matrix circuit for forming a liquid crystal cell on an electrically insulating substrate,
Forming a protrusion at a predetermined position of the matrix circuit; forming an electric insulating layer so as to cover the protrusion and the matrix circuit on which the protrusion is not formed; and etching the electric insulating layer. And then exposing the protrusion, and forming a pixel electrode on the surface of the protrusion and the electric insulating layer and connecting the protrusion to the pixel electrode. It is a method of manufacturing a matrix substrate.

According to the present invention, the matrix substrate for liquid crystal has a step of forming a matrix circuit for forming a liquid crystal cell on the electrically insulating substrate, and a projection portion formed at a predetermined position of the matrix circuit. A step, a step of forming an electric insulating layer so as to cover the protruding portion and a matrix circuit in which the protruding portion is not formed, a step of etching the electric insulating layer to expose the protruding portion, and the protruding portion And forming a pixel electrode on the surface of the electrical insulating layer,
It is manufactured through a process of connecting the protrusion and the pixel electrode. As a result, the connection portion that electrically connects the pixel electrode and the matrix circuit is formed by etching the electrically insulating layer until the protrusion formed in the matrix circuit is exposed, so that the connection portion is formed. Therefore, it is not necessary to use a photomask. Therefore,
When forming the connection between the pixel electrode and the matrix circuit and the pixel electrode, it is sufficient to use only one photomask when forming the pixel electrode. The number of sheets used can be reduced.

Further, in the present invention, in the step of forming the electric insulating layer so as to cover the protruding portion and the matrix circuit in which the protruding portion is not formed, the electric insulating layer is formed so as to have a flat surface. The step of etching the electrically insulating layer to expose the protrusions is characterized by etching the entire surface of the electrically insulating layer until the protrusions are exposed.

According to the present invention, in the step of forming the electric insulating layer so as to cover the protruding portion and the matrix circuit in which the protruding portion is not formed, the electric insulating layer is formed so that the surface becomes flat. Etching the electrically insulating layer,
In the step of exposing the protrusion, the electrical insulating layer,
The entire surface is etched until the protrusion is exposed. As a result, the pixel electrode is formed on the electric insulating layer having a flat surface without connection holes, and the connecting portion for electrically connecting the pixel electrode and the matrix circuit does not have unevenness on the electric insulating layer. Since it is formed, a liquid crystal matrix substrate having a highly flat surface can be obtained. When a liquid crystal display device is manufactured using such a liquid crystal matrix substrate having high surface flatness, it is possible to uniformly perform the substrate surface alignment treatment performed at the time of manufacturing, and thus improve the reliability of the alignment treatment. You can

In the present invention, the matrix circuit is a thin film transistor active matrix circuit including a plurality of thin film transistors. In the step of forming the thin film transistor active matrix circuit, a film of a gate electrode material is formed on the electrically insulating substrate. A step of forming a gate electrode layer with a gate electrode layer, forming a resist layer on the surface of the gate electrode layer, performing halftone exposure by adjusting the exposure amount of the resist layer, and patterning the gate electrode layer; A step of sequentially laminating an insulating layer, a first semiconductor layer to be a channel region, a second semiconductor layer to be an ohmic contact layer, and a metal layer to be a source electrode and a drain electrode; and a resist layer on the surface of the metal layer. Halftone exposure by adjusting the exposure amount on the resist layer. And a step of forming the first semiconductor layer and the second semiconductor layer in an island shape by etching, and a step of patterning the metal layer and forming a channel region in the first semiconductor layer. And a step of forming and covering a passivation film.

According to the invention, a thin film transistor active matrix circuit including a plurality of thin film transistors is provided.
Forming a gate electrode layer on the electrically insulating substrate with a gate electrode material to form a gate electrode layer; forming a resist layer on the surface of the gate electrode layer; and adjusting the exposure amount on the resist layer to obtain a halftone A step of exposing and patterning the gate electrode layer, a gate insulating layer, a first semiconductor layer to be a channel region, a second semiconductor layer to be an ohmic contact layer, and a metal layer to be a source electrode and a drain electrode are sequentially formed. Stacking step, forming a resist layer on the surface of the metal layer, performing halftone exposure by adjusting the exposure amount of the resist layer, and etching the first semiconductor layer and the second semiconductor layer Forming an island shape by a method, patterning the metal layer and forming a channel region in the first semiconductor layer, It is formed through a step of covering by forming a Shibeshon film. Accordingly, one photomask is used to pattern the gate electrode layer, the islands of the first semiconductor layer and the second semiconductor layer are formed, and the metal layer is patterned. The thin film transistor active matrix circuit can be formed by using only one photomask for forming the channel region in the first semiconductor layer. Further, when forming the connection portion between the pixel electrode and the thin film transistor active matrix circuit and the pixel electrode,
It is only necessary to use one photomask when forming the pixel electrode. Therefore, it is possible to manufacture a TFT active matrix substrate having a high aperture ratio by stereoscopically overlapping the pixel electrode and the thin film transistor active matrix circuit by using only three photomasks in total.

Further, in the invention, the protrusion is at least selected from the gate electrode layer, the gate insulating layer, the first semiconductor layer, the second semiconductor layer, the metal layer and the passivation film. It is characterized by being formed by laminating one layer and the resist layer.

According to the invention, the protrusion is selected from the gate electrode layer, the gate insulating layer, the first semiconductor layer, the second semiconductor layer, the metal layer and the passivation film. It is formed by stacking at least one layer and the resist layer. This allows the protrusions to be formed simultaneously with the thin film transistor active matrix circuit.

Further, according to the present invention, the step of forming a first conductive portion on a substrate, the step of forming a protrusion at a predetermined position of the first conductive portion, and the formation of the protrusion and the protrusion. A step of forming an electric insulating layer so as to cover the first conductive portion that is not formed, a step of etching the electric insulating layer to expose the protrusion, and a step of exposing the protrusion and the surface of the electric insulating layer. A step of forming a second conductive portion and connecting the protruding portion and the second conductive portion to each other.

According to the present invention, the connecting portion of the electronic circuit board includes a step of forming a first conductive portion on the board, and a step of forming a protrusion at a predetermined position of the first conductive portion. Forming an electrically insulating layer so as to cover the protrusion and the first conductive portion on which the protrusion is not formed,
Etching the electrical insulation layer to expose the protrusion, and forming a second conductive portion on the surface of the protrusion and the electrical insulation layer to connect the protrusion and the second conductive portion. It is formed through the process of making. With this, it is possible to form a connection portion for electrically connecting the first conductive portion covered with the electric insulating layer and the second conductive portion on the surface of the electric insulating layer without using a photomask. It is possible to reduce the number of photomasks used in the manufacturing process of the wiring substrate for forming the electronic circuit.

According to the present invention, the step of forming the electrically insulating layer so as to cover the protruding portion and the first conductive portion on which the protruding portion is not formed includes the step of forming the electrically insulating layer so that the surface becomes flat. The step of etching the electrical insulating layer to expose the protruding portion is characterized in that the entire surface of the electrical insulating layer is etched until the protruding portion is exposed.

According to the invention, in the step of forming the electrically insulating layer so as to cover the protruding portion and the first conductive portion where the protruding portion is not formed, the surface of the electrically insulating layer becomes flat. Form and etch the electrically insulating layer,
In the step of exposing the protrusion, the electrical insulating layer,
The entire surface is etched until the protrusion is exposed. As a result, the second conductive portion is formed on the electrically insulating layer having a flat surface without connection holes, and the first electrically conductive portion covered with the electrically insulating layer and the second surface of the electrically insulating layer are covered. Since the connecting portion for conducting the conductive portion is formed without forming irregularities on the electric insulating layer, the flatness of the surface of the substrate can be improved. Therefore, the disconnection of the second conductive portion formed on the electrical insulating layer can be prevented, and the processing of the substrate after the formation of the second conductive portion can be performed accurately, so that the manufacturing yield of the electronic circuit board can be improved. Can be improved.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION A TFT active matrix substrate 1 will be exemplified below as a liquid crystal matrix substrate which is an embodiment of the present invention. FIG. 1 is a diagram showing a schematic configuration of a TFT active matrix substrate 1. Figure 1
FIG. 3A is a plan view showing a part of the configuration of the TFT active matrix substrate 1. FIG. 1B is a sectional line I- of the TFT active matrix substrate 1 shown in FIG.
It is sectional drawing which shows the cross-sectional structure in I '. Figure 1 (b)
Then, a G-S crossing portion 30 where a scanning gate electrode wiring 34 formed of the gate electrode film 12 and a data source electrode wiring 35 formed of the source / drain electrode film 17 intersect is a switching element. The cross-sectional configurations of the TFT element portion 31, the pixel portion 32 which is the display region, and the terminal portion 33 provided around the TFT active matrix substrate 1 are shown side by side on the assumption that they are formed in series for convenience of explanation.

On the TFT active matrix substrate 1,
A gate electrode film 12, a gate insulating film 14, a first semiconductor layer 15 having a channel region, on the glass substrate 11,
By stacking the second semiconductor layer 16 which is an ohmic contact layer, the source / drain electrode film 17 serving as a source electrode and a drain electrode, and the passivation film 19, the TFT element portion 31 is formed, and the TFT element portion 3 is formed.
1 and the flat surface of the acrylic resin film 20 covering
The pixel electrode 21 a is formed on the surface of the protrusion 40 that protrudes from a predetermined position of the element portion 31 and penetrates the acrylic resin film 20. The pixel electrode 21a is electrically connected to the TFT element unit 31 by the protrusion 40. As shown in FIGS. 1A and 1B, in the TFT active matrix substrate 1, the gate electrode film 12 and the pixel electrode 21 a are formed by interposing the acrylic resin film 20.
Since the pixel electrode 21a and the TFT element portion 31 can be three-dimensionally overlapped by forming and, the high aperture ratio can be obtained. By using the TFT active matrix substrate 1 having such a high aperture ratio, a high-brightness liquid crystal display device can be obtained.

A method of manufacturing the TFT active matrix substrate 1 shown in FIG. 1 will be described. 2 to 15 are sectional views schematically showing the state of each step in manufacturing the TFT active matrix substrate 1. 2 to 15, in FIG.
Similar to (b), the GS crossing portion 30 and the TFT element portion 3 in the cross-sectional structure taken along the section line I-I ′ of FIG.
1, the cross-sectional configurations of the pixel portion 32 and the terminal portion 33 are shown side by side on the assumption that they are connected in series for convenience of explanation.

First, the glass substrate 1 which is an electrically insulating substrate
A film of at least one gate electrode material selected from chromium (Cr), aluminum (Al), tantalum (Ta), etc. is formed on one surface 11a of the first electrode 11 by a sputtering method or the like to form a metal film. 1
Form 2. FIG. 2 shows one surface 1 of the glass substrate 11.
It is a figure which shows the state which formed the gate electrode film 12 in 1a.

A photoresist is uniformly applied to the surface of the gate electrode film 12 to form a resist layer. In the resist layer,
Halftone exposure is performed by adjusting the exposure amount using a slit mask or the like as the first photomask, and resist patterns 13 having different thicknesses are formed in each portion. By performing the halftone exposure in this way, it is possible to form a resist pattern having different thicknesses in each part by one-time photoresist application. FIG. 3 is a diagram showing a state in which a resist pattern 13 having different thicknesses is formed on each surface of the gate electrode film 12. As shown in FIG. 3, the resist pattern 13 is formed to have a thickness A at the protruding portion forming position 41, and G-
The S crossing portion 30 and the TFT element portion 31 are formed to have a thickness B (B <A) smaller than the thickness A, and the terminal portion 33
Is formed to have a thickness C (C> A) larger than the thickness A.

Etching is performed using the resist pattern 13 as a mask to pattern the gate electrode film 12, and then the entire resist pattern 13 is ashed to remove the resist pattern 13 of the GS intersection 30 and the TFT element part 31. . At this time, the resist pattern 13 is formed at the protruding portion forming position 41 and the terminal portion 33.
Is the GS crossing portion 30 and the TFT element portion 3 as described above.
The resist pattern 1 of the G-S crossing portion 30 and the TFT element portion 31 shown in FIG.
A resist pattern 13 having a reduced thickness corresponding to the thickness B of 3 remains. That is, at the protruding portion forming position 41, the thickness A
The resist pattern 13 having a thickness A ′ (= A−B) obtained by subtracting the thickness B from is left, and the resist pattern 13 having a thickness C ′ (= CB) obtained by subtracting the thickness B from the thickness C remains at the terminal portion 33. FIG. 4 is a diagram showing a state where the resist pattern 13 is ashed after the gate electrode film 12 is patterned.

Next, the gate insulating film 14, the three layers of the first semiconductor layer 15 and the second semiconductor layer 16, and the source.
The drain electrode film 17 is sequentially laminated by a plasma CVD method, a sputtering method, or the like. Gate insulating film 1
4, three layers of the first semiconductor layer 15 and the second semiconductor layer 16,
In addition, the source / drain electrode film 17 is continuously formed. The gate insulating film 14 is made of, for example, silicon nitride (S
iN _x ) film or the like. The first semiconductor layer 15 is formed of, for example, an amorphous silicon (a-Si) film. The second semiconductor layer 16 includes n-type impurities such as phosphorus,
It is formed of a silicon (n ⁺ -Si) film in which a pentavalent element such as arsenic and antimony is mixed at a high concentration. The second semiconductor layer 16 is formed as an ohmic contact layer for obtaining good ohmic contact between the first semiconductor layer 15 and the source / drain electrode film 17. The source / drain electrode film 17 is made of chromium (Cr) or aluminum (Al).
And at least one metal material selected from tantalum (Ta) and the like. FIG. 5 shows three parts of the gate insulating film 14, the first semiconductor layer 15 and the second semiconductor layer 16.
It is a figure which shows the state which formed the layer and the source / drain electrode film 17.

Halftone exposure is performed by uniformly applying a photoresist to the entire surface of the source / drain electrode film 17 to form a resist layer and then adjusting the exposure amount using a slit mask or the like as a second photomask. Then, the photoresist pattern 18 having different thickness is formed in each portion by applying the photoresist once. The resist pattern 18 includes the G-S intersection portion 30 and the TFT element portion 3
1 is formed and is not formed in the pixel portion 32 and the terminal portion 33. Of the resist pattern 18 formed in the TFT element portion 31, the resist pattern 18 at a portion corresponding to the position of a channel portion 15a described later is formed as a thin portion 18a thinner than the thickness of the resist pattern 18 at the other portions. . FIG. 6 is a diagram showing a state in which the resist pattern 18 is formed.

Etching is carried out using the resist pattern 18 as a mask to remove the gate insulating film 14, the three layers of the first semiconductor layer 15 and the second semiconductor layer 16, and the source / drain electrode film 17 which are not covered with the resist pattern 18. Then, the first semiconductor layer 15 and the second semiconductor layer 16 of the TFT element part 31 are patterned into an island shape. FIG. 7 shows T
It is a figure which shows the state which patterned the 1st semiconductor layer 15 and the 2nd semiconductor layer 16 of FT element part 31 in the shape of an island.

Resist pattern 18 is formed by ashing.
Of the resist pattern 18 corresponding to the position of the channel portion 15a is removed,
The source / drain electrode film 17 is exposed. FIG. 8 is a view showing a state where the thin portion 18a is removed by ashing and the source / drain electrode film 17 is exposed.

Etching is performed using the remaining resist pattern 18 as a mask. At the position where the thin portion 18a is removed, the source / drain electrode film 17 and the second semiconductor layer 16 are removed, and the source / drain electrode film 17 is patterned to separate the source electrode and the drain electrode. Further, the first semiconductor layer 15 is also partially etched, and the first semiconductor layer 1 at the position where the thin portion 18a is removed.
Channel etching is performed to adjust the thickness of 5
The channel portion 15a is formed in the semiconductor layer 15. Figure 9
FIG. 6 is a diagram showing a state where etching is performed using the remaining resist pattern 18 as a mask.

Then, the resist pattern 18 is removed. FIG. 10 is a diagram showing a state in which the resist pattern 18 has been removed.

After removing the resist pattern 18, a silicon nitride (SiN _x ) film or the like is formed and covered by a sputtering method or the like on the entire surface of the substrate to form a passivation film 19 as a protective film. As described above,
The TFT element portion 31 and the protrusion 40 protruding from the TFT element portion 31 are formed. The protrusion 40 is the gate electrode film 1
2, the gate insulating film 14, the first semiconductor layer 15, the second semiconductor layer 16, the source / drain electrode film 17, the passivation film 19, and the resist pattern 13 are laminated, so that they are formed at the same time as the TFT element portion 31. can do. FIG. 11 is a diagram showing a state in which the passivation film 19 is formed.

Acrylic resin is applied on the passivation film 19 to form an acrylic resin film 20 having a flat surface that covers the TFT element portion 31 and the protruding portion 40 protruding from the TFT element portion 31, and 80-100 After prebaking at a temperature of ° C, firing is performed at a temperature of 200 to 250 ° C. 12
FIG. 4 is a diagram showing a state in which an acrylic resin film 20 is formed.

The entire surface of the acrylic resin film 20 is covered with the protrusion 4
After etching until the source / drain electrode film 17 of 0 is exposed, the resist pattern 13 of the terminal portion 33 is removed by using a stripping solution or the like to form the recess 45. FIG.
FIG. 4 is a diagram showing a state in which the resist pattern 13 on the terminal portion 33 is removed after the acrylic resin film 20 is entirely etched.

The entire surface of the protrusion 40 and the acrylic resin film 20 and the surface of the recess 45 of the terminal portion 33, that is, the surface of the gate electrode film 12 and the gate insulating film 14 facing the recess 45 are formed by indium sputtering or the like. -A transparent conductive film 21 is formed by forming a film with a transparent conductive material such as tin oxide (ITO). FIG. 14 is a diagram showing a state in which the translucent conductive film 21 is formed.

The transparent conductive film 21 is patterned using the third photomask, and the surface of the projection 40 and the TFT are patterned.
A pixel electrode 21a is formed on the surface of the acrylic resin film 20 of the element portion 31 and the pixel portion 32, and the protrusion 40 and the pixel electrode 21a are connected to each other. At this time, at the same time, in the terminal portion 33, a contact hole 46 that electrically connects the gate electrode film 12 and the outside is formed. As above, TF
The T active matrix substrate 1 is obtained. FIG. 15 is a diagram showing a state in which the pixel electrode 21a is formed.

As described above, in the method of manufacturing the TFT active matrix substrate 1 according to the present embodiment, the method shown in FIGS.
The TFT active matrix substrate 1 can be manufactured only by using a total of three photomasks in the three steps shown in FIG.

FIG. 16 shows the cross-sectional shape of the photomask 100 capable of halftone exposure used as the first and second photomasks in the manufacture of the active matrix substrate 1 according to this embodiment, and the corresponding amount of transmitted light. It is a figure which shows and the shape of the resist pattern formed. The photomask 100 has a configuration in which a light shielding film 102 is formed on a transparent substrate 101, and includes a transmissive portion 100a, a light shielding portion 100b, and a mesh portion 100c. A photomask that is usually used includes a transmissive portion that is formed so that the amount of transmitted light, that is, the transmitted light amount is 100%, and a light-shielding portion that is formed so that the transmitted light amount is 0%. . The photomask 100 used in the present embodiment aims at a transmission light amount intermediate between the transmission portion 100a and the light shielding portion 100b, in addition to the same transmission portion 100a and the light shielding portion 100b as those of a normally used photomask. The mesh part 100c to be formed is provided. The mesh portion 100c is formed of, for example, a mesh pattern or a slit pattern having an interval smaller than the resolution of light used for exposure. By using such a photomask 100, it is possible to form resist patterns having different thicknesses at respective portions. For example, when a positive type photoresist is exposed using the photomask 100, a resist pattern 200a having a zero resist thickness is formed in a portion corresponding to the transmissive portion 100a, and a light shielding portion 100b is formed.
The resist pattern 200b having the maximum resist thickness is formed in the portion corresponding to, and the resist patterns 200c and 200d having the resist thickness in proportion to the transmitted light amount are formed in the portion corresponding to the mesh portion 100c, and the resist pattern 200 having different thickness is formed in each portion. It

FIG. 17 is a flowchart for explaining a method of manufacturing a TFT active matrix substrate using five photomasks and a method of manufacturing a TFT active matrix substrate using three photomasks. In FIG. 17, each step of the flowchart is represented as a step for each photomask used. A method of manufacturing using five photomasks is called a five-mask process, and a method of manufacturing using three photomasks is called a three-mask process.

First, in both the three-mask process and the five-mask process, a resist pattern for patterning the gate electrode film is formed by the first photomask. However, in the three-mask process, the above-mentioned photomask capable of halftone exposure is used.

Next, in the five-mask process, a resist pattern for patterning the TFT element portion into an island shape is formed by the second photomask, and the source electrode and the drain electrode are separated by the third photomask. And forming a resist pattern for channel etching. On the other hand, in the three-mask process, the resist patterns are formed by the second and third photomasks using one photomask using halftone exposure. That is, in the three-mask process of the present embodiment, a resist pattern for island-shaped patterning of the TFT element portion, separation of the source electrode and the drain electrode, and channel etching is formed using one second photomask. Therefore, the number of photomasks used can be reduced.

In the five-mask process, the photosensitive acrylic resin film 61 for forming contact holes is patterned by the fourth photomask. In the three-mask process, the protrusion 40 is exposed to form a connection portion that electrically connects the TFT element portion 31 and the pixel electrode 21a without forming a contact hole. It is possible to reduce the number of photomasks used without using a photomask.

The patterning of the last pixel electrode film is performed using the fifth photomask in the five-mask process and the third photomask in the three-mask process.

As described above, in the three-mask process of this embodiment, a TFT active matrix substrate having a high aperture ratio can be manufactured by using only three photomasks, and the TFT active matrix substrate is manufactured. The number of photomasks used in the process can be reduced.

As described above, in this embodiment, the acrylic resin film 20 is formed to have a flat surface,
Although the entire surface is etched until the source / drain electrode film 17 of the protrusion 40 is exposed, it is not always necessary to form the surface so as to be flat and to completely etch the surface. However, if the acrylic resin film 20 is formed so as to have a flat surface and the entire surface is etched, the pixel electrode 21a can be formed on the acrylic resin film 20 having a flat surface without connection holes and the like. Further, since the connecting portion for electrically connecting the pixel electrode 21a and the TFT element portion 31 is formed without forming irregularities on the acrylic resin film 20, it is possible to obtain the TFT active matrix substrate 1 having a high surface flatness. You can When a liquid crystal display device is manufactured using a TFT active matrix substrate having a high surface flatness as described above, it is possible to uniformly perform a substrate surface alignment process performed at the time of manufacturing, thus improving the reliability of the alignment process. You can

In this embodiment, the source of the protrusion 40 is
Although the drain electrode film 17 is exposed, the drain electrode film 17 is not limited to this, and the TF in the layer included in the protrusion is not limited to this.
A layer that can electrically connect the matrix circuit such as the T element portion and the pixel electrode may be exposed as a connection layer.

Further, in this embodiment, as shown in FIGS. 12 to 15, the acrylic resin film 20 covers the TFT element portion 31 and the protruding portion 40 protruding from the TFT element portion 31, and the acrylic resin film 20 is formed. Etching the protrusion 4
0 is exposed, and the projection 40 and the acrylic resin film 20 are exposed.
By forming the pixel electrode 21a on the surface of the TFT and connecting the protrusion 40 to the pixel electrode 21a, a connection portion for electrically connecting the TFT element portion 31 and the pixel electrode 21a is formed without using a photomask. ing.

The method of forming such a connecting portion is not limited to the TFT active matrix substrate, but can be used for manufacturing various electronic circuit boards, and a manufacturing process of a wiring board for forming an electronic circuit by this method. It is possible to reduce the number of photomasks used in. Further, it is preferable that the electric insulating layer covering the electronic circuit formed on the substrate is formed so that the surface is flat and the entire surface is etched. As a result, the flatness of the surface of the substrate after the wiring is formed can be improved, the disconnection of the wiring formed on the electrical insulating layer can be prevented, and the processing of the substrate after the wiring can be performed with high accuracy. The manufacturing yield of the substrate can be improved.

[0076]

As described above, according to the present invention, the number of photomasks used at the time of manufacturing is reduced, and the pixel electrodes and the matrix circuit are three-dimensionally overlapped via the electrically insulating layer, and the aperture ratio is increased. An enhanced matrix substrate for liquid crystal can be obtained.

Further, according to the present invention, the pixel electrode and the thin film transistor active matrix circuit are three-dimensionally overlapped via the electrically insulating layer to increase the aperture ratio.
A T active matrix substrate can be obtained.

Further, according to the present invention, the pixel electrode and the thin film transistor active matrix circuit can be electrically connected by the protrusion formed at the same time as the thin film transistor active matrix circuit.

Further, according to the present invention, since it is not necessary to use a photomask for forming a connection portion for electrically connecting the pixel electrode and the matrix circuit, use of the photomask in the manufacturing process of the liquid crystal matrix substrate. The number of sheets can be reduced.

Further, according to the present invention, the pixel electrode is formed on a flat electric insulating layer having no connection hole, and the connecting portion for electrically connecting the pixel electrode and the matrix circuit has unevenness on the electric insulating layer. Since it is formed without forming, it is possible to obtain a liquid crystal matrix substrate having a high surface flatness,
It is possible to improve the reliability of the alignment treatment on the surface of the substrate, which is performed when manufacturing the liquid crystal display device.

Further, according to the present invention, the pixel electrode and the thin film transistor active matrix circuit are three-dimensionally overlapped to manufacture a TFT active matrix substrate having a high aperture ratio by using only three photomasks. You can

Further, according to the present invention, the protrusion can be formed simultaneously with the thin film transistor active matrix circuit.

Further, according to the present invention, a connection portion for conducting the first conductive portion covered with the electric insulating layer and the second conductive portion on the surface of the electric insulating layer is formed without using a photomask. Therefore, it is possible to reduce the number of photomasks used in the manufacturing process of the wiring board for forming the electronic circuit.

Further, according to the present invention, the disconnection of the second conductive portion formed on the electric insulating layer can be prevented, and the processing of the substrate after the formation of the second conductive portion can be performed accurately. The manufacturing yield of electronic circuit boards can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a TFT active matrix substrate 1.

FIG. 2 is a diagram showing a state in which a gate electrode film 12 is formed on one surface 11a of a glass substrate 11.

FIG. 3 is a diagram showing a state in which a resist pattern 13 having different thicknesses is formed on each surface of a gate electrode film 12.

FIG. 4 is a diagram showing a state in which the resist pattern 13 is subjected to ashing after the gate electrode film 12 is patterned.

5 is a diagram showing a state in which a gate insulating film 14, three layers of a first semiconductor layer 15 and a second semiconductor layer 16, and a source / drain electrode film 17 are formed.

FIG. 6 is a diagram showing a state in which a resist pattern 18 is formed.

FIG. 7 is a diagram showing a state in which the first semiconductor layer 15 and the second semiconductor layer 16 of the TFT element section 31 are patterned in an island shape.

FIG. 8 is a diagram showing a state where the thin portion 18a is removed by ashing to expose the source / drain electrode film 17.

FIG. 9 is a diagram showing a state where etching is performed using the remaining resist pattern 18 as a mask.

FIG. 10 is a diagram showing a state in which the resist pattern 18 is removed.

FIG. 11 is a view showing a state in which a passivation film 19 is formed.

FIG. 12 is a diagram showing a state in which an acrylic resin film 20 is formed.

FIG. 13 is a diagram showing a state in which the resist pattern 13 on the terminal portion 33 is removed after the acrylic resin film 20 is entirely etched.

FIG. 14 is a diagram showing a state in which a transparent conductive film 21 is formed.

FIG. 15 is a diagram showing a state in which a pixel electrode 21a is formed.

FIG. 16 is a cross-sectional shape of a photomask 100 capable of halftone exposure, which is used as the first and second photomasks in the manufacture of the active matrix substrate 1 according to the present embodiment, and the corresponding amount of transmitted light and formation. It is a figure which shows the shape of the resist pattern.

FIG. 17 is a flowchart illustrating a method of manufacturing a TFT active matrix substrate using five photomasks and a method of manufacturing a TFT active matrix substrate using three photomasks in comparison.

FIG. 18: TFT with high aperture ratio obtained by conventional technology
It is a figure which shows an example of an active matrix substrate.

FIG. 19 is a diagram showing a state in which a gate electrode film 52 is formed on the entire one surface 51a of the glass substrate 51.

FIG. 20 is a resist pattern 53 on the gate electrode film 52.
It is a figure which shows the state which formed.

FIG. 21 is a diagram showing a state in which the gate electrode film 52 is patterned.

FIG. 22 is a diagram showing a state in which three layers of a gate insulating film 54, a first semiconductor layer 55, and a second semiconductor layer 56 are formed.

FIG. 23 is a resist pattern 57 on the second semiconductor layer 56.
It is a figure which shows the state which formed.

FIG. 24 is a diagram showing a state in which two layers of a first semiconductor layer 55 and a second semiconductor layer 56 of the TFT element part 71 are patterned into an island shape.

FIG. 25 is a diagram showing a state in which a source / drain electrode film 58 is formed.

FIG. 26 is a view showing a state in which a resist pattern 59 is formed on the source / drain electrode film 58.

FIG. 27 is a diagram showing a state where etching is performed using the resist pattern 59 as a mask.

FIG. 28 is a diagram showing a state in which the resist pattern 59 is removed.

FIG. 29 is a diagram showing a state in which a passivation film 60 is formed.

FIG. 30 is a diagram showing a state in which a photosensitive acrylic resin film 61 is formed.

FIG. 31 is a diagram showing a state in which the photosensitive acrylic resin film 61 is patterned.

FIG. 32 is a view showing a state in which contact holes 63a and 63b are formed.

FIG. 33 is a diagram showing a state in which a transparent conductive film 64 is formed.

FIG. 34 is a diagram showing a state in which a pixel electrode 64a is formed.

[Explanation of symbols]

1 TFT active matrix substrate 11 glass substrate 12 gate electrode films 13 and 18 resist pattern 14 gate insulating film 15 first semiconductor layer 15a channel portion 16 second semiconductor layer 17 source / drain electrode film 18a thin portion 19 passivation film 20 acrylic resin Film 21 Translucent conductive film 21a Pixel electrode 30 G-S crossing part 31 TFT element part 32 Pixel part 33 Terminal part 34 Gate electrode wiring 35 Source electrode wiring 40 Projection part 41 Protrusion part formation position 45 Recess 46 Contact hole 100 Photomask 100a Transmission part 100b Light shielding part 100c Mesh part 101 Light transmitting substrate 102 Light shielding film 200, 200a, 200b, 200c, 200d Resist pattern

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H092 HA04 JA26 JA46 KB04 KB14                       KB22 KB24 MA05 MA17 NA07                       NA15 NA27                 5F110 AA16 AA30 BB01 CC07 DD02                       EE03 EE04 EE44 FF03 FF28                       FF30 GG02 GG15 GG43 GG45                       GG58 HK03 HK04 HK09 HK14                       HK21 HK25 HK33 HK35 HL07                       NN03 NN24 NN27 NN34 NN72                       QQ02 QQ09

Claims (9)

[Claims] 1. A matrix substrate for liquid crystals, wherein a matrix circuit for forming a liquid crystal cell is formed on an electrically insulating substrate, and an electrically insulating layer formed so as to cover the matrix circuit, and the matrix circuit. A protrusion protruding from a predetermined position of the protrusion and penetrating the electric insulating layer, and formed on the surface of the protrusion and the electric insulating layer, and electrically connected to the matrix circuit by the protrusion. A matrix substrate for a liquid crystal, comprising: 2. The matrix circuit is a thin film transistor active matrix circuit including a plurality of thin film transistors, and the thin film transistor active matrix circuit includes a gate electrode layer, a gate insulating layer, and a first semiconductor layer having a channel region, Second which is ohmic contact layer
2. The liquid crystal matrix substrate according to claim 1, further comprising a semiconductor layer, a metal layer serving as a source electrode and a gate electrode, and a passivation film. 3. The projection is at least one layer selected from the gate electrode layer, the gate insulating layer, the first semiconductor layer, the second semiconductor layer, the metal layer and the passivation film. 3. The liquid crystal matrix substrate according to claim 2, which has a laminated structure of: and a resist layer. 4. A step of forming a matrix circuit for forming a liquid crystal cell on an electrically insulating substrate, a step of forming a protrusion at a predetermined position of the matrix circuit, and a step of forming the protrusion and the protrusion. A step of forming an electric insulating layer so as to cover the matrix circuit that is not formed; a step of etching the electric insulating layer to expose the protruding portion; and a pixel electrode on the surface of the protruding portion and the electric insulating layer. And a step of connecting the protrusions to the pixel electrodes, the method for manufacturing a liquid crystal matrix substrate. 5. The step of forming an electrically insulating layer so as to cover the protrusions and the matrix circuit in which the protrusions are not formed, the electrically insulating layer is formed to have a flat surface, 5. The method of manufacturing a liquid crystal matrix substrate according to claim 4, wherein in the step of etching the insulating layer to expose the protrusion, the entire surface of the electrical insulating layer is etched until the protrusion is exposed. 6. The matrix circuit is a thin film transistor active matrix circuit including a plurality of thin film transistors. In the step of forming the thin film transistor active matrix circuit, a gate electrode material is formed on the electrically insulating substrate to form a gate electrode. A step of forming a layer, a step of forming a resist layer on the surface of the gate electrode layer, performing halftone exposure by adjusting the exposure amount of the resist layer, and patterning the gate electrode layer, a gate insulating layer, A step of sequentially laminating a first semiconductor layer to be a channel region, a second semiconductor layer to be an ohmic contact layer, and a metal layer to be a source electrode and a drain electrode, and forming a resist layer on the surface of the metal layer, A process of performing halftone exposure by adjusting the exposure amount on the resist layer A step of forming the first semiconductor layer and the second semiconductor layer in an island shape by etching, a step of patterning the metal layer and a channel region in the first semiconductor layer, and a passivation film 6. A method of manufacturing a liquid crystal matrix substrate according to claim 4, further comprising: 7. The projection is at least one layer selected from the gate electrode layer, the gate insulating layer, the first semiconductor layer, the second semiconductor layer, the metal layer, and the passivation film. 7. The method for manufacturing a liquid crystal matrix substrate according to claim 6, wherein the substrate is formed by stacking the resist layer and the resist layer. 8. A step of forming a first conductive portion on a substrate, a step of forming a protrusion at a predetermined position of the first conductive portion, and the protrusion and the protrusion not formed. A step of forming an electrically insulating layer so as to cover the first conductive portion; a step of etching the electrically insulating layer to expose the protruding portion; and a second step on the surface of the protruding portion and the electrically insulating layer. A step of forming a conductive portion and connecting the protruding portion and the second conductive portion to each other. 9. The step of forming an electrically insulating layer so as to cover the protruding portion and the first conductive portion where the protruding portion is not formed, the electrically insulating layer is formed so that the surface becomes flat. 9. The electronic circuit board connection according to claim 8, wherein the step of etching the electrical insulation layer to expose the protrusions comprises etching the entire surface of the electrical insulation layer until the protrusions are exposed. Part formation method.