JP2003285476A - Printing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printing system that can perform a high speed printing operation without stopping DMA transfer by adding dummy data to the rear part of print data in a printing system including a printer. <P>SOLUTION: A host device 2 forms print data by using an application 4. When the size of the print data is less than a predetermined number of bytes, the host device 2 adds the dummy data to the print data and sends it to the printer 3. The printer 3 performs buffering of the predetermined number of bytes of the print data. When the predetermined number of bytes of the print data is buffered, the print data is transferred to a memory 15 by the DMA transfer, and then the operation is repeated, thereby completing the transferring of the print data. As the above structure, the print data is continuously transferred by the DMA transfer, thereby realizing the higher DMA transfer of the print data. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing system including a printing device such as a printer device.

[0002]

2. Description of the Related Art Today, there has been proposed a printing system in which a printer device connected to a network such as a LAN (local area network) is used, print data is transmitted from a host device such as a personal computer, and a printing process is performed. . In such a printing system, there is a strong demand for higher printing speed.

Therefore, in order to speed up the printing process, when a plurality of bytes of print data are received from a host device, a process of transferring the print data to one memory by DMA transfer is performed. For example, when the processing capacity of the MPU is 64 bits, it is possible to access 8 bytes at a time. For example, when the system bus of the printer device also supports 64 bits (8 bytes), the following DMA processing is performed. It is carried out.

FIG. 17 is a diagram for explaining the above process and shows the data format of print data. The arrow ↑ shown in the figure indicates the timing of DMA transfer that occurs every 8 bytes. The print data consists of a paper setting command and a print command. The paper setting command consists of commands such as "print mode", "size", "resolution", and "smoothing", and the print command is "text" and "image". Command. Note that the paper setting command is a command set for each page, and the data length of the print command changes depending on the image to be printed.

The print data output from the host device has the above configuration, and the printer device analyzes the above command to create bitmap data and expands it in the frame memory. However, the data length of the print command is not constant as described above. Therefore, as shown in the figure, the end of the page is
It may not end with a multiple of 8. That is, there are cases where data that is less than 8 bytes remains.

Conventionally, in the above-mentioned case, the data of the fractional number of bytes is read and processed by the program processing.

[0007]

However, in the above conventional processing, when the print data has a fraction,
It takes a predetermined time to shift to the program processing. That is, if the fractional print data is not read, the page data is not completed, so the DMA processing is temporarily stopped and the fractional processing is performed by the program processing.

At present, the above-mentioned predetermined time is, for example, 0.5 seconds, but since it is not always monitored that the transfer of the print data is stopped, the data transfer is delayed by about 1.0 second. Further, in this stop state, even if the host device tries to transmit the print data, the DMA process is not possible because the DMA process is stopped, and it is necessary to restart the DMA process to enable reception.

The present invention has been made in view of the above problems, and transmits print data to a printer device by adding dummy data after the print data and transferring the print data at high speed without stopping the DMA transfer. A printing system for performing the above is provided.

[0010]

According to the invention described in claim 1, the above-mentioned problem is solved by: a host device for creating print data and outputting the print data; and a memory for storing the print data from the host device. In a printing system having a printing device for recording and performing a printing process on the host device, the host device has an adding means for adding dummy data when the print data does not end in a predetermined number of bytes, and the printing device is The present invention can be achieved by providing a printing system characterized by including a transfer unit that DMA-transfers print data transmitted from a host device for each predetermined number of bytes, and records the DMA-transferred print data in the memory.

The system may be connected to a network such as a LAN, or the host device and the printing device may be connected locally.
The print data is data including a paper setting command and a print command, and is created by the host device. When the print data does not end within a predetermined number of bytes, dummy data is added.

With this configuration, print data of a predetermined number of bytes or more is always input to the printer side, and D
MA transfer can be continuously performed, and unnecessary dummy data can be disposed of later by discarding processing or the like. Therefore, the DMA transfer can be continuously performed, and the DMA transfer of the print data becomes faster.

According to a second aspect of the invention, in the invention of the first aspect, when the predetermined number of bytes is n bytes, the dummy data to be added is n-1 bytes of data. With this configuration, for example, when the predetermined number of bytes is 8 bytes, 7 bytes of dummy data may be added, and when the predetermined number of bytes is 16 bytes, 15 bytes of dummy data may be added.

According to a third aspect of the present invention, in the first or second aspect, the printing device includes a counting means for counting the number of bytes of print data transmitted from the host device, and the counting means has the predetermined byte. When the input of several print data is confirmed, the print data is DMA-transferred.

With this configuration, it is possible to more efficiently perform the DMA transfer of print data. The description of claim 4 is the same as the description of claim 1, 2 or 3.
The printing device has a time measuring unit, and when the print data is not input to the printing device for a certain period of time, the time measuring unit detects a delay of input of the print data and forcibly DMAs the print data.
It is a structure to transfer.

Here, the above-mentioned fixed time is a time which is not longer than the time when the input of the print data is stopped and the software processing is performed instead of the DMA transfer, and it is detected that the input of the print data is stopped in a shorter time. , DMA transfer is continued. According to a fifth aspect of the present invention, in the fourth aspect, a discharge code is described at the end of the print data, and the transfer unit performs the DMA transfer only when the discharge code is detected. .

With this configuration, the end point of the print data is surely detected, and the DMA transfer of the print data less than the predetermined number of bytes is prevented in the middle of the print data.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. <First Embodiment> FIG. 1A is a system configuration diagram of a printing system of the present invention.

In the figure, the printing system of this example is LA
It is constructed on a network such as N, and the network 1 is connected with various devices such as a personal computer, a storage device, a scanner, and a printer device.
The printing system of the present example is constructed in the network 1 having the above-mentioned configuration, and is a host device 2 composed of a personal computer or the like, and a printer device 3.

The host device 2 is composed of an application 4, a printer driver 5, a spooler 6 and a port monitor 7, and performs the processing shown in FIG. 1 (b). That is, the application 4 is word software or spreadsheet software for creating print data, and creates print data according to the application (step (hereinafter referred to as STP) 1).
Then, the created print data is sent to the printer driver 5 and converted into an intermediate code corresponding to the printer device 3 (STP2). Then, when it is sent to the spooler 6 and the spooler processing is completed (YES in STP3), dummy data is added to the end of the print data (STP4).

After that, the print data is sent to the port monitor 7, and the print data is sent to the designated output destination (STP5). For example, a plurality of printer devices are connected to the network 1, and print data is transmitted to the designated printer device.
The instruction of the output destination of the print data is described in the header added to the print data.

On the other hand, the printer device 3 comprises an interface (I / F) controller 8 and an engine section 9. The I / F controller 8 includes a reception controller 10 and a ROM
11, font storage unit 12, display control unit 13, video interface (I / F) 14, memory 15, ASIC
(Application specific integrated circuit) 16,
And MPU17. Also, the engine unit 9
Is a head control unit 18, a motor control unit 19, a high voltage control unit 2
0, fixing controller 21, paper feed controller 22, paper discharge controller 23
It is composed of.

The MPU 17 controls according to the program recorded in the ROM 11 and uses the memory 15 as a work area. The memory 15 is composed of a standard RAM 15a and an expansion RAM 15b. For example, the standard RAM 15a
Is a built-in DRAM, and the expansion RAM 15b is an added DIMM (dual in-line memory module).

The reception controller 10 receives the print data supplied from the host device 2 and transfers it to the memory 15 under the control of the ASIC 16. At this time, the reception controller 10
The data transfer from the memory to the memory 15 is a DMA transfer. When a predetermined amount of print data is stored in the memory 15, the MPU
A font storage unit 1 performs analysis processing of print data.
Bitmap data corresponding to the character code is read from 2 to create drawing data. The drawing data created in this way is transferred to the engine unit 9 via the video I / F 14.

The engine section 9 sends the transferred drawing data to the head control section 18 to perform printing processing on recording paper. At this time, the engine unit 9 controls the motor control unit 19,
The photosensitive drum, the transport roller, etc. are rotated to feed the recording paper, and the high voltage controller 20 is controlled to supply the developing bias voltage and the charging voltage. Further, the fixing control unit 21 controls the temperature, the paper feed control unit 22 controls the supply of the recording paper, and the paper ejection control unit 23 causes the recording paper to be discharged to the outside of the machine.

FIG. 2 is a system diagram when the print data input to the reception control unit 10 is DMA-transferred to the memory 15. The reception control unit 10 receives print data from the host device 2 described above byte by byte. When receiving the print data, the reception control unit 10 sends a request signal (DREQ) to A
The print data of 8 bytes is sent to the SIC 16, and when the acknowledge signal (DACK) is responded from the ASIC 16, the print data of 8 bytes is transferred to the ASIC 16.

The ASIC 16 latches the transferred print data and then outputs it to the memory 15. In this case, the print data is output to the data bus (MD) of the memory 15 and stored in the memory 15. The reception stop signal (R
EC STOP) is a signal for stopping the reception of print data from the host device 2 described above. The count signal (CNT) counts the number of bytes of print data. In addition, the count clear signal (CNT CL
R) is a signal for clearing the data of the number of bytes received by the reception control unit 10. Fifored signal (FIFO
RD) is a read signal output from the MPU 17 when the reception control unit 10 receives print data.

Further, INT is an interrupt signal, and AD
Is an address data bus, MA is an address bus of the memory 15, and MD is a data bus of the memory. Further, MEM RD is a memory read signal,
WR is a memory write signal. The specific function of each signal will be described in the description of the processing operation described later.

On the other hand, FIG. 3 is a diagram for explaining a specific configuration of the reception control unit 10. The reception control unit 10 includes a 1-byte reception unit 10a, a counter 10b, a buffer 10c, OR gates 10d, 10e, 10f, and a gate circuit 1.
It is composed of 0 g. The 1-byte receiving unit 10a receives the print data supplied from the host device 2 byte by byte. When the 1-byte receiving unit 10a receives 1-byte print data, it sends an addition signal to the counter 10b,
The count value of the counter 10b is incremented by 1.

The print data received by the 1-byte receiving unit 10a is sent to the buffer 10c byte by byte and held in each FIFO (Fifo (First In First Out)) of the buffer 10c. Then, when the next 1-byte print data is received, the inside of the FIFO is shifted,
Finally, 8 bytes of print data is held. That is, the input print data is sequentially shifted in the buffer 10c, and the 8-byte print data is stored. Then, when the reception of the print data is completed, the count value of the counter 10b becomes "8", and the request signal (DREQ) described above is obtained.
To the ASIC 16, and the ASIC 16 sends an interrupt signal (INT) to the MPU 17.

Further, the OR gate 10f sends the fifo read signal (FIFO RD) output from the MPU 17 to the gate circuit 10g, and the signal is stored in the buffer 10c.
The byte print data is transferred to the ASIC 16. The counter 10b is supplied with a count clear signal (CNT CLR) from the ASIC 16 to clear the count data of the counter 10b.

FIG. 4 is a diagram showing a specific configuration of the ASIC 16. As shown in the figure, the ASIC 16 includes a DMA address section 16a, a DMA capacity section 16b, and a data latch 1.
6c and a selector 16d. The DMA address unit 16a is the address bus (MA) of the memory 15 described above.
And outputs the address bus (MA) to the memory 15. The DMA capacity unit 16b counts the transfer capacity of DMA transfer. For example, once D
The 8-byte print data is transferred to the memory 15 by MA transfer, the DMA address is +8, and the DMA capacity is −.
8.

The data latch 16c has a function of latching print data when the print data is transferred to the memory 15, and latches 8 bytes of print data. Further, the selector 16d, based on the read signal (RD) or the write signal (WR) output from the MPU 17, outputs the corresponding fifo read signal (FIFO RD), reception stop signal (REC STOP), and count clear signal (CNT C).
It has a function of selecting (LR) and outputting it to the reception control unit 10. In the above configuration, FIG. 5 is a time chart for explaining the process of this example.

Before describing the processing operation, the format of print data supplied from the host device 2 will be described. The data format shown in FIG. 6 is the format of the print data used in the processing of this example, and the arrow ↑ indicates the timing of the DMA transfer that occurs every 8 bytes as described above. The print data is composed of a paper setting command and a print command. The paper setting command includes data such as “print mode”, “size”, “resolution”, and “smoothing”, and the print command includes “character” and “character”. The image command is included. However, in this example, for example, 7-byte dummy data is described at the end of the print data.

In the flowchart shown in FIG. 5, first, the first 1-byte print data (H1) is transferred from the host device 2 via the network, and then 8-byte print data is sequentially transferred (H1 to H8). That is, in this case, the 8-byte print data of a shown in FIG. 6 is transferred. When the 8-byte print data is supplied (timing shown in FIG. 5), the request signal (DR
EQ) is output to the ASIC 16.

The ASIC 16 sends this request signal (DR
An acknowledge signal (DACK) is output based on EQ) (timing shown in FIG. 5) and transmitted from the ASIC 16 to the reception control unit 10. The transmission data (print data) held in the buffer 10c based on the acknowledge signal (DACK) is transferred to the ASIC 16,
It is once latched by the data latch 16c. And MP
In accordance with the write signal (WR) output from U17, 8-byte print data is written in the memory 15 (timing shown in FIG. 5).

After that, an acknowledge signal (DACK)
Falls (timing shown in FIG. 5), "8" is added to the DMA address 16a, and the address bus is released. Next, the reception control unit 10 sequentially inputs the next 8-byte print data (b shown in FIG. 6) supplied from the host device 2 byte by byte, and the next 8-byte print data is held in the buffer 10c. Then, the print data is DMA-transferred to the memory 15 via the ASIC 16.

Therefore, the print data shown in FIG. 6 is transferred to the memory 15 every 8 bytes while repeating the above-mentioned processing. That is, the print data c, d, ... Shown in FIG.
・ Sequentially transfer. After that, when the print data corresponding to the paper discharge data described at the end of the print command is sent,
Although the transfer of the actual data included in the print command ends,
In this example, 7 bytes of dummy data are further added, and the discharge data is also transferred together with the dummy data. That is, the dummy data is also written in the memory 15 by the same processing as the above processing. This dummy data does not substantially include a command function and is simply inserted, but the DMA transfer continues without stopping. However, the dummy data stored in the memory 15 can be read and discarded.

Therefore, it is not necessary to stop the input of print data by the above processing and stop the DMA transfer for a predetermined time to perform the soft processing. More specifically, if the dummy data is not inserted and the print command corresponding to the paper discharge is read, the reception control unit 10 shifts the buffer 10c to hold the print data, but the subsequent print data is not input. Absent. Therefore, the value of the counter 10b does not reach 8 and the processing is stopped. Then, when a predetermined time elapses, the reception stop signal (REC S
TOP) is output, the input of print data to the 1-byte receiving unit 10a is stopped, and software processing is performed. Therefore, as described above, the transfer process is delayed by about 1 second.

On the other hand, in the present example, the above-mentioned problem does not occur, and the print data continues to be DMed by the dummy data.
Since the A transfer is performed, the print data can be transferred to the memory 15 at high speed. For example, in the case of the example shown in FIG. 6, the next page data is supplied after the dummy data, but the above process can be repeated without any problem. In this case, the next page data can be determined to be updated by performing command analysis.

As described above, by adding the dummy data to the end of the print data, the print data is continuously DMAed.
Since the data is transferred, the print data can be transferred at high speed. In the first embodiment, the dummy data is added to the end of one page, but in the case of a plurality of pages, the dummy data may be added only to the last page.

Further, the host device 2 may acquire the transfer unit information at the time of the DMA transfer from the printer device 3 and set the size of the dummy data based on this information. For example, if the DMA transfer is in units of 16 bytes,
It is 15 bytes of dummy data. <Second Embodiment> Next, a second embodiment of the present invention will be described.

In this example, the ASIC 16 has the configuration shown in FIG. That is, the timer 16e, the adder 16f, and the OR gates 16g and 16h are added. The details will be described below. The timer 16e is set to a time-up time of, for example, about 0.2 seconds. When the time print data is not input, the timer 16e times up, and a fifo read signal (FIFO RD) is received via the OR gate 16g.
0, and also outputs a reception stop signal (REC STOP) via the OR OR gate 16h. Also, adder 1
6f adds the DMA address.

FIG. 8 is a time chart for explaining the processing of this example. The example in the figure is an example in which the input of print data is stopped after the input of 4 bytes of print data. in this case,
The 4-byte print data is the last data of the print command including the above-mentioned paper discharge command.

In this case as well, print data is transferred from the host device 2 via the network in 1-byte units (H1 to H
4) When the supply of the print data of the 4th byte is completed (Fig. 8
The timing shown in FIG. 8), the next print data is not input, so the timer 16e times out (timing shown in FIG. 8). Then, the timer 16e outputs the time-up signal (TUP), and the reception stop signal (REC
STOP), and fifo read signal (FIFO R
D) is output (at the timing shown in FIG. 8).

The fifo read signal (FIFO R
The 4-byte print data held in the buffer 10c by D) is written in the memory 15 via the data latch 16c. Writing of print data to the memory 15 is performed by a memory write signal (MEMWR) (timing shown in FIG. 8).

At this time, 8 bytes of data are stored. Since the adder 16f adds the DMA address and the count signal (CNT) to make the added data a DMA address, the MPU 17 prints 4 bytes. It can be seen that only data has been received and the MPU 17 can start creating drawing data based on this information.

After that, the timer 16e is reset to stop the output of the fifo read signal (FIFO RD) and the output of the reception stop signal (REC STOP) (FIG. 8).
, The timing of). By performing the processing as described above, the fraction data can be received by the hardware processing without adding the dummy data, and the transfer processing of the print data can be performed without waiting a long predetermined time. Therefore, according to this example, it is possible to reduce the transfer data as compared with the first embodiment.

In this example, a 0.2 second timer is used as the timer 16e, but the timer is not limited to this. Also in this example, the above processing may be performed by adding dummy data. Further, FIG. 9 is a diagram for explaining a modification of the second embodiment, and particularly shows the reception control unit 10. Compared to the configuration of the reception control unit 10 shown in FIG. 3 described above, a comparator 10h is provided. This comparator 10
Reference numeral h is a circuit for comparing the discharge codes, and the code number (0Ch) of the discharge code is recorded therein.

Therefore, the process described above is performed, and the print data described at the end of the print command is stored in the buffer 1
When the data is stored in the FIFO 8 of 0c, both data are compared by the comparator 10h. When the print data stored in the FIFO 8 is a paper ejection code, the code numbers match, and the comparator 10h outputs a paper ejection code detection signal (Exit). Then, this detection signal (Exi
By performing the same processing as described above based on t), the discharge code can be detected by hardware processing without adding dummy data, and the transfer processing of print data can be performed without waiting for a predetermined time.

Further, as shown in FIG. 10, the detection signal (Exit) may be connected to the above-mentioned timer 16e so that the printing is not started when the discharge code is not received. FIG. 11 is a time chart explaining the above process. As shown in the figure, print data (H
After 1) is input, the next data is not input, timer 1
6e is timed up, and according to the first embodiment, the print data transfer process is performed. However, in this case, since it is not the paper discharge code, the transmission process cannot be restarted (B shown in FIG. 11). On the other hand, when the discharge code is a fraction, a fractional DMA transfer is executed (C shown in FIG. 11). <Third Embodiment> Next, a third embodiment of the present invention will be described.

As described in the first embodiment,
When the print data is transferred every 8 bytes, if a fraction occurs, the transfer process is performed by the software process, and the subsequent data transfer is prepared. Therefore, a complicated process of resetting the DMA is required. Therefore, in this example, the input of print data is monitored by a timer, and if there is no input even after a certain period of time, flash out (forcibly transfer and save the fractional data that cannot be DMA-transferred because 8 bytes are not aligned). Is performed to perform a quick DMA resetting process. The details will be described below.

FIG. 12 is a system diagram illustrating this example. The print data from the personal computer PC (corresponding to the host device 2 of the first embodiment) is sent to the printer device via the Centro interface 30. In this case, similar to the above, print data of 8 bits 1 byte
Data is transferred eight times by handshaking of the busy signal and acknowledge signal, and print data data of 8 bytes is received. The data reception DMA 31 buffers 8 bytes of print data and transfers the data to the memory 32.

Also in this example, the size of the system bus is 64.
The data is a bit, and the data temporarily buffered in the data reception DMA 31 is transferred to the memory by DMA transfer. Here, the timer 33 is the Centro interface 3
The print data supplied via 0 is monitored, and a counter (not shown) is started from 0. Then, when the counter reaches the specified value before the next strobe signal is input, it is determined that the received data has been separated, and the data reception DM
A flashout request is automatically issued to A31.

The specified value of the counter is a value preset by I / O access or the like. When the data reception DMA 31 finishes transferring the buffered print data to the memory 32 in accordance with the flash-out request, an interrupt is generated, the flash-out is automatically executed, and the system bus main control unit 34 is notified. .

When the system bus main control unit 34 detects this interrupt, it prepares for receiving the next print data.
The data reception DMA 31 is reset. By performing the processing as described above, it is possible to construct a system having an efficient flash-out function while minimizing the load on the software.

By the above processing, when the print data is not input for a certain period of time, the data reception DMA 31 is automatically stopped by the hardware and the flash-out is performed, so that the software can be configured simply and the load is reduced. Can be reduced and the processing speed can be improved.

In the above description, the data reception path from the outside is Centronics, but it may be a serial interface such as RS232C or a LAN board. The data is not limited to 8 bytes, and may be 16 bytes, 32 bytes, or the like. <Fourth Embodiment> Next, a fourth embodiment of the present invention will be described.

Conventionally, when two expansion boards are mounted and image data is received, the image data are individually operated and received. However, it takes time to receive the data, which causes a decrease in printing speed. So, in this example, the first board is connected to the upper bits, the second board is connected to the lower bits,
It is a configuration that enables simultaneous access.

FIG. 13 is a block diagram of the I / F controller of the printer apparatus of this example. In the figure, an expansion board 40 and an expansion board 41 are connected, and these are connected by a bus controller 43 and a local bus 42.
In addition, a flash ROM that stores the program
44, mask ROM 4 storing font data
5, an EEPROM 46 for storing printer settings, a hard disk (HDD) 47, and a video controller 48 are also connected. The expansion board 40 is connected to the lower [7: 0] of the 16-bit bus, and the expansion board 41 is connected to the upper [15: 8] of the 16-bit bus.

FIG. 14 shows a block diagram of the bus controller 43. 15 is a block diagram of the I / O controller 52 shown in FIG. The local bus is accessed when the memory controller 53 is accessed from the MPU 49, and the memory controller 53 outputs a request to the I / 0 controller 52 by setting the LREQ signal to "L".

At this time, control signals such as addresses and read / write signals are actually operating, but since they are not directly related, description thereof will be omitted. The expansion boards 40 and 41 output the request by setting the DREQ signal 1 and the DREQ signal 2 to "L". Bus arbiter 5 that received these request signals
5 performs arbitration processing and controls whether to accept the request.
Then, in response to the received request, the LACK signal or the DACK signal 1 and the DACK signal 2 are set to "L" to give the right to use the bus.

By controlling in this way, the expansion boards 40 and 41 can operate simultaneously. That is, when there are a plurality of expansion boards, data can be received at the same time, so that data can be transferred at a higher speed. <Fifth Embodiment> Next, a fifth embodiment of the present invention will be described.

In this example, print data can be transmitted / received without stopping the image data input request when the external bus is accessed. The details will be described below. Note that, also in this example, the drawings of FIGS. 13 to 14 described above are used, and the numbers of the respective circuits are as described above.

FIG. 16 is a flow chart for explaining the processing of this example. When transmitting / receiving the command from the MPU 17, first, / LREQ becomes "L" (timing shown in FIG. 16), and when the bus controller 43 determines that the expansion board 40 is accessible, / LACK is set to "L" ( At the timing shown in FIG. 16), the read signal and the write signal are output during this period. Therefore, the command data is transferred as shown in FIG.

Further, at this time, when the input signal (/ DREQ1) of the print data from the expansion board 40 becomes active at "L", the bus controller 43 controls not to activate / DACK1. Then, after the data processing from the MPU 17 is completed, the bus controller 43
DACK1 is set to "L" (timing shown in FIG. 16).

Similarly, for the data from the expansion board 41, the print data input signal (/
When DREQ2) becomes active at "L", the bus controller 43 adjusts data processing from other devices and sets / DACK2 to "L" (timing shown in FIG. 16).

As described above, according to this example, the bus controller 43 can efficiently process the access request from each device.

[0069]

As described above, according to the present invention,
DMA transfer can be continuously performed, and print data D
MA transfer can be performed at high speed. Further, it is possible to reliably detect the end point of the print data and prevent the DMA transfer of the print data which does not reach the predetermined number of bytes in the middle of the print data.

[Brief description of drawings]

FIG. 1A is a system configuration diagram of a printing system of the present invention, and FIG. 1B is a flowchart illustrating processing of a host device.

FIG. 2 prints the print data input to the reception control unit in a memory.
It is a system diagram at the time of MA transfer.

FIG. 3 is a specific circuit configuration diagram of a reception control unit.

FIG. 4 is a specific circuit configuration diagram of an ASIC.

FIG. 5 is a time chart illustrating the first embodiment.

FIG. 6 is a data format of print data.

FIG. 7 is a system diagram illustrating a second embodiment.

FIG. 8 is a time chart illustrating a second embodiment.

FIG. 9 is a time chart illustrating a modified example of the second embodiment.

FIG. 10 is a system diagram illustrating a configuration of an ASIC of a modified example of the second embodiment.

FIG. 11 is a time chart illustrating a process of a modified example of the second embodiment.

FIG. 12 is a system diagram illustrating a third embodiment.

FIG. 13 is a system diagram illustrating a fourth embodiment.

FIG. 14 is a diagram illustrating a configuration of a bus controller.

FIG. 15 is a diagram illustrating a configuration of a main controller.

FIG. 16 is a time chart illustrating a fifth embodiment.

FIG. 17 is a data format for explaining a conventional example.

[Explanation of symbols]

1 network 2 Host device 3 Printer 4 applications 5 Printer driver 6 spooler 7 port monitor 8 I / F controller 9 Engine part 10 Reception control unit 11 ROM 12 font storage 13 Display control unit 14 Video interface (I / F) 15 memory 15 16 ASIC 17 MPU 18 head controller 19 Motor control unit 20 High voltage controller 21 Fixing controller 22 Paper feed controller 23 Paper ejection control unit 31 Data reception DMA 32 memory 34 System Bus Main Control Unit 40, 41 expansion board 42 Local Bus 43 Bus controller 44 Flash ROM 45 mask ROM 46 EEPROM 47 Hard Disk (HDD) 49 MPU 55 Bus Arbiter

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shingo Uehara             2-229 Sakuragaoka, Higashiyamato-shi, Tokyo             Casio Computer Co., Ltd. Tokyo office (72) Inventor Satoshi Kataoka             2-229 Sakuragaoka, Higashiyamato-shi, Tokyo             Casio Computer Co., Ltd. Tokyo office F-term (reference) 2C061 AP01 AQ06 HH05 HK18 HK19                       HQ22                 2C187 AC07 AE07 BF05 BG17 BH05                       BH09 FD01 JA01                 5B021 AA01 BB00 CC05

Claims (5)

[Claims] 1. A printing system comprising: a host device that creates print data and outputs the print data; and a printing device that records the print data from the host device in a memory and prints the print data. Has an adding unit for adding dummy data when the print data does not end with a predetermined number of bytes, and the printing apparatus transfers the print data transmitted from the host device by DMA for each of the predetermined number of bytes. A printing system comprising means for recording print data transferred by DMA in the memory. 2. The printing system according to claim 1, wherein when the predetermined number of bytes is n bytes, the dummy data to be added is n-1 bytes of data. 3. The printing device comprises counting means for counting the number of bytes of the print data transmitted from the host device, and when the counting means confirms the input of the print data of the predetermined number of bytes, the print data is DMAed. The printing system according to claim 1, wherein the printing system transfers. 4. The printing device has a clocking means, and when the print data is not input to the printing device for a certain period of time, the clocking means detects a delay in inputting the print data and forcibly DMAs the print data. The printing system according to claim 1, 2, or 3, wherein the printing system transfers. 5. A discharge code is described at the end of the print data, and the transfer unit performs the DMA transfer only when the discharge code is detected.
The printing system described.