JP2003273947A - Direct conversion receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize amplitude difference between I and Q and to keep performance of reception characteristics stable by calculating a position of a demodulated symbol point after setting AGC (automatic gain control) by a control method equal to I, Q in a direct conversion receiver that uses a modulation/demodulation system of which the signal point allocation such as QPSK (quadri-phase shift keying) and π/4 shift QPSK is equal from an original point. <P>SOLUTION: The direct conversion receiver is basically constituted of a base band processing circuit, a band-pass filter, an RF amplifier, an AGC amplifier, a low-pass filter, an A/D converter and a D/A converter and the reception characteristics are stabilized by using level detection and a symbol position detector for AGC control and performing control so that I, Q amplitude becomes constant at a symbol point. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct conversion receiver incorporated in a base station, a vehicle-mounted station, or a mobile station that can be used in a wireless communication system, and a wireless communication system using the same, and more particularly to direct conversion reception. The present invention relates to a receiver having an AGC function for detecting a reception level and receiving at a constant level by using the H.264 system and the LOW-IF reception system, and a wireless communication system using the receiver.

[0002]

2. Description of the Related Art Due to the sophistication and complexity of wireless communication systems in recent years, there is a demand for hardware capable of supporting a plurality of wireless communication systems in one receiving device. Among them, the direct conversion receiving system has been attracting attention because of its effects of downsizing and cost reduction. Less than,
The configuration and operating principle of the direct conversion receiver will be described with reference to FIG.

In the figure, a received signal input from an antenna 1 is input to a bandpass filter 2 and passes a signal in a desired frequency band. The signal from which the interference wave has been removed is RF
It is input to the amplifier 3 and separated by the quadrature demodulator 5 into in-phase (I) and quadrature (Q) components. The quadrature demodulator 5 includes a distributor 4,
The mixers 6-1, 6-2 and the 90-degree phase shifter 8 are included.
The power input to the quadrature demodulator 5 is split into two by the splitter 4. One of the carrier wave signals input from the PLL frequency synthesizer 18 is input to the mixer 6-1 and the other is input to the mixer 6-2 via the 90-degree phase shifter 8. The in-phase component I signal and the quadrature component Q signal are obtained by mixing carrier signals having 90-degree different phases.

Unwanted components of the I and Q signals are removed by low-pass filters 9-1 and 9-2, respectively, and are input to AGC amplifiers 10-1 and 10-2. AGC amplifier 10-
1, 10-2 control so that the gain is small when the input signal level is high, and the gain is increased when the input signal level is low.
It operates so that the signal level input to 1-2 becomes an optimum level.

The signals converted into digital signals by the A / D converters 11-1 and 11-2 are processed by the baseband processing unit 1
At 5, processing such as code reproduction is performed. In the direct conversion method, since the input signal and the carrier frequency (LO) match, the LO leak signal becomes a DC component as it is due to mixing, which causes performance degradation in demodulation processing. Therefore, DC offset correction processing is required. In FIG. 2, the DC detection / correction unit 16 is operated from the I / Q input signal.
Is used to detect an offset, and a DC voltage that cancels this offset is applied to the D / A converter 12-
The DC offset is corrected by generating it in the Nos. 1 and 12-2 and adding it to the adders 7-1 and 7-2.

The AGC processing section 17 controls the AGC amplifiers 10-1 and 10-2 according to the level of the input signal. The control voltage is output so that a desired gain is obtained in accordance with the detected reception level, and the AGC amplifiers 10-1, 1
The gain of 0-2 is adjusted to control the input level to be constant. The above control makes it possible to prevent the deterioration of the reception characteristics.

[0007]

Generally, AGC operation only in the RF band requires high gain in the base band. Therefore, noise in the baseband band is also amplified. Therefore, when the reception input level can be sufficiently secured, it is necessary to operate the gain in the baseband as low as possible.

Therefore, when the I / Q separation is performed as in the conventional direct conversion receiver, separate AGC amplifiers are required, so that amplitude deviation easily occurs between the I and Q. If an amplitude deviation between I and Q occurs, there is a problem that the reception characteristics are significantly deteriorated (bit error rate increases).

[0009]

In order to solve the above problems, the present invention detects the symbol positions of I and Q demodulated signals and corrects only I (or Q) so that they become constant. To prevent the deterioration of the reception characteristics due to the amplitude deviation between I and Q,
An object of the present invention is to provide a direct conversion receiver that can be operated stably.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a direct conversion receiver according to the present invention. In the figure, a received signal input from an antenna 1 is input to a bandpass filter 2 and passes a signal in a desired frequency band. The signal from which the interference wave has been removed is input to the RF amplifier 3 and separated by the quadrature demodulator 5 into in-phase (I) and quadrature (Q) components. The quadrature demodulator 5 includes a distributor 4, a mixer 6-1,
6-2 and 90 degree phase shifter 8. The power input to the quadrature demodulator 5 is split into two by the splitter 4. One of the carrier wave signals input from the PLL frequency synthesizer 18 is input to the mixer 6-1 and the other is input to the mixer 6-2 via the 90-degree phase shifter 8. The in-phase component I signal and the quadrature component Q signal are obtained by mixing carrier signals having 90-degree different phases.

Unwanted components of the I / Q signals are removed by the low-pass filters 9-1 and 9-2, respectively, and the AGC amplifier 1
It is input to 0-1 and 10-2. AGC amplifier 10-
1 and 10-2 operate so as to reduce the gain when the input signal level is high, and increase the gain when the input signal level is low.
The dynamic range can be secured by controlling the signal level input to 1-2 to the optimum level. The signals converted into digital signals by the A / D converters 11-1 and 11-2 are subjected to processing such as code reproduction in the baseband processing unit 15. For the DC offset correction processing, the DC detection correction unit 16 detects an offset from the I and Q input signals, controls the D / A converters 12-1 and 12-2 to generate a voltage, and cancels the offset voltage.

Next, the AGC operation will be described with reference to FIGS. FIG. 3 (1) shows a symbol point arrangement when a QPSK signal is demodulated. In FIG. 3, when there is no gain difference between the demodulated I and Q signals, as in (1),
Symbol points of I and Q are arranged on a concentric circle at equal intervals. However, when there is a gain difference between I and Q, as shown in (2), there is a difference between the amplitudes of I and Q, resulting in an ellipse. Therefore, a correction function for correcting this gain difference is required.

Further, the AGC method which operates in response to input level fluctuation will be briefly described. FIG. 4 shows a delay detection circuit and an AGC processing unit 17, which are a part of the baseband processing circuit shown in the digital processing unit 14 shown in FIG.
The I / Q baseband signals input to the A / D 11-1 and A / D 11-2 in FIG. 1 are regenerated as symbol clocks by the timing extraction circuit 21 shown in FIG. Using this clock, the symbol sampling circuit 20-1,
In 20-2, data is sampled for each symbol point and input to the differential detection circuit 22. Delay detection circuit 22
The signal is detected by.

The differential detection circuit 22 includes delay devices 23-1, 2-3.
3-2, 23-3, multipliers 24-1, 24-2, 24-
3, 24-4 and adders 25-1, 25-2,
The differentially encoded signal is decoded from the current symbol and the signal one symbol before. After that, the data is reproduced by the polarity judgment or the like. In addition, A / D11-1, A / D11-2
The I and Q baseband signals input to the are input to the level detection and AGC control circuit unit 27 to detect the reception level. The D / A 19 is controlled according to the detected reception level to change the AGC voltage so that the reception level becomes constant.

Next, the AG according to the present invention when the I and Q deviations occur
The C operation will be described. For each symbol, part of the sampled signal is input to the symbol point detector 26. Here, the position of the symbol point is calculated and compared with the previously calculated expected value, and if different, the gain is varied only on the Q side so as to be a constant value (or only on the I side). In this embodiment, the gain deviation is corrected by multiplying the Q signal input to the multiplier 29 by a constant. In modulation schemes such as QPSK and π / 4 shift QPSK, since there is no symbol having the same phase angle, the I and Q deviations can be easily detected by detecting the phase angle at the symbol point.

FIG. 3 shows an example of QPSK modulation. Figure 3
When there is no gain difference between I and Q as in (1), each symbol point has a distance √2 of 45 degrees, 135 degrees, 225 degrees, and 315 degrees.
It can be seen that it takes a phase angle of degrees. However, Q is now √3
If a double amplitude error occurs, the symbol point arrangement is as shown in FIG. When only looking at the distance of the symbols, each symbol (a, b, c, d) is equal at the distance "2", but when looking at the phase angle, it becomes 60 degrees for the symbol a.
It can be seen that the deviation from the expected value. Therefore, the amplitude error can be corrected by fixing I and multiplying the Q side by (1 / √3). In the symbol point detector 26, from the demodulated I and Q signals x2 and y2, the phase angle φ (ATAN (y
2 / x2)) is calculated to calculate the deviation of the symbol position from the expected values of 45 degrees, 135 degrees, 225 degrees, and 315 degrees.

If the absolute values of the I and Q amplitude values are the same as in QPSK, the gain difference can be calculated by comparing | x2 | and | y2 |. As described above, in the modulation method in which the symbol points are arranged on the concentric circles, the amplitude deviation between I and Q can be detected by calculating the phase angle.

Further, the location of the correction need not be limited to the digital processing section, but may be the analog section (before being input to the D / A).

[0019]

According to the present invention, even if an amplitude difference between the demodulated I and Q signals occurs, the phase angle at the symbol point is controlled to be maintained at a predetermined value, so that the I and Q amplitude error is suppressed. It can be minimized, and the reception characteristics of the direct conversion receiver can be stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional receiver.

FIG. 3 is a symbol position of QPSK (with / without I / Q deviation).

FIG. 4 is a block diagram of a digital processing unit showing an essential part of the present invention.

[Explanation of symbols]

1: antenna, 2: band pass filter (BPF),
3: RF amplifier, 4: distributor, 5: quadrature demodulator, 6-
1, 6-2: mixer, 7-1, 7-2: adder, 8: 9
0 degree phase shifter, 9-1, 9-2: low-pass filter (LP
F), 10-1, 10-2: AGC, 11-1, 11-
2: A / D converter, 12-1, 12-2, 13-
1, 13-2, 19: D / A converter, 14: digital processing unit, 15: baseband processing unit, 16: DC detection and correction unit, 17: AGC processing unit, 18: PLL frequency synthesizer, 20-1, 20-2: Symbol sampling circuit, 21: Timing extraction circuit, 22: Delay detection circuit, 23-1, 23-2, 23-3: Delay element, 24
-1, 24-2, 24-3, 24-4: Multiplier, 25-
1, 25-2: adder, 26: symbol position detector, 2
7: level detection and AGC controller, 28: AGC controller, 29: multiplier.

Claims (4)

[Claims] 1. An analog signal processing section for band limiting, amplifying, and frequency converting a received radio frequency signal, and an A / D for converting an output signal of the analog signal processing section into a digital signal.
In a direct conversion receiver having a conversion unit and a digital signal processing unit for processing the digital signal, AGC means for controlling the input level of the analog unit so as to keep it constant, the I component and the Q component being simultaneously A direct conversion receiver comprising an AGC means for operating and an AGC means for operating either one of the I component and the Q component, and configured to reduce the level deviation between the I component and the Q component. . 2. The direct conversion receiver according to claim 1, wherein the AGC means samples the received signal for each symbol point, calculates the position of the symbol point, and compares the symbol point with a specified value. A to control to be the same
A direct conversion receiver characterized by being a GC means. 3. The direct conversion receiver according to claim 2, wherein a modulation method in which symbol points are arranged on concentric circles,
A direct conversion receiver comprising an AGC means for obtaining an amplitude deviation from the ratio of the I component and the Q component, and operating either one of the I component and the Q component so that the ratio becomes the same. 4. The direct conversion receiver according to claim 2, wherein a modulation method in which symbol points are arranged on concentric circles,
A direct conversion receiver characterized by including an AGC means for calculating a phase angle from the I component and the Q component and operating either one of the I component and the Q component so that the phase angle becomes a correct phase angle. .