JP2003259626A - Boosting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a boosting circuit which can perform boosting motion even when a power voltage approximates to a threshold. <P>SOLUTION: This boosting circuit is equipped with a capacitor CP1 for amplifying a voltage, and p-channel transistors PT1 and PT2 for charge transfer. Then, the voltage over the power voltage VCC is applied to gates of the p- channel transistors PT1 and PT2. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit, and more particularly to a booster circuit including a charge transfer transistor.

[0002]

2. Description of the Related Art Conventionally, a booster circuit for boosting a power supply voltage to a voltage higher than the power supply voltage has been known. FIG. 10 is a schematic diagram for explaining the concept of a conventional general booster circuit, and FIG. 11 is a schematic diagram for explaining the circuit configuration of a conventional booster circuit corresponding to FIG. First, referring to FIG. 10, the conventional booster circuit includes diode portions 101 and 102 and a capacitor 103. The reason why the diode portions 101 and 102 are provided in this way is as follows. That is, when the node VB is boosted by the capacitor 103, the node VB is
It will be the above level. At this time, it is necessary to prevent current from flowing backward from the node VB to the power supply voltage terminal (VCC). Further, since a current flows from the node VB to the output terminal Vout, a high voltage level needs to be transmitted to the output terminal Vout. In addition, the capacitor 103
When the signal Vboot for booting the node becomes L level, the node VB becomes lower than the output terminal Vout. In this case, from the output terminal Vout to the node VB
It is necessary to prevent current from flowing backward. In this way, the current flows only from left to right, so that the output terminal Vout is boosted. For this reason, the diode units 101 and 1 having the function of a valve for controlling the current are provided.
02 is required.

As the operation of the conventional booster circuit shown in FIG. 10, when the boot signal Vboot is at the L level, the power supply voltage terminal VCC is supplied to the node VB via the diode portion 101. As a result, the node VB is charged to VCC. Further, when the boot signal Vboot is at the H level, the node VB is connected to the VC by the capacitor 103.
The voltage is boosted above C and the boosted level is transmitted to the output terminal Vout via the diode 102.

Further, the diode portion 101 shown in FIG.
Normally, n-channel transistors 151 and 152 as shown in FIG. 11 are used for and 102, respectively. The n-channel transistors 151 and 152
Has a source follower type MOS diode configuration in which the drain and the gate are short-circuited. As the capacitor 103, a MOS capacitor 153 in which the source and drain of the N-channel transistor are short-circuited is used.

[0005]

In the conventional booster circuit shown in FIG. 11, n-channel transistors 151 and 1 are used.
Since 52 has a configuration in which the drain and the gate are short-circuited, V is transmitted when the potential is transmitted from the drain to the source.
A voltage drop of t (threshold voltage) occurs. Therefore, in the conventional booster circuit, the n-channel transistor 15
The disadvantage arises that only levels lower by Vt of 1 and 152 can be transmitted. This inconvenience is V
When CC (power supply voltage) is sufficiently higher than Vt (threshold voltage), it does not matter so much.

However, when the power supply voltage (VCC) is close to the threshold voltage (Vt), there is a problem that the boosting operation cannot be performed. For example, VCC = 1.2V, Vt = 0.
The case of 7V will be described. The initial value of the node VB is
1.2V-0.7V = 0.5V. At 0.5V,
Since it is Vt or less, the n-channel transistor forming the capacitor 153 does not turn on. Therefore, the capacitor 153 cannot operate, and the boost operation cannot be performed. As described above, the conventional booster circuit has a problem that the boosting operation cannot be performed with a low power supply voltage (low VCC).

Incidentally, n of the conventional booster circuit shown in FIG.
It is also conceivable that the channel transistors 151 and 152 are p-channel transistors. However,
In order to form the p-channel transistor into a diode structure, it is necessary to short the gate and drain of the p-channel transistor. Therefore, in this case as well, there is a problem that a voltage drop occurs by the threshold voltage of the p-channel transistor. . Further, since the N well which is the substrate of the p-channel transistor and the p-type source / drain region have a PN junction, there is also a problem that a forward current flows from the p-type source / drain region to the substrate (N well). is there.

The present invention has been made to solve the above problems, and one object of the present invention is to:
It is an object of the present invention to provide a booster circuit capable of performing boosting operation even with a low power supply voltage.

Another object of the present invention is to prevent a forward current to the substrate which occurs when a p-channel transistor is used as a charge transfer transistor in the above booster circuit.

[0010]

In order to achieve the above object, a booster circuit according to a first aspect of the present invention includes a first capacitor for amplifying a voltage and a charge transfer transistor, and a gate of the charge transfer transistor. Is applied with a voltage equal to or higher than the power supply voltage.

According to the first aspect of the present invention, as described above, by applying a voltage equal to or higher than the power supply voltage to the gate of the charge transfer transistor, the voltage drop corresponding to the threshold voltage of the charge transfer transistor (threshold drop). Can be avoided. As a result, the voltage can be transmitted without the threshold voltage dropping, so that the boosting operation can be performed even when the power supply voltage is close to the threshold voltage.

A booster circuit according to a second aspect of the present invention is the booster circuit according to the first aspect, wherein the charge transfer transistor includes a p-channel transistor, and an output node is connected to the substrate potential of the p-channel transistor. With this configuration, the substrate of the p-channel transistor (n-type well)
Is higher than the p-type source / drain of the p-channel transistor, it is possible to prevent a forward current from flowing from the p-type source / drain of the p-channel transistor to the substrate (n-type well) of the p-channel transistor. it can.

According to a third aspect of the present invention, in the booster circuit according to the first or second aspect, the charge transfer transistor includes a first p-channel transistor having one terminal connected to a first node supplied with a power supply voltage, and a second p-channel transistor. A third p-channel transistor including a channel transistor, one terminal connected to a power supply voltage and the other terminal connected to the first node, the third p-channel transistor having a timing other than when the first capacitor is in an ON state By turning on, the power supply voltage is supplied to the first node. According to this structure, since the power supply voltage can be supplied to the first node at a timing other than the boosting operation, it is possible to prevent the boosted potential from flowing back to the power supply voltage side.

According to a fourth aspect of the present invention, in the boosting circuit according to the third aspect, the second capacitor is connected to the first node. According to this structure, the load capacitance of the first node increases, so that the fluctuation of the power supply potential of the first node can be suppressed.

A booster circuit according to a fifth aspect of the present invention is the structure of the third or fourth aspect, further comprising a fourth p-channel transistor having one terminal connected to the first node and the other terminal connected to the gate of the second p-channel transistor. . With this configuration, the power supply potential of the first node is
It can be supplied to the gate of the second p-channel transistor via the fourth p-channel transistor.

A booster circuit according to a sixth aspect of the present invention is the booster circuit according to the fifth aspect, further comprising a third capacitor connected to the gate of the second p-channel transistor for increasing the gate voltage of the second p-channel transistor. Is connected to the gate of the fourth p-channel transistor. With this configuration,
When the signal for booting the third capacitor is at the L level, the fourth p-channel transistor is turned on, so that the power supply potential is supplied from the first node to the gate of the second p-channel transistor. When the signal for booting the third capacitor is at the H level, the fourth p-channel transistor is turned off, and the third capacitor supplies a voltage equal to or higher than the power supply potential to the gate of the second p-channel transistor. Thus, the second p-channel transistor can be turned on by applying the power supply potential to the gate of the second p-channel transistor, and the second p-channel transistor can be applied with a voltage equal to or higher than the power supply potential. The channel transistor can be turned off.

According to a seventh aspect of the present invention, in the boosting circuit of the sixth aspect, the signal for booting the third capacitor becomes L level only during the H level period of the signal for booting the first capacitor. According to this structure, since the power supply potential is supplied from the first node to the gate of the second p-channel transistor during the period when the first capacitor is performing the boosting operation, the first capacitor is performing the boosting operation. The second p-channel transistor can be turned on only during the period when it is present. This can prevent the boosted potential supplied to the output terminal via the second p-channel transistor from flowing back to the boosted node side.

The booster circuit according to the eighth aspect of the present invention is the third aspect of the present invention.
In any one of the configurations 7 to 7, a fourth capacitor for boosting the gate voltage of the first p-channel transistor is further connected to the gate of the first p-channel transistor, and the first capacitor and the fourth capacitor are booted at the same time. . According to this structure, since the gate potential of the first p-channel transistor and the potential of the boosting node are the same voltage, it is possible to prevent the boosted potential from flowing back through the first p-channel transistor.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic diagram showing the structure of a booster circuit according to a first embodiment of the present invention. First, the configuration of the booster circuit 1 according to the first embodiment will be described with reference to FIG. First, the booster circuit 1 according to the first embodiment is a circuit for boosting VCC to 2VCC. In the booster circuit 1 of the first embodiment, the p-channel transistor PT1 and the p-channel transistor PT2 are used as the charge transfer transistors. One terminal of the p-channel transistor PT1 is connected to the node VP which is a virtual VCC (power supply voltage), and the other terminal is connected to the boost node VB. One terminal of the p-channel transistor PT2 is connected to the boost node VB,
The other terminal is connected to the output terminal Vout. The booster node VB has a capacitor CP1 having a configuration in which the source and drain of the n-channel transistor are short-circuited.
The gate of is connected.

The p-channel transistor PT1 and the p-channel transistor PT2 are examples of the "first p-channel transistor" and the "second p-channel transistor" in the present invention, respectively. Also, the capacitor C
P1 is an example of the "first capacitor" in the present invention.

The node VP has a structure in which the source and drain of the n-channel transistor are short-circuited, and a capacitor CP2 for increasing the additional capacitance of the node VP is connected. In addition, by connecting the capacitor CP2 to the node VP,
The fluctuation of the voltage level of P can be suppressed to a small level. As a result, power supply fluctuation (noise) can be suppressed. Further, the node VP has the power supply voltage VC at the node VP.
A p-channel transistor PT3 for supplying C is connected. A p-channel transistor PT5 is connected between the node VP and the node VL.
The node VL has an n-channel transistor NT1.
One terminal is connected. The other terminal of the n-channel transistor NT1 is grounded. Also, node V
The gate of a capacitor CP4 having a configuration in which the source and the drain of the n-channel transistor are short-circuited is connected to L.

A p-channel transistor PT4 is connected between the node VP and the node VG.
The gate of the capacitor CP3 is connected to the node VG. Signal Vd for booting capacitor CP3
Are supplied to the gate of the p-channel transistor PT4. The p-channel transistor PT3 and the p-channel transistor PT4 are respectively referred to as the “third-part transistor” of the present invention.
2 is an example of a “p-channel transistor” and a “fourth p-channel transistor”. In addition, capacitors CP2 and C
P3 and CP4 are the "second capacitor", "third capacitor" and "fourth capacitor" of the present invention, respectively.
Is an example.

Although not shown in FIG. 1, the substrates (N wells) of the p-channel transistors PT1, PT2, PT3 and PT4 are all output potential Vout (2VC).
Connected to C). Therefore, it is possible to prevent a forward current from flowing from the p-type source / drain regions of the p-channel transistors PT1 to PT4 toward the substrate (N well).

Further, boost node VB and node VL are simultaneously booted by capacitors CP1 and CP4, respectively, so that the boost level is prevented from flowing backward to node VP. In this case, the node Vb is 0
Since the node operates between V and VCC, the node V
Even if b is VCC, if the node VL becomes VCC + Vt or more, current flows backward from the node VL to the node VP. Further, the boosted node VB also starts to flow back to the node VP side when VCC + 2Vt or higher. However, for example, V
If CC = 1.2V and Vt = 0.7V, the node VB
Is not backflowed to 2.6V, it is understood that no problem occurs up to the boosted potential of 2VCC (2.4V). In addition, p-channel transistors PT1 to PT4
The N-well, which is the substrate of, is all output potential Vout (2
VCC), the threshold voltage Vt of the p-channel transistors PT1 to PT4 increases due to the substrate bias effect. Therefore, backflow in the p-channel transistors PT1 to PT4 can be further prevented.

A p-channel transistor PT for transmitting the level of the boosting node VB to the output terminal Vout.
The second gate, node VG, operates between VCC and a voltage above VCC. When node VG is at VCC, the level of boosted node VB is transmitted to output node Vout. This is because even if the gate of the p-channel transistor PT2 is VCC, if the source of the p-channel transistor PT2 is Vcc + Vt or higher, the p-channel transistor PT2 is turned on. In addition, the boosting node VB is generated by the fall of the boot signal Vboot.
When it becomes VCC, it is necessary to prevent the boosted level transferred to the output node Vout from flowing back to the boosted node VB. For this purpose, the p-channel transistor PT
The p-channel transistor PT2 is turned off by boosting the node VG, which is the gate of the second gate, to VCC or higher.

FIG. 2 is a waveform diagram of the input signal of the booster circuit according to the first embodiment shown in FIG. The operation of the booster circuit 1 according to the first embodiment in accordance with the clock signal will be described with reference to FIGS. 1 and 2.

First, in the initial state, since nodes Va, Vb and Vc are at the L level, p-channel transistors PT3 and PT5 are on and n-channel transistor NT1 is off. Therefore, the nodes VP and VL are connected to the power supply voltage (VC
It is precharged to C). From the previous cycle, the boost node VB is in the floating state at VCC, and the node VG is in the floating state at VCC or higher. From this state, the node Va and the node Vb change to the H level, whereby the p-channel transistor PT
Since 3 and PT5 are turned off, nodes VP and VL are also in a floating state of VCC.

After that, the boot signal Vboot is set to the H level, so that the nodes VB and VL are boosted to VCC or higher by the capacitors CP1 and CP4. At this time, the node VL is VC
Since it is C or higher, the boosted level of the boosted node VB does not flow back to the node VP. The electric charge of the booted node VL slightly flows back to the node VP. Even if the charge of the node VL slightly flows back to the node VP in this way, the node VP does not exceed VCC + Vt.
No backflow to VCC occurs. In this state, p
The node VG which is the gate of the channel transistor PT2
Is higher than VCC, the p-channel transistor PT
2 is in the off state. Therefore, in this state, the boosting level of boosting node V is not transferred to output node Vout.

After that, the node Vd becomes L level, and the p-channel transistor PT4 is turned on. As a result, the node VP and the node VG are connected to each other, so that the potential of the node VG becomes VCC. In this case p
Since the source of the channel transistor PT2 is VCC or higher, the gate of the p-channel transistor PT2 is VC
Even if it is C, the p-channel transistor PT2 is turned on. As a result, the boosted boosted node V
The B level is transferred to the output node Vout. After that, when the node Vd becomes H level, the p-channel transistor PT4 is turned off, and the node VG is booted to become VCC or more. As a result, the p-channel transistor PT2 is turned off.
At this time, the charges of the node VG slightly flow back to the node VP, but there is no problem.

After the p-channel transistor PT2 is turned off, the boot signal Vboot becomes L level.
As a result, the boost node VB becomes a voltage near VCC. In this case, since the p-channel transistor PT2 is in the off state, the output node Vout is not pulled and its level is not lowered. After that, the node Vc becomes H level, so that the n-channel transistor NT1
Is turned on, the node VL becomes L level.
As a result, the p-channel transistor PT1 is turned on, and the power supply potential VCC is supplied to the boost node VB.

Next, the node Va is set to the L level to turn on the p-channel transistor PT3. As a result, the voltage dropped from VCC of the node VP is returned to VCC. There is no problem even if the fall timing of the node Va is slightly delayed. After that, by lowering the node Vc, the n-channel transistor NT
After turning 1 off, the node Vb is lowered to turn on the p-channel transistor PT5. As a result, the node VL becomes VCC, and the p-channel transistor PT1 is turned off. As a result, the boosting node VB becomes floating and stands by for the boot signal.

FIG. 3 is a schematic diagram showing a simulation circuit including the booster circuit of the first embodiment shown in FIG. In the simulation circuit according to the first embodiment, a ring oscillator unit 2, an input signal control circuit unit 3 and a bias circuit unit 4 are added to the booster circuit unit 1 according to the first embodiment. Here, when the booster circuit unit 1 of the first embodiment is operated at VCC = 1.2V to 1.8V, the frequency changes by one digit or more in a normal ring oscillator. This is for the following reason. That is, when the VCC is 1.2V, the operation is in the sub-threshold region, whereas when the VCC is 1.8V, the operation range is in the normal range, and the driving capability of the transistor is greatly different. is there. In this case, when VCC is 1.8V, the current consumption becomes very large. For this reason,
In the simulation circuit shown in FIG. 3, the inverter circuit 2a or the NAND circuit 2b of the ring oscillator unit 2 is used.
Without directly connecting the p-channel transistor of
It is configured to be connected to VCC through the p-channel transistor 2c or 2d biased by the bias circuit unit 4.

The bias circuit section 4 is configured to output a low voltage when the VCC is low and a high voltage when the VCC is high. As a result, the p-channel transistors 2c and 2d biased by the bias circuit unit 4 are always operated in the subthreshold region, so that frequency characteristics independent of VCC are obtained.

Further, since the waveform shown in FIG. 2 is generated by utilizing the inverter delay in the ring oscillator section 2, not only the size of the inverter but also the odd-numbered stages are connected to the NAND circuit 2a.
I have to. As a result, the setting (H level) is applied all at once. As a result, the L level period can be shortened.

Further, in the simulation circuit shown in FIG. 3, the inverter for driving the capacitor CP1 for booting the boosting node VB of the booster circuit unit 1 has a very large transistor size, which is different from a normal inverter. , The input signals to the p-channel transistor 3a and the n-channel transistor 3b are separately generated by the input signal control circuit unit 3. Thereby, the simultaneous ON state of the p-channel transistor 3a and the n-channel transistor 3b in the transient state at the time of input can be eliminated. As a result, low power consumption and steep output waveform can be achieved. When the simulation was performed using VCC = 1.2V using the simulation circuit shown in FIG. 3, it was confirmed that the voltage was boosted to 2.4V (2VCC). As a result, there is no threshold voltage drop and V
It was confirmed that CC can be boosted to 2 VCC.

(Second Embodiment) FIG. 4 is a schematic diagram showing the structure of a booster circuit according to a second embodiment of the present invention. FIG. 5 is a schematic diagram showing the internal configuration of the gate boot circuit of the booster circuit of the second embodiment shown in FIG.

First, the booster circuit according to the second embodiment will be described with reference to FIGS. 4 and 5. In the booster circuit 11 according to the second embodiment, the p-channel transistor PT1 and the p-channel transistor PT2 are used as the charge transfer transistors. One terminal of the p-channel transistor PT1 is connected to the power supply voltage terminal VCC, and the other terminal is connected to the boost node C. One terminal of the p-channel transistor PT2 is connected to the boost node C, and the other terminal is connected to the output node V.
It is connected to OUT. The N well (not shown) that is the substrate of the p channel transistors PT1 and PT2 is connected to the output node VOUT (2VCC). The gate of the capacitor CP1 is connected to the boost node C. p-channel transistor PT1
To the gate A of the p-channel transistor PT2 is connected to the gate boot circuit 11a.
The gate boot circuit 11b is connected.

The gate boot circuits 11a and 11b are
It is a circuit that outputs an input clock of amplitude VCC as amplitude 2VCC. The gate boot circuits 11a and 11
b is the inverters 111 and 11 as shown in FIG.
2, capacitor 113, and p-channel transistor 1
14 and 115 and n-channel transistors 116 and 117.

The booster circuit 11 according to the second embodiment shown in FIGS. 4 and 5 is a circuit for boosting VCC to 2 VCC. P-channel transistor P forming a diode
The gate voltages of T1 and PT2 are independently controlled by the gate boot circuits 11a and 11b, respectively. Therefore, the p-channel transistor PT1 and the p-channel transistor PT2 have a threshold voltage (V
The potential can be transmitted without a voltage drop of t). Further, since 2VCC is applied to the gates A and B of the p-channel transistors PT1 and PT2, respectively, the p-channel transistors PT1 and PT2
2 can be cut off to 2 VCC when off. In addition, p-channel transistors PT1 and P
Since the substrate potential of T2 is set to VOUT (2VCC), the substrate (N well) potentials of the p-channel transistors PT1 and PT2 are higher than the potential of the p-type source / drain regions. Therefore, it is possible to prevent a forward current from flowing from the p-type source / drain regions of p-channel transistors PT1 and PT2 to the substrate (N well).

FIG. 6 is a waveform diagram showing an input signal of the booster circuit according to the second embodiment shown in FIG. 4 to 6
Next, the operation of the booster circuit 11 according to the second embodiment will be described with reference to FIG.

First, when the clock C is at L level,
The clock A sequentially changes to H level, L level, and H level. As a result, the gate A of the p-channel transistor PT1 sequentially changes to 2VCC, 0V and 2VCC. When the clock A is at the L level, the p-channel transistor PT1 is turned on, so that the boosting node C is charged to VCC. On the other hand, when the clock C is at the L level, the clock B is at the H level,
The gate B of the p-channel transistor PT2 is 2VCC
become. As a result, the p-channel transistor PT2 is turned off, and there is no backflow of current from the output node VOUT, and the potential of the output node VOUT does not drop.

When the clock C is at H level,
The boosting node C is boosted to 2VCC by the capacitor CP1. At this time, since the clock A is at the H level before and after the clock C is at the H level, the gate A of the p-channel transistor PT1 is at 2VCC.
Therefore, the p-channel transistor PT1 is turned off, so that no current flows backward from the node C to VCC. On the other hand, when the clock C is at the H level, the clock B is at the L level, so the p-channel transistor P
The gate B of T2 is at 0V. For this reason, the p-channel transistor PT2 is turned on, and the boosted potential of the node C is efficiently output to the output node VOUT without a threshold drop.

In the second embodiment, as described above, the p-channel transistor PT as the charge transfer transistor is used.
By independently controlling the gates A and B of 1 and PT2 by the gate boot circuits 11a and 11b, it is possible to prevent the threshold voltage of the p-channel transistors PT1 and PT2 from dropping. As a result, the boosting operation can be performed even when the power supply voltage VCC is close to the threshold voltage Vt.

FIG. 7 is a schematic diagram showing a simulation circuit including the booster circuit according to the second embodiment shown in FIG. Referring to FIG. 7, in the simulation circuit according to the second embodiment, the booster circuit unit 1 according to the second embodiment is used.
1, a ring oscillator unit 12 and an input signal control circuit unit 13 are added. In this case, the ring oscillator unit 12 has an output frequency of 50 MHz at VCC = 1.2V.
Has been optimized to be. Using the simulation circuit according to the second embodiment shown in FIG. 7, VCC = 1.
When the simulation was performed at 2 V, it was 0.55
It was found that the voltage was boosted to 2.4 V in about μsec. As a result, it was confirmed that the booster circuit unit 11 according to the second embodiment can boost VCC to 2VCC without a threshold voltage drop.

(Third Embodiment) FIG. 8 is a schematic diagram showing the structure of a booster circuit according to a third embodiment of the present invention. Referring to FIG. 8, in the booster circuit 21 according to the third embodiment, unlike the above-described second embodiment, n-channel transistors NT1 and N1 are used as charge transfer transistors.
T2 is used. The gate boot circuit 11a is connected to the gate A of the n-channel transistor NT1, and the gate boot circuit 11b is connected to the gate B of the n-channel transistor NT2. Boost node C
Is connected to the gate of the capacitor CP1. The substrates of the n-channel transistors NT1 and NT2 are grounded.

The booster circuit 2 according to the third embodiment
The configurations of the first gate boot circuits 11a and 11b and the capacitor CP1 are the same as those of the booster circuit 11 according to the second embodiment shown in FIG. The booster circuit 21 according to the third embodiment has the same VCC as the second embodiment.
Is a circuit that boosts the voltage to 2 VCC.

2VCC is applied to the gates of the n-channel transistors NT1 and NT2 of the booster circuit 21 according to the third embodiment via the gate boot circuits 11a and 11b, respectively. This causes the threshold voltage (Vt) of the n-channel transistors NT1 and NT2.
The potential can be transmitted without a minute voltage drop. As a result, the boosting operation can be performed even when the power supply voltage VCC is close to the threshold voltage Vt.

FIG. 9 is a waveform diagram of the input signal of the booster circuit according to the third embodiment shown in FIG. The operation of the booster circuit 21 according to the third embodiment will be described with reference to FIGS. 8 and 9. First, when the clock C is at L level, the clock A sequentially changes to L level, H level, and L level. As a result, the gate A becomes 0V, 2VC
It changes to C and 0V sequentially. Since the n-channel transistor NT1 is turned on when the clock A is at the H level, the node C is charged with VCC. On the other hand, when the clock C is at the L level, the clock B is at the L level, so the gate B of the n-channel transistor NT2 is
Is 0V. Therefore, the n-channel transistor NT
Since 2 is in the off state, there is no reverse current flow from the output node VOUT to the node C. As a result, the output node VO
The UT potential does not drop.

When the clock C is at H level,
The node C is boosted to 2VCC by the capacitor CP1. At this time, the clock A is at the L level before and after the clock C is at the H level. As a result, the gate A of the n-channel transistor NT1 becomes 0V, and the n-channel transistor NT1 is turned off.
As a result, there is no reverse current flow from node C to VCC.
On the other hand, when the clock C is at the H level, the clock B is at the H level, so the n-channel transistor NT
The gate B of 2 becomes 2VCC. As a result, the n-channel transistor NT2 is turned on, so that the node C
The boosted potential of is transmitted to VOUT without a drop in threshold voltage.

It should be understood that the embodiments disclosed this time are exemplifications in all respects and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes meanings equivalent to the scope of claims for patent and all modifications within the scope.

For example, in the above second and third embodiments, the circuit having the internal structure shown in FIG. 5 is shown as the gate boot circuit, but the present invention is not limited to this, and the amplitude VC
The circuit may have another internal configuration as long as it is a circuit that outputs the C input clock as an amplitude of 2 VCC.

[0053]

As described above, according to the present invention, it is possible to provide a booster circuit capable of performing a boosting operation even when the power supply voltage is close to the threshold voltage.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of an input signal of the booster circuit according to the first embodiment shown in FIG.

3 is a schematic diagram showing a simulation circuit including the booster circuit of the first embodiment shown in FIG. 1. FIG.

FIG. 4 is a schematic diagram showing the configuration of a booster circuit according to a second embodiment of the present invention.

5 is a schematic diagram showing an internal configuration of a gate boot circuit of the booster circuit according to the second embodiment shown in FIG. 4. FIG.

6 is a waveform diagram of an input signal of the booster circuit according to the second embodiment shown in FIG.

7 is a schematic diagram showing a simulation circuit including a booster circuit according to the second embodiment shown in FIG.

FIG. 8 is a schematic diagram showing the configuration of a booster circuit according to a third embodiment of the present invention.

9 is a waveform diagram of an input signal of the booster circuit according to the third embodiment shown in FIG.

FIG. 10 is a schematic diagram for explaining the concept of a conventional general booster circuit.

11 is a schematic diagram for explaining a circuit configuration of a conventional booster circuit corresponding to FIG.

[Explanation of symbols]

PT1 p-channel transistor (first p-channel transistor) PT2 p-channel transistor (second p-channel transistor) PT3 p-channel transistor (third p-channel transistor) PT4 p-channel transistor (fourth p-channel transistor) CP1 capacitor (first capacitor) CP2 capacitor ( Second capacitor) CP3 capacitor (third capacitor) CP4 capacitor (fourth capacitor) 1, 11, 21 Booster circuits 11a, 11b Gate boot circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Takano             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F term (reference) 5H730 AS04 BB02 BB08 DD04 DD12                       DD13

Claims (8)

[Claims] 1. A booster circuit comprising: a first capacitor for amplifying a voltage; and a charge transfer transistor, wherein a voltage higher than a power supply voltage is applied to the gate of the charge transfer transistor. 2. The booster circuit according to claim 1, wherein the charge transfer transistor includes a p-channel transistor, and an output node is connected to a substrate potential of the p-channel transistor. 3. The charge transfer transistor includes a first p-channel transistor whose one terminal is connected to a first node to which a power supply voltage is supplied, and a second p-channel transistor, one terminal of which is connected to the power supply voltage. And a third p-channel transistor having the other terminal connected to the first node, wherein the third p-channel transistor is turned on at a timing other than when the first capacitor is turned on, whereby the first p-channel transistor is turned on. Supply the power supply voltage to the node,
The booster circuit according to claim 1 or 2. 4. The booster circuit according to claim 3, wherein a second capacitor is connected to the first node. 5. A fourth p-channel transistor having one terminal connected to the first node and the other terminal connected to the gate of the second p-channel transistor,
The booster circuit according to claim 3 or 4. 6. A third capacitor connected to the gate of the second p-channel transistor for increasing a gate voltage of the second p-channel transistor, wherein a signal for booting the third capacitor is the fourth p-channel transistor. Connected to the gate of
The booster circuit described in. 7. A signal for booting the third capacitor is
7. The booster circuit according to claim 6, wherein the booster circuit becomes L level only during a period when the signal for booting the first capacitor is at H level. 8. A fourth capacitor connected to the gate of the first p-channel transistor for boosting the gate voltage of the first p-channel transistor, the first capacitor and the fourth capacitor being booted simultaneously. The booster circuit according to any one of claims 3 to 7.