JP2003258010A - Ic chip array structure on substrate and method for manufacturing semiconductor device using the substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the imbalance of resin fluidity on a substrate at transfer resin molding of a semiconductor device. <P>SOLUTION: A plurality of IC chips are arranged and mounted on the substrate in the direction of X-Y coordinates in the form of a lattice, and sealant resin is injected from one side of the substrate toward its opposite side for sealing the IC chips in bloc on the substrate. After sealing, the IC chips are divided into pieces along the substrate for manufacturing chip-size packages. With respect to the IC chip arrangement structure on the substrate for the manufacture, the arranged position of the IC chips 2 on the substrate 1 is partly displaced for varying the flow resistance of the injected resin, and the arrival time of the injected resin is almost balanced along the whole opposite side. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC chip array structure on a substrate and a method for manufacturing a semiconductor device using the substrate, and more particularly to a plurality of I
When arranging and mounting C chips on a substrate, encapsulating the IC chips on the substrate by the transfer resin molding method, and dividing the IC chips into individual pieces after encapsulation to manufacture a chip size package And an IC chip array structure on a substrate and a method for manufacturing a semiconductor device using the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and thinning of semiconductor devices, ball grid array (BGA) type resin mold packages have been widely used. As one of this type, for example, Japanese Patent Laid-Open No. 2000-1274
There is a chip size package (CSP) as shown in the 5th announcement. The structure of this package will be described with reference to the general process diagram of FIG. 5. First, FIG.
A plurality of ICs on a substrate 1 (tape or rigid substrate) on which circuit patterns and the like are formed as shown in FIG.
The chip 2 is die-bonded, and then the IC chip 2 and the circuit pattern are connected by a bonding wire 3 to form an IC.
A substrate with chips is completed. In addition,
No wire bonding is required for the flip chip structure.

The conventional substrate will be described in more detail. As shown in the plan view of FIG. 6, the IC chip 2 mounted on the substrate 1 has an XY coordinate arrangement in the substrate 1. (Horizontal and vertical in FIG. 6)
They are regularly arranged in a grid pattern (matrix pattern) with a constant array pitch p (4 rows and 8 columns in this example) in both directions. In addition, the grid-like lines described so as to surround the IC chip 2 in FIG. 6 are not only the boundary line indicating the region of each IC chip 2 but also the cutting line when the CSP is individually separated in a later step. There is no line actually.

Next, as shown in FIG.
The substrate 1 in the state of (a) is loaded in the transfer resin molding die 4, and resin molding is performed so as to cover all the IC chips 2 evenly. At this time, the thickness of the sealing resin is set to a minimum thickness such that the upper surface of the IC chip 2 or the bonding wire 3 is not exposed. After release, the solder balls 5 are joined to the back surface side of the substrate 1 to form a BGA structure, and then cut along the boundary line shown in FIG. 6 to obtain individual CSPs as shown in FIG. 5C. Becomes The solder balls 5 may be joined together after being divided into individual pieces.

[0005]

As described above, the conventional arrangement of the IC chips on the substrate is, as shown in FIG. 6, arranged in a grid pattern with a constant arrangement pitch p in both the XY coordinate directions. It is arranged. When resin-encapsulating this substrate by the transfer resin molding method, as shown in FIG.
The resin is injected by flowing in the Y direction between the IC chips 2 and on the IC chip 2 from one side of the long side (all lower sides of FIG. 7) to the opposite side (all upper sides of FIG. 7).

In the grid array of the IC chips, since the plurality of IC chips are linearly arrayed in the Y direction (resin injection direction), the flow behavior of the injected resin 6 is mounted in one row in the Y direction. The flow resin on the line connecting the centers of the formed IC chips 2 and the flow resin between the row of IC chips 2 in the Y direction and the row of the adjacent IC chips 2 have different flow resistances due to the difference in flow resistance. There is a difference. As a result, the injection resin 6 on the central line of the IC chip row has an extremely slow flow velocity as compared with the injection resin 6 between the adjacent IC chip rows, and the tendency is as shown in FIG. (The closer to the opposite side) becomes more prominent. This is because the IC chip arrangement is also continuously arranged in one row in the Y direction with respect to the resin flow direction (Y-axis direction), and this conventional grid-like arrangement serves as a flow balance of the injected resin. I have to say that is a poor condition.

As a result of such imbalance of resin fluidity, when conditions such as PKG arrangement pitch (PKG size), chip size, chip thickness, and mold resin thickness are severe, in the worst case, the mold on the IC chip is molded. Voids are entrained in the resin, and as a result, defects such as generation of voids on the IC chip or exposure of the upper surface of the IC chip occur.

The present invention has been made to solve these problems. By optimizing the IC chip arrangement on the substrate for the resin fluidity, the resin filling balance during transfer resin molding is balanced. For the purpose of improving the encapsulation quality.
The purpose of the present invention is to contribute to design advantages such as improvement of manufacturing yield by reducing void entrainment voids on C chip, expansion of chip size allowable range, and reduction of resin mold thickness.

[0009]

SUMMARY OF THE INVENTION According to the present invention, a plurality of IC chips are mounted on a substrate arranged in a grid pattern in the XY coordinate directions, and sealed from one side of the substrate toward the opposite side. In an IC chip array structure on a substrate used for manufacturing a chip size package by injecting a resin to collectively encapsulate the IC chip on the substrate and then dividing the IC chip into individual pieces after encapsulation, The arrangement position of the IC chips on the substrate is partially shifted to change the flow resistance of the injected resin so that the arrival time of the injected resin is approximately balanced over the entire opposite side.

Further, as a concrete means for achieving the object of the present invention, in the IC chip array structure on the substrate, every other row of the IC chip array in the X direction is used.
In the IC chip arrangement structure on the substrate, the frontmost IC chip and the last IC chip in the Y direction are relatively shifted by one pitch in the X direction. The IC chips are arranged in an offset manner, and the X-direction rows between them are sequentially shifted at a pitch that is evenly distributed according to the number of rows, and the IC chips are arranged in an offset arrangement.

Further, as a concrete means for achieving the object of the present invention, in the IC chip arrangement structure on the substrate, the XY coordinate on the substrate is rotated by 45 degrees, and the X on the rotational coordinate is set. The IC chips are arranged at equal pitches in the -Y direction.
In the IC chip array structure on the substrate,
The IC chips in the front row and the last row in the Y direction are relatively shifted in the X direction by one pitch, and the straight lines connecting the IC chips shifted by one pitch are aligned with each other in the Y direction. The -Y coordinate is rotated, and the IC chips are arranged in a grid pattern on the rotated coordinate.

Further, according to the present invention, a plurality of IC chips are mounted on a substrate arranged in a grid pattern in the XY coordinate directions, and a sealing resin is injected from one side of the substrate to the opposite side. IC chips on a substrate are collectively encapsulated on the substrate, and after encapsulation, the IC chips are divided into individual pieces together with the substrate to manufacture a chip size package. The chips are partially displaced to form a barrier against the flowable resin, and the resin whose channel is bent by this barrier is made to flow in a zigzag shape from one side of the substrate to the opposite side for resin sealing. It is the one. Then, when the resin-sealed IC chip is divided into individual pieces together with the substrate, first cut into strips for each row in the X direction, and then individually cut in the Y direction to manufacture a chip size package. I have to.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. 1 to 4 are plan views showing an embodiment of a substrate used in the present invention. As shown in each drawing, a feature of the present invention is that a plurality of IC chips are arranged in a grid pattern (matrix pattern) and mounted on a substrate such as a tape or a rigid substrate, and the substrate and the IC chips are packaged together. In the MAP (matrix array package) method for resin encapsulation, by optimizing the IC chip intervals or IC chip mounting angles arranged in a grid pattern, the resin filling balance during transfer resin molding is balanced. It is intended to improve the encapsulation quality and is characterized by the arrangement structure of the IC chips on the substrate.

FIG. 1 shows an IC on a substrate of the present invention.
FIG. 3 is a plan view of the first embodiment showing a chip array structure. As shown in FIG. 1, the arrangement structure of the IC chips 2 does not have the IC chips arranged in a grid pattern at a uniform pitch p in the XY coordinate directions (horizontal and vertical orthogonal coordinates) as in the conventional structure. In particular, the IC chips 2 are arranged so that the IC chips 2 are not continuously arranged on the same Y axis (vertical line). That is, in FIG. 1, the pitch in the X direction is set to (1/2) every other row so that all the IC chips (here, four) in each Y direction column are not arranged on the same Y axis.
The array structure is shifted by p.

In the case where the IC chip mounting surface is collectively transfer resin molded by the MAP method using the tape or the rigid substrate as described above, the resin is applied from one side of the long side of the substrate (all lower sides of FIG. 1). Is injected under pressure, and the resin is made to flow toward the opposite side (all the upper sides of FIG. 1) to enclose the entire surface of the IC chip with resin. In that case, when the resin filling is promoted by the press fitting, the I in the front row is
Between C chip arrays (portion where IC chip is not mounted)
The resin flow speed of is faster than that of the IC chip mounting part, but when the injected resin progresses and reaches the IC chip shifted in the X direction of the rear row, this IC chip becomes a barrier and the resin flow Is prevented, and by repeating this, the resin flows in a zigzag shape toward the opposite side. That is,
By slightly changing the arrangement of the IC chips, the flow resistance of the injected resin can be made uniform, and the time required for the injected resin to reach all the opposite sides can be roughly balanced. As a result, the imbalance of the resin flow is corrected and the resin filling balance is improved.

FIG. 2 is a diagram showing a second embodiment of the present invention and is a plan view showing an IC chip arrangement structure on a substrate. As shown in FIG. 2, the IC chips 2 are arranged such that the front row (the bottom row shown) and the last row (the top row shown) are on the same Y axis, and the middle row is one pitch (p). The size is arranged in the X direction by an amount evenly distributed. Here, the array is offset by (1/3) p.

FIG. 3 is a plan view showing a third embodiment of the present invention. As shown in FIG. 3, the mounting angle of the IC chip 2 on the substrate 1 is changed.
I in the direction of the rotation coordinate axis rotated by 45 degrees with respect to the Y Cartesian coordinate
This is a structure in which the C chips 2 are arranged at a uniform pitch (p), and it is an effective arrangement particularly when the IC chips 2 are square. However, in this case, the length of one side of the square IC chip must be (1/2) p or more in order to become an obstacle of the fluid resin.

FIG. 4 is a plan view showing a fourth embodiment of the present invention. The arrangement shown in FIG. 4 is similar to that in FIG. 3, but the mounting angle of the IC chips 2 on the substrate 1 is changed. In this case, the IC chips 2 in the front row and the last row in the Y direction are arranged.
Are relatively shifted in the X direction by one pitch (p), and the XY coordinates are rotated by θ degrees so that the straight line connecting the IC chips, which is shifted by one pitch, has an angle that matches the Y direction. The IC chips 2 are arranged in a grid pattern on the rotation coordinates. Here, θ = tan ⁻¹ (1/3).

Next, the IC described in each of the above embodiments
A method of manufacturing a semiconductor device using a substrate having a chip arrangement will be described. Here, the substrate is resin-encapsulated by the transfer resin molding method,
FIG. 5 shows a case of manufacturing a CSP having a BGA structure.
Description will be given with reference to general process diagrams of (a), (b), and (c).

First, in FIG. 5 (a), a substrate 1 made of a tape or a rigid substrate is provided with wiring patterns constituting a circuit, a die pad on which an IC chip 2 is mounted, external connection terminals and the like. , The die pads are formed in the same arrangement as that of the IC chips 2.
The IC chips 2 are sequentially die-bonded to the die pads on the substrate 1 to obtain various IC chip arrangement structures as described in the embodiments. Then, the IC chip 2 and the circuit pattern are connected by the bonding wire 3 by wire bonding, and the substrate having the IC chip array structure of the present invention is completed.

Next, as shown in FIG. 5 (b), the substrate 1 is loaded into a transfer resin molding die 4, and one side on the long side of the substrate (for example, the entire lower side of FIG. 1) to the opposite side. The molten resin is press-fitted toward (the entire upper side). The resin that has been press-fitted flows in the resin molding die 4, and the entire surface of the substrate is resin-molded with a thickness such that the IC chip 2 and the bonding wire 3 are not exposed.
In that case, when the resin filling is promoted by the press-fitting, the resin flow between the IC chip arrays in the front row (the part where the IC chip is not mounted) becomes faster as compared with the IC chip mounting portion, but the resin filling does not occur. When the IC chip progresses and reaches the shifted IC chip in the rear row, the IC chip obstructs the resin flow,
As a result, the imbalance of the resin flow is corrected and the resin filling is well balanced.

Next, the resin-molded substrate is taken out of the mold, solder balls are bonded to the back side of the substrate by reflow or the like to form a BGA structure package, and then each IC chip is cut and separated by dicing. FIG. 5C is a sectional view showing the individual CSP. Here, when the encapsulated substrate is diced into individual IC chips, when the IC chip arrangement is not in a grid pattern, that is, when the IC chip boundaries are not connected in a straight line, especially in the Y direction side. At the time of cutting, it is necessary to cut and separate the X-direction side into strips in advance, and then again cut the Y-direction side into pieces.

[0023]

As described above, the conventional semiconductor device uses the substrate in which a plurality of IC chips are arranged and mounted in a matrix, and therefore flows between the IC chip rows during resin molding. There is a difference in the flow velocity between the injection resin, which has no obstacles in the flow path, such as resin, and the injection resin in which the flow path is blocked by the IC chip. Therefore, the resin injected from one side of the substrate is the opposite side The difference in the time required to reach the temperature reaches the point where the quality of the resin mold deteriorates.

However, according to the present invention, the matrix arrangement of the IC chips is partially displaced or X-
By rotating the Y coordinate and changing the IC chip mounting angle, the IC chips are rearranged to balance the resistance balance during resin flow over the entire surface of the substrate. As a result, the design quality is improved by improving the encapsulation quality during transfer resin molding, that is, improving the manufacturing yield by reducing void entrainment voids on the IC chip, expanding the chip size allowable range, and reducing the resin mold thickness. It has become possible to greatly contribute to sex.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view showing a third embodiment of the present invention.

FIG. 4 is a plan view showing a fourth embodiment of the present invention.

FIG. 5 is a general manufacturing process (a), (b) of CSP;
It is a schematic sectional drawing which shows (c).

FIG. 6 is a plan view showing an IC chip array on a conventional substrate.

FIG. 7 is a plan view showing a flow behavior of a conventional injected resin.

[Explanation of symbols]

1 substrate 2 IC chip 3 Bonding wire 4 resin mold 5 solder balls 6 injection resin

Claims (7)

[Claims] 1. A plurality of IC chips are arranged and mounted on a substrate in a grid pattern in the XY coordinate directions, and a sealing resin is injected from one side of the substrate to the opposite side to form an IC.
Encapsulate the C chips on the substrate all together, and then enclose the IC
In an IC chip array structure on a substrate used when a chip size package is manufactured by dividing a chip into individual pieces, the array position of the IC chips on the substrate is partially shifted to An IC chip array structure on a substrate, characterized in that the flow resistance is variable and the arrival time of the injected resin is approximately balanced over the entire opposite side. 2. The substrate according to claim 1, wherein in the IC chip array structure on the substrate, the columns in the X direction are arranged every other row while being shifted by 1/2 pitch of the IC chip array. IC chip array structure. 3. In the IC chip array structure on the substrate, the IC chips in the front row and the last row in the Y direction are arranged relatively offset by one pitch in the X direction, and the rows in the X direction between them are arranged in the number of rows. 2. The IC chip arrangement structure on a substrate according to claim 1, wherein the IC chips are arranged in an offset manner by sequentially displacing them at a pitch that is evenly distributed according to the above. 4. In the IC chip array structure on the substrate, the XY coordinates on the substrate are rotated by 45 degrees, and the IC chips are arrayed at a uniform pitch in the XY directions on the rotational coordinates. An IC chip array structure on a substrate according to claim 1, wherein: 5. In the IC chip array structure on the substrate, the IC chips in the front row and the last row in the Y direction are relatively shifted by one pitch in the X direction, and the IC chips are shifted by this one pitch. 2. The substrate according to claim 1, wherein the XY coordinates are rotated so that a straight line connecting between them becomes an angle that coincides with the Y direction, and the IC chips are arranged in a grid pattern on the rotated coordinates. IC chip array structure. 6. A plurality of IC chips are arranged and mounted on a substrate in a grid pattern in the XY coordinate directions, and a sealing resin is injected from one side of the substrate to the opposite side.
Encapsulate the C chips on the substrate all together, and then enclose the IC
In a method of manufacturing a semiconductor device using a substrate, in which a chip is divided into individual pieces for manufacturing a chip size package, an IC on the substrate is provided.
The chips are partially displaced to form a barrier against the flowable resin, and the resin whose channel is bent by this barrier is made to flow in a zigzag shape from one side of the substrate to the opposite side for resin sealing. And a method for manufacturing a semiconductor device using a substrate. 7. A chip size package is manufactured by dividing the resin-sealed IC chip into individual pieces along with a substrate by first cutting into strips for each row in the X direction and then individually cutting in the Y direction. 7. A method of manufacturing a semiconductor device using the substrate according to claim 6, wherein.