JP2003258045A - Method for probe testing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately sort a nondefective product and a defective product in a method for probe-testing a semiconductor device formed on a semiconductor substrate. <P>SOLUTION: The method for probe-testing comprises steps of bringing a probe needle 32 into contact with pads P1, P2 of an element to be pretested in the semiconductor device 10, pretesting the confirmation of operability under predetermined conditions hard to be operated as compared with standard operating conditions, conducting a contact state improving countermeasure between the pads P1, P2 and the needle 32 if the operation of the element to be pretested is not confirmed in the pretesting, and then conducting the testing of the device 10. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe test method for a semiconductor device formed on a semiconductor substrate.

[0002]

2. Description of the Related Art In a packaged semiconductor device, after a large number of semiconductor devices having a predetermined circuit are formed on a single semiconductor substrate, the semiconductor substrate is divided into individual semiconductor devices, and each of the divided semiconductor devices is divided. It is completed by packaging the semiconductor device. 2. Description of the Related Art Conventionally, a semiconductor device is inspected for electrical performance on a semiconductor substrate before being divided and packaged, and a good product and a defective product are selected. In this test,
A probe test using a probe needle is often performed. The semiconductor device is provided with a pad for connecting to an element that constitutes a circuit. In a probe test, a probe needle is brought into contact with this pad, and an electric signal is input / output to / from the semiconductor device through the probe needle. Check electrical performance with. Therefore, in the probe test, if the contact state between the probe needle and the pad is poor, the semiconductor device, which should normally operate normally, does not operate and is treated as a defective product.

[0003]

The contact state between the probe needle and the pad depends on the magnitude of the contact pressure between the probe needle and the pad. That is, when the contact pressure between the probe needle and the pad is low, the contact resistance between the probe needle and the pad is high, and the semiconductor device, which should normally operate normally, does not operate. In addition, an oxide film may be formed on the pad surface, and in the probe test, it is necessary to bring the probe needle and the pad into contact with each other at a high pressure to break through the oxide film. For these reasons, it is desirable that the probe test be performed with the contact pressure between the probe needle and the pad as high as possible. However, if the contact pressure between the probe needle and the pad is too high, the pad may be damaged by the probe needle, and the contact pressure between the probe needle and the pad cannot be increased indefinitely.

Particularly, in a semiconductor device having an oscillation circuit,
If the contact pressure between the probe needle and the pad is as small as possible, both the contact resistance component and the capacitance component of the oxide film on the pad surface become a load on the oscillation circuit, and the oscillation circuit is likely to be unable to oscillate or deteriorate in characteristics. Originally good semiconductor devices are easily treated as defective.

In view of the above circumstances, it is an object of the present invention to provide a probe test method capable of accurately selecting a good product and a defective product.

[0006]

A probe test method of the present invention for achieving the above object is a probe test method for a semiconductor device formed on a semiconductor substrate, wherein a probe is applied to a pad of a pre-test target element in the semiconductor device. When a needle is contacted and a pre-test is performed to confirm whether or not the pre-test target device operates under predetermined conditions that make it difficult to operate compared to the standard operating conditions, and when the pre-test target device operation cannot be confirmed in the pre-test, The semiconductor device is tested after the contact state between the pad and the probe needle is improved.

In the probe test method of the present invention, first,
Confirm whether or not the pre-test target device can operate under certain conditions that make it difficult to operate compared to standard operating conditions, and if the operation cannot be confirmed, take contact condition improvement measures and then conduct a semiconductor device test (main test). Therefore, it is possible to accurately select a good product and a defective product.

Further, in the probe test method of the present invention, it is preferable that the predetermined condition is a condition in which the operation is the most difficult within the operation standard range of the pretest target element.

By performing a pre-test under such a predetermined condition and taking a contact state improvement measure when the operation confirmation cannot be obtained, a good product and a defective product are checked in the main test in all the operation standard range. Can be accurately sorted.

Here, in the probe test method of the present invention, the contact state improvement measure may be an increase in the contact pressure of the probe needle with respect to the pad, or the pretest target element constitutes an oscillation circuit. The pad may be a circuit component, and the pad may include a crystallite pad that connects the oscillator circuit component to a crystallite, or the semiconductor device test may be a test of the pretest target device. May be

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a diagram schematically showing a state in which a probe test of a semiconductor device is performed using the probe test method of this embodiment.

The probe test method of the present embodiment is carried out by using a probe test apparatus having a stage that can be raised and lowered. In FIG. 1, among the probe test apparatus 2,
Only the stage 21 that can be moved up and down is shown as indicated by the arrow in the figure. Further, the probe test method of the present embodiment is
It is performed on one semiconductor substrate (wafer) 1 on which a large number of semiconductor devices (chips) 10 are formed. Each semiconductor device 10
Is provided with an oscillating circuit and a plurality of pads P1 and P2 connected to the elements constituting the oscillating circuit.

As shown in FIG. 1, a large number of semiconductor devices 10 are provided.
The one semiconductor substrate 1 on which is formed is placed on a stage 21 that can be raised and lowered. A probe card 3 is arranged above the semiconductor substrate 1 placed on the stage 21 with a predetermined distance from the pad surface of the semiconductor device 10. The probe card 3 has a crystal element 31 and a plurality of probe needles 32.

When the stage 21 on which the semiconductor substrate 1 is mounted rises, the pads P of the semiconductor device 10 to be tested.
The probe needle 32 of the probe card comes into contact with 1 and P2. Note that the pads P1 and P2 of the semiconductor device 10 and the probe needles 32 of the probe card are in contact with each other by the pads P1 and P2.
It may be performed by relative movement of P2 and the probe needle 32. For example, the stage 21 may be fixed and the probe card 3 may be lowered, or the stage 21 may be raised and the probe card 3 may be lowered. Good.

FIG. 2 is a circuit diagram of the semiconductor device shown in FIG. 1 with probe needles in contact with the pads.

FIG. 2 shows the semiconductor device 10 and the crystal element 31. The semiconductor device 10 shown in FIG. 2 is a semiconductor device that undergoes a probe test. The crystal element 31 shown in FIG. 2 is provided on the probe card 3 having a plurality of probe needles.

An oscillation circuit is formed in the semiconductor device 10. The oscillation circuit is composed of a variable capacitance diode 11 which is a PN junction capacitor, a CMOS inverter 12, and the illustrated resistors and capacitors. CM
The power supply voltage VDD is applied to the power supply terminal of the OS inverter 12. The ground terminal of the CMOS inverter 12 is connected to the ground GND. Further, the pad P1 is connected to the input side of the CMOS inverter 12, and the pad P2 is connected to the output side of the CMOS inverter 12 via the resistor Rd. Pad P2
The capacitor Cd and the capacitor C0 are connected in parallel between the ground terminal and the ground GND. A capacitor Cp and a capacitor Cg are connected in series between the pad P1 and the ground GND. The variable capacitance diode 11 is connected between the connection point of the capacitors Cp and Cg and the ground GND, and the resistor R1 is connected between this connection point and the input terminal V _in . Further, a resistor Rf is connected to both ends of the CMOS inverter 12.

In addition, FIG. 2 shows a state in which one of the probe needles of the probe card 3 is in contact with the pad P1 and the other probe needle is in contact with the pad P2. When the probe needle of the probe card 3 contacts the pads P1 and P2 of the semiconductor device in this manner, the crystallite 31 of the probe card 3 has the pads P1 and P2.
Will be connected between the two.

The input terminal V _in of the semiconductor device 10 has 0 V to
A control voltage Vc of 3.3V is applied. The applied control voltage Vc passes through the resistor R1 and the variable capacitance diode 11
Is applied as a reverse bias voltage. The capacitance of the variable capacitance diode 11 changes according to the magnitude of the applied control voltage Vc. The frequency of the oscillation signal output from the output terminal V _out changes according to the change in the capacitance of the variable capacitance diode 11.

The standard operating conditions of the semiconductor device shown in FIG.
The power supply voltage VDD is 3.3V. The operating standard range of the power supply voltage (limit operating power supply voltage range) is 2.5 to 5.
It is 0V. At the lowest voltage of 2.5V, the semiconductor device is the most difficult to operate. On the other hand, the operating standard range of the control voltage Vc is 0V to 3.3V. But,
Since it is normally used near its midpoint of 1.65 V, it is considered that 1.65 V is the standard operating condition of the control voltage Vc in the present invention. And, the operation is most difficult at 0V which is the lowest voltage.

FIG. 3 is a flow chart showing the flow of each step of the probe test method of this embodiment.

In carrying out the probe test method of the present embodiment, an operator, as shown in FIG. 1, has one semiconductor substrate 1 on which the semiconductor device 10 to be tested is formed on the stage 21 of the probe test apparatus 2. To place. At this stage, the pads P1 and P2 of the semiconductor device on the stage are
And the probe needle 32 are separated from each other. In the probe test, if the contact state between the probe needle and the pad is poor, in the semiconductor device of this embodiment, the oscillation circuit
Oscillation cannot be performed or characteristics are deteriorated, and a semiconductor device that should normally operate normally does not operate and is treated as a defective product. The contact state between the probe needle and the pad depends on the magnitude of the contact pressure between the probe needle and the pad. In this embodiment, as described later, the stage is raised to improve the contact state between the probe needle and the pad, and the contact pressure between the probe needle and the pad is increased. Generally, when the contact pressure between the probe needle and the pad is increased, the contact resistance between the probe needle and the pad tends to decrease. Further, when the contact pressure between the probe needle and the pad is increased, even if an oxide film is formed on the pad surface, the probe needle easily breaks through the oxide film. However, if the stage is raised too much, the contact pressure between the probe needle and the pad becomes too high, and the probe needle may damage the pad. Therefore, the probe test apparatus stores a prescribed value of the height of the stage so that the pad is not damaged by the rise of the stage.

In the probe test method of this embodiment, at least one pretest is performed before the main test. In this embodiment, the element to be pre-tested and the semiconductor device to be tested are the same, and both are the oscillation circuits shown in FIG.

[0025] In this test in the present embodiment, 0V～3 the voltage applied to the power supply terminal of the CMOS inverter of the semiconductor device while changing the operating standard range of 2.5V to 5.0V, the input terminal V _in. A control voltage Vc of 3 V is applied to check whether the frequency of the oscillation signal output from the output terminal V _out appropriately changes according to the magnitude of the control voltage Vc. That is, in the main test of the present embodiment, it is checked whether or not the semiconductor device normally operates not only under the standard operating conditions but also within the entire operating standard range of the power supply voltage VDD and the control voltage Vc.

On the other hand, the pre-test performed before such a main test is a test for confirming the contact state between the pad of the pre-test target element and the probe needle.

First, the operator sets the conditions for the pretest in the probe test apparatus (step S1).
The probe test apparatus raises and lowers the stage shown in FIG. 1 and applies a voltage to the pre-test target element of the semiconductor substrate placed on the stage according to the set conditions during the pre-test. This step S1
In the condition setting in, the semiconductor device CMO shown in FIG.
The power supply voltage value for pretest applied to the power supply terminal of the S inverter, the control voltage value for pretest applied to the input terminal V _in, and the like are set. In the pre-test in the present embodiment, the test is performed under the condition that it is hard to operate as compared with the standard operation condition. Here, with respect to the power supply voltage whose standard operating condition is 3.3V, the power supply voltage value for pretest is set to 2.5V at which the semiconductor device to be tested is hard to operate. Also, the standard operating condition is 0V to 3.
Regarding the control voltage Vc of 3V, 0V at which the semiconductor device to be tested is most difficult to operate is set as the control voltage value for pretest.

As described above, the pretest is performed by setting the most difficult operating condition within the allowable operating standard range for all of the main conditions that affect the ease of operation of the pretest target element. The contact state between the pad of the semiconductor device and the probe needle can be evaluated with the highest sensitivity. However, it is not essential for the present invention to set such a condition that is most difficult to operate as a condition of the pretest, and it is more difficult to operate than the standard condition, and a condition suitable for evaluation of the contact state may be appropriately set. In addition, when there are a plurality of main conditions that affect the ease of operation of the pre-test target element, it is not essential to set all of them to conditions that make them harder to operate than the standard conditions. For example, it is possible to set only the condition that has the greatest influence to a condition in which it is difficult to operate as compared with the standard condition, and set the other conditions to the standard condition.

Next, the operator sets the height of the stage of the probe test apparatus (step S2). The height setting in step S2 is to set the height of the stage at the start of the first pretest, and is set in the probe test apparatus that raises and lowers the stage. As mentioned above,
At the stage of mounting one semiconductor substrate on which the semiconductor device to be tested is formed on the stage, the pads P1 and P2 of the semiconductor device on the stage and the probe needle 32 are separated from each other. Pads P1 and P when height is raised
2 and the probe needle 32 contact each other, and as the height of the stage is further raised, the contact pressure between the pads P1 and P2 and the probe needle 32 gradually increases. The stage height here is set by, for example, further raising a predetermined amount from a position where a contact sensor (not shown) provided on the probe card detects physical contact of the probe needle with the pad. To do. The height of the stage set in step S2 is the same as that of the pads P1, P2
The contact pressure between the probe needle 32 and the probe needle 32 is sufficiently low. At this stage height, there is no possibility that the pad may be damaged by the contact of the probe needle.

These steps S1 and S2
Upon completion of the setting in, the probe test apparatus starts the pretest based on the set conditions in response to the operation of the operator (step S3). That is, the probe test apparatus raises the stage to the height set in step S2, and thereafter applies a voltage of 2.5 V to the power supply terminal of the CMOS inverter of the semiconductor device which is the pre-test target element, and at the same time, inputs the voltage. 0 at terminal V _in
A voltage of V is applied.

When the pretest is performed, the probe test apparatus determines whether the pretest target element on the stage operates depending on whether the oscillation signal output from the output terminal V _out of the pretest target element is observed. Is determined (step S4). That is, at this stage, whether or not the oscillation frequency is within the standard is not confirmed, but the operation of the pretest target element is confirmed by whether or not the oscillation is confirmed. If it is determined that the probe needle is operating, the contact state between the probe needle and the pad is good, and the stage height at that point is optimal, and the probe is attached to the pad at the stage height at that point. This test is executed with the needle in contact (step S5). In this test, which is executed in this way, it is performed after confirming that the contact state between the pad and the probe needle is good by a pre-test that is performed under conditions that make it difficult to operate compared to the standard conditions. Good products can be accurately sorted. When this test is completed, the execution of the probe test method of this embodiment on one semiconductor device is completed. Then, the probe test of the next semiconductor device 10 formed on the same semiconductor substrate 1 is performed.

On the other hand, if it is determined in step S4 that the operation is not normal, the process proceeds to step S6. At the time of proceeding to step S6, the reason why the pretest target device does not operate normally is that the contact state between the pad and the probe needle is bad, and the pretest target device, that is, in this case, the semiconductor device of the main test target is There are two possible reasons: defective products. In step S6,
The probe test apparatus determines whether or not the pretest is completed. Whether or not the pretest is completed is determined by whether or not the contact pressure between the probe needle and the pad is too high, that is,
It is determined whether or not the height of the stage has reached a specified value stored in the probe test apparatus. When the height of the stage has reached the specified value, it is determined that the semiconductor device to be tested is defective, and the implementation of the probe test method of the present embodiment ends. On the other hand, when it is determined that the stage height has not reached the specified value yet and the pretest has not been completed, it is assumed that the contact state between the pad and the probe needle is bad, and the stage height shown in FIG. Is reset (step S7). In the resetting in step S7, the contact pressure between the pads P1 and P2 and the probe needle 32 is increased, so that the probe test apparatus is set to a value that increases the height of the stage. The probe test apparatus stores in advance how much the stage should be raised during this resetting. The stage is preferably raised between 1 μm and 5 μm. The resetting in step S7 is performed by the probe test apparatus itself. Such step S7 corresponds to the contact state improvement measure according to the present invention.
When step S7 is executed, the process returns to step S3, and in step S3, the pretest is performed by raising the stage to the height reset in step S7. Therefore, in the pre-test performed here, the contact pressure between the pads P1 and P2 and the probe needle 32 is higher than that in the previous pre-test, the contact resistance tends to be low, and oxide is generated on the pad surface. However, the probe needle can easily break through the oxide.

Next, the semiconductor device formed on the same one semiconductor substrate is tested by the probe test method of this embodiment and the probe test method which does not employ the probe test method of this embodiment. . In the probe test, the Vmin defect is a defect that is most affected by the contact state between the probe needle and the pad. This Vmin failure is said to occur when a semiconductor device, which should normally operate normally, does not operate normally when 2.5 V, which is the lowest voltage within the operating standard range, is applied to the power supply terminal of the CMOS inverter of the semiconductor device. It is bad. In the test result performed without adopting the probe test method of the present embodiment, 193 such Vmin defects were found, but in the test result of the probe test method of the present embodiment, it was drastically reduced to only 10. did. From this,
In the probe test performed without adopting the probe test method of the present embodiment, 183 semiconductor devices that are originally not defective in Vmin are regarded as defective products in Vmin defect, and the probe test method of the present embodiment is It can be said that this is a probe test method that can accurately select good products and defective products.

In the above-described probe test method of the present embodiment, the oxide is generated on the pad surface easily pierced by the probe needle by raising the stage, but the present invention is not limited to this. The oxide generated on the pad surface may be destroyed by applying an excessive current to the probe needle, and the pads P1 and P of the semiconductor device 10 may be destroyed.
Various measures can be taken to improve the contact state between the probe needle 32 and the probe needle 32. Further, the probe test method of the present invention can be applied to a probe test of a semiconductor device having an oscillation circuit as shown in FIG. 2 and a probe test of a semiconductor device having various circuits. However, it is particularly suitable for a probe test of a semiconductor device having a pad whose operation state is sensitively affected by the contact state with the probe needle, such as a crystal oscillator pad connected to a crystal oscillator via a probe needle. Can be applied to.

In the probe test method of the embodiment described above, the same oscillator circuit is used as the target element of the pre-test in the probe test of the semiconductor device having the oscillator circuit as the subject of this test. However, in addition to a circuit whose operation is sensitively affected by the contact state between the pad and the probe needle, such as an oscillation circuit, it also includes other circuits.
Even in a probe test of a large-scale semiconductor device, a circuit whose operation is sensitively affected by a contact state can be suitably applied by using a pretest target element.

If there is no circuit suitable for use as a pre-test target element in the part to be tested, it is possible to provide a circuit that is sensitive to the contact state exclusively for the pre-test. . However, also in this case, it is necessary to perform the main test in the state where the contact state is confirmed to be good in the pre-test. Therefore, the main body portion to be subjected to the main test and the pre-test target element are combined and formed in the respective chips to form a semiconductor device. Then, the pre-test is performed with the probe needle in contact with both the pad that needs to be contacted for the main test and the pad that needs to be contacted for the pre-test, and the contact state may be good. If it can be confirmed, perform the main test as it is.

[0037]

As described above, according to the probe test method of the present invention, a good product and a defective product can be accurately selected.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a state in which a probe test of a semiconductor device is performed using the probe test method of the present embodiment.

FIG. 2 is a circuit diagram of the semiconductor device shown in FIG. 1 in a state where a probe needle is in contact with a pad.

FIG. 3 is a flowchart showing a flow of each process of the probe test method of the present embodiment.

[Explanation of symbols]

1 Semiconductor substrate 10 Semiconductor device 11 Variable capacitance diode 12 CMOS inverter 2 probe test equipment 21 stages P1, P2 pad 3 probe card 31 Crystal 32 probe needle

Claims (5)

[Claims] 1. A probe test method for a semiconductor device formed on a semiconductor substrate, wherein a probe needle is brought into contact with a pad of a pre-test target element in the semiconductor device, and the standard operating condition of the pre-test target element is compared. Perform a pre-test to confirm whether it is possible to operate under a predetermined condition that makes it difficult to operate, and if the operation of the pre-test target element cannot be confirmed in the pre-test, take measures to improve the contact state between the pad and the probe needle. From the above, a probe test method for carrying out a test of the semiconductor device. 2. The probe test method according to claim 1, wherein the predetermined condition is a condition in which an operation is most difficult within an operation standard range of the pre-test target element. 3. The probe test method according to claim 1, wherein the contact state improvement measure is an increase in contact pressure of the probe needle with respect to the pad. 4. The pre-test target element is an oscillation circuit constituent element that constitutes an oscillation circuit, and the pad includes a crystallite pad that connects the oscillation circuit constituent element to a crystallite. The probe test method according to any one of 1 to 3. 5. The test of the semiconductor device is a test of the pre-test target element.
5. The probe test method according to any one of 4 to 4.