JP2003255904A - Display device and driving circuit for display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, in a liquid crystal display device which is provided with a switch group for distributing (demultiplexing) column voltages to be outputted from a column driving circuit and for outputting the demultiplexed column voltages to column electrodes of a pixel part, when the output phase of a column voltage is more delayed than control signals S1 to S3 of a switch, after a column voltage being in a previous state is once applied on column electrodes, an essential column voltage is applied on the column electrodes, and as a result, an unnecessary waveform fluctuation is caused in the application voltage of the column voltage and this becomes a cause with which power consumption is increased in the display device. <P>SOLUTION: Non-overlap periods when all of control signals of switches become 'low' are provided to the display device and the timing of respective signals are stipulated so that column voltages are changed in these periods. In short, column voltages are made to be changed in a state when the switch group are all in OFF states. Thus, a phenomenon in which a previous column voltage is once applied on the column electrodes is avoided in the display device and the unnecessary voltage fluctuation is prevented and the increasing of the power consumption can be avoided in the display device. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which controls display brightness by an applied voltage, and more particularly to a display device using a liquid crystal element, an EL element, plasma and a driving circuit (eg LSI) thereof.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 11-32751 discloses a driving technique of a display device which controls display brightness by an applied voltage.
There is a display device described in Japanese Patent No. 8 publication. This liquid crystal display device
A switch group for distributing (demultiplexing) the column voltage output from the column driving circuit and outputting the column voltage to the column electrode of the pixel portion is provided. As a result, the number of output terminals of the drive circuit can be made smaller than the number of column electrodes, and it is possible to cope with simplification of the drive circuit and high density of the pixel portion.

[0003]

In the above prior art, as shown in FIG. 1 and FIG.
The column voltages of (red), G (green), and B (blue) are output in a time-division manner, and these are distributed by a selection signal, so that a desired column voltage is applied to the column electrodes. Here, for example, the column voltage C
The output phase of 1 is the selection signals S1 to S3 due to circuit delay or the like.
If it is delayed, the column voltage in the previous state is once applied and then the original column voltage is applied, as shown in FIG. As a result, in the applied voltage of the column voltage, unnecessary waveform fluctuations (circled in the figure) occur with respect to the waveform shown in FIG. This fluctuation causes unnecessary power loss and increases power consumption. However, in the prior art, the changes of the column voltage C1 and the selection voltages S1 to S3 are described as the same timing, and the possibility of the above-mentioned waveform fluctuation and the method of avoiding it have not been considered.

[0004]

To solve the above problems, the display device of the present invention is provided with a non-overlap period in which all of the selection signals S1 to S3 are "low" as shown in FIG. The timing of each signal is specified so that the column voltage changes within this period. That is, the column voltage changes when all the switches in the distribution unit are in the OFF state. Thereby, the phenomenon that the previous column voltage is once applied can be avoided, unnecessary voltage fluctuation can be prevented, and increase in power consumption can be avoided.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to FIGS. FIG. 5 is a diagram showing the configuration of the display device according to the first embodiment of the present invention. Figure 5
, 501 is a column driving unit, 502 is a panel unit, 50
3 is a power supply unit. In the column driver 501, 504 is a system interface, 505 is a data register, 5
06 is a memory write control unit, 507 is a display memory, 50
8 is a timing generation unit, 509 is a memory read control unit,
Reference numeral 510 is a time division unit, 511 is a column voltage generation unit, and 512 is a column voltage output unit. In addition, in the panel portion 502, 5
Reference numeral 13 is a distribution unit, 514 is a pixel unit, and 515 is a row drive unit. These are, for example, low-temperature polysilicon TFT elements, which are integrally formed on a glass substrate. A display element driven by the pixel portion 514 is, for example, a TN liquid crystal, and multicolor display is performed by applying a predetermined voltage level. The display data input to the display device is digital data of 6 bits for each of R (red), G (green), and B (blue).

First, the operation of the column driving section 501 will be described. Control data for controlling the operation of the display device is given from the CPU to the column driving unit 501. The control data includes
It includes display data and its display position, the number of drive lines, frame frequency, and the like. The interface between the CPU and the column driving unit 501 is, for example, a so-called 8
It complies with the 0-system bus interface, and as shown in FIG. 6, CS indicating the chip selection and data register 505.
Address / data selection RS, data write start instruction WR, data read start instruction R
D, the actual value of the address / data, D, is provided via the system bus. And these signal groups are
It has a cycle for designating an address of the data register 505 and a cycle for writing data. These cycles will be described with reference to FIG. 7. First, in the addressing cycle, CS is "low", RS is "low", R
The operation is performed when D is set to "high", D is set to a predetermined address value, and then WR is set to "low". On the other hand, in the data write cycle, when CS is “low”, RS is “high”, RD is “high”, D is set to predetermined data, and then WR is set to “low”, the operation is performed. To be executed. It should be noted that these operations are pre-programmed by an operating system and application software that control the entire apparatus.

The system interface 504 is a part for decoding the control data, and in the addressing cycle, a signal for putting the corresponding address into the write state, and in the data writing cycle, the data to be written,
It outputs to each data register 505.

In the data register 505, the register of the designated address is set to the write state, and the data is stored in this register. The control data written in the data register 505 is written in different addresses. Then, the various control data stored in the data register 505 is output to each block. For example, display data is output to the display memory 507, display position data is output to the memory write control unit 506, and data relating to the number of drive lines, frame frequency, etc. is output to the timing generation unit 508.

The memory write controller 506 decodes the display position data and selects the bit line and the word line in the display memory 507 corresponding to this. At the same time, the display data is output from the data register 505 to the display memory 507, and the write operation is completed.

The timing generator 508 itself generates the timing signal group shown in FIG. 8 based on the drive information given from the data register 505, and the memory read controller 5
09, the time division unit 510, and the column voltage generation unit 512.

The memory read controller 509 decodes the signal output from the timing generator 508 and selects the word line in the corresponding display memory 507. This behavior is
For example, one line is selected one by one from the word line in which the display data of the first line of the screen is stored, and after the last line, the operation returns to the first line and repeats this operation. At the same time as the word line selecting operation, the display data for one row is sequentially and collectively output from the data line of the display memory 507. Here, the timing of switching the word line is determined by the timing generation unit 508.
It is assumed that the timing of selecting the word line of the first row in synchronization with the line signal given from the is synchronized with the frame signal given from the timing generation unit 508.

The time division unit 510 time division (multiplexer) the display data for one row given from the display memory 507. In this operation, as shown in FIG. 9, the period of the line signal is divided into three by using the divided signals D1 to D3 provided from the timing generation unit 508, and the display data is output in the order of R, G, and B. Hereinafter, the time-division display data will be referred to as time-division data.

The column voltage generator 511 is a block for generating a column voltage required when converting the time division data into voltage levels, and its internal structure is shown in FIG. In FIG. 10, VDH is a reference voltage for generating a column voltage,
VDH is supplied from the power supply unit 103. Then, 64 types of column voltages V0 to V63 are generated by resistively dividing the reference voltage VDH, and each column voltage is buffered by the operational amplifier of the voltage follower circuit.
The number of column voltage levels is 64 because the input display data is 6 bits (= 64 types).

As shown in FIG. 11, the column voltage output unit 512 outputs 1 out of 64 types of column voltages according to the AC signal supplied from the timing generation unit 508 and the time division data.
This block selects and outputs a level. FIG. 12 shows a specific example of the above selection operation.

Next, the operation of the panel section 502 will be described.

First, the pixel portion 514 is composed of a three-terminal TFT element, a liquid crystal layer, and a storage capacitor. The drain terminal of the TFT element is a column electrode, the gate terminal is a row electrode, and the source terminal is connected to a liquid crystal cell and a storage capacitor. To be done. A common counter electrode is provided on the opposite side of the liquid crystal layer and is electrically connected to the liquid crystal layer. Further, the other terminal of the storage capacitor is connected to the preceding row electrode. In order to realize this structure, for example, the column electrodes and the row electrodes are formed in a matrix on one inner surface of two transparent substrates that sandwich the liquid crystal, and the counter electrode is formed in a solid shape on the other inner surface. The circuit configuration of this pixel is a so-called Cadd structure, but it is also applicable to a so-called Cst structure in which the terminal of the storage capacitor is connected to the storage line.

The distribution unit 513 distributes (demultiplexes) the column voltage supplied from the column driving unit 501, and the pixel unit 5
It is a block for outputting to the 14 column electrodes, and can be realized by the circuit configuration using the TFT element shown in FIG. Also,
The operation is similar, and as shown in FIG.
The switch is ON when the selection signals S1 to S3 are "high".
Then, the column voltage is applied to the column electrode. Note that S1 to S
3 is supplied from a power supply unit 503 described later.

The row driver 515, as shown in FIG.
"High" is applied to the first row electrode in synchronization with the frame signal transferred from the timing generation unit 505 in the column drive circuit 501.
Row voltage is applied, and thereafter, a "high" row voltage is sequentially applied to the row of the next stage in synchronization with the transferred gate signal. Here, the timing when the row voltage changes to “low” is after all the RGB column electrode applied voltages have been determined. The operation of the row driving unit 515 can be easily realized by applying a shift register circuit.

Next, the operation of the power supply unit 503 will be described.

The power supply unit 503 generates a counter voltage, which is a voltage applied to the counter electrode, and selection signals S1 to S3. First, in generating the counter voltage, the timing generation unit 5
The AC signal transferred from 08 is converted into a level necessary for driving the liquid crystal and output. For example, as shown in FIG. 14, the amplitude of the counter voltage is converted to be larger than the amplitude of the column voltage. Since the polarity of the liquid crystal applied voltage is the polarity of the column voltage seen from the counter voltage, the polarity of the liquid crystal applied voltage is inverted in conjunction with the AC signal. This operation is equivalent to so-called common inversion drive.

Next, for the selection signals S1 to S3, the timing waveforms shown in FIG. 14 are generated based on the divided signals D1 to D3. Further, the “high” of S1 to S3 is the distribution unit 5
The voltage level of the output is converted so that the TFT element 13 is turned on and "low" is turned off.

In addition to the above-mentioned operation, the power supply unit 503 generates a power supply voltage necessary for the display device of the present invention and outputs it to each block. This operation can be realized by means for boosting the power supply voltage given from the outside and means for adjusting the boosted voltage. In addition, control information such as voltage adjustment,
It is assumed that the data is transferred from the data register 505 in the column driver 501.

As described above, the display device according to the first embodiment of the present invention is provided with the non-overlap period in which all of the selection signals S1 to S3 shown in FIG. The timing of each signal is specified so that the voltage changes. That is, the column voltage changes when all the switches in the distribution unit 513 are in the OFF state. As a result, the phenomenon that the column voltage in the previous state is once applied can be avoided, unnecessary voltage fluctuation can be prevented, and increase in power consumption can be avoided.

In the first embodiment of the present invention, the common inversion drive is taken as an example, but the invention is not limited to this, and so-called dot inversion drive or column inversion drive in which the opposing voltage is not oscillated. Is also easily applicable. In the present embodiment, the type of display is TF.
Although the T liquid crystal is used, the present invention is not limited to this, and can be applied to other displays whose display brightness is controlled by the voltage level, such as an organic EL display. The column driving unit 501 and the power supply unit 503 according to the first embodiment of the present invention.
May be integrated in individual LSIs depending on the application, or both may be integrated into one.

Next, the second embodiment of the present invention will be described with reference to FIG.
The description will be made using # 18. The above-described first embodiment of the present invention is a type in which the display device is directly connected to the system bus, and this configuration is often used for small displays mainly for mobile phones. On the other hand, the second embodiment of the present invention is intended to be applied to a configuration in which a display device is connected to a graphic controller and is often used in a large-sized display.

FIG. 16 is a diagram showing the structure of a display device according to the second embodiment of the present invention. In FIG. 16, 16
01 is a timing controller, 1602 is a column driver, 160
Reference numeral 3 is a panel portion, and 1904 is a power supply portion. Column drive unit 16
In FIG. 02, reference numeral 1605 is an acquisition latch unit, 1606 is a synchronization latch unit, 1607 is a time division unit, 1608 is a column voltage generation unit, and 1609 is a column voltage output unit. Further, in the panel portion 1603, 1610 is a distributing portion, 1611 is a pixel portion, and 1612 is a row driving portion, and these are also low temperature polysilicon TFT elements, for example, and are integrally formed on a glass substrate. The display element driven by the pixel portion 514 is also a TN liquid crystal, for example, and multicolor display is performed by applying a predetermined voltage level. In addition, the display data input to the display device is also R (red), G
(Green), B (blue) 6-bit digital data each.

The timing control section 1601 is a block for generating a sync signal group required for the display device from the sync signal group output from the graphic controller. First,
The graphic controller outputs the sync signal group and the display data shown in FIG. 17, which is a so-called raster scan signal group which is generally used in the TFT liquid crystal. The timing control 1601 is based on these synchronization signal groups, and has an alternating signal, a division signal, a gate signal,
And a clear signal are generated and output at the timings shown in FIG. The clear signal has a phase later than the line signal, and the gate signal has a phase earlier than the line signal.

The column driving section 1602 has a timing control section 1
This block receives the synchronization signal and the display data output from 601 and converts them into a column voltage to output. First, the fetch latch unit 1605 fetches one row of display data in synchronization with the rising edge of the dot clock while the clear signal is cleared while the clear signal is "high" and the valid period signal is "high". The synchronization latch unit 1606 is the acquisition latch unit 160.
The color-reduction display data output from No. 5 is captured in synchronization with the line signal and output to the time division unit 1607. Time division unit 160
7, column voltage generation unit 1608, and column voltage output unit 1609
The configuration and operation of the time division unit 51 according to the first embodiment of the present invention
0, the column voltage generation unit 511, and the column voltage output unit 512 have the same configuration and operation.

The operations of the panel unit 1603 and the power supply unit 1604 are the same as those of the panel unit 502 and the power supply unit 503 according to the first embodiment of the present invention, and therefore their explanations are omitted.

The second embodiment of the present invention described above is
Similar to the first embodiment of the present invention, the column voltage changes within the non-overlap period in which all the switches in the distribution unit 1610 are in the OFF state. This avoids the phenomenon that the column voltage in the previous state is once applied,
It is possible to prevent unnecessary voltage fluctuations and avoid an increase in power consumption.

In the second embodiment of the present invention, the common inversion drive is taken as an example, but the invention is not limited to this, and so-called dot inversion drive or column inversion drive in which the opposing voltage is not oscillated. Is also easily applicable. In the present embodiment, the type of display is TF.
Although the T liquid crystal is used, the present invention is not limited to this, and can be applied to other displays whose display brightness is controlled by the voltage level, such as an organic EL display. The timing control unit 1601, the column driving unit 1602, and the power supply unit 1604 according to the second embodiment of the present invention may be integrated into individual LSIs or may be integrated into one, depending on the application. .

Further, in the first and second embodiments of the present invention, RGB is time-divided, but it is not limited to this, and it may be divided into two or four or more.

[0033]

In a liquid crystal display device having a switch group for distributing (demultiplexing) the column voltage output from the column driving circuit and outputting the column voltage to the column electrodes of the pixel portion, all the control signals of the switches are "low". “Non-overlap period” is provided, and the timing of each signal is specified so that the column voltage changes within this period. That is, the column voltage changes when all the switch groups are in the OFF state. Thereby, the phenomenon that the previous column voltage is once applied can be avoided, unnecessary voltage fluctuation can be prevented, and increase in power consumption can be avoided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device according to a conventional technique.

FIG. 2 is a timing chart showing an operation of a display device according to a conventional technique.

FIG. 3 is a timing chart showing the operation of the display device according to the conventional technique.

FIG. 4 is a timing chart showing the operation of the display device according to the present invention.

FIG. 5 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of input signals of the system interface according to the first embodiment of the present invention.

FIG. 7 is a timing chart showing an operation of an input signal of the system interface according to the first embodiment of the present invention.

FIG. 8 is a timing chart showing an output signal of the timing generation section according to the first embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the time division unit according to the first embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a column voltage generation unit according to the first embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a column voltage output unit according to the first embodiment of the present invention.

FIG. 12 is a diagram showing an operation of the column voltage output unit according to the first embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram showing a configuration of a pixel portion according to the first embodiment of the present invention.

FIG. 14 is a timing chart showing the operation of the power supply unit according to the first embodiment of the present invention.

FIG. 15 is a timing chart showing the operation of the panel section according to the first embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 17 is a timing chart showing an input signal of the timing control section according to the second embodiment of the present invention.

FIG. 18 is a timing chart showing an output signal of the timing control section according to the second embodiment of the present invention.

[Explanation of symbols]

501 ... Column drive unit, 502 ... Panel unit, 503 ... Power supply unit, 504 ... System interface, 505 ... Data register, 506 ... Memory write control unit, 507 ... Display memory, 508 ... Timing generation unit, 509 ... Memory read control unit Reference numeral 510 ... Time division unit, 511 ... Column voltage generation unit, 512 ... Column voltage output unit, 513 ... Distribution unit, 514 ...
Pixel part, 515 ... Row drive part, 1601 ... Timing control part, 1605 ... Acquisition latch part, 1606 ... Synchronization latch part.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 623G 623H 623R 623V 624 624B 633 633D (72) Inventor Kazuo Daimon Kodaira, Tokyo 5-20-1 Kamimizuhonmachi Incorporated company Hitachi Ltd. Semiconductor group (72) Inventor Toshimitsu Matsudo 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd. Display group (72) Inventor Atsuhiro Higa Totsuka, Yokohama, Kanagawa 292 Yoshida-cho, Tokyo Stock company F term in Hitachi Imaging Information System (reference) 2H093 NA16 NC01 NC09 NC11 NC16 NC22 NC26 NC29 NC34 ND39 5C006 AA01 AA16 AA22 AC11 AC27 AC28 AF04 AF22 AF43 AF52 AF71 AF85 BB13 BB16 BC16 BC23 BF02 BF05 BF03 BF04 BF03 BF04 BF03 BF04 BF15 BF16 BF24 BF34 EB05 FA16 FA25 FA37 FA42 FA 47 FA56 5C080 AA05 AA06 AA10 BB05 CC03 DD05 DD23 DD25 DD26 EE17 EE29 EE30 FF11 GG17 HH01 HH09 JJ02 JJ03 JJ04 KK02 KK04

Claims (8)

[Claims] 1. A counter electrode is formed on one inner surface of two substrates arranged to face each other with a liquid crystal layer interposed therebetween, and a plurality of row electrodes and column electrodes orthogonal to each other are formed on the inner surface of the other substrate. And a switching element with three terminals near each intersection of the column electrode,
And a first pixel, a second electrode, and a third terminal of the switching element are respectively connected to the row electrode, the column electrode, the liquid crystal layer, and the storage capacitor.
The opposite side of the liquid crystal layer is connected to the opposite electrode, and the opposite side of the storage capacitor is connected to the pixel electrode connected to the row electrode, and display data input from a higher-level device is converted into a column voltage, and liquid crystal driving is performed. And a column driving section that generates a display synchronization signal for a time period and outputs the column voltage for one row by time division (multiplexer) according to the display synchronization signal, and the column voltage output in the time division for one row. A distribution unit for distributing (demultiplexing) to a column voltage and outputting to the column electrode, and a row voltage for line-sequentially controlling ON / OFF of the switching element are provided to the row electrode in a row according to the display synchronization signal. A row drive section that sequentially outputs the potentials, which generates a reference voltage of the row voltage and the column voltage, outputs a counter voltage to the counter electrode according to the display synchronization signal, and outputs a control signal of the distributor. Table with power supply circuit to output to distribution unit In the display device, a display device is provided, in which a period during which the distribution operation in the distribution unit is intermittently stopped is provided, and the time-divided column voltage is switched within this period. 2. The display circuit according to claim 1, wherein the pixel portion, the distribution portion, and the row driving portion are integrally formed on the same substrate. 3. A display memory for storing one screen of display data supplied from a host device, a data register for storing control data supplied from the host device, and a display synchronization signal for driving liquid crystal based on the control data. A timing generation unit for generating, a time division unit for time division (multiplexer) of display data for one row read from the display memory, and conversion of the time division display data into column voltage,
In a display drive circuit including a column voltage output section that outputs according to the display synchronization signal and a column voltage generation section that generates the column voltages of a plurality of levels, the column voltage output in time division is used as the column voltage for one row. Control signal for distribution (demultiplexer) to the output, and the control signal causes the distribution operation to pause intermittently, and the output timing so that the time-divided column voltage switches within this pause period. A drive circuit for a display characterized by: 4. The display drive circuit according to claim 3, wherein an interface with a host device is a system bus direct connection type, and control data including display data is transferred from a CPU connected to the system bus. A display drive circuit characterized by: 5. A latch circuit for storing one row of display data supplied from a host device, a timing control unit for converting a synchronization signal supplied from the host device into a predetermined display synchronization signal, and the output from the latch circuit. A time division unit that time-divisions (multiplexes) one row of display data, and converts the time-divided display data into a column voltage.
In a display drive circuit including a column voltage output section that outputs according to the display synchronization signal and a column voltage generation section that generates the column voltages of a plurality of levels, the column voltage output in time division is used as the column voltage for one row. Control signal for distribution (demultiplexer) to the output, and the control signal causes the distribution operation to pause intermittently, and the output timing so that the time-divided column voltage switches within this pause period. A drive circuit for a display characterized in that 6. The display drive circuit according to claim 5, wherein the host device is a graphic controller, and the display data and the synchronizing signal group for raster scan are transferred from the graphic controller. circuit. 7. The display drive circuit according to claim 3 or 5, wherein the operation of intermittently suspending the distribution operation is performed by temporarily turning off all switches included in the distribution unit. A liquid crystal drive circuit for display, which is realized. 8. A pixel unit in which a plurality of pixels are arranged in a matrix, and display data input from a higher-level device is converted into a column voltage, and a display synchronization signal for driving a liquid crystal is generated, and the display synchronization signal is generated. According to the above, a column driving unit that outputs the column voltage for one row by time division (multiplexer) and outputs the column voltage output by the time division to the column voltage for one row (demultiplexer) and the column electrode. A row driving unit that sequentially outputs the row voltage for controlling the on / off of the switching elements line-sequentially to the row electrodes one by one according to the display synchronization signal; and the row voltage. In a display device including a power supply circuit that generates a reference potential of the column voltage, outputs a counter voltage to the counter electrode according to the display synchronization signal, and outputs a control signal of the distributor to the distributor. , In the distributor That the dispensing operation is provided intermittently period to pause a display device characterized by switching the said time divided column voltage within this period.